Testing system and method for carrying out batch system-level testing on embedded memory

Abstract

The invention discloses a testing system and method for batch system-level testing of an embedded memory, and the system is characterized in that the testing system comprises a plurality of testing nodes, a network module, a control module, and a monitoring module; the method comprises the following steps: determining the type and the number of embedded memories to be tested, configuring a test node environment and loading the memories; after configuration and loading are completed, the control module issues a test command, the node control computer of each test node receives and analyzes the test command and distributes the test command to the incubator and the FGPA platform of each test subsystem, and the FGPA platform issues the test command after receiving the command. Clustering management is carried out on the embedded memories needing to be tested through the network, the resource utilization rate and the testing efficiency are improved, remote control, management and monitoring of testing are achieved, a system-level testing method capable of being carried out in the high-low temperature environment is designed, an FPGA platform is adopted, and the system-level testing efficiency is improved. And the test driver can be flexibly formulated according to different types of embedded memories.

Description

Technical Field

[0001] The present invention belongs to the field of memory testing, and more specifically, relates to a testing system and method for performing batch system-level testing on embedded memories. Background Art

[0002] In the verification of embedded memory, system-level testing is a key link. System-level testing refers to the testing of the entire embedded memory device: the host computer issues a test command, and the memory responds to the test command. Especially for memories in the industrial and automotive fields, reliability testing of the memory is an indispensable link, and a large number of system-level tests are required to check the reliability of the memory.

[0003] Traditionally, this test usually tests a single memory, and there is no method for large-scale testing. In the existing technology, batch testing is mainly used to test multiple memories of an integrated circuit or a single chip, and there is no batch and clustered system-level testing of the memory itself. In order to test memories of different specifications and types, memory manufacturers often need to spend a lot of time and material resources.

[0004] At the same time, the existing technology also lacks research related to system-level testing in a temperature chamber environment. Frequent temperature change adjustments and environmental changes are necessary links, and it is impossible to ensure large-scale verification in high and low temperature environments and achieve test efficiency while ensuring test results. There is also a lack of clustered and networked management, resulting in low utilization of test resources, inconvenient operation and monitoring tests, and for embedded storage devices, such as eMMC and UFS, it is necessary to replace hardware according to the device type, which lacks flexibility. Summary of the invention

[0005] In response to the need for improvement of the prior art, the present invention proposes a test system and test method for batch system-level testing of embedded memories. It ensures that large-scale verification can be carried out in high and low temperature environments and that large-scale testing efficiency can be achieved while ensuring the test effect; and the utilization rate of test resources is not high, and the operation and monitoring test are flexible and convenient, and can be applied to hardware testing of memories of different specifications.

[0006] A test system for performing batch system-level tests on embedded memories, the test system comprising a plurality of test nodes, a network module, a control module, and a monitoring module; the plurality of test nodes are used for performing batch system-level tests; the network module is used for connecting a plurality of test nodes; the control module is connected to the network module and is used for controlling the test nodes to perform system-level tests; the monitoring module is connected to the network module and is used for checking the test progress, responding to query requests and feeding back query results.

[0007] Among them, the test node includes a node control computer, a temperature box, and multiple test modules; the node control computer is used to control the test process of the test node, and receive, analyze and distribute the test commands sent by the control module to the test node; the temperature box is used to adjust the temperature of the system-level test.

[0008] Wherein, the test module includes multiple test subsystems, a cooling device, and a cavity.

[0009] Among them, the test subsystem includes an embedded memory, a receiving device, a connecting board, and an FPGA platform; the receiving device is used to receive the embedded memory, the FPGA platform is used to configure the test driver according to the type of the memory under test and issue test commands to the memory under test, and the connecting board is used to connect the receiving device and the FPGA platform.

[0010] The FPGA platforms of the multiple test subsystems are all placed in the same cavity, and the cooling device is used to adjust the temperature of the FPGA platform.

[0011] Wherein, the containing device is specifically a fixture.

[0012] Wherein, the connecting plate is a temperature-insulating connecting plate, which is configured to isolate the FPGA platform from the test environment of the receiving device.

[0013] A test method for performing batch system-level testing on an embedded memory, the method comprising: Determine the type and quantity of embedded memory to be tested, configure the test node environment according to the type and quantity of embedded memory, and load the embedded memory; After configuration and loading are completed, the control module sends test commands. The node control computer of each test node receives and analyzes the test commands and distributes them to the incubator and the FGPA platform of each test subsystem. After receiving the commands, the FGPA platform sends test commands to the embedded memory to be tested.

[0014] According to the above scheme, the configuration of the test node environment includes: setting the test time, setting the temperature of the incubator of each test node, setting the start temperature of the cooling device, configuring the FPGA platform test driver corresponding to the embedded memory to be tested, and configuring the mounting device corresponding to the embedded memory to be tested.

[0015] A computer-readable storage medium stores a computer program, which, when executed by a processor of a computer, enables the computer to execute the above-mentioned test method for performing batch system-level testing on embedded memories.

[0016] The beneficial effects achieved by the present invention are: (1) Multiple test nodes can be used to perform system-level tests on multiple embedded memories under different conditions at the same time, and the network module can be used to manage the test nodes in a clustered manner, thereby improving resource utilization and test efficiency.

[0017] (2) By adjusting the test temperature in a temperature chamber, different test environments for system-level testing of embedded memory can be achieved, and the system-level test results of embedded memory in high and low temperature environments can be verified.

[0018] (3) According to different types of embedded memories, the FPGA platform corresponding to different test subsystems can flexibly formulate test drivers; it can also directly replace the test board or test subsystem according to the type of object under test, making the test system more flexible.

[0019] (4) The monitoring module and control module enable remote control, monitoring and management of the test, making it easier for testers to operate. Testers no longer have to stay at the control module to view the test progress, but can view the test progress anytime and anywhere through electronic devices such as mobile phones / computers. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a main component diagram of the system of the present invention; Figure 2 It is a structural diagram of the test system of the present invention; Figure 3 It is a test node structure diagram of the embodiment; Figure 4 It is a structural diagram of the test module of the embodiment; Figure 5 It is a structural diagram of the test subsystem of the embodiment; Figure 6 The figure is a flow chart of the testing method of the present invention.

[0021] In the figure: 1-test node; 2-network module; 3-control module; 4-monitoring module; 5-communication; 6-temperature box; 7-test module; 8-node control computer; 9-test subsystem; 10-cooling device; 11-cavity. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0023] This embodiment provides a test system for performing batch system-level tests on embedded memories, such as Figure 1 This is the main component diagram of this system, and the specific structure diagram of each component is as follows Figure 2 , Figure 3 , Figure 4 and Figure 5 shown.

[0024] like Figure 2 As shown, the test system includes multiple test nodes 1, a network module 2, a control module 3, and a monitoring module 4; the multiple test nodes 1 are used to perform batch system-level tests; the network module 2 is used to connect multiple test nodes; the control module 3 is the master control of the entire system, and is also connected to the network module 2, and is used to issue test commands and control the test nodes 1 to perform system-level tests. The device used can be a computer; the monitoring module 4 is also connected to the network module 2, and is preferably a monitoring program, which is used to view the test progress, and can respond to various query requests and feedback query results. The device used by the monitoring module 4 can be a mobile phone, computer and other electronic devices. During the test, the staff connects the control module 3 and the monitoring module 4 through the network module 2 to realize remote monitoring, remote control, and remote management of the test.

[0025] The control module 3 can communicate with the test node 1, and send various information to the test node 1, such as starting test commands, checking test status, collecting test results, etc. The test commands sent include the specific test nodes participating in the test and the specific content of the test, such as time, incubator temperature, etc., which belong to the control, management, and monitoring process; the monitoring module 4 also communicates with the control module 3, and is also a part of the monitoring process. The tester does not have to stay at the control module 3 to view the test progress, and can view the test progress anytime and anywhere through electronic devices such as mobile phones and computers.

[0026] Among them, Figure 3 As shown, the test node 1 includes a node control computer 8, a temperature box 6, and multiple test modules 7; the temperature box 6 is used to adjust the test temperature so that the embedded memory can be tested at the system level under different temperature environments, and can verify the mass test effect of high and low temperature environments. Each test node 1 can independently perform a system-level test with a high and low temperature environment. The node control computer 8 can control the test process of the test node, receive and analyze the test command sent by the system control module 3 to the test node 1, and distribute it to the temperature box 6 and the FGPA platform of each test subsystem 9. There is a communication process in the control process to transmit the control information to the temperature box 6 or the test module 7.

[0027] Among them, Figure 4 As shown, the test module 7 includes a plurality of test subsystems 9 , a cooling device 10 , and a cavity 11 .

[0028] Among them, Figure 5As shown, the test subsystem 9 is the smallest unit for performing tests on embedded memory, including embedded memory, a receiving device, a connecting plate, and an FPGA platform; the receiving device is used to receive the embedded memory, the FPGA platform is used to set the test drive and issue interactive commands to the embedded memory, and the connecting plate is used to connect the receiving device and the FPGA platform. The FPGA platforms of multiple test subsystems 9 are all placed in the same cavity 11, and the cavity 11 has good airtightness, and is accompanied by a cooling device 10, which can be a fan or a water-cooling structure. The temperature of the FPGA platform can be adjusted by the cooling device 10, so that the temperature of the FPGA platform can be controlled. In this embodiment, the receiving device used is a fixture, and the connecting plate used is a temperature-insulating connecting plate, which isolates the FPGA platform from the test environment of the receiving device.

[0029] This embodiment also proposes a test method for performing batch system-level testing on embedded memory, such as Figure 6 As shown, the method includes: S1. Determine the type and quantity of the embedded memory to be tested, configure the test node environment according to the type and quantity of the embedded memory, and load the embedded memory.

[0030] Before the test begins, the environment is first built to determine the object to be tested, that is, to determine the type and quantity of the embedded memory to be tested. Then, the test node environment is configured according to the object to be tested, that is, the type and quantity of the embedded memory to be tested. The above belongs to the environment building process.

[0031] Configuring the test node environment includes: setting the test time, setting the temperature of the incubator 6, setting the start temperature of the cooling device 10, configuring the FPGA platform test driver corresponding to the embedded memory to be tested, and configuring the mounting device corresponding to the embedded memory to be tested.

[0032] Typically, emmc has a dedicated test board, and ufs also has a dedicated test board. As another embodiment of the present application, the test board can also be directly replaced according to the type of embedded memory to be tested as the test subsystem 9 in this embodiment.

[0033] S2. After configuration and loading are completed, the control module 3 sends a test command, and the node control computer 8 of each test node 1 receives and analyzes the test command and distributes it to the incubator 6 and the FGPA platform of each test subsystem 9. After receiving the command, the FGPA platform sends a test command to the embedded memory to be tested.

[0034] By changing the temperature of the incubator 6 of each test node 1, system-level testing and large-scale verification of the embedded memory can be achieved under different temperature environments. The FPGA platform can be isolated from the test environment of the housing through the thermal insulation connecting plate and the cooling device 10, ensuring that the FPGA platform in the closed cavity is not affected by high and low temperature environments.

[0035] In summary, the entire test process is: determine the test object, configure the test node environment, load the embedded memory, and send commands from the control module 3, including the test nodes involved in the test and the test content. After the control module 3 sends the command, the node control computer 8 of each test node 1 receives the command, parses and distributes the command to the incubator 6 and each FPGA platform, and then the FPGA platform sends the test command to the test object.

[0036] As another embodiment of the present invention, the present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor of a computer, enables the computer to execute the test method for performing batch system-level testing on embedded memories as described above.

[0037] The present invention performs batch system-level tests on multiple embedded memories through multiple test nodes 1, and performs cluster management of test resources through a network module 2, thereby improving resource utilization and test efficiency; and adjusts the test temperature through an incubator 6, so that the system-level test effects under high and low temperature environments can be verified in large quantities, making up for the lack of research related to system-level testing in an incubator environment in the prior art; at the same time, through an FPGA platform, test drivers can be flexibly formulated according to different types of embedded memories, making the test system more flexible; remote control, monitoring and management of the test are realized through a control module 3 and a monitoring module 4, which facilitates the operation of test personnel. The test personnel do not have to stay at the control module 3 to view the test progress, and can view the test progress through electronic devices such as mobile phones / computers anytime and anywhere.

[0038] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A test system for batch system-level testing of embedded memory, characterized in that: The test system includes multiple test nodes, a network module, a control module, and a monitoring module; the multiple test nodes are used to perform batch system-level tests; the network module is used to connect multiple test nodes; the control module is connected to the network module, and is used to issue test commands and control the test nodes to perform system-level tests; the monitoring module is connected to the network module, and is used to view the test progress, respond to query requests, and feedback query results.

2. The test system for performing batch system-level testing on embedded memory according to claim 1, characterized in that: The test node includes a node control computer, a temperature chamber, and multiple test modules; the node control computer is used to control the test process of the test node, and receive, analyze and distribute the test commands sent by the control module to the test node; the temperature chamber is used to adjust the temperature of the system-level test.

3. The test system for performing batch system-level testing on embedded memory according to claim 2, characterized in that: The test module includes a plurality of test subsystems, a cooling device, and a cavity.

4. The test system for performing batch system-level testing on embedded memory according to claim 3, characterized in that: The test subsystem includes an embedded memory, a receiving device, a connecting board, and an FPGA platform; the receiving device is used to receive the embedded memory, the FPGA platform is used to configure the test driver according to the type of the memory under test and issue test commands to the memory under test, and the connecting board is used to connect the receiving device and the FPGA platform.

5. The test system for performing batch system-level testing on embedded memory according to claim 3 or claim 4, characterized in that: The FPGA platforms of the multiple test subsystems are all placed in the same cavity, and the temperature cooling device is used to adjust the temperature of the FPGA platform.

6. The test system for performing batch system-level testing on embedded memory according to claim 4, characterized in that: The containing device is specifically a fixture.

7. The test system for performing batch system-level testing on embedded memory according to claim 4, characterized in that: The connecting plate is a temperature-insulating connecting plate, which is configured to isolate the FPGA platform from the test environment of the receiving device.

8. A test method for batch system-level testing of embedded memory, characterized in that: The method comprises: Determine the type and quantity of embedded memory to be tested, configure the test node environment according to the type and quantity of embedded memory, and load the embedded memory; After configuration and loading are completed, the control module sends test commands. The node control computer of each test node receives and analyzes the test commands and distributes them to the incubator and the FGPA platform of each test subsystem. After receiving the commands, the FGPA platform sends test commands to the embedded memory to be tested.

9. The test method for performing batch system-level testing on embedded memory according to claim 8, characterized in that: The configuration of the test node environment includes: setting the test time, setting the temperature of the incubator, setting the start temperature of the cooling device, configuring the FPGA platform test driver, and configuring the receiving device corresponding to the embedded memory to be tested.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor of a computer, the computer is caused to execute the test method for performing batch system-level testing on embedded memories as described in any one of claim 8 or claim 9.

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