Discharging circuit for suppressing current peak by utilizing Miller effect of MOS (Metal Oxide Semiconductor) tube

Abstract

The invention belongs to the field of lithium battery core testing, and discloses a discharging circuit for suppressing a current peak by utilizing the Miller effect of an MOS (Metal Oxide Semiconductor) transistor, which comprises a booster circuit, a rectifying circuit, a filter circuit, a discharging loop and a tested circuit, the booster circuit is used for amplifying the input voltage and outputting the amplified input voltage to the rectifying circuit; the rectifying circuit is used for converting the alternating current signal output by the booster circuit into a positive signal and outputting the positive signal; the filter circuit is used for smoothing and filtering the signal output by the rectifying circuit; and the discharge loop is used for increasing the discharge speed of the tested circuit and inhibiting the current peak generated at the discharge moment based on the Miller effect of the MOS tube. According to the invention, the Miller effect of the MOS tube is utilized to suppress the current peak generated at the moment of discharging, and the output voltage precision and the discharging speed are not influenced, so that the peak current generated by the internal and external capacitors in the discharging loop at the moment of discharging becomes smaller.

Description

Technical Field

[0001] The invention relates to the field of lithium battery core testing, and in particular to a discharge circuit which utilizes the Miller effect of a MOS tube to suppress current spikes. Background Art

[0002] The pulse test method is one of the commonly used measurement methods to identify short circuits or micro short circuits between the positive and negative electrodes of lithium battery cells. The pulse test is divided into three stages: charging, voltage maintenance and discharge. After the voltage maintenance stage, the lithium battery cell under test needs to be discharged.

[0003] Due to the need for rapid discharge, the resistance of the discharge circuit is relatively small. In order to stabilize the output voltage, the capacitance of the filter capacitor at the output end is relatively large. When the capacitance of the lithium battery cell being tested is high, at the moment of discharge, the capacitance of the external lithium battery cell and the internal filter capacitor are superimposed together, which will produce a large current spike in the discharge circuit and a large voltage drop. This voltage drop may affect the judgment of the lithium battery cell test, and excessive current may cause damage to the discharge circuit. Reducing the capacitance of the filter capacitor will affect the output voltage accuracy, and increasing the resistance of the discharge resistor will extend the discharge time.

[0004] Therefore, how to provide a discharge circuit that utilizes the Miller effect of a MOS tube to suppress current spikes is a problem that needs to be solved urgently. Summary of the invention

[0005] The embodiment of the present invention provides a discharge circuit that uses the Miller effect of a MOS tube to suppress current spikes, so as to solve the problem in the prior art that a discharge circuit generates a large current spike and a large voltage drop, which may affect the judgment of the lithium battery cell test, and the excessive current may damage the discharge circuit. Specifically, it relates to the suppression of the current spike generated at the moment of discharge during the lithium battery cell test.

[0006] According to an embodiment of the present invention, a discharge circuit is provided for suppressing current spikes by utilizing the Miller effect of a MOS tube.

[0007] In one embodiment, a discharge circuit for suppressing current spikes by using the Miller effect of a MOS tube includes a boost circuit, a rectifier circuit, a filter circuit, a discharge loop, and a circuit under test; wherein the boost circuit is connected to the rectifier circuit, and the rectifier circuit is sequentially connected to the filter circuit, the discharge loop, and the circuit under test; A boost circuit, used to amplify the input voltage and output it to the rectifier circuit; A rectifier circuit, used for converting the AC signal output by the boost circuit into a positive signal output; A filter circuit, used for smoothing and filtering the signal output by the rectifier circuit; The discharge circuit is used to speed up the discharge of the circuit under test and suppress the current spike generated at the moment of discharge based on the Miller effect of the MOS tube.

[0008] In one embodiment, the boost circuit is a boost transformer TF1 , and the output end of the boost transformer TF1 is connected to the rectifier circuit.

[0009] In one embodiment, the rectifier circuit includes a diode D12, a diode D13, a diode D14, and a diode D15; Among them, the anode of diode D14 is connected to the cathode of diode D12 and the a-end of step-up transformer TF1, and the anode of diode D15 is connected to the cathode of diode D13 and the b-end of step-up transformer TF1; the cathode of diode D14 is connected to the cathode of diode D15, the filter circuit, the discharge circuit and the circuit under test in sequence; the anode of diode D12 is connected to the anode of diode D13, the filter circuit, the discharge circuit and the circuit under test in sequence.

[0010] In one embodiment, the diode D12 , the diode D13 , the diode D14 , and the diode D15 form a full-bridge rectifier circuit.

[0011] In one embodiment, the filter circuit includes a capacitor C4, a capacitor C7, a resistor R31, a resistor R32, a resistor R33, a resistor R34 and a resistor R36; Among them, capacitor C4 is connected in series with capacitor C7, and resistor R31 is connected in series with resistor R32, resistor R33, resistor R34 and resistor R36 in sequence; one end of capacitor C4 is connected in sequence with one end of resistor R31, the positive electrode of diode D13, the discharge loop and the circuit under test, and one end of capacitor C7 is connected in sequence with one end of resistor R36, the negative electrode of diode D15, the discharge loop and the circuit under test.

[0012] In one embodiment, the resistor R31 , the resistor R32 , the resistor R33 , the resistor R34 , and the resistor R36 are all load resistors.

[0013] In one embodiment, the discharge circuit includes a MOS tube T1, a capacitor C6, a resistor R37 and a resistor R38; Among them, the e end of the MOS tube T1 is connected to one end of the capacitor C6 and one end of the resistor R37 in sequence, the f end of the MOS tube T1 is connected to the circuit under test and one end of the resistor R31 in sequence, the g end of the MOS tube T1 is connected to the other end of the capacitor C6 and the MOS tube control signal end in sequence, the other end of the resistor R37 is connected to one end of the resistor R38, and the other end of the resistor R38 is connected to the circuit under test and one end of the resistor R36 in sequence.

[0014] In one embodiment, the e-end of the MOS transistor T1 is a drain, the f-end of the MOS transistor T1 is a source, and the g-end of the MOS transistor T1 is a gate.

[0015] In one embodiment, the capacitor C6 is disposed between the gate and the drain of the MOS transistor T1 , and the capacitor C6 is connected in parallel with the Miller capacitor inside the MOS transistor T1 , so that the capacitance value of the equivalent Miller capacitor of the MOS transistor T1 is increased.

[0016] In one embodiment, the circuit under test includes a capacitor C5 and a resistor R35; The capacitor C5 is connected in parallel with the resistor R35, and one end of the capacitor C5 and the resistor R35 is connected to one end of the resistor R38, and the other end of the capacitor C5 and the resistor R35 is connected to the f end of the MOS tube T1.

[0017] The technical solution provided by the embodiment of the present invention may have the following beneficial effects: (1) The present invention utilizes the Miller effect of the MOS tube to suppress the current spike generated at the moment of discharge without affecting the output voltage accuracy and discharge speed. By adding a capacitor between the G pole and the D pole of the MOS tube, the Miller platform and switching time of the MOS tube are lengthened, thereby reducing the peak current generated by the internal and external capacitors in the discharge circuit at the moment of discharge.

[0018] (2) The present invention provides a discharge circuit that utilizes the Miller effect of a MOS tube to suppress current spikes. A high-capacitance filter capacitor is used to ensure the accuracy of the output voltage. A low-resistance discharge resistor is used to ensure the discharge speed of the lithium battery cell under test. The Miller effect of the MOS tube is used to extend the switching time of the MOS tube, thereby reducing the peak current at the moment of discharge and the voltage drop caused by it, thereby improving the accuracy of the pulse test method in the voltage maintenance stage, and will not affect the accuracy of the output voltage of the pulse test method in the charging and voltage maintenance stages, thereby improving the reliability of the measurement. In addition, the circuit structure of the present invention is simple and the cost is low.

[0019] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0021] Figure 1 The present invention is a circuit diagram showing a discharge circuit for suppressing current spikes by utilizing the Miller effect of a MOS tube according to an exemplary embodiment.

[0022] Reference numerals: 1. Boost circuit; 2. Rectifier circuit; 3. Filter circuit; 4. Discharge circuit; 5. Circuit under test. DETAILED DESCRIPTION

[0023] The following description and accompanying drawings fully illustrate the specific embodiments of this article so that those skilled in the art can practice them. The parts and features of some embodiments can be included in or replace the parts and features of other embodiments. Herein, the terms "first", "second", etc. are only used to distinguish one element from another element, without requiring or implying any actual relationship or order between these elements. In fact, the first element can also be called the second element, and vice versa. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the structure, device or equipment including a series of elements not only include those elements, but also include other elements that are not clearly listed, or also include elements inherent to such structure, device or equipment. In the absence of more restrictions, the elements defined by the sentence "comprise one..." do not exclude the existence of other identical elements in the structure, device or equipment including the elements. Each embodiment is described in a progressive manner herein, and each embodiment focuses on the differences from other embodiments, and the same similar parts between the embodiments can be referred to each other. The terms "longitudinal", "lateral", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like in this document indicate the orientation or position relationship based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing this document and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. In the description of this document, unless otherwise specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a mechanical connection or an electrical connection, or it can be the internal communication of two elements, it can be directly connected, or it can be indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to the specific circumstances. In this document, unless otherwise specified, the term "multiple" means two or more. In this document, the character " / " indicates that the objects before and after are in an "or" relationship. For example, A / B means: A or B. In this document, the term "and / or" is a description of the association relationship of objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B. It should be understood that, although the steps in the flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders.Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these sub-steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps. Each module in the device or system of the present application can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so that the processor calls and executes the operations corresponding to the above modules. In the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0024] Figure 1 An embodiment of a discharge circuit for suppressing current spikes by using the Miller effect of a MOS tube according to the present invention is shown.

[0025] In this optional embodiment, the discharge circuit for suppressing current spikes by using the Miller effect of the MOS tube includes a boost circuit 1, a rectifier circuit 2, a filter circuit 3, a discharge circuit 4 and a circuit under test 5; wherein the boost circuit 1 is connected to the rectifier circuit 2, and the rectifier circuit 2 is connected to the filter circuit 3, the discharge circuit 4 and the circuit under test 5 in sequence; A boost circuit 1 is used to amplify the input voltage and output it to a rectifier circuit 2; The rectifier circuit 2 is used to convert the AC signal output by the boost circuit 1 into a positive signal output; The filter circuit 3 is used for smoothing and filtering the signal output by the rectifier circuit 2; The discharge circuit 4 is used to accelerate the discharge speed of the circuit under test 5 and suppress the current spike generated at the moment of discharge based on the Miller effect of the MOS tube.

[0026] In one embodiment, the boost circuit 1 is a boost transformer TF1 , and the output end of the boost transformer TF1 is connected to the rectifier circuit 2 .

[0027] In one embodiment, the rectifier circuit 2 includes a diode D12, a diode D13, a diode D14 and a diode D15; Among them, the anode of the diode D14 is connected to the cathode of the diode D12 and the a-end of the step-up transformer TF1, and the anode of the diode D15 is connected to the cathode of the diode D13 and the b-end of the step-up transformer TF1; the cathode of the diode D14 is connected to the cathode of the diode D15, the filter circuit 3, the discharge loop 4 and the circuit under test 5 in sequence; the anode of the diode D12 is connected to the anode of the diode D13, the filter circuit 3, the discharge loop 4 and the circuit under test 5 in sequence.

[0028] In one embodiment, the diode D12 , the diode D13 , the diode D14 , and the diode D15 form a full-bridge rectifier circuit.

[0029] In one embodiment, the filter circuit 3 includes a capacitor C4, a capacitor C7, a resistor R31, a resistor R32, a resistor R33, a resistor R34 and a resistor R36; Among them, capacitor C4 is connected in series with capacitor C7, and resistor R31 is connected in series with resistor R32, resistor R33, resistor R34 and resistor R36 in sequence; one end of capacitor C4 is connected in sequence with one end of resistor R31, the positive electrode of diode D13, the discharge loop 4 and the circuit under test 5, and one end of capacitor C7 is connected in sequence with one end of resistor R36, the negative electrode of diode D15, the discharge loop 4 and the circuit under test 5.

[0030] In one embodiment, the resistor R31 , the resistor R32 , the resistor R33 , the resistor R34 , and the resistor R36 are all load resistors.

[0031] In one embodiment, the discharge circuit 4 includes a MOS tube T1, a capacitor C6, a resistor R37 and a resistor R38; Among them, the e end of the MOS tube T1 is connected to one end of the capacitor C6 and one end of the resistor R37 in sequence, the f end of the MOS tube T1 is connected to the circuit under test 5 and one end of the resistor R31 in sequence, the g end of the MOS tube T1 is connected to the other end of the capacitor C6 and the MOS tube control signal end in sequence, the other end of the resistor R37 is connected to one end of the resistor R38, and the other end of the resistor R38 is connected to the circuit under test 5 and one end of the resistor R36 in sequence.

[0032] In one embodiment, the e-end of the MOS transistor T1 is a drain, the f-end of the MOS transistor T1 is a source, and the g-end of the MOS transistor T1 is a gate.

[0033] In one embodiment, the capacitor C6 is disposed between the gate and the drain of the MOS transistor T1 , and the capacitor C6 is connected in parallel with the Miller capacitor inside the MOS transistor T1 , so that the capacitance value of the equivalent Miller capacitor of the MOS transistor T1 is increased.

[0034] In one embodiment, the circuit under test 5 includes a capacitor C5 and a resistor R35; The capacitor C5 is connected in parallel with the resistor R35, and one end of the capacitor C5 and the resistor R35 is connected to one end of the resistor R38, and the other end of the capacitor C5 and the resistor R35 is connected to the f end of the MOS tube T1.

[0035] In order to facilitate understanding of the above technical solutions of the present invention, the above technical solutions of the present invention are further described below from the perspective of architecture and principle, as follows: like Figure 1In the figure, TF1 is a step-up transformer, which can amplify the input voltage and output it; diode D14, diode D15, diode D12 and diode D13 form a full-bridge rectifier circuit, which can convert the AC signal output by the step-up transformer TF1 into a positive signal output; capacitor C7 and capacitor C4 are filter capacitors, which can smooth and filter the signal output by the rectifier circuit to stabilize the output voltage; resistors R31, R32, R33, R34 and R36 are internal load resistors with large resistance values, which can stabilize the output voltage; resistors R37 and R38 are discharge resistors with small resistance values, which can enable the DUT to discharge quickly; capacitor C6 is connected between the gate and drain of MOS tube T1, which is equivalent to being connected in parallel with the Miller capacitor inside MOS tube T1, so that the equivalent Miller capacitor of MOS tube T1 increases. C5 and R35 are connected in parallel, which is equivalent to the DUT.

[0036] Working principle: At the moment of discharge, the gate of MOS tube T1 is sent to a high level. At this time, MOS tube T1 is turned on, and the filter capacitors C7, C4 and the equivalent capacitor C5 of the measured product generate a current C·dU / dt on the discharge resistors R37 and R38, where C represents capacitance, U represents voltage, and t represents time. Since the switching time of the MOS tube is short, dt is very small and C·dU / dt is very large, so the current flowing through R1 and R2 is very large. After adding capacitor C6, the Miller capacitance of MOS tube T1 becomes larger, the conduction time of the MOS tube becomes longer, dt becomes larger, C·dU / dt becomes smaller, and the current flowing through R1 and R2 becomes smaller.

[0037] The present invention is not limited to the structures that have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof.

Claims

1. A discharge circuit that utilizes the Miller effect of a MOS tube to suppress current spikes, characterized in that: The discharge circuit comprises a boost circuit (1), a rectifier circuit (2), a filter circuit (3), a discharge loop (4) and a circuit to be tested (5); The boost circuit (1) is connected to the rectifier circuit (2), and the rectifier circuit (2) is connected in sequence to the filter circuit (3), the discharge circuit (4) and the circuit under test (5); The boost circuit (1) is used to amplify the input voltage and output it to the rectifier circuit (2); The rectifier circuit (2) is used to convert the AC signal output by the boost circuit (1) into a positive signal output; The filter circuit (3) is used to perform smooth filtering on the signal output by the rectifier circuit (2); The discharge circuit (4) is used to accelerate the discharge speed of the circuit under test (5) and, based on the Miller effect of the MOS tube, suppress the current spike generated at the moment of discharge.

2. A discharge circuit for suppressing current spikes by using the Miller effect of a MOS tube according to claim 1, characterized in that: The boost circuit (1) is a boost transformer TF1, and the output end of the boost transformer TF1 is connected to the rectifier circuit (2).

3. A discharge circuit for suppressing current spikes by using the Miller effect of a MOS tube according to claim 2, characterized in that: The rectifier circuit (2) comprises a diode D12, a diode D13, a diode D14 and a diode D15; The anode of the diode D14 is connected to the cathode of the diode D12 and the end a of the step-up transformer TF1, and the anode of the diode D15 is connected to the cathode of the diode D13 and the end b of the step-up transformer TF1. The cathode of the diode D14 is connected in sequence to the cathode of the diode D15, the filter circuit (3), the discharge circuit (4) and the circuit under test (5); The anode of the diode D12 is connected in sequence to the anode of the diode D13, the filter circuit (3), the discharge circuit (4) and the circuit under test (5).

4. A discharge circuit for suppressing current spikes by using the Miller effect of a MOS tube according to claim 3, characterized in that: The diode D12, the diode D13, the diode D14 and the diode D15 form a full-bridge rectifier circuit.

5. The discharge circuit for suppressing current spikes by using the Miller effect of a MOS tube according to claim 3, characterized in that: The filter circuit (3) comprises a capacitor C4, a capacitor C7, a resistor R31, a resistor R32, a resistor R33, a resistor R34 and a resistor R36; The capacitor C4 is connected in series with the capacitor C7, and the resistor R31 is connected in series with the resistor R32, the resistor R33, the resistor R34 and the resistor R36 in sequence; One end of the capacitor C4 is connected in sequence to one end of the resistor R31, the positive electrode of the diode D13, the discharge circuit (4) and the circuit under test (5); one end of the capacitor C7 is connected in sequence to one end of the resistor R36, the negative electrode of the diode D15, the discharge circuit (4) and the circuit under test (5).

6. A discharge circuit for suppressing current spikes by using the Miller effect of a MOS tube according to claim 5, characterized in that: The resistor R31 , the resistor R32 , the resistor R33 , the resistor R34 , and the resistor R36 are all load resistors.

7. A discharge circuit for suppressing current spikes by using the Miller effect of a MOS tube according to claim 5, characterized in that: The discharge circuit (4) comprises a MOS tube T1, a capacitor C6, a resistor R37 and a resistor R38; The e end of the MOS tube T1 is connected to one end of the capacitor C6 and one end of the resistor R37 in sequence, the f end of the MOS tube T1 is connected to the circuit under test (5) and one end of the resistor R31 in sequence, the g end of the MOS tube T1 is connected to the other end of the capacitor C6 and the MOS tube control signal end in sequence, the other end of the resistor R37 is connected to one end of the resistor R38, and the other end of the resistor R38 is connected to the circuit under test (5) and one end of the resistor R36 in sequence.

8. The discharge circuit for suppressing current spikes by using the Miller effect of a MOS tube according to claim 7, characterized in that: The e end of the MOS transistor T1 is a drain, the f end of the MOS transistor T1 is a source, and the g end of the MOS transistor T1 is a gate.

9. A discharge circuit for suppressing current spikes by using the Miller effect of a MOS tube according to claim 8, characterized in that: The capacitor C6 is arranged between the gate and the drain of the MOS transistor T1 , and the capacitor C6 is connected in parallel with the Miller capacitor inside the MOS transistor T1 , so that the capacitance value of the equivalent Miller capacitor of the MOS transistor T1 is increased.

10. The discharge circuit for suppressing current spikes by using the Miller effect of a MOS tube according to claim 7, characterized in that: The circuit under test (5) comprises a capacitor C5 and a resistor R35; The capacitor C5 is connected in parallel with the resistor R35, and one end of the capacitor C5 and the resistor R35 is connected to one end of the resistor R38, and the other end of the capacitor C5 and the resistor R35 is connected to the f end of the MOS tube T1.

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