Device for improving feedback precision by using multiple encoders

Abstract

The utility model discloses a device for improving feedback precision by using a plurality of encoders, which belongs to the technical field of design based on integrated circuit application and comprises a power management module connected with an encoder module, a signal processing module and a signal output circuit. The encoder module is connected with the signal processing module, and the signal processing module is connected with the signal output circuit; through the connection mode, the power management module provides power for the whole device, the encoder module improves high-precision feedback of motor motion, the signal processing module collects and processes signals of the encoder module, and the signal output circuit generates differential signals from the synthesized signals and outputs the differential signals. Error measurement does not need to be carried out on each device, the device can be directly installed for use, and the production efficiency can be greatly improved.

Description

[Technical field]

[0001] The utility model relates to the technical field of design based on integrated circuit application, and in particular to a device for improving feedback accuracy by using multiple encoders. [Background Technology]

[0002] In the field of motion control, if the mechanical movement wants to achieve higher accuracy, high-precision feedback is required, such as the currently commonly used grating encoder. However, when you want to further improve the feedback accuracy, you need to use other methods to compensate for some errors in the feedback. The existing solution requires error measurement for each device, and expensive measuring instruments are required during the measurement process, and the efficiency is low. When large quantities are required, the delivery speed is often not met. Since the data that needs to be compensated for each motor is different, it is necessary to import different compensation data into each driver, and there is no way to achieve unification; after compensation, the driver and motor are bound together. If the driver or motor needs to be replaced later, it needs to be compensated again, and the flexibility will be discounted. And when the original accuracy changes due to external factors, such as the concentricity of the code disk is affected or the bearing is aged and worn, the data needs to be re-measured and compensated.

[0003] For example, Chinese patent CN116169901A discloses a device and method for improving the precision of multi-motor synchronous control, including a host computer, an unwinding motor M1 driver, a printing motor M2 driver, a printing motor M3 driver, a winding motor M4 driver, an unwinding motor M1, a printing motor M2, a printing motor M3, a winding motor M4, an unwinding motor M1 speed sensor, a printing motor M2 speed sensor, a printing motor M3 speed sensor, and a winding motor M4 device. An adaptive inverse sliding mode controller is designed to improve the tracking performance of a single motor control system; a speed feedback correction compensation module is used for multiple electric speed sensors; the synchronous control system of the machine adopts an improved deviation coupling control strategy, uses a model reference identification method to identify the real-time moment of inertia of the permanent magnet synchronous motor, and sends it to a speed compensator to calculate a variable coupling gain, and the output synchronization error is fed back to the speed loop, thereby improving the control precision of the multi-motor synchronous control system.

[0004] However, this technology has the following problems: if the drive or motor needs to be replaced later, re-compensation is required, which reduces flexibility. [Contents of the utility model]

[0005] In view of the above-mentioned shortcomings of the prior art, the utility model provides a device for improving feedback accuracy by using multiple encoders.

[0006] In order to achieve the above object, a device for improving feedback accuracy using multiple encoders is designed, comprising a power management module, the power management module is connected to an encoder module, a signal processing module, and a signal output circuit; the encoder module is connected to the signal processing module, and the signal processing module is connected to the signal output circuit;

[0007] The power management module includes a power reminder circuit, a 3.3V power circuit, a 2.5V power circuit and a 1.2V power circuit. The power reminder circuit, the 3.3V power circuit, the 2.5V power circuit and the 1.2V power circuit are all electrically connected to a 5V power supply. The 5V power supply is connected to the encoder module and the signal output circuit. The 3.3V power circuit is connected to the signal processing module and the signal output circuit. The 2.5V power circuit is connected to the signal processing module and the signal output circuit. The 1.2V power circuit is connected to the signal processing module.

[0008] Furthermore, the power reminder circuit includes a capacitor C1, a capacitor C5, a resistor R1 and a light-emitting diode D2; the capacitor C1 is connected in parallel with the capacitor C5, and the capacitor C1 and the capacitor C5 are connected in series with the resistor R1 and the light-emitting diode D2; one end of the capacitor C1 and one end of the capacitor C5 are electrically connected to a 5V power supply, and the other end of the capacitor C1 and the other end of the capacitor C5 are grounded; the 3.3V power supply circuit includes a 3.3V power supply chip, a capacitor C2 and a capacitor C6; the fourth pin of the 3.3V power supply chip is connected to the capacitor C2 , capacitor C6 are connected in parallel, capacitor C2 and capacitor C6 are connected in parallel, the first pin of the 3.3V power chip, one end of capacitor C2, and one end of capacitor C6 are all grounded; the third pin of the 3.3V power chip is electrically connected to the 5V power supply, and the other end of capacitor C2 and the other end of capacitor C6 both output 3.3V voltage; the 2.5V power circuit and the 1.2V power circuit are connected in the same way as the 3.3V power circuit, the 2.5V power circuit outputs a 2.2V voltage, and the 1.2V power circuit outputs a 1.2V voltage.

[0009] Furthermore, the encoder module is an encoder; the encoder is provided with two groups and the installation positions differ by 180 degrees; the encoder includes a grating signal acquisition chip, a configuration chip, a subdivision chip and a capacitor and resistor module; the grating signal acquisition chip and the configuration chip are electrically connected to the subdivision chip, and the grating signal acquisition chip, the configuration chip and the subdivision chip are electrically connected to a 5V power supply.

[0010] Furthermore, the grating signal acquisition chip comprises an A-pin, an A+ pin, a B+ pin, a B-pin, a Z+ pin, a Z-pin, an LED+ pin, an LED- pin, an LEDR pin, a VCCA pin, a GNDA pin, a SEL1 pin, a SEL2 pin, a VCC pin and a GND pin; the A-pin, the A+ pin, the Z+ pin and the Z-pin are all electrically connected to the segmentation chip (213), two LED+ pins are provided and both are electrically connected to a 5V power supply, the LED- pin is electrically connected to the LEDR pin, the VCCA pin, the SEL2 pin and the VCC pin are all electrically connected to the 5V power supply, two SEL1 pins are provided and both are grounded, and the GNDA pin and the GND pin are both grounded; the configuration chip comprises eight pins; the first pin, the second pin, the third pin, the fourth pin and the seventh pin are all grounded; the eighth pin is electrically connected to the 5V power supply, the The fifth pin and the sixth pin are both electrically connected to the segmentation chip, and the fifth pin and the sixth pin are both electrically connected to the 5V power supply through a resistor; the segmentation chip includes twenty pins, the tenth pin and the eleventh pin of the segmentation chip are respectively electrically connected to the fifth pin and the sixth pin of the configuration chip in a one-to-one correspondence, the first pin is electrically connected to the Z+ pin, the second pin is electrically connected to the Z- pin, the third pin is electrically connected to the A+ pin, the fourth pin is electrically connected to the A- pin, the first pin, the second pin, the third pin, the fourth pin, the seventh pin, the eighth pin, and the fifth pin are all connected in series with the capacitor and then in parallel, the fifth pin is connected in parallel with the sixth pin and then grounded, the seventh pin is electrically connected to B+, the eighth pin is electrically connected to B-, the twelfth pin, the thirteenth pin, the fourteenth pin, the fifteenth pin, the eighteenth pin, and the nineteenth pin are all connected to the signal processing module through a resistor, the sixteenth pin is grounded, and the seventeenth pin is connected to the 5V power supply.

[0011] Furthermore, the encoder also includes a capacitor and resistor module; the capacitor and resistor module includes 6 capacitors and 2 resistors; the 6 capacitors are connected in series with the 2 resistors, the 6 capacitors are connected in parallel in sequence, one end of the 6 capacitors is grounded, and the other end is electrically connected to a 5V power supply.

[0012] Furthermore, the signal processing module includes an FPGA chip, a reset circuit, a crystal oscillator circuit and a data configuration circuit; the input end of the FPGA chip is electrically connected to the output ends of the two groups of encoders, the output end of the reset circuit, the output end of the crystal oscillator circuit, the 3.3V power supply circuit, the 2.5V power supply circuit, and the 1.2V power supply circuit, and the output end of the FPGA chip is connected to the signal output circuit; the input ends of the reset circuit and the crystal oscillator circuit are electrically connected to the 3.3V power supply circuit, and the data configuration circuit is electrically connected to the 3.3V power supply circuit and the 2.5V power supply circuit.

[0013] Furthermore, the pins of the FPGA chip are connected to a data configuration circuit, and the A1 pin, A16 pin, C4 pin, C7 pin, C10 pin, C13 pin, E3 pin, E14 pin, F4 pin, G3 pin, G14 pin, H5 pin, H12 pin, H14 pin, K3 pin, K14 pin, M3 pin, M14 pin, P4 pin, P7 pin, P10 pin, P13 pin, T1 pin, and T16 pin are all electrically connected to a 3.3V power supply circuit, and the D13 pin, G6 pin, G7 pin, and G8 pin are electrically connected to a 3.3V power supply circuit. The pin, G9 pin, G10 pin, H6 pin, H11 pin, K7 pin, and N4 pin are all electrically connected to the 1.2V power supply circuit, and the F12 pin and L5 pin are all electrically connected to the 2.5V power supply circuit; the B2 pin, B15 pin, C5 pin, C12 pin, D5 pin, D7 pin, D10 pin, E4 pin, E12 pin, E13 pin, F1 pin, F2 pin, G4 pin, G5 pin, H7 pin, H8 pin, H9 pin, H10 pin, H13 pin, H15 pin, H16 pin, J3 pin, The J7 pin, the J8 pin, the J9 pin, the J10 pin, the K4 pin, the K13 pin, the M4 pin, the M5 pin, the M13 pin, the N7 pin, the N10 pin, the P5 pin, the P12 pin, the R2 pin, and the R15 pin are all grounded; the FPGA chip (31) further comprises a plurality of capacitors which are sequentially connected in parallel; the twelfth pin, the thirteenth pin, the fourteenth pin, the fifteenth pin, the eighteenth pin, and the nineteenth pin of the subdivision chip are all connected to the K16 pin, the K15 pin, the L16 pin, the L15 pin, the N16 pin, the N1 The 5 pins are electrically connected one by one; the reset circuit includes a capacitor C10 and a resistor R2; the capacitor C10 is connected in series with the resistor R2, and the capacitor C10 is grounded; the resistor R2 is electrically connected to the 3.3V power supply circuit, and the capacitor C10 and the resistor R2 are both electrically connected to the M16 pin of the FPGA chip; the crystal oscillator circuit includes a crystal oscillator chip, four pins, a resistor R3 and a capacitor C9; the second pin is electrically connected to the fourth pin through the capacitor C9, the second pin is grounded, and the fourth pin is connected to the 3.3V power supply circuit; the third pin is electrically connected to the E16 pin of the FPGA chip through the resistor R3.

[0014] Furthermore, the data configuration circuit includes a chip for storing data and a JTAG interface for burning data; the input end of the chip for storing data is electrically connected to a 3.3V power supply circuit, and the input end of the JTAG interface for burning data is electrically connected to a 2.5V power supply circuit.

[0015] Furthermore, the data storage chip includes eight pins, a capacitor C11 and a resistor R7; the first pin is electrically connected to the D2 pin of the FPGA chip, the second pin is electrically connected to the H2 pin of the FPGA chip through the resistor R7, the sixth pin is electrically connected to the H1 pin of the FPGA chip, the fifth pin is electrically connected to the C1 pin of the FPGA chip, the third pin, the seventh pin and the eighth pin are all electrically connected to the 3.3V power supply circuit, the seventh pin and the eighth pin are connected in series with the capacitor C11 and grounded, and the fourth pin is grounded; the JTAG interface for burning data includes eight pins , resistor R4, resistor R5 and resistor R6; the first pin is electrically connected to resistor R4, the fifth pin is electrically connected to resistor R5; the seventh pin is electrically connected to resistor R6, the first pin, the second pin and the eighth pin are connected in parallel and grounded; the fourth pin, the fifth pin and the seventh pin are connected in parallel and electrically connected to a 2.5V power supply circuit; the first pin is electrically connected to the H3 pin of the FPGA chip, the third pin is electrically connected to the J4 pin of the FPGA chip (31), the fifth pin is electrically connected to the J5 pin of the FPGA chip, and the seventh pin is electrically connected to the H4 pin of the FPGA chip.

[0016] Further, the signal output circuit includes a differential chip and an output connector; the output end of the differential chip is electrically connected to the input end of the output connector, the input end of the differential chip is electrically connected to the 3.3V power supply circuit and the 5V power supply, the input end of the output connector is electrically connected to the 3.3V power supply circuit and the 5V power supply, and the input end of the differential chip is electrically connected to the output end of the FPGA chip; the differential chip includes sixteen pins, a capacitor C59 and a first indicator light circuit, the fourth pin and the sixteenth pin are both connected to the 5V power supply, the sixteenth pin is grounded through the capacitor C59, the eighth pin is grounded, and one end of the first indicator light circuit is electrically connected to the 3.3V power supply circuit The output connector comprises eight pins, an indicator light D1 and a second indicator light circuit. The first pin of the output connector is connected to a 5V power supply, and the first pin of the output connector is also grounded through the indicator light D1. The second pin, the third pin, the fourteenth pin, the thirteenth pin, the tenth pin and the eleventh pin of the differential chip are electrically connected to the third pin, the fourth pin, the fifth pin, the sixth pin, the seventh pin and the eighth pin of the output connector in a one-to-one correspondence. One end of the second indicator light circuit is electrically connected to a 3.3V power supply circuit, and the other end thereof is electrically connected to the T3 pin of the FPGA chip.

[0017] Compared with the prior art, the utility model has the following advantages:

[0018] (1) When the utility model is in use, the 3.3V power supply circuit, the 2.5V power supply circuit, the 1.2V power supply circuit, and the 5V power supply provide power for the entire device, the encoder module improves the high-precision feedback of the motor movement, the signal processing module collects and processes the signal of the encoder module, and the signal output circuit generates a differential signal from the synthesized signal and outputs it.

[0019] (2) The utility model does not require error measurement for each device and can be used directly after installation, which can greatly improve production efficiency and unify the processing of all motors. The accuracy is improved without increasing the burden on the driver, which makes the range of driver options wider when doing projects. The replacement of the driver at a later time will not affect the system accuracy. When key components are affected by external factors, such as the concentricity of the code disk is affected or the bearing is aged and worn, it will not affect the accuracy of the external output feedback.

[0020] (3) When the utility model is in use, two encoders are integrated into the same PCB. Users can also use external encoders according to actual conditions and connect the data to the device. The grating signal acquisition chip and the configuration chip acquire signals and transmit the signals to the segmentation chip. The segmentation chip converts the analog quantity into digital quantity and transmits it to the FPGA chip. The JTAG interface of the burning data is used to burn the program to the FPGA, and the program is stored on the chip that stores the data to ensure that the program is not lost when the power is off. The differential chip is used to generate the signal in the FPGA chip into a differential signal and output it from the output connector. [Drawings]

[0021] Figure 1 It is the structural principle block diagram of the utility model;

[0022] Figure 2 This is a structural principle block diagram of the encoder module of the utility model;

[0023] Figure 3 This is a circuit diagram of the power management module of the utility model;

[0024] Figure 4 The present invention is a circuit diagram of the encoder;

[0025] Figure 5 This is a circuit diagram of the FPGA chip of the utility model;

[0026] Figure 6 It is a circuit diagram of the reset circuit and the crystal oscillator circuit of the utility model;

[0027] Figure 7 A circuit diagram of the data configuration circuit of the utility model;

[0028] Figure 8 It is a circuit diagram of the signal output circuit of the utility model;

[0029] In the figure: 1. Power management module; 11. Power reminder circuit; 12. 3.3V power circuit; 13. 2.5V power circuit; 14. 1.2V power circuit; 2. Encoder module; 21. Encoder; 211. Grating signal acquisition chip; 212. Configuration chip; 213. Segmentation chip; 214. Capacitor and resistor module; 3. Signal processing module; 31. FPGA chip; 32. Reset circuit; 33. Crystal oscillator circuit; 34. Data configuration circuit; 341. Data storage chip; 342. JTAG interface for burning data; 4. Signal output circuit; 41. Differential chip; 42. Output connector. [Specific implementation method]

[0030] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments:

[0031] Example 1

[0032] Please refer to the instruction manual Figure 1-8 , a device using multiple encoders to improve feedback accuracy, including a power management module 1, the power management module 1 is connected to an encoder module 2, a signal processing module 3, and a signal output circuit 4; the encoder module 2 is connected to the signal processing module 3, and the signal processing module 3 is connected to the signal output circuit 4;

[0033] The power management module 1 includes a power reminder circuit 11, a 3.3V power circuit 12, a 2.5V power circuit 13 and a 1.2V power circuit 14. The power reminder circuit 11, the 3.3V power circuit 12, the 2.5V power circuit 13 and the 1.2V power circuit 14 are all connected to a 5V power supply. The 5V power supply is connected to the encoder module 2 and the signal output circuit 4. The 3.3V power circuit 12 is connected to the signal processing module 3 and the signal output circuit 4. The 2.5V power circuit 13 is connected to the signal processing module 3 and the signal output circuit 4. The 1.2V power circuit 14 is connected to the signal processing module 3.

[0034] When the utility model is in use, the 3.3V power supply circuit 12, the 2.5V power supply circuit 13 and the 1.2V power supply circuit 14, and the 5V power supply provide power for the entire device, the encoder module 2 improves the high-precision feedback of the motor movement, the signal processing module 3 collects and processes the signal of the encoder module 2, and the signal output circuit 4 generates a differential signal from the synthesized signal and outputs it; the utility model does not need to measure the error of each device, and can be used directly after installation, which can greatly improve the production efficiency and unify the processing of all motors. While the accuracy is improved, the burden on the driver does not increase. When doing a project, the driver has a wider range of choices, and the replacement of the driver at a later time does not affect the system accuracy. When key components are affected by external factors, such as the concentricity of the code disk is affected or the bearing is aged and worn, it does not affect the accuracy of the external output feedback.

[0035] Example 2

[0036] like Figure 1-8 As shown in the figure, as a preferred embodiment of the utility model, the power reminder circuit 11 includes a capacitor C1, a capacitor C5, a resistor R1 and a light emitting diode D2; the capacitor C1 is connected in parallel with the capacitor C5, and the capacitor C1 and the capacitor C5 are connected in series with the resistor R1 and the light emitting diode D2; one end of the capacitor C1 and one end of the capacitor C5 are electrically connected to the 5V power supply, and the other end of the capacitor C1 and the other end of the capacitor C5 are grounded; the 3.3V power supply circuit 12 includes a 3.3V power supply chip, a capacitor C2 and a capacitor C6; the fourth pin of the 3.3V power supply chip is connected to the capacitor C 2. Capacitors C6 are connected in parallel, capacitors C2 and C6 are connected in parallel, the first pin of the 3.3V power chip, one end of capacitor C2, and one end of capacitor C6 are all grounded; the third pin of the 3.3V power chip is electrically connected to the 5V power supply, and the other end of capacitor C2 and the other end of capacitor C6 both output 3.3V voltage; the 2.5V power circuit 13 and the 1.2V power circuit 14 are connected in the same way as the 3.3V power circuit 12, the 2.5V power circuit 13 outputs a 2.2V voltage, and the 1.2V power circuit 14 outputs a 1.2V voltage.

[0037] The encoder module 2 is an encoder 21; the encoder 21 is provided with two groups and the installation positions differ by 180 degrees; the encoder 21 comprises a grating signal acquisition chip 211, a configuration chip 212, a subdivision chip 213 and a capacitor and resistor module 214; the grating signal acquisition chip 211 and the configuration chip 212 are electrically connected to the subdivision chip 213, and the grating signal acquisition chip 211, the configuration chip 212 and the subdivision chip 213 are electrically connected to a 5V power supply; data complementation is performed according to a corresponding algorithm, thereby eliminating the error caused by the concentricity of the code disk during installation; and reducing the error caused by the unevenness of the code disk scale and the unevenness of the bearing ball, so as to achieve the purpose of improving the feedback accuracy; the subdivision chip 213 converts the analog quantity into a digital quantity.

[0038] The grating signal acquisition chip 211 includes an A-pin, an A+pin, a B+pin, a B-pin, a Z+pin, a Z-pin, an LED+pin, an LED-pin, a LEDR pin, a VCCA pin, a GNDA pin, a SEL1 pin, a SEL2 pin, a VCC pin and a GND pin; the A-pin, the A+pin, the Z+pin and the Z-pin are all electrically connected to the segmentation chip 213, the LED+pin is provided with two and is electrically connected to the 5V power supply, the LED-pin is electrically connected to the LEDR pin, the VCCA pin, the SEL2 pin and the VCC pin are all electrically connected to the 5V power supply, the SEL1 pin is provided with two and is grounded, and the GNDA pin and the GND pin are all grounded; the configuration chip 212 includes eight pins; the first pin, the second pin, the third pin, the fourth pin and the seventh pin are all grounded; the eighth pin is electrically connected to the 5V power supply, the fifth pin and the sixth pin are all The subdivision chip 213 is electrically connected to the subdivision chip 213, and the fifth pin and the sixth pin are both electrically connected to the 5V power supply through a resistor; the subdivision chip 213 includes twenty pins, the tenth pin and the eleventh pin of the subdivision chip 213 are respectively electrically connected to the fifth pin and the sixth pin of the configuration chip 212 in a one-to-one correspondence, the first pin is electrically connected to the Z+ pin, the second pin is electrically connected to the Z- pin, the third pin is electrically connected to the A+ pin, and the fourth pin is electrically connected to the A- pin. The first pin, the second pin, the third pin, the fourth pin, the seventh pin, the eighth pin, and the fifth pin are all connected in series with the capacitor and then in parallel, the fifth pin is connected in parallel with the sixth pin and then grounded, the seventh pin is electrically connected to B+, the eighth pin is electrically connected to B-, the twelfth pin, the thirteenth pin, the fourteenth pin, the fifteenth pin, the eighteenth pin, and the nineteenth pin are all connected to the signal processing module 3 through a resistor, the sixteenth pin is grounded, and the seventeenth pin is connected to the 5V power supply.

[0039] The encoder 21 also includes a capacitor-resistor module 214; the capacitor-resistor module 214 includes 6 capacitors and 2 resistors; the 6 capacitors are connected in series with the 2 resistors, the 6 capacitors are connected in parallel in sequence, one end of the 6 capacitors is grounded, and the other end thereof is electrically connected to a 5V power supply.

[0040] The signal processing module 3 includes an FPGA chip 31, a reset circuit 32, a crystal oscillator circuit 33 and a data configuration circuit 34; the input end of the FPGA chip 31 is electrically connected to the output ends of the two groups of encoders, the output end of the reset circuit 32, the output end of the crystal oscillator circuit 33, the 3.3V power supply circuit 12, the 2.5V power supply circuit 13, and the 1.2V power supply circuit 14, and the output end of the FPGA chip 31 is connected to the signal output circuit 4; the input ends of the reset circuit 32 and the crystal oscillator circuit 33 are electrically connected to the 3.3V power supply circuit 12, and the data configuration circuit 34 is electrically connected to the 3.3V power supply circuit 12 and the 2.5V power supply circuit 13.

[0041] The pins of the FPGA chip 31 are connected to the data configuration circuit 34, and the A1 pin, A16 pin, C4 pin, C7 pin, C10 pin, C13 pin, E3 pin, E14 pin, F4 pin, G3 pin, G14 pin, H5 pin, H12 pin, H14 pin, K3 pin, K14 pin, M3 pin, M14 pin, P4 pin, P7 pin, P10 pin, P13 pin, T1 pin, and T16 pin are all electrically connected to the 3.3V power supply circuit 12, and the D13 pin, G6 pin, G7 pin, G8 pin, and G9 pin are all electrically connected to the 3.3V power supply circuit 12. The pin, G10 pin, H6 pin, H11 pin, K7 pin, and N4 pin are all electrically connected to the 1.2V power supply circuit 14, and the F12 pin and L5 pin are all electrically connected to the 2.5V power supply circuit 13; the B2 pin, B15 pin, C5 pin, C12 pin, D5 pin, D7 pin, D10 pin, E4 pin, E12 pin, E13 pin, F1 pin, F2 pin, G4 pin, G5 pin, H7 pin, H8 pin, H9 pin, H10 pin, H13 pin, H15 pin, H16 pin, J3 pin, J7 pin, The J8 pin, the J9 pin, the J10 pin, the K4 pin, the K13 pin, the M4 pin, the M5 pin, the M13 pin, the N7 pin, the N10 pin, the P5 pin, the P12 pin, the R2 pin, and the R15 pin are all grounded. The FPGA chip 31 also includes multiple groups of capacitors which are connected in parallel in sequence. The twelfth pin, the thirteenth pin, the fourteenth pin, the fifteenth pin, the eighteenth pin, and the nineteenth pin of the subdivision chip 213 are all connected to the K16 pin, the K15 pin, the L16 pin, the L15 pin, the N16 pin, and the N15 pin of the FPGA chip 31 through resistors. One corresponding electrical connection; the reset circuit 32 includes a capacitor C10 and a resistor R2; the capacitor C10 is connected in series with the resistor R2, and the capacitor C10 is grounded; the resistor R2 is electrically connected to the 3.3V power supply circuit 12, and the capacitor C10 and the resistor R2 are both electrically connected to the M16 pin of the FPGA chip 31; the crystal oscillator circuit 33 includes a crystal oscillator chip, four pins, a resistor R3 and a capacitor C9; the second pin is electrically connected to the fourth pin through the capacitor C9, the second pin is grounded, and the fourth pin is connected to the 3.3V power supply circuit 12; the third pin is electrically connected to the E16 pin of the FPGA chip 31 through the resistor R3.

[0042] The data configuration circuit 34 includes a chip 341 for storing data and a JTAG interface 342 for burning data; the input end of the chip 341 for storing data is electrically connected to the 3.3V power supply circuit 12, and the input end of the JTAG interface 342 for burning data is electrically connected to the 2.5V power supply circuit 13.

[0043] The chip 341 storing data includes eight pins, a capacitor C11 and a resistor R7; the first pin is electrically connected to the D2 pin of the FPGA chip 31, the second pin is electrically connected to the H2 pin of the FPGA chip 31 through the resistor R7, the sixth pin is electrically connected to the H1 pin of the FPGA chip 31, the fifth pin is electrically connected to the C1 pin of the FPGA chip 31, the third pin, the seventh pin and the eighth pin are all electrically connected to the 3.3V power supply circuit 12, the seventh pin and the eighth pin are connected in series with the capacitor C11 and grounded, and the fourth pin is grounded; the JTAG interface 342 for burning data includes Eight pins, resistor R4, resistor R5 and resistor R6; the first pin is electrically connected to resistor R4, the fifth pin is electrically connected to resistor R5; the seventh pin is electrically connected to resistor R6, the first pin, the second pin and the eighth pin are connected in parallel and grounded; the fourth pin, the fifth pin and the seventh pin are connected in parallel and electrically connected to the 2.5V power supply circuit 13; the first pin is electrically connected to the H3 pin of the FPGA chip 31, the third pin is electrically connected to the J4 pin of the FPGA chip 31, the fifth pin is electrically connected to the J5 pin of the FPGA chip 31, and the seventh pin is electrically connected to the H4 pin of the FPGA chip 31.

[0044] When the utility model is in use, two encoders 21 are integrated into the same PCB. Users can also use external encoders according to actual conditions and connect data to the device. The grating signal acquisition chip 211 and the configuration chip 212 collect signals and transmit the signals to the segmentation chip 213. The segmentation chip 213 converts analog quantities into digital quantities and transmits them to the FPGA chip 31. The JTAG interface 342 for burning data burns the program to the FPGA, and stores the program on the chip 341 for storing data to ensure that the program is not lost when power is off.

[0045] Example 3

[0046] like Figure 1-8As shown in the figure, as a preferred embodiment of the utility model, the signal output circuit 4 includes a differential chip 41 and an output connector 42; the output end of the differential chip 41 is electrically connected to the input end of the output connector 42, the input end of the differential chip 41 is electrically connected to the 3.3V power supply circuit 12 and the 5V power supply, the input end of the output connector 42 is electrically connected to the 3.3V power supply circuit 12 and the 5V power supply, and the input end of the differential chip 41 is electrically connected to the output end of the FPGA chip 31; the differential chip 41 includes sixteen pins, a capacitor C59 and a first indicator light circuit, the fourth pin and the sixteenth pin are both connected to the 5V power supply, the sixteenth pin is grounded through the capacitor C59, the eighth pin is grounded, one end of the first indicator light circuit is connected to the 3.3V power supply circuit 12 and the 5V power supply. .3V power supply circuit 12, and the other end of which is electrically connected to pin D16 of FPGA chip 31; the output connector 42 includes eight pins, indicator light D1 and a second indicator light circuit, the first pin of the output connector 42 is connected to the 5V power supply, and the first pin of the output connector 42 is also grounded through the indicator light D1, the second pin, the third pin, the fourteenth pin, the thirteenth pin, the tenth pin, and the eleventh pin of the differential chip 41 are electrically connected to the third pin, the fourth pin, the fifth pin, the sixth pin, the seventh pin, and the eighth pin of the output connector 42 in a one-to-one correspondence, one end of the second indicator light circuit is electrically connected to the 3.3V power supply circuit 12, and the other end of the second indicator light circuit is electrically connected to pin T3 of FPGA chip 31.

[0047] When the present invention is in use, the differential chip 41 is used to generate a signal in the FPGA chip 31 into a differential signal and output it from the output connector 42 .

[0048] The contents not described in detail in this specification belong to the prior art known to professional and technical personnel in the field. The standard parts used can be purchased from the market, and special-shaped parts can be customized according to the records in the specification and drawings. The specific connection methods of each part adopt mature conventional means such as bolts, rivets, welding, etc. in the prior art. The machinery, parts and equipment adopt conventional models in the prior art, and the circuit connection adopts the conventional connection method in the prior art, which will not be described in detail here.

[0049] The present invention is not limited to the above-mentioned implementation modes, and any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be considered as equivalent replacement modes and shall be included in the protection scope of the present invention.

Claims

1. A device for improving feedback accuracy using multiple encoders, comprising a power management module (1), characterized in that: The power management module (1) is connected to an encoder module (2), a signal processing module (3), and a signal output circuit (4); the encoder module (2) is connected to the signal processing module (3), and the signal processing module (3) is connected to the signal output circuit (4); The power management module (1) comprises a power reminder circuit (11), a 3.3V power circuit (12), a 2.5V power circuit (13) and a 1.2V power circuit (14); the power reminder circuit (11), the 3.3V power circuit (12), the 2.5V power circuit (13) and the 1.2V power circuit (14) are all electrically connected to a 5V power supply; the 5V power supply is connected to the encoder module (2) and the signal output circuit (4); the 3.3V power circuit (12) is connected to the signal processing module (3) and the signal output circuit (4); the 2.5V power circuit (13) is connected to the signal processing module (3) and the signal output circuit (4); and the 1.2V power circuit (14) is connected to the signal processing module (3).

2. The device for improving feedback accuracy using multiple encoders according to claim 1, characterized in that: The power reminder circuit (11) comprises a capacitor C1, a capacitor C5, a resistor R1 and a light emitting diode D2; the capacitor C1 is connected in parallel with the capacitor C5, and the capacitor C1 and the capacitor C5 are connected in series with the resistor R1 and the light emitting diode D2; one end of the capacitor C1 and one end of the capacitor C5 are electrically connected to a 5V power supply, and the other end of the capacitor C1 and the other end of the capacitor C5 are grounded; the 3.3V power supply circuit (12) comprises a 3.3V power supply chip, a capacitor C2 and a capacitor C6; the fourth pin of the 3.3V power supply chip is connected in parallel with the capacitor C2 and the capacitor C6 , capacitor C2 and capacitor C6 are connected in parallel, the first pin of the 3.3V power chip, one end of the capacitor C2, and one end of the capacitor C6 are all grounded; the third pin of the 3.3V power chip is electrically connected to the 5V power supply, and the other end of the capacitor C2 and the other end of the capacitor C6 both output a 3.3V voltage; the 2.5V power circuit (13) and the 1.2V power circuit (14) are connected in the same manner as the 3.3V power circuit (12), the 2.5V power circuit (13) outputs a 2.2V voltage, and the 1.2V power circuit (14) outputs a 1.2V voltage.

3. The device for improving feedback accuracy using multiple encoders according to claim 2, characterized in that: The encoder module (2) is an encoder (21); the encoder (21) is provided with two groups and the installation positions differ by 180 degrees; the encoder (21) comprises a grating signal acquisition chip (211), a configuration chip (212), a subdivision chip (213) and a capacitance and resistance module (214); the grating signal acquisition chip (211) and the configuration chip (212) are all electrically connected to the subdivision chip (213), and the grating signal acquisition chip (211), the configuration chip (212) and the subdivision chip (213) are all electrically connected to a 5V power supply.

4. The device for improving feedback accuracy using multiple encoders according to claim 3, characterized in that: The grating signal acquisition chip (211) comprises an A-pin, an A+pin, a B+pin, a B-pin, a Z+pin, a Z-pin, an LED+pin, an LED-pin, an LEDR pin, a VCCA pin, a GNDA pin, a SEL1 pin, a SEL2 pin, a VCC pin and a GND pin; the A-pin, the A+pin, the Z+pin and the Z-pin are all electrically connected to the segmentation chip (213); two LED+pins are provided and are both electrically connected to a 5V power supply; the LED-pin is electrically connected to the LEDR pin; the VCCA pin, the SEL2 pin and the VCC pin are all electrically connected to the 5V power supply; two SEL1pins are provided and are both grounded; the GNDA pin and the GND pin are both grounded; the configuration chip (212) comprises eight pins; the first pin, the second pin, the third pin, the fourth pin and the seventh pin are all grounded; the eighth pin is electrically connected to the 5V power supply; the fifth pin and the sixth pin are all The subdivision chip (213) is electrically connected to the subdivision chip (213), and the fifth pin and the sixth pin are both electrically connected to a 5V power supply through a resistor; the subdivision chip (213) comprises twenty pins, the tenth pin and the eleventh pin of the subdivision chip (213) are respectively electrically connected to the fifth pin and the sixth pin of the configuration chip (212) in a one-to-one correspondence, the first pin is electrically connected to the Z+ pin, the second pin is electrically connected to the Z- pin, the third pin is electrically connected to the A+ pin, the fourth pin is electrically connected to the A- pin, the first pin, the second pin, the third pin, the fourth pin, the seventh pin, the eighth pin, and the fifth pin are all connected in series with a capacitor and then connected in parallel, the fifth pin is connected in parallel with the sixth pin and then grounded, the seventh pin is electrically connected to B+, and the eighth pin is electrically connected to B-; the signal processing module (3) is respectively connected to the twelfth pin, the thirteenth pin, the fourteenth pin, the fifteenth pin, the eighteenth pin, and the nineteenth pin through a resistor, the sixteenth pin is grounded, and the seventeenth pin is connected to a 5V power supply.

5. The device for improving feedback accuracy using multiple encoders according to claim 4, characterized in that: The encoder (21) further comprises a capacitor-resistor module (214); the capacitor-resistor module (214) comprises 6 capacitors and 2 resistors; the 6 capacitors are connected in series with the 2 resistors, the 6 capacitors are connected in parallel in sequence, one end of the 6 capacitors is grounded, and the other ends are electrically connected to a 5V power supply.

6. The device for improving feedback accuracy using multiple encoders according to claim 5, characterized in that: The signal processing module (3) comprises an FPGA chip (31), a reset circuit (32), a crystal oscillator circuit (33) and a data configuration circuit (34); the input end of the FPGA chip (31) is electrically connected to the output ends of the two sets of encoders, the output end of the reset circuit (32), the output end of the crystal oscillator circuit (33), the 3.3V power supply circuit (12), the 2.5V power supply circuit (13) and the 1.2V power supply circuit (14); the output end of the FPGA chip (31) is connected to the signal output circuit (4); the input ends of the reset circuit (32) and the crystal oscillator circuit (33) are electrically connected to the 3.3V power supply circuit (12), and the data configuration circuit (34) is electrically connected to the 3.3V power supply circuit (12) and the 2.5V power supply circuit (13).

7. The device for improving feedback accuracy using multiple encoders according to claim 6, characterized in that: The pins of the FPGA chip (31) are connected to a data configuration circuit (34); the 3.3V power supply circuit (12) is electrically connected to the A1 pin, A16 pin, C4 pin, C7 pin, C10 pin, C13 pin, E3 pin, E14 pin, F4 pin, G3 pin, G14 pin, H5 pin, H12 pin, H14 pin, K3 pin, K14 pin, M3 pin, M14 pin, P4 pin, P7 pin, P10 pin, P13 pin, T1 pin, and T16 pin, respectively; the 1.2V power supply circuit (14) is electrically connected to the D13 pin, G6 pin, and , G7 pin, G8 pin, G9 pin, G10 pin, H6 pin, H11 pin, K7 pin, and N4 pin are electrically connected, and the 2.5V power supply circuit (13) is electrically connected to the F12 pin and the L5 pin respectively; the B15 pin, C5 pin, C12 pin, D5 pin, D7 pin, D10 pin, E4 pin, E12 pin, E13 pin, F1 pin, F2 pin, G4 pin, G5 pin, H7 pin, H8 pin, H9 pin, H10 pin, H13 pin, H15 pin, H16 pin, J3 pin, J7 pin, The J8 pin, the J9 pin, the J10 pin, the K4 pin, the K13 pin, the M4 pin, the M5 pin, the M13 pin, the N7 pin, the N10 pin, the P5 pin, the P12 pin, the R2 pin, and the R15 pin are all grounded, and the FPGA chip (31) further comprises a plurality of capacitors which are sequentially connected in parallel; the twelfth pin, the thirteenth pin, the fourteenth pin, the fifteenth pin, the eighteenth pin, and the nineteenth pin of the subdivision chip (213) are all electrically connected to the K16 pin, the K15 pin, the L16 pin, the L15 pin, the N16 pin, and the N15 pin of the FPGA chip (31) through resistors in a one-to-one correspondence. ; The reset circuit (32) includes a capacitor C10 and a resistor R2; the capacitor C10 is connected in series with the resistor R2, and the capacitor C10 is grounded; the resistor R2 is electrically connected to the 3.3V power supply circuit (12), and the capacitor C10 and the resistor R2 are both electrically connected to the M16 pin of the FPGA chip (31); the crystal oscillator circuit (33) includes a crystal oscillator chip, four pins, a resistor R3 and a capacitor C9; the second pin is electrically connected to the fourth pin through the capacitor C9, the second pin is grounded, and the fourth pin is connected to the 3.3V power supply circuit (12); the third pin is electrically connected to the E16 pin of the FPGA chip (31) through the resistor R3.

8. The device for improving feedback accuracy using multiple encoders according to claim 7, characterized in that: The data configuration circuit (34) comprises a chip (341) for storing data and a JTAG interface (342) for burning data; the input end of the chip (341) for storing data is electrically connected to a 3.3V power supply circuit (12), and the input end of the JTAG interface (342) for burning data is electrically connected to a 2.5V power supply circuit (13).

9. The device for improving feedback accuracy using multiple encoders according to claim 8, characterized in that: The data storage chip (341) comprises eight pins, a capacitor C11 and a resistor R7; the first pin is electrically connected to the D2 pin of the FPGA chip (31), the second pin is electrically connected to the H2 pin of the FPGA chip (31) through the resistor R7, the sixth pin is electrically connected to the H1 pin of the FPGA chip (31), the fifth pin is electrically connected to the C1 pin of the FPGA chip (31), the third pin, the seventh pin and the eighth pin are all electrically connected to the 3.3V power supply circuit (12), the seventh pin and the eighth pin are both connected in series with the capacitor C11 and grounded, and the fourth pin is grounded; the JTAG interface (342) for burning data comprises The device comprises eight pins, a resistor R4, a resistor R5 and a resistor R6; the first pin is electrically connected to the resistor R4, the fifth pin is electrically connected to the resistor R5; the seventh pin is electrically connected to the resistor R6, the first pin, the second pin and the eighth pin are connected in parallel and then grounded; the fourth pin, the fifth pin and the seventh pin are connected in parallel and then electrically connected to a 2.5V power supply circuit (13); the first pin is electrically connected to the H3 pin of the FPGA chip (31), the third pin is electrically connected to the J4 pin of the FPGA chip (31), the fifth pin is electrically connected to the J5 pin of the FPGA chip (31), and the seventh pin is electrically connected to the H4 pin of the FPGA chip (31).

10. The device for improving feedback accuracy using multiple encoders according to claim 9, characterized in that: The signal output circuit (4) comprises a differential chip (41) and an output connector (42); the output end of the differential chip (41) is electrically connected to the input end of the output connector (42); the input end of the differential chip (41) is electrically connected to a 3.3V power supply circuit (12) and a 5V power supply; the input end of the output connector (42) is electrically connected to a 3.3V power supply circuit (12) and a 5V power supply; the input end of the differential chip (41) is electrically connected to the output end of the FPGA chip (31); the differential chip (41) comprises sixteen pins, a capacitor C59 and a first indicator light circuit; the fourth pin and the sixteenth pin are both connected to a 5V power supply; the sixteenth pin is grounded through the capacitor C59; the eighth pin is grounded; one end of the first indicator light circuit is electrically connected to the 3.3V power supply circuit (12); and the output connector (42) is electrically connected to the 3.3V power supply circuit (12); and the output connector (42) is electrically connected to the 5V power supply circuit (12); and the input end of the differential chip (41) is electrically connected to the output end of the FPGA chip (31); The output connector (42) comprises eight pins, an indicator light D1 and a second indicator light circuit. The first pin of the output connector (42) is connected to a 5V power supply. The first pin of the output connector (42) is also grounded through the indicator light D1. The second pin, the third pin, the fourteenth pin, the thirteenth pin, the tenth pin and the eleventh pin of the differential chip (41) are electrically connected to the third pin, the fourth pin, the fifth pin, the sixth pin, the seventh pin and the eighth pin of the output connector (42) in a one-to-one correspondence. One end of the second indicator light circuit is electrically connected to the 3.3V power supply circuit (12), and the other end thereof is electrically connected to the T3 pin of the FPGA chip (31).

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