Locking detection circuit of high-precision charge pump phase-locked loop
By designing a high-precision lock detection circuit in the phase-locked loop circuit, and using multi-layer detection and filtering mechanisms, the problem of insufficient detection accuracy of the traditional phase-locked loop at high frequencies is solved, and the performance and reliability of the system are significantly improved.
Patent Information
- Application Number
- CN202411551601.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-01
- Publication Date
- 2025-02-11
AI Technical Summary
The lock detection circuit of the traditional phase-locking loop has insufficient detection accuracy at high frequency, which is prone to misjudgment of the locking state due to slight phase jitter, affecting system performance.
A high-precision charge pump phase-locking loop lock detection circuit is designed, and a combination of the first detection circuit and the second detection circuit are adopted. The first detection loop initially detects the phase difference through the frequency phase detector and the flip-flop, and the second detection loop further detects through the pulse filtering loop, and uses a counter to ensure the locked state of the phase locked loop.
It improves the performance and reliability of phase-locked loops in high-frequency applications, reduces misjudgment, enhances the stability and anti-interference ability of the system, and ensures data synchronization and system performance optimization.
Smart Images
Figure CN119420349A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a lock detection circuit of a high-precision charge pump phase-locked loop. Background Art
[0002] Phase-locked loops (PLLs) play an important role in electronic devices such as serial communications and RF wireless transceivers. Charge pump phase-locked loops are popular because of their easy integration, low power consumption, and high performance. However, with the continuous increase in the frequency of the lock and the phase frequency detector (PFD), the traditional lock detection circuit is unable to meet the detection accuracy. At high frequencies, even a small phase jitter may cause the output signal to be unstable, which may be misjudged as normal lock, thus affecting the overall performance of the system. Summary of the invention
[0003] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to propose a lock detection circuit of a high-precision charge pump phase-locked loop, which adopts the following technical solution:
[0004] A lock detection circuit of a high-precision charge pump phase-locked loop, comprising a first detection circuit, a phase frequency detector, a third trigger D3 and a fourth trigger D4, wherein the input end of the phase frequency detector 11 receives a reference signal rclk and an input signal nclk, the input pin 3D of the third trigger D3 receives a first output signal up of the phase frequency detector 11, and the clock pin ck3 receives the input signal nclk; the input pin of the fourth trigger D4 receives a second output signal down of the phase frequency detector 11, and the clock pin ck4 receives the reference signal rclk; the positive output ends of the third trigger D3 and the fourth trigger D4 are connected to an OR gate OR1, the output end of the OR gate OR1 is connected to a counter and its reset pin RCK, and the first detection circuit is used to preliminarily detect whether the phase difference between the reference signal rclk and the input signal nclk exceeds a first preset value;
[0005] A second detection circuit, the second detection circuit comprising a pulse filtering circuit, for further detecting whether a phase difference between the reference signal rclk and the input signal nclk exceeds a second preset value;
[0006] The counter is connected to the output end of the first detection loop and the second detection loop. When the phase difference between the reference signal rclk and the input signal nclk exceeds the first preset value or the second preset value, the counter is reset, otherwise the counter counts normally; when the count value of the counter reaches the preset value, it indicates that the phase-locked loop is in a locked state.
[0007] As a further improvement, the input pins of the third trigger D3 and the fourth trigger D4 are provided with a second delay unit.
[0008] As a further improvement, the first output signal up and the second output signal down are connected to the pulse filtering loop through an OR gate 2 OR2, and the OR gate 2 OR2 is also connected to the input end of the counter.
[0009] As a further improvement, the pulse filtering circuit includes an even-numbered inverter and a current control circuit, and the input end of the current control circuit is connected to the second delay unit for adjusting the discharge current control output of the first-stage inverter to filter the narrow pulse signal.
[0010] As a further improvement, the time delay of the second delay unit is adjustable, and its adjustment range matches the filtering pulse width of the pulse filtering loop.
[0011] As a further improvement, it also includes an OR gate OR3, the output end of the OR gate OR1, the output end of the OR gate OR2 and the output end of the counter are connected to the input end of the OR gate OR3, and the output end of the OR gate OR3 is connected to the input end of the counter.
[0012] As a further improvement, the above counter is provided with a control signal pin for adjusting the counter count.
[0013] Compared with the prior art, the present invention has the following beneficial effects:
[0014] First, the present invention preliminarily detects the phase difference between the reference signal rclk and the input signal nclk through the first detection loop. When the phase difference between the reference signal rclk and the input signal nclk exceeds the first preset value, the reset signal is triggered to reset the counter. The loop can quickly detect large frequency deviations, reduce misjudgments, increase detection speed, and reduce system complexity. Under the condition of low operating frequency, a relatively accurate lock detection circuit can be realized, which is very easy to realize and has low power consumption and cost. At the same time, it can also work in conjunction with the second detection loop to achieve higher-precision lock detection. This design significantly improves the performance and reliability of the charge pump phase-locked loop in high-frequency applications.
[0015] Secondly, the present invention also includes a second detection loop, wherein the pulse filtering circuit includes a plurality of inverters connected in series, and the discharge speed of the output node is controlled by adjusting the discharge current of the first-stage inverter, thereby realizing effective filtering of narrow pulses. When the phase difference between rclk and nclk is small enough, that is, the pulse width is small enough, it will be filtered out by the pulse filtering circuit, and no reset signal will be generated to reset the counter. The counter keeps counting until the count value reaches a preset value, indicating that the phase-locked loop is in a locked state. Based on the rough detection of the first detection loop, the second detection loop further accurately detects and confirms the locked state of the phase-locked loop, ensuring that the system works stably and accurately at high frequencies, and improving the performance and reliability of the charge pump phase-locked loop in high-frequency applications.
[0016] Thirdly, in the present invention, a counter is used to ensure the locking state of the phase-locked loop. The lock can only be indicated when the counter reaches the set timing value, which can reduce misjudgment caused by instantaneous fluctuations or noise, improve the stability and anti-interference ability of the system, ensure data synchronization and optimization of system performance, and avoid the phase-locked loop from frequently switching between locking and unlocking, thereby enhancing the reliability and overall performance of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0018] Figure 1 It is a schematic diagram of the circuit structure of the present invention;
[0019] Figure 2 It is a circuit diagram of the pulse filtering circuit in the present invention;
[0020] Figure 3 1 is a waveform diagram of each signal in an embodiment of the present invention;
[0021] Figure 4 is a waveform diagram of each signal in another case of an embodiment of the present invention;
[0022] Figure 5 4 is a waveform diagram of each signal under ideal conditions of the present invention. DETAILED DESCRIPTION
[0023] In order to facilitate understanding by those skilled in the art, the structure of the present invention is further described in detail with reference to the embodiments in conjunction with the accompanying drawings:
[0024] In the description of the present invention, the terms “first” and “second” are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features, and therefore cannot be understood as limiting the present invention.
[0025] like Figure 1 As shown, the present application provides a lock detection circuit of a high-precision charge pump phase-locked loop, including a first detection circuit 1, a second detection circuit and a counter, wherein the first detection circuit 1 is used to roughly detect the phase difference between a reference signal rclk and an input signal nclk. Based on the rough detection of the first detection circuit 1, the second detection circuit further accurately detects and confirms the lock state of the phase-locked loop, ensuring that the system works stably and accurately at high frequencies, thereby improving the performance and reliability of the charge pump phase-locked loop in high-frequency applications.
[0026] like Figure 1 As shown, the first detection loop 1 includes a frequency detector 11, a third trigger D3 and a fourth trigger D4, the input end of the frequency detector 11 receives a reference signal rclk and an input signal nclk, the input pin 3D of the third trigger D3 receives a first output signal up of the frequency detector 11, and the clock pin ck3 receives the input signal nclk; the input pin of the fourth trigger D4 receives a second output signal down of the frequency detector 11, and the clock pin ck4 receives the reference signal rclk; the positive output ends of the third trigger D3 and the fourth trigger D4 output a third output signal tr_up and a fourth output signal tr_down respectively, and the third output signal tr_up and the fourth output signal tr_down are connected to an OR gate OR1, and the output end of the OR gate OR1 is connected to a counter and its reset pin RCK.
[0027] The first detection loop 1 is used for preliminarily detecting whether the phase difference between the reference signal rclk and the input signal nclk exceeds a first preset value.
[0028] like Figure 1 As shown, the internal structure of the frequency detector 11 is the prior art, including a first trigger D1 and a second trigger D2, the input pin D1 of the first trigger D1 and the input pin D2 of the second trigger D2 are both connected to a high level, the clock pin ck1 of the first trigger D1 inputs a reference signal rclk, and the clock pin ck2 of the second trigger D2 inputs an input signal nclk, which comes from the output signal of the frequency divider. The positive output pin Q1 of the first trigger D1 outputs a first output signal up, and the positive output pin Q2 of the second trigger D2 outputs a second output signal down, and the first output signal up and the second output signal down are respectively connected to the input pins of the fourth trigger D4 and the third trigger D3, and are connected to the reset pins of the first trigger D1 and the second trigger D2 through an AND gate AND1.
[0029] In a specific embodiment, similar to a traditional phase-locked loop system, a reference chip needs to be selected. In a laboratory environment, a charge pump phase-locked loop chip with good performance is tested and selected as a reference chip using equipment such as a spectrum analyzer. Its output signal is used as the above-mentioned reference signal nclk, which will not be repeated here.
[0030] like Figure 1 As shown, the output end of AND gate AND1 is provided with a first delay unit, and the input pin 3D of the third trigger D3 and the input pin 4D of the fourth trigger D4 are provided with a second delay unit 12. The purpose is to improve the stability and reliability of the system, which will not be repeated here.
[0031] like Figure 1 As shown, the reset pins of the third trigger D3 and the fourth trigger D4 are connected to a reset key.
[0032] like Figure 1-Figure 2 As shown, the second detection circuit 2 includes a pulse filtering circuit 21, which is used to further detect whether the phase difference between the reference signal rclk and the input signal nclk exceeds a second preset value.
[0033] like Figure 1-Figure 2 As shown, the pulse filtering circuit includes a multi-stage inverter and a current control loop 211, wherein the multi-stage inverter is an even-numbered inverter to ensure that the filtered signal has the same polarity as the initial signal. The output of the frequency detector 11, i.e., the first output signal up and the second output signal down, are connected to the pulse filtering loop 21 through the OR gate OR2, and the output end of the OR gate OR2 is also connected to the input end of the counter.
[0034] like Figure 1 As shown, it also includes an OR gate OR3, the output end of the OR gate OR1, the output end of the OR gate OR2 and the output end of the counter are connected to the input end of the OR gate OR3, and the output end of the OR gate OR3 is connected to the input end of the counter.
[0035] like Figure 1 As shown, the counter is connected to the output end of the first detection loop 1 and the second detection loop 2. When the phase difference between the reference signal (rclk) and the input signal (nclk) exceeds the first preset value or the second preset value, the counter is reset, otherwise the counter counts normally; when the count value of the counter reaches the preset value, it indicates that the phase-locked loop is in a locked state. The counter is also provided with a control signal pin for adjusting the counter count.
[0036] The following will explain the working conditions of the lock detection circuit in conjunction with some signal waveform diagrams of certain situations:
[0037] (1) When the reference signal rclk and the input signal nclk are both no signal or low level, the cki signal output from the output end of the OR gate OR2 will not generate a pulse, and the other inputs of the OR gate OR3 are also no signal or low level, so the counter will not count, and its output signal locked outputs a low level, and the circuit indicates that it is not locked;
[0038] (2) When the reference signal rclk has a signal input, but the input signal nclk has no signal input, the reference signal rclk inputs a high level, the first output signal up outputs a high level, while the input signal nclk has no signal, the second output signal down outputs a low level, and no reset signal can be generated to pull down the first output signal up. Therefore, the first output signal up is passed through the OR gate three OR3 to make the cki signal output a high level, the counter counts once, and the circuit indicates that it is not locked;
[0039] (3) When the reference signal rclk has no signal input, but the input signal nclk has a signal input, the operation of the detection circuit is similar to the process described in (2), and the circuit indicates that it is not locked, which will not be repeated here;
[0040] (4) When both the reference signal rclk and the input signal nclk have signal input, and the phase of the input signal nclk lags behind the reference signal rclk, that is, Figure 2-Figure 3 The signal waveform state shown will have the following working conditions:
[0041] (4a) Figure 2 As shown, if the phase difference between the reference signal rclk and the input signal nclk is small, as the reference signal rclk and the input signal nclk rise, after a short delay, the first output signal up and the second output signal down will be pulled high successively, and the first output signal up will generate the first delay signal up_dl after passing through the second delay unit 12, and the second output signal down will also generate the second delay signal down_dl after passing through the second delay unit 12. If the rise of the input signal nclk occurs before the rise of the first delay signal up_dl, that is, before the input pin 3D of the third trigger D3 receives the rising signal, the clock pin ck3 has received the rising signal, then the third output signal tr_up keeps outputting a low level signal, and no reset operation is generated on the counter, and the counter keeps counting normally;
[0042] (4b) Figure 3As shown, if the phase difference between the reference signal rclk and the input signal nclk is large, the signal transmission is roughly the same as described in (4a), except that the input signal nclk rises after the first delay signal up_dl rises, that is, before the input pin 3D of the third trigger D3 receives the rising signal, the clock pin ck3 has not received the rising signal. Then, after the clock pin ck3 triggers the rising edge, the third output signal tr_up outputs a high level, triggering the counter to reset.
[0043] It should be pointed out that the above description does not explicitly state that the delays caused by the first delay unit or the second delay unit 12 are all delays caused by the components themselves, including inherent delays, propagation delays, etc., which are inevitable situations in integrated circuit design, and the following similar situations will not be repeated.
[0044] It should be emphasized that through Figure 2 and Figure 3 The circuit operation description is not difficult to understand. The first preset value is the phase difference between the input signal nclk and the rising edge of the reference signal rclk before the first delay signal up_dl rises. The first preset value can be adjusted by adjusting the second delay unit 12.
[0045] In the case of a relatively low operating frequency, a relatively accurate detection and locking circuit can be obtained only through the first detection loop 1, which has lower power consumption and implementation cost.
[0046] However, when the operating frequency is high, a slight phase deviation between the two input signals of the phase frequency detector 11 will cause abnormal jitter of the output high-frequency signal, so a second test loop is required for further detection.
[0047] like Figure 2 The pulse filtering circuit shown includes a four-stage inverter and a current control loop 211. The current control loop 211 is a circuit network composed of multiple NMOS and PMOS transistors. The discharge current is controlled by adjusting the first delay unit and the second delay unit 12, thereby affecting the discharge speed of the output node of the first-stage inverter 212. This structure allows the circuit to adjust the discharge speed according to the width of the input pulse, ensuring that only pulses with sufficient width can pass through the first-stage inverter 212 and be transmitted to the subsequent inverter, while narrower pulses will be filtered out due to the slow discharge speed. For example, if the high-level pulse width is too narrow, when the output node of the first-stage inverter 212 has not yet dropped to the voltage that causes the second-stage inverter to flip the phase, the input becomes a low level again, and the output of the first-stage inverter 212 is pulled up again, causing the subsequent inverter to be unable to flip, thereby achieving filtering of narrow pulses. Those skilled in the art should be able to design and debug the current control loop 211 according to requirements, so the circuit structure is not described in detail here.
[0048] Combination Figure 1 and Figure 4 Ideally, the rising edges of the reference signal rclk and the input signal nclk are aligned, and the pulse width of the signal cki is determined by the AND gate AND1 and the first delay unit. For ease of description, we define the pulse width of the signal cki as τ. In non-ideal situations, the width of the signal cki will increase with the phase difference between the reference signal rclk and the input signal nclk. Therefore, it is only necessary to set the filter pulse width of the above-mentioned pulse filter circuit to be close to τ to achieve theoretical precise alignment. The actual degree of alignment also depends on the resolution of τ that can be set and the influence of PVT. Through the above-mentioned circuit and setting, it is ensured that when the phase difference between the reference signal rclk and the input signal is less than a certain value, the counter maintains normal counting. The phase difference between the above-mentioned reference signal rclk and the input signal is less than a certain value, which is the second preset value.
[0049] It should be understood that by adjusting the first delay unit and the second delay unit 12, the current discharge speed is adjusted to be equivalent to adjusting the filter pulse width. The process of adjusting the pulse width to be close to τ is to adjust the second preset value. Those skilled in the art should be able to reasonably set the second preset value according to the locking requirements and considering the component parameters, and no limitation is made here.
[0050] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A lock detection circuit for a high-precision charge pump phase-locked loop, characterized in that: include A first detection circuit (1) comprises a frequency detector (11), a third trigger (D3) and a fourth trigger (D4); the input end of the frequency detector (11) receives a reference signal (rclk) and an input signal (nclk); the input pin (3D) of the third trigger (D3) receives a first output signal (up) of the frequency detector (11), and the clock pin (ck3) receives the input signal (nclk); the input pin of the fourth trigger (D4) receives a second output signal (down) of the frequency detector (11), and the clock pin (ck4) receives the reference signal (rclk); the positive output ends of the third trigger (D3) and the fourth trigger (D4) are connected to an OR gate 1 (OR1), and the output end of the OR gate 1 (OR1) is connected to a counter and its reset pin (RCK); the first detection circuit (1) is used to preliminarily detect whether the phase difference between the reference signal (rclk) and the input signal (nclk) exceeds a first preset value; A second detection circuit (2), the second detection circuit comprising a pulse filtering circuit (21), used to further detect whether the phase difference between the reference signal (rclk) and the input signal (nclk) exceeds a second preset value; A counter is connected to the output ends of the first detection loop (1) and the second detection loop (2); when the phase difference between a reference signal (rclk) and an input signal (nclk) exceeds a first preset value or a second preset value, the counter is reset; otherwise, the counter counts normally; when the count value of the counter reaches a preset value, it indicates that the phase-locked loop is in a locked state.
2. The lock detection circuit of a high-precision charge pump phase-locked loop according to claim 1, characterized in that: The input pins of the third trigger (D3) and the fourth trigger (D4) are provided with a second delay unit (12).
3. The lock detection circuit of a high-precision charge pump phase-locked loop as claimed in claim 2, characterized in that: The first output signal (up) and the second output signal (down) are connected to the pulse filtering loop through OR gate 2 (OR2), and the OR gate 2 (OR2) is also connected to the input end of the counter.
4. The lock detection circuit of a high-precision charge pump phase-locked loop as claimed in claim 3, characterized in that: The pulse filtering circuit (21) comprises an even-numbered inverter and a current control circuit (211), wherein the input end of the current control circuit (211) is connected to the second delay unit (12) and is used to adjust the discharge current of the first-stage inverter (212) to control the discharge speed of the output so as to filter the narrow pulse signal.
5. The lock detection circuit of a high-precision charge pump phase-locked loop as claimed in claim 4, characterized in that: The time delay of the second delay unit (12) is adjustable, and its adjustment range matches the filtering pulse width of the pulse filtering circuit (21).
6. The lock detection circuit of a high-precision charge pump phase-locked loop as claimed in claim 3, characterized in that: It also includes an OR gate three (OR3), wherein the output end of the OR gate one (OR1), the output end of the OR gate two (OR2) and the output end of the counter are connected to the input end of the OR gate three (OR3), and the output end of the OR gate three (OR3) is connected to the input end of the counter.
7. A lock detection circuit for a high-precision charge pump phase-locked loop as claimed in claim 6, characterized in that: The counter is provided with a control signal pin for adjusting the counter count.