A thermal noise cancellation high speed pipelined successive approximation hybrid analog-to-digital converter

Abstract

The application discloses a kind of thermal noise elimination high-speed pipeline successive approximation hybrid analog-digital converter, including first sampling branch and second sampling branch, wherein, first sampling branch is bottom plate sampling, for after sampling clock signal becomes low level predetermined time, MSB bit of the input sampling signal is quantized;Second sampling branch is top plate sampling, for directly quantizing MSB bit of the input sampling signal after sampling clock signal becomes low, and first sampling branch is also used for after second sampling branch completes MSB bit quantization, according to the quantization result of second sampling branch, the remaining bit number of sampling signal is quantized.The application solves the amplitude attenuation problem caused by bottom plate technology and the problem of insufficient time utilization, while solving the trade-off problem between residual thermal noise average power and power consumption.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a high-speed pipeline successive approximation hybrid analog-to-digital converter with thermal noise cancellation. Background Technology

[0002] Pipelined-SAR ADCs (hybrid analog-to-digital converters) are currently the mainstream architecture in the field of high-speed, high-precision ADCs. However, the thermal noise introduced by the sampling switch has always been a key factor limiting performance improvement in this field. The average power of sampling thermal noise is related to the size of the sampling capacitor. The larger the sampling capacitor, the lower the average power of thermal noise, but the design difficulty also increases due to the increased load on the sampling switch. Conversely, the smaller the sampling capacitor, the lower the bandwidth requirement of the sampling switch, but the average power of the noise will increase.

[0003] The proposed thermal noise cancellation technique for Pipelined-SAR ADCs works by sampling the signal using bottom-plate sampling technology and storing the thermal noise introduced by the sampling switch as an offset in the offset capacitor between the first and second stages of the operational amplifier through a specific timing sequence. Due to this offset storage technique, the multiplicative digital-to-analog converter (MDAC) amplifies only the margin information and excludes the thermal noise introduced by the sampling switch.

[0004] The application of thermal noise cancellation technology is inseparable from bottom plate sampling technology, but this technology has two problems: The first problem is that bottom plate sampling technology is affected by the parasitic capacitance and feedback capacitance at the upper plate of the sampling capacitor, which causes the amplitude of the acquired signal to be attenuated, losing some fundamental energy, resulting in a decrease in the effective number of bits and signal-to-noise ratio of the ADC; The second problem is that compared with top plate sampling, bottom plate sampling technology undergoes a signal flipping process and requantization after sampling, which consumes a certain amount of time. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a thermal noise-canceling high-speed pipelined successive approximation hybrid analog-to-digital converter. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] This invention provides a thermal noise-cancelled high-speed pipelined successive approximation hybrid analog-to-digital converter, comprising a first sampling branch and a second sampling branch, wherein...

[0007] The first sampling branch is a bottom plate sampling, used to quantize the MSB bits of the input sampling signal after the sampling clock signal goes low for a predetermined time;

[0008] The second sampling branch is a top plate sampling branch, which is used to quantize the MSB bits of the input sampling signal directly after the sampling clock signal goes low. The first sampling branch also quantizes the remaining bits of the sampling signal according to the quantization result of the second sampling branch after the MSB bit quantization is completed by the second sampling branch.

[0009] In one embodiment of the present invention, the first sampling branch includes a capacitor array C. S1N Capacitor array C S1P Operational amplifier A1, Operational amplifier A 2,3 Offset capacitor C N1 Offset capacitor C N2 Feedback capacitor C F1 Feedback capacitor C F2 Switches K1, K2, K3, K4, K5, K6, K7, K8, K9, K10, K17, and K18, wherein...

[0010] The switch K1 and the capacitor array C S1P Series connected at the first differential input terminal V IP With the first input terminal V of the operational amplifier A1 IP1 Between the switch K2 and the capacitor array C S1n Series connected to the second differential input terminal V IN With the second input terminal V of the operational amplifier A1 IN1 Between, the first differential input terminal V IP and the second differential input terminal V IN Used for inputting sampling signals;

[0011] The offset capacitor C N1 Connected to the first output terminal V of the operational amplifier A1 OP1 With the operational amplifier A 2,3 The first input terminal V IP2 Between, the offset capacitor C N2 Connected to the second output terminal V of the operational amplifier A1 ON1 With the operational amplifier A 2,3 The second input terminal V IN2 between;

[0012] The feedback capacitor C F1 The switch K5 is connected in series with the first input terminal V of the operational amplifier A1. IP1 With the operational amplifier A 2,3 The second output terminal V ON2 Between, the feedback capacitor C F2The switch K10 is connected in series with the second input terminal V of the operational amplifier A1. IN2 With the operational amplifier A 2,3 First output terminal V OP2 between;

[0013] The first terminal of the switch K3 is connected to the first differential input terminal V. IP The second terminal is connected to the feedback capacitor C. F1 Between switch K4 and switch K5, the first terminal of switch K4 is connected to the common-mode voltage input terminal V. CM The second terminal is connected to the feedback capacitor C. F1 Between the switch K5 and the switch K8; the first terminal of the switch K8 is connected to the second differential input terminal V. IN The second terminal is connected to the feedback capacitor C. F2 Between switch K10 and switch K9, the first terminal of switch K9 is connected to the common-mode voltage input terminal V. CM The second terminal is connected to the feedback capacitor C. F2 Between and the switch K10;

[0014] The switch K6 is connected to the common-mode voltage input terminal V. CM With the operational amplifier A 2,3 The first input terminal V IP2 Between, the switch K7 is connected to the common-mode voltage input terminal V. CM With the operational amplifier A 2,3 The second input terminal V IN2 between;

[0015] The switch K17 is connected to the common-mode voltage input terminal V. CM With the first input terminal V of the operational amplifier A1 IP1 Between, the switch K18 is connected to the common-mode voltage input terminal V. CM With the second input terminal V of the operational amplifier A1 IN1 between;

[0016] Switches K1, K2, K3, K8, K6, and K7 are all controlled by the sampling clock signal CLKS; switches K4 and K9 are both controlled by the clock signal φ1; switches K5 and K10 are both controlled by the clock signal AMP; and switches K17 and K18 are both controlled by the clock signal CLKSE.

[0017] In one embodiment of the present invention, the first sampling branch further includes switches K11 and K12, wherein,

[0018] The switch K11 is connected to the operational amplifier A. 2,3 The second output terminal V ON2 Between the first input terminal of the subsequent ADC; the switch K12 is connected to the operational amplifier A. 2,3 First output terminal V OP2 Between the second input terminal of the subsequent ADC;

[0019] Both switch K11 and switch K12 are controlled by the clock signal AMP.

[0020] In one embodiment of the present invention, when the sampling clock signal CLKS goes low, the clock signal φ1 goes high, and when the clock signal φ1 goes low, the clock signal AMP goes high.

[0021] The sum of the duration of the clock signal φ1 being at a high level and the duration of the clock signal AMP being at a high level is equal to the duration of the sampling clock signal CLKS being at a low level.

[0022] The clock signal CLKSE and the sampling clock signal CLKS are triggered to a high level simultaneously, and the high level duration of the clock signal CLKSE is less than the predetermined high level duration of the sampling clock signal CLKS.

[0023] In one embodiment of the present invention, the second sampling branch includes comparator COM1, comparator COM2, and capacitor array C. S2N Capacitor array C S2P Switches K13, K14, K15, and K16; and a logic control module, wherein...

[0024] The switch K13 is connected to the operational amplifier A. 2,3 The first input terminal V IP2 The switch K14 is connected between the first input terminal of the comparator COM1 and the operational amplifier A. 2,3 The second input terminal V IN2 Between the second input terminal of the comparator COM1;

[0025] The switch K15 is connected to the first differential input terminal V. IP The switch K16 is connected between the first input terminal of the comparator COM2 and the second differential input terminal V. IN Between the second input terminal of the comparator COM2;

[0026] The capacitor array C S2P The capacitor array C is connected between the ground terminal and the first input terminal of the comparator COM2. S2NThe output of comparator COM1 is connected between the ground terminal and the second input terminal of comparator COM2, and the output terminal of comparator COM1 is connected to the first input terminal of the logic control module. The output terminal of comparator COM2 is connected to the second input terminal of the logic control module.

[0027] The output of the logic control module is connected to the capacitor array C. S1N and the capacitor array C S1P It is used to change the capacitor array C based on the output results of the comparators COM1 and COM2. S1N and the capacitor array C S1P The voltage connected to the next stage board corresponding to the capacitor;

[0028] The switches K13, K14, K15 and K16 are all controlled by the sampling clock signal CLKS.

[0029] In one embodiment of the present invention, the operational amplifier A1 includes MOSFETs M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, and M12, a common-mode feedback circuit CMFB, switch K19, and switch K20, wherein...

[0030] The source of MOSFET M1, the source of MOSFET M2, the source of MOSFET M3, and the source of MOSFET M4 are all connected to the power supply terminal VDD. The drain of MOSFET M1, the drain of MOSFET M2, the drain of MOSFET M3, the drain of MOSFET M4, and the source of MOSFET M5 are all connected to the source of MOSFET M6.

[0031] The gate of the MOSFET M5 is connected to the gate of the MOSFET M7, and serves as the first input terminal V of the operational amplifier A1. IP1 The drain of MOSFET M5 is connected to the drain of MOSFET M7, and serves as the second output terminal V of operational amplifier A1. ON1 The gate of the MOS transistor M6 is connected to the gate of the MOS transistor M8, and serves as the second input terminal V of the operational amplifier A1. IN1 The drain of MOSFET M6 is connected to the drain of MOSFET M8, and serves as the first output terminal V of operational amplifier A1. OP1 ;

[0032] The source of MOSFET M7 is connected to the source of MOSFET M8, the drain of MOSFET M9, the drain of MOSFET M10, the drain of MOSFET M11, and the drain of MOSFET M12; the sources of MOSFET M9, M10, M11, and M12 are all connected to the ground terminal.

[0033] The gates of both MOSFET M1 and MOSFET M9 are connected to the second output terminal V of operational amplifier A1. ON1 The gates of MOS transistor M4 and MOS transistor M12 are both connected to the first output terminal V of operational amplifier A1. OP1 ;

[0034] The gate input clock signal φ2B of the MOS transistor M3 and the gate input clock signal φ2 of the MOS transistor M11;

[0035] The two input terminals of the common-mode feedback circuit CMFB are respectively connected to the operational amplifier A. 2,3 First output terminal V OP2 Second output terminal V ON2 The first terminal of the switch K19 is connected to the common-mode voltage input terminal V. CM The second end is connected to the gate of the MOS transistor M2 and the gate of the MOS transistor M10; the first end of the switch K20 is connected to the output of the common-mode feedback circuit CMFB, and the second end is connected to the gate of the MOS transistor M2.

[0036] The switch K19 is controlled by the clock signal CLKS, and the switch K20 is controlled by the clock signal CLKSB.

[0037] In one embodiment of the present invention, the clock signal φ2B and the clock signal φ2 are opposite signals, and the clock signal CLKS and the clock signal CLKSB are opposite signals.

[0038] In one embodiment of the present invention, the operational amplifier A 2,3 This includes MOSFETs M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, M23, M24, M25, M26, M27, and M28, as well as switches S1 and S2.

[0039] The sources of MOSFETs M13, M17, M21, and M25 are all connected to the power supply terminal VDD. The drain of MOSFET M13, the gate of MOSFET M14, the gate of MOSFET M15, and the drain of MOSFET M16 are all connected to the operational amplifier A. 2,3 The second output terminal V ON2 The gate of MOSFET M13 is connected to the drain of MOSFET M14, the drain of MOSFET M17, the drain of MOSFET M19, and the source of MOSFET M18; the gate of MOSFET M16 is connected to the drain of MOSFET M15, the drain of MOSFET M20, the drain of MOSFET M18, and the source of MOSFET M19.

[0040] The sources of both MOSFET M14 and MOSFET M15 are connected to the common-mode voltage input terminal V. CM The gate of the MOS transistor M17 is connected to the gate of the MOS transistor M20 and serves as the operational amplifier A. 2,3 The second input terminal V IN2 The first terminal of the switch S1 is connected to the common-mode voltage input terminal V. CM The second terminal is connected to the gate of the MOS transistor M17, and the gate of the MOS transistor M18 is input with a first bias voltage V. BL The gate input of the MOS transistor M19 is a second bias voltage V. BH The sources of the MOSFETs M16, M20, M24, and M28 are all connected to the ground terminal GND.

[0041] The drain of MOSFET M25, the gate of MOSFET M26, the gate of MOSFET M27, and the drain of MOSFET M28 are all connected to operational amplifier A. 2,3 First output terminal V OP2 The gate of MOSFET M25 is connected to the drain of MOSFET M26, the drain of MOSFET M21, the drain of MOSFET M22, and the source of MOSFET M23; the gate of MOSFET M28 is connected to the drain of MOSFET M27, the drain of MOSFET M23, the drain of MOSFET M24, and the source of MOSFET M22.

[0042] The sources of both MOSFET M26 and MOSFET M27 are connected to the common-mode voltage input terminal V. CM The gate of the MOS transistor M21 is connected to the gate of the MOS transistor M24 and serves as the operational amplifier A.2,3 The first input terminal V IP2 The first terminal of the switch S2 is connected to the common-mode voltage input terminal V. CM The second terminal is connected to the gate of the MOS transistor M21, and the gate of the MOS transistor M23 is input with a first bias voltage V. BL The gate input of the MOS transistor M22 is a second bias voltage V. BH .

[0043] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0044] 1. This invention proposes a high-efficiency thermal noise cancellation high-speed pipelined successive approximation hybrid analog-to-digital converter, including a first sampling branch and a second sampling branch. The first sampling branch is a bottom-plate sampling method used to quantize the MSB bits of the input sampled signal after the sampling clock signal goes low for a predetermined time. The second sampling branch is a top-plate sampling method used to directly quantize the MSB bits of the input sampled signal after the sampling clock signal goes low. Furthermore, the first sampling branch is also used to quantize the remaining bits of the sampled signal based on the quantization result of the second sampling branch after the MSB bit quantization is completed. By combining top-plate and bottom-plate sampling techniques, one bit of quantization time budget is saved, increasing the time allocated to margin amplification, improving the linearity of the system, and solving the amplitude attenuation problem and insufficient time utilization problem caused by bottom-plate technology.

[0045] 2. This invention uses variable bandwidth technology to make the bandwidth of the first-stage operational amplifier (i.e., operational amplifier A1) change according to its functional requirements. Under the premise of a slight increase in power consumption, it can greatly improve the signal-to-noise ratio and solve the trade-off between the average power of residual thermal noise and power consumption.

[0046] 3. This invention allows the feedback capacitor to participate in the sampling process, which reduces the amplitude attenuation problem caused by the bottom plate sampling and effectively improves the signal-to-noise ratio of the system.

[0047] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of a module for a high-speed pipeline successive approximation hybrid analog-to-digital converter with thermal noise cancellation provided in an embodiment of the present invention;

[0049] Figure 2 This is a schematic diagram of a thermal noise cancellation high-speed pipeline successive approximation hybrid analog-to-digital converter provided in an embodiment of the present invention;

[0050] Figure 3This is a timing diagram of a thermal noise cancellation high-speed pipeline successive approximation hybrid analog-to-digital converter provided in an embodiment of the present invention;

[0051] Figure 4 This is a circuit diagram of a fully differential variable bandwidth ring amplifier provided in an embodiment of the present invention. Detailed Implementation

[0052] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, describes a thermal noise cancellation high-speed pipeline successive approximation hybrid analog-to-digital converter proposed according to the present invention.

[0053] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0054] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0055] Example 1

[0056] To address the aforementioned issues, this invention proposes a high-efficiency, thermally noise-cancelled, high-speed pipelined successive approximation hybrid analog-to-digital converter (ADC). It employs bottom-plate and top-plate sampling techniques to enable the ADC to quantize the MSB (most significant bit) of the input signal during signal transitions, reducing the time budget. The feedback capacitor in the MDAC is used to sample the input signal, mitigating signal amplitude attenuation. A variable bandwidth fully differential ring amplifier is proposed to resolve the trade-off between bandwidth and power consumption. However, due to the small capacitance of the sampling capacitor in this technique, the signal sampled by the bottom-plate technique experiences amplitude attenuation due to parasitic capacitance. To mitigate this, the lower-stage board of the feedback capacitor in this patent is connected to the input signal and participates in the sampling process when the sampling clock is high. After sampling, during the quantization phase, the lower-stage board of the feedback capacitor is connected to the VCM, thereby avoiding amplitude attenuation.

[0057] Please see Figure 1 , Figure 1 This is a schematic diagram of a high-speed pipelined successive approximation hybrid analog-to-digital converter (ADC) with thermal noise cancellation provided in an embodiment of the present invention. The ADC includes a first sampling branch and a second sampling branch. The first sampling branch is a bottom-plate sampling branch, used to quantize the MSB bits of the input sampled signal after the sampling clock signal CLKS goes low for a predetermined time. The second sampling branch is a top-plate sampling branch, used to directly quantize the MSB bits of the input sampled signal after the sampling clock signal goes low. Furthermore, after the second sampling branch completes the MSB bit quantization, the first sampling branch quantizes the remaining bits of the sampled signal based on the quantization result of the second sampling branch.

[0058] Specifically, the first sampling branch samples from the bottom plate, and the second sampling branch samples from the top plate. When the sampling clock signal goes low, the first sampling branch needs a certain amount of time to start quantization, while the second sampling branch can quantize directly. Therefore, the second sampling branch directly quantizes the MSB bits of the sampled signal after the sampling clock signal goes low. After the second sampling branch completes the MSB bit quantization, the first sampling branch then completes the quantization of the remaining bits of the first-stage ADC based on the result of the second sampling branch.

[0059] Further, please see Figure 2 , Figure 2 This is a schematic diagram of a high-speed pipeline successive approximation hybrid analog-to-digital converter with thermal noise cancellation provided in an embodiment of the present invention. The first sampling branch of this embodiment includes a capacitor array C. S1N Capacitor array C S1P Operational amplifier A1, Operational amplifier A 2,3 Offset capacitor C N1 Offset capacitor C N2Feedback capacitor C F1 Feedback capacitor C F2 Switches K1, K2, K3, K4, K5, K6, K7, K8, K9, K10, K17, and K18.

[0060] Switch K1 and capacitor array C S1P Series connected at the first differential input terminal V IP With the first input terminal V of operational amplifier A1 IP1 Between switch K2 and capacitor array C S1n Series connected to the second differential input terminal V IN With the second input terminal V of operational amplifier A1 IN1 Between, the first differential input terminal V IP Second differential input V IN Used for input sampling signal; offset capacitor C N1 Connected to the first output terminal V of operational amplifier A1 OP1 With operational amplifier A 2,3 The first input terminal V IP2 Between, the offset capacitance C N2 Connected to the second output terminal V of operational amplifier A1 ON1 With operational amplifier A 2,3 The second input terminal V IN2 Between; feedback capacitor C F1 Switch K5 is connected in series with the first input terminal V of operational amplifier A1. IP1 With operational amplifier A 2,3 The second output terminal V ON2 Between, the feedback capacitor C F2 Switch K10 is connected in series at the second input terminal V of operational amplifier A1. IN2 With operational amplifier A 2,3 First output terminal V OP2 between.

[0061] The first terminal of switch K3 is connected to the first differential input terminal V. IP The second terminal is connected to the feedback capacitor C. F1 Between switch K5 and switch K4, the first terminal of switch K4 is connected to the common-mode voltage input terminal V. CM The second terminal is connected to the feedback capacitor C. F1 Between switch K5 and switch K8; the first terminal of switch K8 is connected to the second differential input terminal V. IN The second terminal is connected to the feedback capacitor C. F2 Between switch K10 and switch K9, the first terminal of switch K9 is connected to the common-mode voltage input terminal V. CM The second terminal is connected to the feedback capacitor C. F2Between switch K10 and switch K6; switch K6 is connected to the common-mode voltage input terminal V. CM With operational amplifier A 2,3 The first input terminal V IP2 Between, switch K7 is connected to the common-mode voltage input terminal V. CM With operational amplifier A 2,3 The second input terminal V IN2 Between; switch K17 is connected to the common-mode voltage input terminal V. CM With the first input terminal V of operational amplifier A1 IP1 Between, switch K18 is connected to the common-mode voltage input terminal V. CM With the second input terminal V of operational amplifier A1 IN1 Between; switches K1, K2, K3, K8, K6 and K7 are all controlled by the sampling clock signal CLKS, switches K4 and K9 are all controlled by the clock signal φ1, switches K5 and K10 are all controlled by the clock signal AMP, and switches K17 and K18 are all controlled by the clock signal CLKSE.

[0062] Furthermore, the first sampling branch also includes switches K11 and K12, wherein switch K11 is connected to operational amplifier A. 2,3 The second output terminal V ON2 Between the first input terminal of the subsequent ADC; switch K12 is connected to operational amplifier A. 2,3 First output terminal V OP2 Between the second input terminal of the subsequent ADC; both switches K11 and K12 are controlled by the clock signal AMP.

[0063] When the sampling clock signal CLKS goes low, the clock signal φ1 goes high; when the clock signal φ1 goes low, the clock signal AMP goes high. The sum of the duration of clock signal φ1 being high and the duration of clock signal AMP being high equals the duration of sampling clock signal CLKS being low. Clock signal CLKSE and sampling clock signal CLKS both trigger to high levels simultaneously, and the duration of clock signal CLKSE being high is less than the predetermined duration of clock signal CLKS being high.

[0064] See also Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of a thermal noise cancellation high-speed pipeline successive approximation hybrid analog-to-digital converter provided in an embodiment of the present invention; Figure 3 This is a timing diagram of a high-speed pipelined successive approximation hybrid analog-to-digital converter with thermal noise cancellation provided in an embodiment of the present invention. The second sampling branch in this embodiment includes comparator COM1, comparator COM2, and capacitor array C.S2N Capacitor array C S2P Switches K13, K14, K15, and K16; a logic control module, wherein switch K13 is connected to operational amplifier A. 2,3 The first input terminal V IP2 Switch K14 is connected between the first input terminal of comparator COM1 and operational amplifier A. 2,3 The second input terminal V IN2 Between the second input terminal of comparator COM1 and the second input terminal; switch K15 is connected to the first differential input terminal V. IP Switch K16 is connected between the first input terminal of comparator COM2 and the second differential input terminal V. IN Between the second input terminal of comparator COM2; capacitor array C S2P The capacitor array C is connected between the ground terminal and the first input terminal of comparator COM2. S2N The ground terminal is connected between the ground terminal and the second input terminal of comparator COM2. The output terminal of comparator COM1 is connected to the first input terminal of the logic control module, and the output terminal of comparator COM2 is connected to the second input terminal of the logic control module. The output terminal of the logic control module is connected to the capacitor array C. S1N and capacitor array C S1P It is used to change the capacitor array C based on the output results of comparators COM1 and COM2. S1N and capacitor array C S1P The voltage connected to the lower-level board corresponding to the capacitor; switches K13, K14, K15 and K16 are all controlled by the sampling clock signal CLKS.

[0065] Specifically, during the successive quantization process of the SAR ADC, the comparison results of comparators COM1 and COM2 are stored in the corresponding registers within the SAR LOGIC module, and the output of each register is connected to the capacitor array C. S1N and capacitor array C S1P The internal switching mechanism corresponds to the capacitor's downstream board. Its working principle is as follows: after comparators COM1 and COM2 complete the comparison, the comparison result is written into the corresponding register within the SAR LOGIC module, thereby changing the capacitor array C. S1N and capacitor array C S1P The voltage on the capacitor array changes due to the potential connected to the lower stage board of the capacitor. This voltage difference is then compared by the comparator, and the process repeats until all quantization is completed.

[0066] Further, please see Figure 4 , Figure 4This invention provides a fully differential variable bandwidth ring amplifier (including operational amplifier A1 and operational amplifier A1). 2,3 The circuit diagram of the operational amplifier A1 is shown below. The operational amplifier A1 includes MOSFETs M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, and M12, a common-mode feedback circuit CMFB, switch K19, and switch K20.

[0067] The sources of MOSFETs M1, M2, M3, and M4 are all connected to the power supply terminal VDD. The drains of MOSFETs M1, M2, M3, and M4, as well as the source of MOSFET M5, are all connected to the source of MOSFET M6. The gate of MOSFET M5 is connected to the gate of MOSFET M7 and serves as the first input terminal VDD of operational amplifier A1. IP1 The drain of MOSFET M5 is connected to the drain of MOSFET M7, and serves as the second output terminal V of operational amplifier A1. ON1 The gate of MOSFET M6 is connected to the gate of MOSFET M8 and serves as the second input terminal V of operational amplifier A1. IN1 The drain of MOSFET M6 is connected to the drain of MOSFET M8, and serves as the first output terminal V of operational amplifier A1. OP1 .

[0068] The source of MOSFET M7 is connected to the source of MOSFET M8, the drain of MOSFET M9, the drain of MOSFET M10, the drain of MOSFET M11, and the drain of MOSFET M12; the sources of MOSFETs M9, M10, M11, and M12 are all connected to ground; the gates of MOSFETs M1 and M9 are both connected to the second output terminal V of operational amplifier A1. ON1 The gates of MOSFET M4 and MOSFET M12 are both connected to the first output terminal V of operational amplifier A1. OP1 The gate input clock signal φ2B of MOSFET M3 and the gate input clock signal φ2 of MOSFET M11.

[0069] The two inputs of the common-mode feedback circuit CMFB are connected to operational amplifier A. 2,3 First output terminal V OP2 Second output terminal V ON2 The first terminal of switch K19 receives the common-mode voltage V. CMThe second terminal is connected to the gate of MOSFET M2 and the gate of MOSFET M10; the first terminal of switch K20 is connected to the output terminal of the common-mode feedback circuit CMFB, and the second terminal is connected to the gate of MOSFET M2; switch K19 is controlled by clock signal CLKS, and switch K20 is controlled by clock signal CLKSB. Clock signal φ2B and clock signal φ2 are opposite signals, and clock signal CLKS and clock signal CLKSB are opposite signals.

[0070] Operational amplifier A 2,3 It includes MOSFETs M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, M23, M24, M25, M26, M27, and M28, as well as switches S1 and S2.

[0071] The sources of MOSFETs M13, M17, M21, and M25 are all connected to the power supply terminal VDD. The drains of MOSFET M13, the gates of MOSFET M14 and M15, and the drain of MOSFET M16 are all connected to operational amplifier A. 2,3 The second output terminal V ON2 The gate of MOSFET M13 is connected to the drain of MOSFETs M14, M17, and M19, and the source of MOSFET M18; the gate of MOSFET M16 is connected to the drain of MOSFETs M15, M20, and M18, and the source of MOSFET M19; the source of MOSFETs M14 and M15 are both connected to a common-mode voltage V. CM The gate of MOSFET M17 is connected to the gate of MOSFET M20 and serves as operational amplifier A. 2,3 The second input terminal V IN2 The first terminal of switch S1 is input with common-mode voltage V. CM The second terminal is connected to the gate of MOSFET M17, and the gate of MOSFET M18 is input with a first bias voltage V. BL The gate input of MOSFET M19 is the second bias voltage V. BH The sources of MOSFETs M16, M20, M24, and M28 are all connected to the ground terminal GND.

[0072] The drain of MOSFET M25, the gate of MOSFET M26, the gate of MOSFET M27, and the drain of MOSFET M28 are all connected to operational amplifier A. 2,3 First output terminal V OP2The gate of MOSFET M25 is connected to the drain of MOSFET M26, the drain of MOSFET M21, the drain of MOSFET M22, and the source of MOSFET M23; the gate of MOSFET M28 is connected to the drain of MOSFET M27, the drain of MOSFET M23, the drain of MOSFET M24, and the source of MOSFET M22; the source of MOSFET M26 and the source of MOSFET M27 are both input with a common-mode voltage V. CM The gate of MOSFET M21 is connected to the gate of MOSFET M24 and serves as operational amplifier A. 2,3 The first input terminal V IP2 The first terminal of switch S2 is input with common-mode voltage V. CM The second terminal is connected to the gate of MOSFET M21, and the gate of MOSFET M23 is input with a first bias voltage V. BL The gate input of MOSFET M22 is the second bias voltage V. BH .

[0073] The working principle of this analog-to-digital converter is as follows:

[0074] Combination Figure 3 and Figure 4 As shown, initially when clock signals CLKS, CLKSE, and φ2 are high, switches K1, K2, K6, K7, K15, K16, K3, K8, K19, and K20 are simultaneously closed, while switches K4, K5, K9, K10, K11, and K12 are open. The signal is then fed by the first sampling branch, the second sampling branch, and the feedback capacitor C. F1 and feedback capacitor C F2 Simultaneous sampling. When CLKSE changes from high to low, K19 and K20 are disconnected, and noise information is stored in capacitor array C. S1N and capacitor array C S1P At this point, operational amplifier A1 amplifies the noise signal and stores it in offset capacitor C. N1 and offset capacitor C N2 At this time, since MOSFETs M3 and M11 are in the conducting state, a large current flows through the first stage of the operational amplifier (operational amplifier A1), and the operational amplifier A1 is in a large bandwidth operating mode, which accelerates the sampling and amplification of noise. When the noise storage is completed, when the clock φ2 goes low, MOSFETs M3 and M11 are in the off state, a small current flows through the first stage of the operational amplifier, and the operational amplifier operates in a small bandwidth mode to reduce the power consumption of the operational amplifier.

[0075] When the clock signal CLKS goes low, switches K1, K2, K15, K16, K3, K6, K7, and K8 are opened. Traditional thermal noise cancellation structures use bottom-plate sampling. However, bottom-plate sampling requires a certain amount of time after the sampling clock signal CLKS goes low to complete the voltage transition before quantization can begin. This voltage transition process consumes a significant time budget. To overcome this problem, the analog-to-digital converter of this invention employs dual sampling, including a first sampling branch and a second sampling branch. The added second sampling branch is top-plate sampling. While the first sampling branch (bottom-plate sampling branch) is still in the transition process, the second sampling branch (top-plate sampling branch) first performs MSB quantization, making full use of the transition time. Then, quantization continues after the first sampling branch completes its transition.

[0076] Compared to traditional architectures, the architecture of this invention can save one quantization time budget. The quantization process is as follows: After the clock signal CLKS goes low, comparator COM2 first quantizes the MSB bits of the input sampled signal. The quantized result is written to the first register of the logic control module, and then the capacitor array C is changed. S1N and capacitor array C S1P The voltage across the capacitor array changes due to the potential connected to the lower stage board of the capacitor. This voltage difference is then compared by comparator COM1, and the comparison result of comparator COM1 is written to the second register of the logic control module, which continues to change the voltage across the capacitor array C. S1N and capacitor array C S1P The internal capacitor corresponds to the potential connected to the lower stage board, and this cycle repeats until comparator COM1 completes the quantization of all bits. Simultaneously, when the sampling clock signal CLKS goes low, clock φ1 goes high, at which point switches K4 and K9 close, and the feedback capacitor C... F1 and feedback capacitor C F2 The lower-level board is connected to a common-mode voltage V CM After the quantization phase ends, clock φ1 goes low and clock φ2 goes high. At this time, switches K5, K10, K11, and K12 are closed, and operational amplifiers A1 and A2 are activated. 2,3 The margin information is amplified and transmitted to the backend ADC.

[0077] As described above, in traditional thermal noise cancellation techniques, a signal flipping process occurs after sampling, followed by requantization. To fully utilize this flipping time, this invention adds a second sampling branch. This second sampling branch acquires the input signal at time ts through top plate sampling and quantizes the MSB bits of the input signal after sampling. Since this second sampling branch only quantizes the MSB bits of the sampled signal, the capacitor array C... S2N and capacitor array C S2PThe total capacitance value can be appropriately reduced. Although increased sampling noise may lead to MSB bit comparison errors, this error can be eliminated by inter-stage redundancy design. When the capacitor array C in the first sampling branch... S1N and capacitor array C S1P After the signal inversion step is completed, the second sampling branch has completed the quantization of the MSB bits. In this way, the first sampling branch can directly perform the quantization of the second bit using the quantization result of the MSB bits of the second sampling branch, reducing the waste of time.

[0078] Furthermore, assume the feedback capacitor C F1 and feedback capacitor C F2 It does not participate in the sampling process because of the capacitor array C S1N and capacitor array C S1P There are feedback capacitors and parasitic capacitors at the upper plate, with the first differential input terminal V... IP Taking the input signal as an example, the actual signal amplitude sampled by the analog-to-digital converter is:

[0079]

[0080] in, This represents the parasitic capacitance of the first differential input terminal.

[0081] As can be seen, the signal amplitude has attenuated, resulting in a loss of fundamental frequency energy. To alleviate this phenomenon, such as... Figure 2 The circuit shown and Figure 3 The timing diagram shows that when the clock signal CLKS is high, the input signals, except for those connected to the capacitor array C... S1N and capacitor array C S1P A feedback capacitor C is also connected to the outside of the lower electrode plate. F1 and feedback capacitor C F2 The lower plate, when Φ1 is high, capacitor array C S1N and capacitor array C S1P The lower plate is connected to the common-mode voltage V. CM With the first differential input terminal V IP The input signal, the sampled signal amplitude is:

[0082]

[0083] As can be seen, the feedback capacitor C F1 and feedback capacitor C F2 After adding the sampling operation, the problem of input signal amplitude attenuation was alleviated, and the loss of fundamental wave energy was reduced.

[0084] Furthermore, to address the trade-off between bandwidth and power consumption in traditional thermal noise cancellation techniques, this invention proposes a fully differential variable bandwidth ring amplifier. Variable bandwidth technology is employed in the first stage of the operational amplifier, adjusting the bandwidth by changing the current of the first stage at different times to adapt to various operating scenarios and achieve high energy efficiency.

[0085] correspond Figure 4 In the timing diagram at the top right corner, the bandwidth of the first stage of the operational amplifier is adjustable within the time interval Δt (t1~t3). During the time interval Δt1 (t1~t2), Φ2 is at a high level, at which time M3 and M4 are turned on, and the current flowing through the first stage of the operational amplifier is large, increasing the bandwidth of the first stage of the operational amplifier and accelerating its establishment of sampling thermal noise. During the time interval Δt2 (t2~t3), Φ2 drops to a low level, causing M3 and M4 to turn off, and the current flowing through the first stage of the operational amplifier is small. The bandwidth of the first stage of the operational amplifier is reduced to meet the bandwidth requirements during the margin amplification process, thereby improving the circuit's energy efficiency ratio.

[0086] During the time interval △t (t1~t3) w p It is a time-varying function (in design) w p1 Greater than w p2 )

[0087]

[0088] in, w p The symbol representing the bandwidth of operational amplifier A1. w p1 express Bandwidth within a time period w p2 express Bandwidth within a time period.

[0089] The equivalent bandwidth of the first stage of the operational amplifier during the entire time interval Δt can be expressed as follows.

[0090]

[0091] Comparing the variable bandwidth with the constant bandwidth, the ratio of the equivalent input thermal noise power is:

[0092]

[0093] in, This represents the thermal noise power equivalent to the residual power at the input in the case of variable bandwidth. This represents the thermal noise power equivalent to the residual thermal noise at the input terminal under constant bandwidth conditions.

[0094] As can be seen from the above formula, simply increasing the bandwidth of the first stage of the operational amplifier within the time interval Δt1 (t1~t2) can significantly reduce the average power of the sampling thermal noise, while also enabling the first stage of the operational amplifier to have a high energy efficiency ratio.

[0095] This invention proposes a high-efficiency thermal noise-cancelling high-speed pipelined successive approximation hybrid analog-to-digital converter (ADC), comprising a first sampling branch and a second sampling branch. The first sampling branch is a bottom-plate sampling method used to quantize the MSB bits of the input sampled signal after the sampling clock signal goes low for a predetermined time. The second sampling branch is a top-plate sampling method used to directly quantize the MSB bits of the input sampled signal after the sampling clock signal goes low. Furthermore, the first sampling branch is also used to quantize the remaining bits of the sampled signal based on the quantization result of the second sampling branch after the MSB bit quantization is completed. By combining top-plate and bottom-plate sampling techniques, one bit of quantization time budget is saved, increasing the time allocated to margin amplification, improving the linearity of the system, and solving the amplitude attenuation problem and insufficient time utilization problem caused by bottom-plate technology.

[0096] This invention utilizes variable bandwidth technology to allow the bandwidth of the first-stage operational amplifier (A1) to vary according to its functional requirements. This significantly improves the signal-to-noise ratio (SNR) with a slight increase in power consumption, resolving the trade-off between the average power of residual thermal noise and power consumption. Furthermore, this invention incorporates the feedback capacitor into the sampling process, mitigating the amplitude attenuation problem caused by bottom-plate sampling and effectively enhancing the system's SNR.

[0097] In the several embodiments provided by this invention, it should be understood that the apparatus and methods disclosed in this invention can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of modules is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0098] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or in the form of hardware plus software functional modules.

[0099] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-speed pipelined successive approximation hybrid analog-to-digital converter with thermal noise cancellation, characterized in that, Includes a first sampling branch and a second sampling branch, wherein, The first sampling branch is a bottom plate sampling, used to quantize the MSB bits of the input sampling signal after the sampling clock signal goes low for a predetermined time; The second sampling branch is a top plate sampling branch, which is used to quantize the MSB bits of the input sampling signal directly after the sampling clock signal goes low. The first sampling branch also quantizes the remaining bits of the sampling signal according to the quantization result of the second sampling branch after the MSB bit quantization is completed by the second sampling branch.

2. The thermal noise cancellation high-speed pipeline successive approximation hybrid analog-to-digital converter according to claim 1, characterized in that, The first sampling branch includes a capacitor array C S1N Capacitor array C S1P Operational amplifier A1, Operational amplifier A 2,3 Offset capacitor C N1 Offset capacitor C N2 Feedback capacitor C F1 Feedback capacitor C F2 Switches K1, K2, K3, K4, K5, K6, K7, K8, K9, K10, K17, and K18, wherein... The switch K1 and the capacitor array C S1P Series connected at the first differential input terminal V IP With the first input terminal V of the operational amplifier A1 IP1 Between the switch K2 and the capacitor array C S1n Series connected to the second differential input terminal V IN With the second input terminal V of the operational amplifier A1 IN1 Between, the first differential input terminal V IP and the second differential input terminal V IN Used for inputting sampling signals; The offset capacitor C N1 Connected to the first output terminal V of the operational amplifier A1 OP1 With the operational amplifier A 2,3 The first input terminal V IP2 Between, the offset capacitor C N2 Connected to the second output terminal V of the operational amplifier A1 ON1 With the operational amplifier A 2,3 The second input terminal V IN2 between; The feedback capacitor C F1 The switch K5 is connected in series with the first input terminal V of the operational amplifier A1. IP1 With the operational amplifier A 2,3 The second output terminal V ON2 Between, the feedback capacitor C F2 The switch K10 is connected in series with the second input terminal V of the operational amplifier A1. IN2 With the operational amplifier A 2,3 First output terminal V OP2 between; The first terminal of the switch K3 is connected to the first differential input terminal V. IP The second terminal is connected to the feedback capacitor C. F1 Between switch K4 and switch K5, the first terminal of switch K4 is connected to the common-mode voltage input terminal V. CM The second terminal is connected to the feedback capacitor C. F1 Between the switch K5 and the switch K8; the first terminal of the switch K8 is connected to the second differential input terminal V. IN The second terminal is connected to the feedback capacitor C. F2 Between switch K10 and switch K9, the first terminal of switch K9 is connected to the common-mode voltage input terminal V. CM The second terminal is connected to the feedback capacitor C. F2 Between and the switch K10; The switch K6 is connected to the common-mode voltage input terminal V. CM With the operational amplifier A 2,3 The first input terminal V IP2 Between, the switch K7 is connected to the common-mode voltage input terminal V. CM With the operational amplifier A 2,3 The second input terminal V IN2 between; The switch K17 is connected to the common-mode voltage input terminal V. CM With the first input terminal V of the operational amplifier A1 IP1 Between, the switch K18 is connected to the common-mode voltage input terminal V. CM With the second input terminal V of the operational amplifier A1 IN1 between; Switches K1, K2, K3, K8, K6, and K7 are all controlled by the sampling clock signal CLKS; switches K4 and K9 are both controlled by the clock signal φ1; switches K5 and K10 are both controlled by the clock signal AMP; and switches K17 and K18 are both controlled by the clock signal CLKSE.

3. The thermal noise cancellation high-speed pipeline successive approximation hybrid analog-to-digital converter according to claim 2, characterized in that, The first sampling branch also includes switches K11 and K12, wherein, The switch K11 is connected to the operational amplifier A. 2,3 The second output terminal V ON2 Between the first input terminal of the subsequent ADC; the switch K12 is connected to the operational amplifier A. 2,3 First output terminal V OP2 Between the second input terminal of the subsequent ADC; Both switch K11 and switch K12 are controlled by the clock signal AMP.

4. The thermal noise cancellation high-speed pipeline successive approximation hybrid analog-to-digital converter according to claim 3, characterized in that, When the sampling clock signal CLKS goes low, the clock signal φ1 goes high; when the clock signal φ1 goes low, the clock signal AMP goes high. The sum of the duration of the clock signal φ1 being at a high level and the duration of the clock signal AMP being at a high level is equal to the duration of the sampling clock signal CLKS being at a low level. The clock signal CLKSE and the sampling clock signal CLKS are triggered to a high level simultaneously, and the high level duration of the clock signal CLKSE is less than the predetermined high level duration of the sampling clock signal CLKS.

5. The thermal noise cancellation high-speed pipeline successive approximation hybrid analog-to-digital converter according to claim 2, characterized in that, The second sampling branch includes comparator COM1, comparator COM2, and capacitor array C. S2N Capacitor array C S2P Switches K13, K14, K15, and K16; and a logic control module, wherein... The switch K13 is connected to the operational amplifier A. 2,3 The first input terminal V IP2 The switch K14 is connected between the first input terminal of the comparator COM1 and the operational amplifier A. 2,3 The second input terminal V IN2 Between the second input terminal of the comparator COM1; The switch K15 is connected to the first differential input terminal V. IP The switch K16 is connected between the first input terminal of the comparator COM2 and the second differential input terminal V. IN Between the second input terminal of the comparator COM2; The capacitor array C S2P The capacitor array C is connected between the ground terminal and the first input terminal of the comparator COM2. S2N The output of comparator COM1 is connected between the ground terminal and the second input terminal of comparator COM2, and the output terminal of comparator COM1 is connected to the first input terminal of the logic control module. The output terminal of comparator COM2 is connected to the second input terminal of the logic control module. The output of the logic control module is connected to the capacitor array C. S1N and the capacitor array C S1P It is used to change the capacitor array C based on the output results of the comparators COM1 and COM2. S1N and the capacitor array C S1P The voltage connected to the next stage board corresponding to the capacitor; The switches K13, K14, K15 and K16 are all controlled by the sampling clock signal CLKS.

6. The thermal noise cancellation high-speed pipeline successive approximation hybrid analog-to-digital converter according to claim 2, characterized in that, The operational amplifier A1 includes MOSFETs M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, and M12, a common-mode feedback circuit CMFB, switch K19, and switch K20. The source of MOSFET M1, the source of MOSFET M2, the source of MOSFET M3, and the source of MOSFET M4 are all connected to the power supply terminal VDD. The drain of MOSFET M1, the drain of MOSFET M2, the drain of MOSFET M3, the drain of MOSFET M4, and the source of MOSFET M5 are all connected to the source of MOSFET M6. The gate of the MOSFET M5 is connected to the gate of the MOSFET M7, and serves as the first input terminal V of the operational amplifier A1. IP1 The drain of MOSFET M5 is connected to the drain of MOSFET M7, and serves as the second output terminal V of operational amplifier A1. ON1 The gate of the MOS transistor M6 is connected to the gate of the MOS transistor M8, and serves as the second input terminal V of the operational amplifier A1. IN1 The drain of MOSFET M6 is connected to the drain of MOSFET M8, and serves as the first output terminal V of operational amplifier A1. OP1 ; The source of MOSFET M7 is connected to the source of MOSFET M8, the drain of MOSFET M9, the drain of MOSFET M10, the drain of MOSFET M11, and the drain of MOSFET M12; the sources of MOSFET M9, M10, M11, and M12 are all connected to the ground terminal. The gates of both MOSFET M1 and MOSFET M9 are connected to the second output terminal V of operational amplifier A1. ON1 The gates of MOS transistor M4 and MOS transistor M12 are both connected to the first output terminal V of operational amplifier A1. OP1 ; The gate input clock signal φ2B of the MOS transistor M3 and the gate input clock signal φ2 of the MOS transistor M11; The two input terminals of the common-mode feedback circuit CMFB are respectively connected to the operational amplifier A. 2,3 First output terminal V OP2 Second output terminal V ON2 The first terminal of the switch K19 is connected to the common-mode voltage input terminal V. CM The second end is connected to the gate of the MOS transistor M2 and the gate of the MOS transistor M10; the first end of the switch K20 is connected to the output of the common-mode feedback circuit CMFB, and the second end is connected to the gate of the MOS transistor M2. The switch K19 is controlled by the clock signal CLKS, and the switch K20 is controlled by the clock signal CLKSB.

7. The thermal noise cancellation high-speed pipeline successive approximation hybrid analog-to-digital converter according to claim 6, characterized in that, The clock signal φ2B and the clock signal φ2 are opposite signals, and the clock signal CLKS and the clock signal CLKSB are opposite signals.

8. The thermal noise cancellation high-speed pipeline successive approximation hybrid analog-to-digital converter according to claim 2, characterized in that, The operational amplifier A 2,3 This includes MOSFETs M13, M14, M15, M16, M17, M18, M19, M20, M21, M22, M23, M24, M25, M26, M27, and M28, as well as switches S1 and S2. The sources of MOSFETs M13, M17, M21, and M25 are all connected to the power supply terminal VDD. The drain of MOSFET M13, the gate of MOSFET M14, the gate of MOSFET M15, and the drain of MOSFET M16 are all connected to the operational amplifier A. 2,3 The second output terminal V ON2 The gate of MOSFET M13 is connected to the drain of MOSFET M14, the drain of MOSFET M17, the drain of MOSFET M19, and the source of MOSFET M18; the gate of MOSFET M16 is connected to the drain of MOSFET M15, the drain of MOSFET M20, the drain of MOSFET M18, and the source of MOSFET M19. The sources of both MOSFET M14 and MOSFET M15 are connected to the common-mode voltage input terminal V. CM The gate of the MOS transistor M17 is connected to the gate of the MOS transistor M20 and serves as the operational amplifier A. 2,3 The second input terminal V IN2 The first terminal of the switch S1 is connected to the common-mode voltage input terminal V. CM The second terminal is connected to the gate of the MOS transistor M17, and the gate of the MOS transistor M18 is input with a first bias voltage V. BL The gate input of the MOS transistor M19 is a second bias voltage V. BH The sources of the MOSFETs M16, M20, M24, and M28 are all connected to the ground terminal GND. The drain of MOSFET M25, the gate of MOSFET M26, the gate of MOSFET M27, and the drain of MOSFET M28 are all connected to operational amplifier A. 2,3 First output terminal V OP2 The gate of MOSFET M25 is connected to the drain of MOSFET M26, the drain of MOSFET M21, the drain of MOSFET M22, and the source of MOSFET M23; the gate of MOSFET M28 is connected to the drain of MOSFET M27, the drain of MOSFET M23, the drain of MOSFET M24, and the source of MOSFET M22. The sources of both MOSFET M26 and MOSFET M27 are connected to the common-mode voltage input terminal V. CM The gate of the MOS transistor M21 is connected to the gate of the MOS transistor M24 and serves as the operational amplifier A. 2,3 The first input terminal V IP2 The first terminal of the switch S2 is connected to the common-mode voltage input terminal V. CM The second terminal is connected to the gate of the MOS transistor M21, and the gate of the MOS transistor M23 is input with a first bias voltage V. BL The gate input of the MOS transistor M22 is a second bias voltage V. BH .

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