Synchronous code detection method, system and device in low earth orbit satellite communication system

Abstract

The embodiment of the invention provides a synchronous code detection method, system and device in a low earth orbit satellite communication system, and the method comprises the steps: grading an obtained maximum frequency offset range value of the low earth orbit satellite communication system, and obtaining frequency offset values of different grades, performing synchronous code capture on a first receiving signal of the input signal flow under the frequency offset values of different grades, and obtaining an initial frequency offset estimation value according to a capture result; compensating a second receiving signal of the input signal flow by using the initial frequency offset estimation value, and performing synchronous code capture on the compensated second receiving signal to obtain a candidate synchronous code position confirmed by coarse compensation; based on the candidate synchronous code position, performing frequency offset estimation on the synchronous code data under the plurality of time slots to obtain a candidate frequency offset estimation value; and compensating a third receiving signal of the input signal flow by using the candidate frequency offset estimation value, and performing synchronous code capture on the compensated third receiving signal to obtain a synchronously captured target synchronous code position. According to the invention, the detection of the synchronous code in the low-orbit satellite communication system is realized.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technology, and in particular to a synchronization code detection method, system and device in a low-orbit satellite communication system. Background Art

[0002] In wireless communication systems (such as LTE (Long Term Evolution), NR (New Radio), etc.), UE (User Equipment) needs to initialize synchronization and establish a connection with a base station. It must first perform cell search synchronization, and the key to achieving cell search synchronization lies in the detection of synchronization codes.

[0003] In the LTE system of the related technology, the implementation process of synchronization code detection is mainly: first, the received signal sequence is downsampled and extracted to generate a local synchronization sequence, and the search starting point is determined. Then, the received signal sequence is subjected to FFT (Fast Fourier Transform) operation and a sliding correlation operation is performed with the local synchronization sequence to obtain a power sequence, and a peak value in the power sequence is searched. It is determined whether the main synchronization code is successfully detected based on the peak value and a preset threshold. When successful detection is determined, the corresponding synchronization code position is calculated based on the peak position.

[0004] With the development of the wireless communication industry, low-orbit satellite communication systems (also known as low-orbit satellite communication systems) use many low-orbit satellites as "base stations" to achieve communication between mobile users or between mobile users and fixed users. It has the advantages of wide coverage and high communication rate, and has become a new type of network communication system that has been vigorously developed in recent years. As a new communication system, the low-orbit satellite communication system is different from the ground 2G / 3G / 4G / 5G network. It has its own unique characteristics in terms of protocol system, network architecture, interface standards, etc., and the above-mentioned synchronization code detection method applied to the LTE system is mainly for ground wireless network scenarios. For low-orbit satellite communication systems, due to the high relative motion speed between low-orbit satellites and ground stations, and the large dynamic and low signal-to-noise caused by the large attenuation of the satellite-to-ground link, the above-mentioned synchronization code detection method for ground wireless network scenarios cannot effectively realize synchronization code detection in low-orbit satellite communication systems. Summary of the invention

[0005] The purpose of the embodiments of the present invention is to provide a method, system and device for detecting synchronization codes in a low-orbit satellite communication system, so as to realize the detection of synchronization codes in the low-orbit satellite communication system. The specific technical solution is as follows:

[0006] In a first aspect, an embodiment of the present invention provides a synchronization code detection method in a low-orbit satellite communication system, the method comprising:

[0007] Acquire a maximum frequency deviation range value of the low-orbit satellite communication system, divide the maximum frequency deviation range value into different bins to obtain frequency deviation values ​​of different bins, perform synchronization code capture on a first received signal of an input signal stream at the frequency deviation values ​​of different bins respectively, and obtain an initial frequency deviation estimation value according to the capture result;

[0008] Compensating a second received signal of the input signal stream by using the initial frequency offset estimation value, and performing synchronization code capture on the compensated second received signal to obtain a candidate synchronization code position confirmed by rough compensation;

[0009] Based on the candidate synchronization code positions, frequency offset estimation is performed on synchronization code data in multiple time slots to obtain candidate frequency offset estimation values;

[0010] The candidate frequency offset estimation value is used to compensate the third received signal of the input signal stream, and synchronization code capture is performed on the compensated third received signal to obtain a target synchronization code position for synchronization capture.

[0011] Optionally, the performing synchronization code capture on the first received signal of the input signal stream at frequency offset values ​​of different bins respectively, and obtaining an initial frequency offset estimation value according to the capture result, includes:

[0012] For each frequency offset value of each bin, the frequency offset value of the bin is compensated to the first received signal of the input signal stream, and the compensated first received signal is subjected to synchronization code capture to obtain a cumulative correlation peak obtained by operating the first received signal sequence and the local sequence in each bin; the cumulative correlation peak represents a result obtained by accumulating the first received signal sequence and the local sequence after the operation;

[0013] Based on the cumulative correlation peak of each bin, the frequency offset value of the bin corresponding to the largest peak value is selected as the initial frequency offset estimation value.

[0014] Optionally, for each frequency offset value of the bin, compensating the frequency offset value of the bin into a first received signal of the input signal stream, performing synchronization code capture on the compensated first received signal, and obtaining a cumulative correlation peak obtained by operating the first received signal sequence and the local sequence for each bin, includes:

[0015] For each frequency offset value of each bin, compensating the frequency offset value of the bin into a first received signal of the input signal stream to obtain a compensated first received signal;

[0016] Quantizing the compensated first received signal to generate a first received signal sequence; the first received signal sequence includes a plurality of data packets, each of which includes a sampling time slot identifier;

[0017] Performing an operation on the first received signal sequence and the local sequence to obtain a first operation result; the first operation result includes a sampling time slot identifier;

[0018] Based on the sampling time slot identifier and the correspondence between the preset time slot and the selection coefficient, performing staggered selection on the first operation result to select corresponding branch data;

[0019] The branch data corresponding to multiple time slots are accumulated and searched for peak values ​​to obtain the accumulated correlation peak of the bin.

[0020] Optionally, the performing quantization processing on the compensated first received signal to generate a first received signal sequence includes:

[0021] When the number of sampling points of the compensated first received signal accumulates to a preset length, calculating the average of the preset length of sampling point values ​​in the compensated first received signal;

[0022] determining a compression threshold based on the mean value;

[0023] Based on the value of each sampling point in the compensated first received signal and the compression threshold, bit compressing the value of each sampling point in the compensated first received signal to obtain compressed data;

[0024] A first received signal sequence is generated based on the compressed data.

[0025] Optionally, the performing operation on the first received signal sequence and a local sequence to obtain a first operation result includes:

[0026] Sequentially taking out a first preset number of data from the first received signal sequence to obtain a third received signal sequence;

[0027] For each third received signal sequence, perform point-to-point multiplication of the third received signal sequence and the local sequence to obtain a cross-correlation sequence;

[0028] For the mutual correlation sequence, summing up the values ​​in the mutual correlation sequence according to a second preset number to obtain an intermediate sequence, and then summing up the values ​​in the intermediate sequence according to the second preset number until two sum values ​​are obtained;

[0029] A modulo operation is performed on the two sum values ​​respectively, and the modulo values ​​are summed to obtain a first operation result.

[0030] Optionally, performing staggered selection on the first operation result to select corresponding branch data based on the sampling time slot identifier and the correspondence between the preset time slot and the selection coefficient includes:

[0031] Read the correspondence table between preset time slots and selection coefficients, determine the starting sampling point of the first operation result in different time slots according to the correspondence between the sampling time slot identifier, the time slot and the selection coefficient, and obtain the branch data in the corresponding time slot.

[0032] Optionally, the using the initial frequency offset estimation value to compensate the second received signal of the input signal stream, and performing synchronization code capture on the compensated second received signal to obtain a candidate synchronization code position confirmed by rough compensation, includes:

[0033] Compensating a second received signal of the input signal stream by using the initial frequency offset estimation value to obtain a compensated second received signal;

[0034] quantizing the compensated second received signal to generate a second received signal sequence; the second received signal sequence includes a plurality of data packets, each of which includes a sampling time slot identifier;

[0035] Performing an operation on the second received signal sequence and the local sequence to obtain a second operation result; the second operation result includes a sampling time slot identifier;

[0036] Based on the sampling time slot identifier and the correspondence between the preset time slot and the selection coefficient, performing staggered selection on the second operation result to select corresponding branch data;

[0037] Performing cumulative calculation and peak search on the branch data corresponding to multiple time slots to obtain cumulative correlation peaks;

[0038] Based on the position of the maximum peak value in the cumulative correlation peaks, a candidate synchronization code position is determined.

[0039] Optionally, performing accumulation operation and peak search on the branch data corresponding to the multiple time slots to obtain the accumulated correlation peak includes:

[0040] For the branch data in each time slot, the data in each branch data is added point by point to obtain a cumulative sum value;

[0041] A peak search is performed on the cumulative sum value to obtain a cumulative correlation peak.

[0042] Optionally, the performing frequency offset estimation on synchronization code data in a plurality of time slots based on the candidate synchronization code position to obtain a candidate frequency offset estimation value includes:

[0043] Based on the candidate synchronization code position, determine the starting position, sliding window spacing and number of sliding windows of the sliding window of the synchronization code data in each time slot;

[0044] Based on the starting position, the sliding window spacing and the number of sliding windows, for the synchronization code data in each time slot, the data in each sliding window is operated to obtain a plurality of third operation results;

[0045] Calculate the cumulative sum of the third operation results in multiple time slots corresponding to each sliding window to obtain a cumulative result;

[0046] A peak search is performed on the accumulated results corresponding to each sliding window, and a candidate frequency offset estimation value is determined according to the maximum peak value in the peak search result.

[0047] In a second aspect, an embodiment of the present invention provides a synchronization code detection device in a low-orbit satellite communication system, the device comprising:

[0048] A binning capture module is used to obtain a maximum frequency deviation range value of the low-orbit satellite communication system, bin the maximum frequency deviation range value to obtain frequency deviation values ​​of different bins, perform synchronization code capture on a first received signal of an input signal stream at frequency deviation values ​​of different bins, and obtain an initial frequency deviation estimation value according to the capture result;

[0049] A coarse compensation confirmation module, used to compensate the second received signal of the input signal stream by using the initial frequency offset estimation value, and to capture the synchronization code of the compensated second received signal to obtain a candidate synchronization code position for coarse compensation confirmation;

[0050] A search and frequency measurement module, configured to estimate the frequency offset of the synchronization code data in a plurality of time slots based on the candidate synchronization code position, and obtain a candidate frequency offset estimation value;

[0051] The synchronization capture module is used to compensate the third received signal of the input signal stream by using the candidate frequency offset estimation value, and perform synchronization code capture on the compensated third received signal to obtain a target synchronization code position for synchronization capture.

[0052] Optionally, the binning and capturing module comprises:

[0053] A bin capture submodule is used to compensate the frequency deviation value of each bin into the first received signal of the input signal stream, and perform synchronization code capture on the compensated first received signal to obtain a cumulative correlation peak obtained by operating the first received signal sequence and the local sequence in each bin; the cumulative correlation peak represents a result obtained by accumulating the operation of the first received signal sequence and the local sequence;

[0054] The frequency offset estimation submodule is used to select the frequency offset value of the bin corresponding to the maximum peak value as the initial frequency offset estimation value based on the cumulative correlation peak of each bin.

[0055] Optionally, the sub-module for capturing by grading includes:

[0056] A first frequency offset compensation unit is used to compensate the frequency offset value of each bin into the first received signal of the input signal stream for the frequency offset value of each bin, so as to obtain a compensated first received signal;

[0057] A first quantization unit is used to perform quantization processing on the compensated first received signal to generate a first received signal sequence; the first received signal sequence includes a plurality of data packets, each of which includes a sampling time slot identifier;

[0058] A first operation unit, configured to operate the first received signal sequence and the local sequence to obtain a first operation result; the first operation result includes a sampling time slot identifier;

[0059] A first staggered selection unit, configured to perform staggered selection on the first operation result based on the sampling time slot identifier and the correspondence between the preset time slot and the selection coefficient, and select corresponding branch data;

[0060] The first peak search unit is used to perform accumulation calculation and peak search on the branch data corresponding to multiple time slots to obtain the accumulated correlation peak of the bin.

[0061] Optionally, the first quantization unit is specifically used to calculate the mean of the values ​​of a preset length of sampling points in the compensated first received signal when the number of sampling points of the compensated first received signal accumulates to a preset length; determine a compression threshold based on the mean; based on the value of each sampling point in the compensated first received signal and the compression threshold, perform bit compression on the value of each sampling point in the compensated first received signal to obtain compressed data; and generate a first received signal sequence based on the compressed data.

[0062] Optionally, the first operation unit is specifically used to take out a first preset number of data from the first received signal sequence in sequence to obtain a third received signal sequence; for each third received signal sequence, perform point-to-point multiplication of the third received signal sequence and a local sequence to obtain a mutual correlation sequence; for the mutual correlation sequence, sum the values ​​in the mutual correlation sequence according to a second preset number to obtain an intermediate sequence, and then sum the values ​​in the intermediate sequence according to the second preset number until two sum values ​​are obtained; perform modulo operation on the two sum values ​​respectively, and sum the modulo values ​​to obtain a first operation result.

[0063] Optionally, the first staggered selection unit is specifically used to read a correspondence table between preset time slots and selection coefficients, determine the starting sampling point of the first operation result in different time slots according to the correspondence between the sampling time slot identifier, the time slot and the selection coefficient, and obtain the branch data in the corresponding time slot.

[0064] Optionally, the rough patch confirmation module includes:

[0065] A second frequency offset compensation unit, configured to compensate a second received signal of the input signal stream by using the initial frequency offset estimation value to obtain a compensated second received signal;

[0066] A second quantization unit is used to perform quantization processing on the compensated second received signal to generate a second received signal sequence; the second received signal sequence includes a plurality of data packets, each of which includes a sampling time slot identifier;

[0067] A second operation unit, configured to operate the second received signal sequence and the local sequence to obtain a second operation result; the second operation result includes a sampling time slot identifier;

[0068] A second staggered selection unit, configured to perform staggered selection on the second operation result based on the sampling time slot identifier and the correspondence between the preset time slot and the selection coefficient, and select corresponding branch data;

[0069] A second peak search unit, used for performing accumulation operation and peak search on the branch data corresponding to a plurality of time slots to obtain a cumulative correlation peak;

[0070] The synchronization code position determination unit is used to determine the candidate synchronization code position based on the position of the maximum peak value in the cumulative correlation peak.

[0071] Optionally, the second peak search unit is specifically used to perform point-to-point accumulation operation on the data in each branch data in each time slot to obtain a cumulative sum value; and perform peak search on the cumulative sum value to obtain a cumulative correlation peak.

[0072] Optionally, the search and frequency measurement module is specifically used to determine the starting position, sliding window spacing and number of sliding windows of the sliding window of the synchronization code data in each time slot based on the candidate synchronization code position; based on the starting position, sliding window spacing and number of sliding windows, for the synchronization code data in each time slot, perform operations on the data in each sliding window to obtain multiple third operation results; calculate the cumulative sum of the third operation results in multiple time slots corresponding to each sliding window to obtain a cumulative result; perform peak search on the cumulative results corresponding to each sliding window, and determine the candidate frequency deviation estimate value based on the maximum peak in the peak search result.

[0073] In a third aspect, an embodiment of the present invention provides a synchronization code detection system in a low-orbit satellite communication system, the system comprising:

[0074] Central processing unit CPU, used for initializing and starting the synchronization code detection module;

[0075] The synchronization code detection module is used to execute the method described in the first aspect above.

[0076] In a fourth aspect, an embodiment of the present invention provides an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus;

[0077] Memory, used to store computer programs;

[0078] The processor is used to implement any of the above methods when executing the program stored in the memory.

[0079] In a fifth aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, any of the above-mentioned methods is implemented.

[0080] Beneficial effects of the embodiments of the present invention:

[0081] The embodiment of the present invention provides a synchronization code detection method, system and device in a low-orbit satellite communication system. First, the maximum frequency deviation range value of the low-orbit satellite communication system is obtained, and the maximum frequency deviation range value is divided into different frequency deviation values, and then the synchronization code is captured for the first received signal of the input signal stream at the frequency deviation values ​​of different frequency deviation values, and the initial frequency deviation estimation value is obtained according to the capture result, so as to realize the synchronization code capture in the different frequency deviation values. However, due to the existence of Doppler frequency deviation and the large number of time slots required to complete the divided capture, the synchronization code position obtained by the divided capture is offset, and then the initial frequency deviation estimation value obtained by the divided capture is used to compensate the second received signal of the input signal stream, and the compensated second received signal is captured by the synchronization code to obtain the candidate synchronization code position confirmed by the rough compensation. Furthermore, based on relatively accurate candidate synchronization code positions, frequency offset estimation is performed on synchronization code data in multiple time slots to obtain more accurate candidate frequency offset estimation values, and the more accurate candidate frequency offset estimation values ​​are used to compensate for the third received signal of the input signal stream, and synchronization code capture is performed on the compensated third received signal to obtain a more accurate target synchronization code position through synchronous capture, thereby realizing synchronization code detection in low-orbit satellite communication systems.

[0082] Of course, it is not necessary to achieve all of the advantages described above at the same time to implement any product or method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0084] Figure 1 It is a principle block diagram of synchronization code detection in the related art;

[0085] Figure 2 A schematic diagram of the location of synchronization codes in a low-orbit satellite communication system;

[0086] Figure 3 A schematic flow chart of a synchronization code detection method in a low-orbit satellite communication system provided by an embodiment of the present invention;

[0087] Figure 4 A schematic diagram of a process of capturing by grading in a synchronization code detection method provided by an embodiment of the present invention;

[0088] Figure 5 A schematic diagram of a quantization process in a synchronization code detection method provided in an embodiment of the present invention;

[0089] Figure 6 A schematic diagram of a sliding-related flow chart in a synchronization code detection method provided in an embodiment of the present invention;

[0090] Figure 7 A schematic diagram of a flow chart of rough filling confirmation in the synchronization code detection method provided in an embodiment of the present invention;

[0091] Figure 8 A schematic diagram of a process of searching and measuring frequency in a synchronization code detection method provided in an embodiment of the present invention;

[0092] Fig. 9 A schematic diagram of a synchronization code capture implementation framework provided by an embodiment of the present invention;

[0093] Fig.10 A block diagram of the implementation principle of the quantization module provided in the embodiment of the present invention;

[0094] Fig.11 A block diagram of the synchronization code implementation principle provided by an embodiment of the present invention;

[0095] Fig.12 A block diagram of the principle of implementing the staggered selection provided by an embodiment of the present invention;

[0096] Fig.13 A block diagram of the time slot accumulation search implementation principle provided by an embodiment of the present invention;

[0097] Fig.14A time slot accumulation search state transition diagram provided by an embodiment of the present invention;

[0098] Fig.15 A frequency offset estimation FFT operation state transition diagram provided by an embodiment of the present invention;

[0099] Fig.16 A block diagram of the interface module implementation principle provided by the embodiment of the present invention;

[0100] Fig.17 This is a structural schematic diagram of a synchronization code detection device in a low-orbit satellite communication system in an embodiment of the present application;

[0101] Fig.18 This is a structural schematic diagram of a synchronization code detection system in a low-orbit satellite communication system in an embodiment of the present application;

[0102] Fig.19 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0103] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field based on this application belong to the scope of protection of the present invention.

[0104] Related Technology In terrestrial wireless communication systems (such as LTE, NR, etc.), the implementation process of synchronization code detection is as follows: Figure 1 As shown, after receiving the RF signal, the user equipment obtains the synchronization channel baseband signal ( Figure 1 The baseband signal is then synchronously multi-path frequency offset compensated ( Figure 1 The compensated signal is slidingly correlated with the local sequence in the sequence correlator, and the correlation result is output to the peak detection module to complete the search and detection of the correlation peak. Finally, the comparator is used to compare the multi-channel correlation peak results, and the branch correlation peak position with the largest peak value is selected as the synchronization point. The corresponding frequency offset compensation value is the Doppler frequency offset, and the synchronization detection result is obtained to complete the detection of the synchronization code.

[0105] With the development of the wireless communication industry, low-orbit satellite communication systems have become a new type of network communication system that has been vigorously developed in recent years. In low-orbit satellite communication systems, due to the high relative speed between low-orbit satellites and ground stations, the large dynamic and low signal-to-noise caused by the large attenuation of the satellite-to-ground link, the synchronization code detection method for ground wireless network scenarios cannot effectively implement synchronization code detection in low-orbit satellite communication systems. Moreover, as a new communication system, the low-orbit satellite communication system has a dedicated communication system. Especially for power-limited areas, spread spectrum technology is required to reduce signal power. In addition, the large Doppler frequency deviation problem caused by the high-speed movement of low-orbit satellites brings great difficulties to the user equipment's initial access to the cell synchronization search. Therefore, there is an urgent need for a synchronization code detection method applied to low-orbit satellite communication systems.

[0106] In order to realize the detection of synchronization code in low-orbit satellite communication system, the embodiment of the present invention takes low-orbit satellite communication as the application background and provides a synchronization code detection method, system and device in low-orbit satellite communication system. The synchronization code detection method in low-orbit satellite communication system provided by the embodiment of the present invention can be applied to the terminal, including: obtaining the maximum frequency deviation range value of the low-orbit satellite communication system, dividing the maximum frequency deviation range value into grades to obtain frequency deviation values ​​of different grades, performing synchronization code capture on the first receiving signal of the input signal stream under the frequency deviation values ​​of different grades respectively, and obtaining an initial frequency deviation estimation value according to the capture result; using the initial frequency deviation estimation value to compensate the second receiving signal of the input signal stream, and performing synchronization code capture on the compensated second receiving signal to obtain a candidate synchronization code position confirmed by rough compensation; based on the candidate synchronization code position, performing frequency deviation estimation on the synchronization code data in multiple time slots to obtain a candidate frequency deviation estimation value; using the candidate frequency deviation estimation value to compensate the third receiving signal of the input signal stream, and performing synchronization code capture on the compensated third receiving signal to obtain the target synchronization code position for synchronization capture.

[0107] In an embodiment of the present invention, the maximum frequency deviation range value of the low-orbit satellite communication system is first obtained, and the maximum frequency deviation range value is divided into grades to obtain frequency deviation values ​​of different grades, and then the first received signal of the input signal stream is captured under the frequency deviation values ​​of different grades, and the initial frequency deviation estimation value is obtained according to the capture result, so as to realize the graded capture of the synchronization code. However, due to the existence of Doppler frequency deviation and the number of time slots required to complete the graded capture is usually large, the synchronization code position obtained by the graded capture is offset, and then the initial frequency deviation estimation value obtained by the graded capture is used to compensate the second received signal of the input signal stream, and the compensated second received signal is captured by the synchronization code to obtain the candidate synchronization code position confirmed by the rough compensation. Furthermore, based on the relatively accurate candidate synchronization code position, the synchronization code data in multiple time slots is estimated by frequency deviation, and a more accurate candidate frequency deviation estimation value is obtained, and the third received signal of the input signal stream is compensated by the more accurate candidate frequency deviation estimation value, and the third received signal after compensation is captured by the synchronization code, so as to obtain a more accurate target synchronization code position by synchronous capture, so as to realize the detection of the synchronization code in the low-orbit satellite communication system.

[0108] The low-orbit satellite communication system transmits control data and service data according to a fixed time slot length. In the downlink, the synchronization code occupies part of the time slot length and the starting position is unknown, such as Figure 2 As shown, the first time slot ( Figure 2 Middle time slot 1), the second time slot ( Figure 2 middle time slot 2), ..., nth time slot ( Figure 2 The starting position of the synchronization code in the time slot n) may be different. Since the length of the synchronization code in a single time slot is limited and the signal-to-noise ratio is low, it is difficult to complete the synchronization code capture using the method in the above-mentioned related technology, and multi-time slot accumulation detection is required. Compared with the ground wireless communication system, the low-orbit satellite communication system faces three main problems in realizing multi-time slot accumulation: the first is the unknown position of the synchronization code; the second is the code chip scaling problem caused by the large Doppler frequency shift; and the third is the engineering realization problem of multi-time slot accumulation.

[0109] The embodiment of the present invention uses a method of capturing synchronization codes multiple times and searching and measuring frequencies to realize the detection of synchronization codes. Figure 3 As shown, Figure 3 A schematic flow chart of a synchronization code detection method in a low-orbit satellite communication system provided by an embodiment of the present invention, the method comprising the following steps:

[0110] S301, obtain the maximum frequency deviation range value of the low-orbit satellite communication system, divide the maximum frequency deviation range value into grades, obtain frequency deviation values ​​of different grades, perform synchronization code capture on the first receiving signal of the input signal stream at the frequency deviation values ​​of different grades, and obtain an initial frequency deviation estimation value according to the capture result.

[0111] Because the frequency deviation value of the received signal in the input signal stream is not clear at the beginning of the synchronization code detection, the maximum frequency deviation range value of the low-orbit satellite communication system is first obtained. In an example, the maximum frequency deviation range value of the low-orbit satellite communication system can be calculated based on the satellite orbit parameters of the low-orbit satellite (such as orbital altitude), communication frequency band and other information. The specific calculation of the maximum frequency deviation range value can refer to the relevant technical implementation. Then, the maximum frequency deviation range value is evenly divided into N grades to obtain N frequency deviation values ​​in different grades. Among them, N is a positive integer, and the value of N can be determined according to the number of time slots accumulated during the synchronization code capture process and the phase error required to track the received signal, and can also be set according to the accuracy of the synchronization capture processing.

[0112] Exemplarily, the maximum frequency deviation range is ±30KHZ (kilohertz), and the frequency deviation value of each level is 2KHZ, that is, the maximum frequency deviation range is evenly divided into 30 levels, and the frequency deviation value corresponding to each level is ±1KHZ.

[0113] For each frequency deviation value of each bin, the frequency deviation compensation method in the relevant technology is used to compensate the frequency deviation value of the bin to the first received signal of the input signal stream to obtain the compensated first received signal, and then the compensated first received signal is subjected to synchronization code capture to obtain the capture result of the synchronization code capture of the compensated first received signal under different frequency deviation values ​​of the bins. The capture result may include the starting position of the synchronization code and the cumulative correlation peak, and then the frequency deviation value of the bin corresponding to the maximum peak value is selected as the initial frequency deviation estimation value, thereby realizing the binned capture of the synchronization code. Among them, the cumulative correlation peak represents the result obtained by adding the first received signal sequence corresponding to the compensated first received signal to the local sequence after operation. The local sequence can specifically be a local PSC (Primary Synchronisation Code) sequence. The first received signal of the input signal stream can be a signal in the data stream output by the DFE (Digital FrontEnd) of the terminal. The DFE is mainly used to perform digital processing such as frequency conversion filtering on the received signal.

[0114] In an embodiment of the present invention, the process of capturing the synchronization code of the first received signal of the input signal stream at different frequency deviation values ​​can be implemented in a serial manner or in a parallel manner. Compared with the parallel manner, the serial manner can save resources.

[0115] S302, compensating a second received signal of an input signal stream by using an initial frequency offset estimation value, and performing synchronization code capture on the compensated second received signal to obtain a candidate synchronization code position that is roughly confirmed.

[0116] The received signal is input in the form of a data stream. When the initial frequency offset estimation value is obtained by the step-by-step capture in step S301, due to the existence of Doppler frequency offset and the number of time slots required to complete the synchronization code step-by-step capture is usually relatively large (i.e., the required time is relatively long), the starting position of the synchronization code obtained by the step-by-step capture in step S301 is actually greatly offset. At this time, the initial frequency offset estimation value obtained by the step-by-step capture is used to compensate the second received signal of the input signal stream to obtain the compensated second received signal, and then the synchronization code is captured on the compensated second received signal to obtain the current latest synchronization code position and use it as a candidate synchronization code position to achieve rough compensation confirmation of the synchronization code. Among them, the second received signal of the input signal stream is the latest received signal, which is later than the first received signal in time.

[0117] In the embodiment of the present invention, the process of synchronization code capture is consistent, and within the time range of synchronization code capture, the frequency deviation value is considered to be a fixed value.

[0118] S303, based on the candidate synchronization code positions, perform frequency offset estimation on the synchronization code data in multiple time slots to obtain candidate frequency offset estimation values.

[0119] Because the initial frequency deviation estimation value is obtained by performing synchronization code capture on the first received signal of the input signal stream under the frequency deviation values ​​of different bins within the maximum frequency deviation range value, that is, a smaller range of frequency deviation values ​​are preliminarily located from the larger range of maximum frequency deviation range values, the candidate synchronization code position is obtained by performing synchronization code capture on the second received signal of the input signal stream under the initial frequency deviation estimation value, that is, the synchronization code position corresponding to the initial frequency deviation estimation value is roughly supplemented and confirmed, and thus the candidate synchronization code position obtained in the above step S302 is more accurate than the synchronization code starting position obtained by bin capture. Furthermore, according to the obtained candidate synchronization code position, the synchronization code data in multiple time slots is estimated for frequency deviation, so that a more accurate frequency deviation estimation value can be obtained, thereby realizing the search and frequency measurement process for the frequency deviation value. Among them, the number of multiple time slots can be set according to actual needs, and the embodiment of the present invention is not specifically limited here.

[0120] S304: Compensate the third received signal of the input signal stream by using the candidate frequency offset estimation value, and perform synchronization code capture on the compensated third received signal to obtain a target synchronization code position for synchronization capture.

[0121] On the basis of obtaining a more accurate frequency offset estimation value, the candidate frequency offset estimation value is further used to compensate the third received signal of the input signal stream to obtain the compensated third received signal, and then the compensated third received signal is subjected to synchronization code capture to obtain the current latest synchronization code position and use it as the final target synchronization code position to complete the synchronization code detection. The third received signal of the input signal stream is the current latest received signal and is later than the second received signal in time.

[0122] In an embodiment of the present invention, the maximum frequency deviation range value of the low-orbit satellite communication system is first obtained, and the maximum frequency deviation range value is divided into grades to obtain frequency deviation values ​​of different grades, and then the first received signal of the input signal stream is captured under the frequency deviation values ​​of different grades, and the initial frequency deviation estimation value is obtained according to the capture result, so as to realize the graded capture of the synchronization code. However, due to the existence of Doppler frequency deviation and the number of time slots required to complete the graded capture is usually large, the synchronization code position obtained by the graded capture is offset, and then the initial frequency deviation estimation value obtained by the graded capture is used to compensate the second received signal of the input signal stream, and the compensated second received signal is captured by the synchronization code to obtain the candidate synchronization code position confirmed by the rough compensation. Furthermore, based on the relatively accurate candidate synchronization code position, the synchronization code data in multiple time slots is estimated by frequency deviation, and a more accurate candidate frequency deviation estimation value is obtained, and the third received signal of the input signal stream is compensated by the more accurate candidate frequency deviation estimation value, and the third received signal after compensation is captured by the synchronization code, so as to obtain a more accurate target synchronization code position by synchronous capture, so as to realize the detection of the synchronization code in the low-orbit satellite communication system.

[0123] In a possible implementation manner, the implementation process of performing synchronization code capture on the first received signal of the input signal stream at frequency offset values ​​of different bins in the above step S301, and obtaining the initial frequency offset estimation value according to the capture result may include:

[0124] Step 1: for each frequency offset value of a bin, the frequency offset value of the bin is compensated to the first received signal of the input signal stream, and the compensated first received signal is subjected to synchronization code capture to obtain a cumulative correlation peak obtained by operating the first received signal sequence and the local sequence for each bin; wherein the cumulative correlation peak represents a result obtained by accumulating the first received signal sequence and the local sequence after the operation;

[0125] Step 2: Based on the cumulative correlation peak of each bin, select the frequency offset value of the bin corresponding to the largest peak value as the initial frequency offset estimation value.

[0126] For each frequency deviation value of each bin, the frequency deviation compensation method in the related technology is used to compensate the frequency deviation value of the bin to the first received signal of the input signal stream to obtain the compensated first received signal, and then the compensated first received signal is synchronized and captured, and the first received signal sequence corresponding to the compensated first received signal is point-to-point correlated with the local sequence, and the correlation results are accumulated to obtain the cumulative correlation peak of the first received signal sequence and the local sequence. The point-to-point correlation can be point-to-point addition or point-to-point multiplication, etc. The cumulative correlation peak represents the result of the accumulation after the correlation operation between the first received signal sequence and the local sequence.

[0127] For the cumulative correlation peak of each bin, compare the peak values ​​of the cumulative correlation peaks of each bin, and select the frequency deviation value of the bin corresponding to the maximum correlation peak as the initial frequency deviation estimate. Correspondingly, the subscript corresponding to the maximum peak correlation peak can be used as the starting position of the synchronization code captured by the bin.

[0128] In the embodiment of the present invention, the first received signal of the input signal stream under different frequency offset values ​​of different bins is captured in different bins through the above steps 1 and 2.

[0129] In one possible implementation, see Figure 4 , Figure 4 A schematic flow chart of the stepwise capture in the synchronization code detection method provided in the embodiment of the present invention, corresponding to the above step 1, for the frequency offset value of each step, the frequency offset value of the step is compensated to the first received signal of the input signal stream, and the synchronization code is captured on the compensated first received signal, and the cumulative correlation peak obtained by calculating the first received signal sequence and the local sequence for each step is obtained, including:

[0130] S401, for each frequency offset value in each bin, compensating the frequency offset value in the bin into a first received signal in an input signal stream to obtain a compensated first received signal.

[0131] S402: Perform quantization processing on the compensated first received signal to generate a first received signal sequence.

[0132] A received signal is input in the form of a data stream. When the number of sampling points of the compensated first received signal reaches a preset length, an average value is calculated for the values ​​of the preset length of sampling points, and a compression threshold is determined based on the average value and the number of bits after quantization compression. Then, based on the determined compression threshold, a numerical mapping is performed on the value of each sampling point in the compensated first received signal to achieve bit compression of the value of each sampling point in the compensated first received signal to obtain compressed data. Then, a data packet is generated from the compressed data stream according to a downlink spread spectrum frame protocol to obtain a first received signal sequence. The first received signal sequence includes multiple data packets, and each data packet includes a sampling time slot identifier.

[0133] The sampling time slot identifier is used to indicate the time slot number formed when the receiving end samples the received signal. The preset length can be set according to actual needs. For example, the preset length is 2 t , t is an integer greater than 1, such as 1024, 2048, etc.

[0134] S403: Perform an operation on the first received signal sequence and the local sequence to obtain a first operation result.

[0135] In one example, the operation performed on the first received signal sequence and the local sequence may be a sliding correlation operation. The sliding correlation operation is a time domain capture method, the principle of which is to perform sliding accumulation of the local sequence and the first received signal sequence within a fixed window length to obtain a correlation result. Specifically, a first preset number of data is taken out from the first received signal sequence in turn, and point-to-point multiplication is performed with the local sequence to obtain multiple mutual correlation sequences. For each mutual correlation sequence, the values ​​in the mutual correlation sequence are summed according to a second preset number to obtain an intermediate sequence, and then the values ​​in the intermediate sequence are summed according to a second preset number until two sum values ​​are obtained, and then the two sum values ​​are respectively modulo-operated, and the modulo values ​​are summed to obtain the first operation result.

[0136] Exemplarily, the local sequence contains 100 data, and the first received signal sequence contains 1000 data. 100 data are taken out from the first received signal sequence in turn, and point-to-point multiplication is performed with the local sequence to obtain multiple mutual correlation sequences. Then, the data in each mutual correlation sequence is slidingly accumulated according to a second preset number, that is, a sliding correlation operation.

[0137] The first operation result includes a sampling time slot identifier, and the sampling time slot identifier included in the first operation result is consistent with the sampling time slot identifier included in the data packet of the first received signal sequence. The first preset number is not less than the second preset number. For example, the first preset number can be 2 a , a is an integer greater than 1, the second preset number can be 4, and so on.

[0138] S404, based on the sampling time slot identifier and the corresponding relationship between the preset time slot and the selection coefficient, perform staggered selection on the first operation result to select corresponding branch data.

[0139] In a possible implementation, this step may be implemented by reading a correspondence table between preset time slots and selection coefficients, determining the starting sampling point for the first operation result under different time slots according to the correspondence between the sampling time slot identifier, the time slot and the selection coefficient, and obtaining the branch data under the corresponding time slot.

[0140] The first received signal sequence includes a sampling time slot identifier. A sliding correlation operation is performed on the first received signal sequence and the local sequence. The first operation result obtained also includes the sampling time slot identifier. Then, the corresponding relationship table between the preset time slot and the selection coefficient can be queried through the sampling time slot identifier to determine the starting sampling point of the first operation result under different time slots to obtain the branch data under the corresponding time slot.

[0141] S405, performing accumulation operation and peak search on the branch data corresponding to the multiple time slots to obtain the accumulated correlation peak of the bin.

[0142] The branch data corresponding to multiple time slots are added point-to-point to obtain the cumulative operation result, and the peak value of the cumulative operation result is searched to obtain the cumulative correlation peak of the bin, so as to further select the frequency deviation value of the bin corresponding to the largest peak value as the initial frequency deviation estimate value for each bin of the cumulative correlation peaks.

[0143] In an embodiment of the present invention, for each frequency deviation value of a bin, the frequency deviation value of the bin is compensated to the first received signal of the input signal stream to obtain the compensated first received signal, and then the compensated first received signal is quantized, synchronization code correlated, staggered selected, and time slot accumulation searched to determine the position of the maximum correlation peak value in the time slot, and obtain the synchronization code position and the initial frequency deviation estimate.

[0144] In one possible implementation, see Figure 5 The above step S402 performs quantization processing on the compensated first received signal to generate a first received signal sequence, and the implementation process may include:

[0145] S501, when the number of sampling points of the compensated first received signal accumulates to a preset length, calculating the average of the preset length of sampling point values ​​in the compensated first received signal.

[0146] The received signal is input in the form of a data stream. When it is determined that the number of sampling points of the compensated first received signal accumulates to a preset length, the average of the preset length of sampling point values ​​in the compensated first received signal is calculated.

[0147] Exemplarily, the compensated first received signal is a complex number with a preset length of 1024. When it is determined that the number of sampling points of the compensated first received signal accumulates to 1024, the means of the real and imaginary parts of the 1024 accumulated sampling points in the compensated first received signal are calculated respectively, and then the means of the real and imaginary parts are summed and averaged to obtain the mean of the 1024 sampling point values ​​in the compensated first received signal. For example, the 1024 sampling points in the compensated first received signal are expressed as: s=s1+s2+s3+…+s1024. Correspondingly, the average of the 1024 sampling points in the compensated first received signal can be expressed as: avg=((Re{s1}+Re{s2}+…+Re{s1020}) / 1024+(Im{s1}+Im{s2}+…+Im{s1024}) / 1024) / 2, wherein Re{s1} represents the real part of the first sampling point, and Im{s1} represents the imaginary part of the first sampling point.

[0148] S502: Determine a compression threshold based on the mean value.

[0149] In one example, the compression threshold can be determined according to the mean and the number of bits after quantization compression. Exemplarily, the compensated first received signal is a baseband data stream with a width of 16 bits, and the number of bits after quantization compression is a width of 5 bits, then the number of compression thresholds is 7, and the values ​​of each compression threshold are 1 / 3 mean, 2 / 3 mean, 3 / 3 mean, 4 / 3 mean, 5 / 3 mean, 6 / 3 mean, and 7 / 3 mean, respectively.

[0150] Optionally, the above average value and compression threshold may be calculated at the beginning of a time slot, a certain effective time length may be set for the compression threshold, and the compression threshold may be re-determined when the effective time length is exceeded.

[0151] S503 , based on the value of each sampling point in the compensated first received signal and the compression threshold, perform bit compression on the value of each sampling point in the compensated first received signal to obtain compressed data.

[0152] Exemplarily, the compression thresholds are 1 / 3 mean, 2 / 3 mean, 3 / 3 mean, 4 / 3 mean, 5 / 3 mean, 6 / 3 mean, and 7 / 3 mean, respectively. When the value of the sampling point in the compensated first received signal (here, the absolute value of the amplitude of the sampling point) is in the interval 0-1 / 3 mean, the mark value of the sampling point is set to 0; when the value of the sampling point in the compensated first received signal is in the interval 1 / 3 mean-2 / 3 mean, the mark value of the sampling point is set to 1; when the value of the sampling point in the compensated first received signal is in the interval 2 / 3 mean-3 / 3 mean, the mark value of the sampling point is set to 2; When the value of the sampling point in the compensated first received signal is between the mean of 3 / 3 and the mean of 4 / 3, the mark value of the sampling point is set to 3; when the value of the sampling point in the compensated first received signal is between the mean of 4 / 3 and the mean of 5 / 3, the mark value of the sampling point is set to 4; when the value of the sampling point in the compensated first received signal is between the mean of 5 / 3 and the mean of 6 / 3, the mark value of the sampling point is set to 5; when the value of the sampling point in the compensated first received signal is between the mean of 6 / 3 and the mean of 7 / 3, the mark value of the sampling point is set to 6; when the value of the sampling point in the compensated first received signal is greater than the mean of 7 / 3, the mark value of the sampling point is set to 7. Further, when the real part of the sampling point in the compensated first received signal is greater than or equal to 0, the value of the sampling point is converted to the mark value ×2+1; when the real part of the sampling point in the compensated first received signal is less than 0, the value of the sampling point is converted to the mark value ×(-2)+1, so as to achieve bit compression of the values ​​of each sampling point in the compensated first received signal and obtain compressed data.

[0153] S504: Generate a first received signal sequence based on the compressed data.

[0154] The compressed data stream is used to generate data packets according to the downlink spread spectrum frame protocol to obtain a first received signal sequence, which includes multiple data packets, each of which may include a sampling time slot identifier, a frame sequence number, and compressed data.

[0155] In the embodiment of the present invention, the compensated first received signal is quantized and compressed, thereby reducing the resources consumed in the subsequent processing of the received signal.

[0156] In one possible implementation, see Figure 6 The implementation process of performing operation on the first received signal sequence and the local sequence to obtain the first operation result in step S403 may include:

[0157] S601, sequentially extract a first preset number of data from a first received signal sequence to obtain a third received signal sequence.

[0158] For example, the first preset number may be 2a , a is an integer greater than 1, and 2 are taken from the first received signal sequence in sequence a data, and obtain a third received signal sequence. The extracted third received signal sequence may be, for example, the 0th to the 2nd a -1 sampling point corresponding to the data, 1st to 2nd a The data corresponding to the sampling points, from 2nd to 2nd a +Data corresponding to 1 sampling point, and so on.

[0159] S602: For each third received signal sequence, perform point-to-point multiplication on the third received signal sequence and the local sequence to obtain a cross-correlation sequence.

[0160] Exemplarily, the length of the extracted third received signal sequence is the same as the length of the local sequence, and each third received signal sequence contains 2 a data, the local sequence is 2 a A real number such as ±1 is used to multiply a third received signal sequence with the local sequence point-to-point to obtain a cross-correlation sequence. Accordingly, each cross-correlation sequence obtained also contains 2 a data.

[0161] S603, for the mutual correlation sequence, summing up the values ​​in the mutual correlation sequence according to a second preset number to obtain an intermediate sequence, and then summing up the values ​​in the intermediate sequence according to the second preset number until two sum values ​​are obtained.

[0162] Exemplarily, the second preset number is 4, then for each mutual correlation sequence, 2 of the mutual correlation sequences are a The data are summed up in groups of 4 to get the value containing 2 a / 4 data intermediate sequences, the intermediate sequences are summed up in groups of 4, each summation reduces the amount of data by 4 times until two summation values ​​are obtained.

[0163] S604, performing a modulo operation on the two sum values ​​respectively, and summing the modulo values ​​to obtain a first operation result.

[0164] The two summed values ​​obtained are both complex data, and approximate modulo operations are performed on the two summed values ​​respectively, and the final modulo values ​​are summed to obtain a first operation result, which is a real number result for a third received signal sequence.

[0165] In one possible implementation, see Figure 7 , Figure 7 A schematic flow chart of rough filling confirmation in the synchronization code detection method provided in an embodiment of the present invention, corresponding to the implementation process of the above step S302, includes:

[0166] S701, compensating a second received signal of an input signal stream by using an initial frequency offset estimation value to obtain a compensated second received signal.

[0167] S702: Perform quantization processing on the compensated second received signal to generate a second received signal sequence.

[0168] The second received signal sequence includes a plurality of data packets, each of which includes a sampling time slot identifier.

[0169] S703: Perform an operation on the second received signal sequence and the local sequence to obtain a second operation result.

[0170] The second operation result includes a sampling time slot identifier.

[0171] S704, based on the sampling time slot identifier and the corresponding relationship between the preset time slot and the selection coefficient, perform staggered selection on the second operation result to select corresponding branch data.

[0172] S705, performing accumulation operation and peak search on the branch data corresponding to the multiple time slots to obtain the accumulated correlation peak.

[0173] The implementation process of step S701 to step S705 may refer to the implementation process of step S401 to step S405 described above, and the embodiments of the present invention will not be repeated here.

[0174] S706, determining a candidate synchronization code position based on the position of the maximum peak value in the cumulative correlation peaks.

[0175] In one example, the subscript position of the position where the maximum peak value in the cumulative correlation peak is located is determined as the candidate synchronization code position.

[0176] In an embodiment of the present invention, an initial frequency offset estimate is obtained by binning capture. However, due to the existence of Doppler frequency offset and the fact that the number of time slots required to complete the binning capture of the synchronization code is usually relatively large (i.e., the time required is relatively long), the starting position of the synchronization code obtained by binning capture actually has a large offset. At this time, the initial frequency offset estimate is used to compensate the second received signal of the input signal stream to obtain a compensated second received signal. The compensated second received signal is then quantized, synchronization code correlated, staggered selected, and time slot accumulated searched to obtain a relatively accurate and latest synchronization code position and use it as a candidate synchronization code position.

[0177] In a possible implementation manner, the implementation process of performing accumulation operation and peak search on the branch data corresponding to multiple time slots in step S705 to obtain the accumulated correlation peak includes:

[0178] Step 3: for the branch data in each time slot, perform point-to-point accumulation operation on the data in each branch data to obtain a cumulative sum value;

[0179] Step 4: Perform peak search on the cumulative sum value to obtain the cumulative correlation peak.

[0180] Exemplarily, the branch data in the first time slot is added point-to-point with each data in the branch data in the second time slot, and then added point-to-point with each data in the branch data in the third time slot, and so on, to obtain the cumulative sum value of the branch data corresponding to multiple time slots, the number of data included in the cumulative sum value is the same as the number of data included in the branch data in one time slot, and then the cumulative sum value is peak searched to obtain the cumulative correlation peak.

[0181] The branch data corresponding to a plurality of time slots are accumulated and peak searched to obtain an accumulated correlation peak, so as to determine the candidate synchronization code position based on the position of the maximum peak in the accumulated correlation peak.

[0182] In one possible implementation, see Figure 8 In the above step S303, based on the candidate synchronization code position, frequency offset estimation is performed on the synchronization code data in multiple time slots. The implementation process of obtaining the candidate frequency offset estimation value may include:

[0183] S801, based on the candidate synchronization code positions, determine the starting position, sliding window spacing and number of sliding windows of the synchronization code data in each time slot.

[0184] S802, based on the starting position, the sliding window spacing and the number of sliding windows, for the synchronization code data in each time slot, calculate the data in each sliding window to obtain multiple third calculation results.

[0185] Exemplarily, taking the FFT operation performed on the data in each sliding window as an example, the multiple time slots are 30 time slots, the sliding window spacing of the sliding window of the synchronization code data in each time slot is 1024, the number of sliding windows is 10, and when the candidate synchronization code positions are determined, the starting positions of the sliding windows of the synchronization code data in each time slot are determined to be 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 respectively. Correspondingly, for the synchronization code data in each time slot, FFT operation is performed on the 0th-1023rd data in the 1st sliding window, the 1st-1024th data in the 2nd sliding window, the 2nd-1025th data in the 3rd sliding window, the 3rd-1026th data in the 4th sliding window, the 4th-1027th data in the 5th sliding window, the 5th-1028th data in the 6th sliding window, the 6th-1029th data in the 7th sliding window, the 7th-1030th data in the 8th sliding window, the 8th-1031st data in the 9th sliding window, and the 9th-1032nd data in the 10th sliding window to obtain the FFT operation results of the synchronization code data in different time slots in different sliding windows, that is, the third operation result.

[0186] When the synchronization code data in the sliding window is less than 1024, the insufficient part is padded with zeros.

[0187] S803, calculating the cumulative sum of the third operation results in multiple time slots corresponding to each sliding window to obtain a cumulative result.

[0188] S804, performing peak search on the accumulated results corresponding to each sliding window, and determining a candidate frequency offset estimation value according to the maximum peak value in the peak search results.

[0189] Exemplarily, the cumulative sum of the FFT operation results in 30 time slots in the 1st to 10th sliding windows is calculated to obtain 10 cumulative results, and peak search is performed on the 10 cumulative results. The maximum peak is determined from each cumulative result, and the index (subscript) of the maximum peak is determined as the frequency offset position, and then the candidate frequency offset estimate is calculated based on the frequency offset position.

[0190] In an embodiment of the present invention, the maximum frequency deviation range value of the low-orbit satellite communication system is first obtained, and the maximum frequency deviation range value is divided into grades to obtain frequency deviation values ​​of different grades, and then the first received signal of the input signal stream is captured under the frequency deviation values ​​of different grades, and the initial frequency deviation estimation value is obtained according to the capture result, so as to realize the graded capture of the synchronization code. However, due to the existence of Doppler frequency deviation and the number of time slots required to complete the graded capture is usually large, the synchronization code position obtained by the graded capture is offset, and then the initial frequency deviation estimation value obtained by the graded capture is used to compensate the second received signal of the input signal stream, and the compensated second received signal is captured by the synchronization code to obtain the candidate synchronization code position confirmed by the rough compensation. Further, based on the relatively accurate candidate synchronization code position, the synchronization code data in multiple time slots is estimated by frequency deviation, and a more accurate candidate frequency deviation estimation value is obtained, and the third received signal of the input signal stream is compensated by the more accurate candidate frequency deviation estimation value, and the third received signal after compensation is captured by the synchronization code, so as to obtain a more accurate target synchronization code position by synchronous capture, so as to realize the detection of the synchronization code in the low-orbit satellite communication system.

[0191] The following describes in detail how to perform the step-by-step capture, coarse compensation confirmation, search and frequency measurement, and synchronous capture in the embodiment of the present invention from the perspective of hardware.

[0192] First, the complete process of realizing synchronization code detection in the embodiment of the present invention is described in detail from the perspective of hardware.

[0193] See also Fig. 9 , Fig. 9A schematic diagram of a synchronization code capture implementation framework provided for an embodiment of the present invention. RFIC (Radio Frequency Integrated Circuits) receives the RF front-end analog signal, performs analog-to-digital conversion on the received analog signal to obtain IQ data, and sends the IQ data to RFIF (Radio Frequency Interface). RFIF receives the IQ data sent by RFIC and forwards it to DFE (Digital Front End). DFE performs digital processing such as frequency conversion filtering on the received signal, and then inputs the output data stream into the synchronization code capture module (SyncCodeCapture) for synchronization code capture calculation. CPU (Central Processing Unit) mainly completes the control and parameter configuration of the synchronization code capture process. In an embodiment of the present invention, data transmission and control between CPU, SyncCodeCapture, DFE and RFIF are all interacted through a bus, such as AHB (Advanced High Performance Bus). Optionally, SyncCodeCapture can be deployed as a hardware accelerator in the communication subsystem of the low-orbit satellite communication system, which can significantly shorten the spread spectrum capture processing delay, reduce the processing pressure of the DSP (Digital Signal Process) / CPU, and provide high-precision synchronization information for subsequent spread spectrum tracking, time slot synchronization, frame synchronization, etc.

[0194] Among them, SyncCodeCapture includes two functions, one is synchronization code capture, and the other is frequency offset estimation. Synchronization code capture is used to determine the position of the synchronization code in the receiving time slot. Specifically, the received signal of the input signal stream (baseband data from DFE) is quantized, synchronized, selected, and searched for in time slot accumulation to determine the position of the maximum correlation peak in the time slot, and obtain the synchronization code position. The synchronization code position can be reported to the CPU through interrupts and / or result registers. Frequency offset estimation is used to measure the frequency offset in the synchronization signal. Specifically, the received signal of the input signal stream is quantized, synchronized, and estimated (including data caching, FFT calculation, and frequency domain accumulation search) to determine the frequency offset value. The frequency offset value can be reported to the CPU through interrupts and / or result registers. Alternatively, the frequency offset estimation determines the frequency offset position, reports the frequency offset position to the CPU, and the CPU converts it into the final frequency offset value. In the embodiment of the present invention, the CPU can schedule the SyncCodeCapture module to perform different functions to respectively realize the tiered capture, coarse compensation confirmation, search frequency measurement, and synchronous capture.

[0195] In an example, the process of CPU combining DFE and SyncCodeCapture to realize synchronization code capture includes:

[0196] Under the control of the upper-layer application, the CPU starts the synchronization code detection function, initializes and starts the DFE and SyncCodeCapture.

[0197] The CPU configures the parameters of DFE and SyncCodeCapture, such as the parameters of the filter in DFE, the number of bins in SyncCodeCapture, the number of bits after quantization compression, etc., and calls DFE and SyncCodeCapture to execute bin capture instructions. DFE controls the receiving signal of the input signal stream to input SyncCodeCapture, and SyncCodeCapture executes the above step S301 to complete bin capture.

[0198] The CPU waits for the SyncCodeCapture bin capture completion interrupt, reads the cumulative correlation peak value, and determines whether all gear capture calculations are completed. If not, it returns to continue executing the bin capture instruction. If it is completed, it compares the cumulative correlation peak values ​​of all gears and selects the frequency deviation value of the bin corresponding to the maximum correlation peak value as the initial frequency deviation estimate.

[0199] The CPU executes the rough patch confirmation instruction, reconfigures the parameters of DFE and SyncCodeCapture according to the initial frequency offset estimation value obtained by the binned capture, and calls DFE and SyncCodeCapture to execute the above step S302 to complete the rough patch confirmation.

[0200] The CPU waits for the SyncCodeCapture rough patch confirmation completion interrupt, reads the maximum correlation peak value and the corresponding offset point in the rough patch confirmation stage, and determines the offset point as the synchronization code rough estimation position, that is, the candidate synchronization code position.

[0201] The CPU executes the search and frequency measurement instruction, configures the parameters of DFE and SyncCodeCapture according to the candidate synchronization code positions obtained by coarse patching, and calls DFE and SyncCodeCapture to execute the above step S303 to complete the search and frequency measurement.

[0202] The CPU waits for the SyncCodeCapture search and frequency measurement completion interrupt, and reads the maximum correlation peak value and the corresponding offset point in the search and frequency measurement phase, determines the offset point as the frequency offset position, and calculates the frequency offset estimate value, i.e., the candidate frequency offset estimate value, based on the frequency offset position.

[0203] The CPU executes the synchronous capture instruction, configures the parameters of DFE and SyncCodeCapture according to the candidate frequency offset estimation value obtained by searching and measuring the frequency, and calls DFE and SyncCodeCapture to execute the above step S304 to complete the synchronous capture.

[0204] The CPU waits for the SyncCodeCapture synchronization capture completion interrupt, and reads the maximum correlation peak value and the corresponding offset point in the synchronization capture stage, and determines the offset point as the precise estimation position of the synchronization code, that is, the target synchronization code position.

[0205] The CPU outputs the target synchronization code position and turns off DFE and SyncCodeCapture.

[0206] Next, the quantization function of SyncCodeCapture in the embodiment of the present invention is described in detail from the perspective of hardware.

[0207] See also Fig.10 , Fig.10 The quantization module provided in the embodiment of the present invention is a block diagram of the implementation principle. The quantization module (quant5bit) mainly implements the bit compression function and is at the forefront of SyncCodeCapture. It converts the 16-bit baseband data stream ( Fig.10 The quantization module input data stream is converted into a 5-bit wide data stream to reduce the resources consumed in subsequent data processing.

[0208] The quantization module mainly includes four parts: data accumulation (ACC), threshold calculation (Thcal), bit compression (BitCompress) and data generation (FrameGenerator). ACC is the raw data accumulation module, which is mainly used to accumulate preset lengths (such as 2 t Sampling points) of the original data (i.e., the received signal in the input signal stream after frequency offset compensation); Thcal is the threshold calculation module, which mainly calculates the 7 threshold values ​​required for bit compression according to the accumulated results of ACC; BitCompress is the bit compression module, which mainly performs numerical mapping on the received signal of the original high-bit-width input signal stream after frequency offset compensation according to the calculated threshold value to achieve the effect of bit compression; FrameGenerator is the frame data generation module, which mainly generates a data packet containing a sampling time slot identifier, a sampling point number, a frame number and compressed data according to the downlink spread spectrum frame protocol for the compressed data stream to facilitate subsequent data processing.

[0209] The functional implementation of the quantization module corresponds to the implementation process of the above-mentioned steps S501 to S504.

[0210] Again, the synchronization code related functions of SyncCodeCapture in the embodiment of the present invention are described in detail from the perspective of hardware.

[0211] The synchronization code correlation function is implemented through the scCorrelator (sliding correlation) module, which is mainly used to implement the synchronization code sliding correlation calculation. After the received signal in the input signal stream with frequency offset compensation is bit compressed, the data rate is extracted to a data stream consistent with the local sequence rate, and then cross-correlated with the local PSC sequence to output the correlation result (Corr).

[0212] See also Fig.11 , Fig.11 The synchronization code correlation implementation principle block diagram provided in the embodiment of the present invention is based on the synchronization sequence length of 2 a For example, in the synchronous code acquisition function, scCorrelator is used to quantize the input signal stream ( Fig.11 Input data) is pushed into the data with a length of 2 at a fixed rate a Register group Reg1-Reg2 a , from 2 a The data taken out from each register group is local-related to the local synchronization code sequence, which is a ±1 real number. This process completes the sign conversion through a logic circuit. Specifically, the taken out data is point-to-point multiplied with the local synchronization code sequence to obtain a cross-correlation sequence. This process does not consume clock cycles.

[0213] After correlation, we get 2 a The cross-correlation sequence of data is summed up in groups of 4. In the embodiment of the present invention, a summing adder is used to implement ( Fig.11 add4), output the second level Complex data, this process consumes 1 clock cycle. Based on the second-level output, the summation calculation is continued in groups of 4, a total of 32 groups, and the third-level output is Complex data, this process consumes 1 clock cycle. Similarly, the data summation is performed, and each level can reduce the data volume by 4 times, consuming 1 clock cycle; based on the output of two complex data at the last level, approximate modulus calculations are performed on the two data respectively, and finally the two modulus values ​​are summed to output a real number result, this process consumes 1 clock cycle.

[0214] scCorrelator is a key module in the synchronization code detection process. It needs to process and generate the correlation results of the data stream in real time. In the synchronization code capture function, scCorrelator converts the 2 aThe sum of the results is calculated and modulo, and the real correlation result is output; in the frequency deviation estimation function, scCorrelator converts the 2 a The results were divided into M groups (2 a / M=K), sum the K complex values ​​in each group and output M groups of complex results.

[0215] The functional implementation of the scCorrelator module corresponds to the implementation process of the above-mentioned steps S601 to S604.

[0216] Furthermore, the staggered selection function of SyncCodeCapture in the embodiment of the present invention is described in detail from the perspective of hardware.

[0217] The misalignment selection function is implemented by the corrMux module, which mainly completes the misalignment selection function of the scCorrelator output data stream. In the downlink synchronization channel of the low-orbit satellite communication system, due to the high-speed relative motion between the transmitter and the receiver, a compression or stretching effect will be produced on the received code chip. If it is not corrected, the correlation peak will be broadened or even split during multi-slot accumulation, which will seriously affect the synchronization code capture result.

[0218] In the present invention, the correction of chip scaling is achieved by delaying or advancing the sampling point as a whole within a certain period of time. Fig.12 As shown, Fig.12 The corrMux module is composed of a shift register group and a selector. The shift register group includes 2L+1 registers ( Fig.12 Corr-L to CorrL), L is an integer greater than 1, the input data (i.e., the scCorrelator output data stream) is pushed into the shift register group at a fixed rate, and the selector selects a certain data output ( Fig.12 When the time slot number is updated, a specific branch is selected according to the staggered selection table. The staggered selection table is generated in advance by the CPU and sent to SyncCodeCapture. In order to reduce the storage capacity of the staggered selection table, each time slot usually corresponds to a selection coefficient, and the selector is updated once the data of a time slot length is output.

[0219] Exemplarily, in time slot X, the offset selection table is read to select register Corr0 to output data. When the accumulated data of one time slot is updated to update the time slot number, the offset selection table is read according to the new time slot X+1 to select register Corr-L+5 to output data, and so on.

[0220] The functional implementation of the corrMux module corresponds to the implementation process of the above step S404.

[0221] Furthermore, the time slot accumulation search function of SyncCodeCapture in the embodiment of the present invention is described in detail from the perspective of hardware.

[0222] The time slot accumulation search function is implemented by the slotACC module, which is used to accumulate the correlation results of multiple time slot sliding. slot time slots, each time slot N sample The correlation accumulation operation of the points is performed, and the peak search and data summation of the correlation results are completed. The location of the peak is the starting position of the synchronization code. slot and N sample It can be set according to the needs, each time slot N sample The dots indicate that the input data for each time slot is N sample indivual.

[0223] like Fig.13 As shown, Fig.13 The slotACC module mainly includes a read / write control, an adder, a peak detection and a cumulative summation module. The input data of the slotACC module is the output data of the corrMux. The read / write control logic is based on N sample The data is added to the existing data in the ACC Buffer (memory) through the read / write address for the cycle, and then the addition result is stored in the ACC Buffer again. The peak detection and cumulative summation modules are based on N sample The maximum value search and cumulative summation are performed periodically. When the slotACC module completes the accumulation of all time slots, it outputs the final peak subscript, cumulative peak value and cumulative summation value. Among them, the peak subscript is the candidate synchronization code position.

[0224] For example, Fig.14 As shown, Fig.14 The time slot accumulation search state transition diagram provided by the embodiment of the present invention. When the slotACC module is started, it enters the waiting state from the idle state. When the data is valid, it enters the read data state, at which time the value of the corresponding position in the buffer is read, and then enters the addition and summation state, in which the input data is added to the buffer read data, and then enters the write data state, in which the addition result is stored in the buffer again. The above state transition can complete the accumulation of input data points of a time slot. When N is completed, slot After the data of each time slot is accumulated, slotACC can output the final result, and then the upper-level control logic will close the slotACC module.

[0225] The functional implementation of the slotACC module corresponds to the implementation process of the above step S705.

[0226] Furthermore, the frequency offset estimation function of SyncCodeCapture in the embodiment of the present invention is described in detail from the perspective of hardware.

[0227] The frequency deviation estimation function is implemented by the frequency deviation estimation module. The frequency deviation estimation module mainly completes the frequency precision estimation of the synchronization code capture function. Through the state machine control, the cached synchronization code group data is calculated and stored, and then the peak value search is performed on each group of merged data. Finally, the index corresponding to the maximum value is searched and the corresponding frequency deviation value is determined. For example, the serial input sampling data of the frequency deviation estimation is grouped into P data, and finally obtained by the PMF (Partial Matching Filter) algorithm. Q point FFT calculation, the remaining points are padded with zeros.

[0228] The function implementation of the frequency offset estimation module corresponds to the implementation process of the above steps S801 to S804.

[0229] For example, Fig.15 As shown, Fig.15 The frequency offset estimation FFT operation state transition diagram provided by the embodiment of the present invention. After the frequency offset estimation module is started, the enable is turned on, and the idle state enters the waiting state. When the waiting is completed, the cache data is read. If there is no cache data, the idle state is returned. If there is cache data and the cache reading is completed, the FFT operation is started and entered. If the FFT operation fails, the idle state is returned. After the FFT operation is completed, the FFT operation results are accumulated. The accumulation operation is completed (i.e. Fig.15 After the accumulation is completed, the system enters the sliding accumulation phase, performs the FFT operation in the smoothing operation, and enters the waiting state after the sliding accumulation is completed. After all the accumulation operations are completed, the system returns to the idle state. After the frequency offset estimation is completed, the upper control logic closes the frequency offset estimation module.

[0230] Furthermore, the functions of the interface module in the embodiment of the present invention are described in detail from the perspective of hardware.

[0231] For example, Fig.16 As shown, Fig.16The interface module provided in the embodiment of the present invention implements the principle block diagram. The interface module (spreadAHB) serves as the interface for SyncCodeCapture to communicate with the CPU. It realizes the communication between SyncCodeCapture and the CPU through the bus interface and the result register interrupt. Its function is to provide the CPU with a register configuration interface so that the upper layer application can control the process, configure parameters and read the results of SyncCodeCapture. The spreadAHB module mainly includes slave registers, an arbitrator and multiple register file modules. Through the arbitrator, the bus can realize the read and write control of multiple register file modules, providing scalable capabilities for the upgrade of SyncCodeCapture.

[0232] See also Fig.17 , Fig.17 This is a structural schematic diagram of a synchronization code detection device in a low-orbit satellite communication system in an embodiment of the present application, the device comprising:

[0233] The binning capture module 1701 is used to obtain the maximum frequency deviation range value of the low-orbit satellite communication system, bin the maximum frequency deviation range value to obtain frequency deviation values ​​of different bins, respectively perform synchronization code capture on the first received signal of the input signal stream under the frequency deviation values ​​of different bins, and obtain an initial frequency deviation estimation value according to the capture result;

[0234] A rough compensation confirmation module 1702 is used to compensate the second received signal of the input signal stream by using the initial frequency offset estimation value, and to capture the synchronization code of the compensated second received signal to obtain a candidate synchronization code position for rough compensation confirmation;

[0235] A search and frequency measurement module 1703 is used to estimate the frequency offset of the synchronization code data in multiple time slots based on the candidate synchronization code position to obtain a candidate frequency offset estimation value;

[0236] The synchronization capture module 1704 is used to compensate the third received signal of the input signal stream by using the candidate frequency offset estimation value, and perform synchronization code capture on the compensated third received signal to obtain a target synchronization code position for synchronization capture.

[0237] The synchronization code detection device in the low-orbit satellite communication system provided by the embodiment of the present invention is applied to first obtain the maximum frequency deviation range value of the low-orbit satellite communication system, and divide the maximum frequency deviation range value into different grades to obtain frequency deviation values ​​of different grades, and then respectively perform synchronization code capture on the first receiving signal of the input signal stream under the frequency deviation values ​​of different grades, and obtain the initial frequency deviation estimation value according to the capture result, thereby realizing the graded capture of the synchronization code. However, due to the existence of Doppler frequency deviation and the fact that the number of time slots required to complete the graded capture is usually large, the synchronization code position obtained by the graded capture is offset, and then the initial frequency deviation estimation value obtained by the graded capture is used to compensate the second receiving signal of the input signal stream, and the compensated second receiving signal is subjected to synchronization code capture to obtain the candidate synchronization code position confirmed by rough compensation. Furthermore, based on relatively accurate candidate synchronization code positions, frequency offset estimation is performed on synchronization code data in multiple time slots to obtain more accurate candidate frequency offset estimation values, and the more accurate candidate frequency offset estimation values ​​are used to compensate for the third received signal of the input signal stream, and synchronization code capture is performed on the compensated third received signal to obtain a more accurate target synchronization code position through synchronous capture, thereby realizing synchronization code detection in low-orbit satellite communication systems.

[0238] Optionally, the above-mentioned binning and capturing module 1701 includes:

[0239] The sub-module for capturing the frequency deviation of each bin is used to compensate the frequency deviation value of the bin into the first received signal of the input signal stream, and to capture the synchronization code of the compensated first received signal, so as to obtain the cumulative correlation peak obtained by operating the first received signal sequence and the local sequence in each bin; the cumulative correlation peak represents the result obtained by accumulating the operation of the first received signal sequence and the local sequence;

[0240] A frequency offset estimation submodule, for selecting the frequency offset value of the bin corresponding to the largest peak value as an initial frequency offset estimation value based on the cumulative correlation peaks of each bin;

[0241] Optionally, the above-mentioned sub-module for capturing by grading includes:

[0242] A first frequency offset compensation unit is used to compensate the frequency offset value of each bin into the first received signal of the input signal stream for the frequency offset value of each bin, so as to obtain a compensated first received signal;

[0243] A first quantization unit is used to perform quantization processing on the compensated first received signal to generate a first received signal sequence; the first received signal sequence includes a plurality of data packets, each of which includes a sampling time slot identifier;

[0244] A first operation unit, configured to operate the first received signal sequence and the local sequence to obtain a first operation result; the first operation result includes a sampling time slot identifier;

[0245] A first staggered selection unit, configured to perform staggered selection on the first operation result based on the sampling time slot identifier and the correspondence between the preset time slot and the selection coefficient, and select corresponding branch data;

[0246] The first peak search unit is used to perform accumulation calculation and peak search on the branch data corresponding to multiple time slots to obtain the accumulated correlation peak of the bin.

[0247] Optionally, the above-mentioned first quantization unit is specifically used to calculate the mean of the values ​​of a preset length of sampling points in the compensated first received signal when the number of sampling points of the compensated first received signal accumulates to a preset length; determine the compression threshold based on the mean; based on the value of each sampling point in the compensated first received signal and the compression threshold, perform bit compression on the value of each sampling point in the compensated first received signal to obtain compressed data; and generate a first received signal sequence based on the compressed data.

[0248] Optionally, the above-mentioned first operation unit is specifically used to take out a first preset number of data from the first received signal sequence in sequence to obtain a third received signal sequence; for each third received signal sequence, perform point-to-point multiplication of the third received signal sequence and the local sequence to obtain a mutual correlation sequence; for the mutual correlation sequence, sum the values ​​in the mutual correlation sequence according to a second preset number to obtain an intermediate sequence, and then sum the values ​​in the intermediate sequence according to the second preset number until two sum values ​​are obtained; perform modulo operation on the two sum values ​​respectively, and sum the modulo values ​​to obtain a first operation result.

[0249] Optionally, the above-mentioned first staggered selection unit is specifically used to read the correspondence table between preset time slots and selection coefficients, determine the starting sampling point of the first operation result in different time slots according to the correspondence between the sampling time slot identifier, the time slot and the selection coefficient, and obtain the branch data in the corresponding time slot.

[0250] Optionally, the rough patch confirmation module 1702 includes:

[0251] A second frequency offset compensation unit, configured to compensate a second received signal of the input signal stream by using the initial frequency offset estimation value to obtain a compensated second received signal;

[0252] A second quantization unit is used to perform quantization processing on the compensated second received signal to generate a second received signal sequence; the second received signal sequence includes a plurality of data packets, each of which includes a sampling time slot identifier;

[0253] A second operation unit, configured to operate the second received signal sequence and the local sequence to obtain a second operation result; the second operation result includes a sampling time slot identifier;

[0254] A second staggered selection unit, configured to perform staggered selection on the second operation result based on the sampling time slot identifier and the correspondence between the preset time slot and the selection coefficient, and select corresponding branch data;

[0255] A second peak search unit, used for performing accumulation operation and peak search on the branch data corresponding to a plurality of time slots to obtain a cumulative correlation peak;

[0256] The synchronization code position determination unit is used to determine the candidate synchronization code position based on the position of the maximum peak value in the cumulative correlation peak.

[0257] Optionally, the second peak search unit is specifically used to perform point-to-point accumulation operation on the data in each branch data in each time slot to obtain a cumulative sum value; and perform peak search on the cumulative sum value to obtain a cumulative correlation peak.

[0258] Optionally, the above-mentioned search and frequency measurement module 1703 is specifically used to determine the starting position, sliding window spacing and number of sliding windows of the sliding window of the synchronization code data in each time slot based on the candidate synchronization code position; based on the starting position, sliding window spacing and number of sliding windows, for the synchronization code data in each time slot, perform operations on the data in each sliding window to obtain multiple third operation results; calculate the cumulative sum of the third operation results in multiple time slots corresponding to each sliding window to obtain a cumulative result; perform peak search on the cumulative results corresponding to each sliding window, and determine the candidate frequency deviation estimate value according to the maximum peak in the peak search result.

[0259] See also Fig.18 , Fig.18 This is a structural schematic diagram of a synchronization code detection system in a low-orbit satellite communication system in an embodiment of the present application, and the system includes:

[0260] The central processing unit CPU1801 is used to initialize and start the synchronization code detection module;

[0261] The synchronization code detection module 1802 is used to execute any of the above synchronization code detection methods in a low-orbit satellite communication system.

[0262] The synchronization code detection system in the low-orbit satellite communication system provided by the embodiment of the present invention is applied to first obtain the maximum frequency deviation range value of the low-orbit satellite communication system, and divide the maximum frequency deviation range value into different bins to obtain frequency deviation values ​​of different bins, and then perform synchronization code capture on the first received signal of the input signal stream at the frequency deviation values ​​of different bins, and obtain the initial frequency deviation estimation value according to the capture result, thereby realizing the binned capture of the synchronization code. However, due to the existence of Doppler frequency deviation and the fact that the number of time slots required to complete binned capture is usually large, the synchronization code position obtained by binned capture is offset, and then the initial frequency deviation estimation value obtained by binned capture is used to compensate the second received signal of the input signal stream, and the compensated second received signal is subjected to synchronization code capture to obtain the candidate synchronization code position confirmed by rough compensation. Furthermore, based on relatively accurate candidate synchronization code positions, frequency offset estimation is performed on synchronization code data in multiple time slots to obtain more accurate candidate frequency offset estimation values, and the more accurate candidate frequency offset estimation values ​​are used to compensate for the third received signal of the input signal stream, and synchronization code capture is performed on the compensated third received signal to obtain a more accurate target synchronization code position through synchronous capture, thereby realizing synchronization code detection in low-orbit satellite communication systems.

[0263] The embodiment of the present invention further provides an electronic device, such as Fig.19 As shown, it includes a processor 1901, a communication interface 1902, a memory 1903 and a communication bus 1904, wherein the processor 1901, the communication interface 1902, and the memory 1903 communicate with each other through the communication bus 1904.

[0264] Memory 1903, used for storing computer programs;

[0265] The processor 1901 is used to implement any of the above-mentioned synchronization code detection methods in the low-orbit satellite communication system when executing the program stored in the memory 1903 to achieve the same technical effect.

[0266] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0267] The communication interface is used for communication between the above electronic device and other devices.

[0268] The memory may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0269] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0270] In another embodiment provided by the present invention, a computer-readable storage medium is also provided, in which a computer program is stored. When the computer program is executed by a processor, it implements any of the above-mentioned synchronization code detection methods in the low-orbit satellite communication system to achieve the same technical effect.

[0271] In another embodiment provided by the present invention, a computer program product containing instructions is also provided. When the computer is run on a computer, the computer executes the synchronization code detection method in any low-orbit satellite communication system in the above-mentioned embodiments to achieve the same technical effect.

[0272] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc.

[0273] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0274] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system / device / electronic device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0275] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A synchronization code detection method in a low-orbit satellite communication system, characterized in that: The method comprises: Acquire a maximum frequency deviation range value of the low-orbit satellite communication system, divide the maximum frequency deviation range value into different bins to obtain frequency deviation values ​​of different bins, perform synchronization code capture on a first received signal of an input signal stream at the frequency deviation values ​​of different bins respectively, and obtain an initial frequency deviation estimation value according to the capture result; Compensating a second received signal of the input signal stream by using the initial frequency offset estimation value, and performing synchronization code capture on the compensated second received signal to obtain a candidate synchronization code position confirmed by rough compensation; Based on the candidate synchronization code positions, frequency offset estimation is performed on synchronization code data in multiple time slots to obtain candidate frequency offset estimation values; The candidate frequency offset estimation value is used to compensate the third received signal of the input signal stream, and synchronization code capture is performed on the compensated third received signal to obtain a target synchronization code position for synchronization capture.

2. The method according to claim 1, characterized in that The step of performing synchronization code capture on the first received signal of the input signal stream at different frequency offset values, and obtaining an initial frequency offset estimation value according to the capture result, comprises: For each frequency offset value of each bin, the frequency offset value of the bin is compensated to the first received signal of the input signal stream, and the compensated first received signal is subjected to synchronization code capture to obtain a cumulative correlation peak obtained by operating the first received signal sequence and the local sequence in each bin; the cumulative correlation peak represents a result obtained by accumulating the first received signal sequence and the local sequence after the operation; Based on the cumulative correlation peak of each bin, the frequency offset value of the bin corresponding to the largest peak value is selected as the initial frequency offset estimation value.

3. The method according to claim 2, characterized in that The method of compensating the frequency offset value of each bin into the first received signal of the input signal stream, performing synchronization code capture on the compensated first received signal, and obtaining a cumulative correlation peak obtained by calculating the first received signal sequence and the local sequence for each bin includes: For each frequency offset value of each bin, compensating the frequency offset value of the bin into a first received signal of the input signal stream to obtain a compensated first received signal; Quantizing the compensated first received signal to generate a first received signal sequence; the first received signal sequence includes a plurality of data packets, each of which includes a sampling time slot identifier; Performing an operation on the first received signal sequence and the local sequence to obtain a first operation result; the first operation result includes a sampling time slot identifier; Based on the sampling time slot identifier and the correspondence between the preset time slot and the selection coefficient, performing staggered selection on the first operation result to select corresponding branch data; The branch data corresponding to multiple time slots are accumulated and searched for peak values ​​to obtain the accumulated correlation peak of the bin.

4. The method according to claim 3, characterized in that The quantizing process is performed on the compensated first received signal to generate a first received signal sequence, including: When the number of sampling points of the compensated first received signal accumulates to a preset length, calculating the average of the preset length of sampling point values ​​in the compensated first received signal; determining a compression threshold based on the mean value; Based on the value of each sampling point in the compensated first received signal and the compression threshold, bit compressing the value of each sampling point in the compensated first received signal to obtain compressed data; A first received signal sequence is generated based on the compressed data.

5. The method according to claim 3, characterized in that: The performing operation on the first received signal sequence and the local sequence to obtain a first operation result includes: Sequentially taking out a first preset number of data from the first received signal sequence to obtain a third received signal sequence; For each third received signal sequence, perform point-to-point multiplication of the third received signal sequence and the local sequence to obtain a cross-correlation sequence; For the mutual correlation sequence, summing up the values ​​in the mutual correlation sequence according to a second preset number to obtain an intermediate sequence, and then summing up the values ​​in the intermediate sequence according to the second preset number until two sum values ​​are obtained; A modulo operation is performed on the two sum values ​​respectively, and the modulo values ​​are summed to obtain a first operation result.

6. The method according to claim 3, characterized in that The step of performing staggered selection on the first operation result based on the sampling time slot identifier and the correspondence between the preset time slot and the selection coefficient to select corresponding branch data includes: Read the correspondence table between preset time slots and selection coefficients, determine the starting sampling point of the first operation result in different time slots according to the correspondence between the sampling time slot identifier, the time slot and the selection coefficient, and obtain the branch data in the corresponding time slot.

7. The method according to claim 1, characterized in that The method of compensating the second received signal of the input signal stream by using the initial frequency offset estimation value, and performing synchronization code capture on the compensated second received signal to obtain a candidate synchronization code position confirmed by rough compensation includes: Compensating a second received signal of the input signal stream by using the initial frequency offset estimation value to obtain a compensated second received signal; quantizing the compensated second received signal to generate a second received signal sequence; the second received signal sequence includes a plurality of data packets, each of which includes a sampling time slot identifier; Performing an operation on the second received signal sequence and the local sequence to obtain a second operation result; the second operation result includes a sampling time slot identifier; Based on the sampling time slot identifier and the correspondence between the preset time slot and the selection coefficient, performing staggered selection on the second operation result to select corresponding branch data; Performing cumulative calculation and peak search on the branch data corresponding to multiple time slots to obtain cumulative correlation peaks; Based on the position of the maximum peak value in the cumulative correlation peaks, a candidate synchronization code position is determined.

8. The method according to claim 7, characterized in that The step of performing accumulation operation and peak search on the branch data corresponding to the multiple time slots to obtain the accumulated correlation peak includes: For the branch data in each time slot, the data in each branch data is added point by point to obtain a cumulative sum value; A peak search is performed on the cumulative sum value to obtain a cumulative correlation peak.

9. The method according to claim 1, characterized in that: The step of performing frequency offset estimation on synchronization code data in a plurality of time slots based on the candidate synchronization code positions to obtain candidate frequency offset estimation values ​​includes: Based on the candidate synchronization code position, determine the starting position, sliding window spacing and number of sliding windows of the sliding window of the synchronization code data in each time slot; Based on the starting position, the sliding window spacing and the number of sliding windows, for the synchronization code data in each time slot, the data in each sliding window is operated to obtain a plurality of third operation results; Calculate the cumulative sum of the third operation results in multiple time slots corresponding to each sliding window to obtain a cumulative result; A peak search is performed on the accumulated results corresponding to each sliding window, and a candidate frequency offset estimation value is determined according to the maximum peak value in the peak search result.

10. A synchronization code detection device in a low-orbit satellite communication system, characterized in that: The device comprises: A binning capture module is used to obtain a maximum frequency deviation range value of the low-orbit satellite communication system, bin the maximum frequency deviation range value to obtain frequency deviation values ​​of different bins, perform synchronization code capture on a first received signal of an input signal stream at frequency deviation values ​​of different bins, and obtain an initial frequency deviation estimation value according to the capture result; A coarse compensation confirmation module, used to compensate the second received signal of the input signal stream by using the initial frequency offset estimation value, and to capture the synchronization code of the compensated second received signal to obtain a candidate synchronization code position for coarse compensation confirmation; A search and frequency measurement module, configured to perform frequency offset estimation on synchronization code data in a plurality of time slots based on the candidate synchronization code positions, and obtain a candidate frequency offset estimation value; The synchronization capture module is used to compensate the third received signal of the input signal stream by using the candidate frequency offset estimation value, and perform synchronization code capture on the compensated third received signal to obtain a target synchronization code position for synchronization capture.

11. The device according to claim 10, characterized in that The step-by-step capture module comprises: A bin capture submodule is used to compensate the frequency deviation value of each bin into the first received signal of the input signal stream, and perform synchronization code capture on the compensated first received signal to obtain a cumulative correlation peak obtained by operating the first received signal sequence and the local sequence in each bin; the cumulative correlation peak represents a result obtained by accumulating the operation of the first received signal sequence and the local sequence; The frequency offset estimation submodule is used to select the frequency offset value of the bin corresponding to the maximum peak value as the initial frequency offset estimation value based on the cumulative correlation peak of each bin.

12. The device according to claim 11, characterized in that The sub-module for capturing by grading comprises: A first frequency offset compensation unit is used to compensate the frequency offset value of each bin into the first received signal of the input signal stream for the frequency offset value of each bin, so as to obtain a compensated first received signal; A first quantization unit is used to perform quantization processing on the compensated first received signal to generate a first received signal sequence; the first received signal sequence includes a plurality of data packets, each of which includes a sampling time slot identifier; A first operation unit, configured to operate the first received signal sequence and the local sequence to obtain a first operation result; the first operation result includes a sampling time slot identifier; A first staggered selection unit, configured to perform staggered selection on the first operation result based on the sampling time slot identifier and the correspondence between the preset time slot and the selection coefficient, and select corresponding branch data; The first peak search unit is used to perform accumulation calculation and peak search on the branch data corresponding to multiple time slots to obtain the accumulated correlation peak of the bin.

13. The device according to claim 12, characterized in that The first quantization unit is specifically used for: When the number of sampling points of the compensated first received signal accumulates to a preset length, calculating the average of the preset length of sampling point values ​​in the compensated first received signal; determining a compression threshold based on the mean value; Based on the value of each sampling point in the compensated first received signal and the compression threshold, bit compressing the value of each sampling point in the compensated first received signal to obtain compressed data; A first received signal sequence is generated based on the compressed data.

14. The device according to claim 12, characterized in that The first computing unit is specifically configured to: Sequentially taking out a first preset number of data from the first received signal sequence to obtain a third received signal sequence; For each third received signal sequence, perform point-to-point multiplication of the third received signal sequence and the local sequence to obtain a cross-correlation sequence; For the mutual correlation sequence, summing up the values ​​in the mutual correlation sequence according to a second preset number to obtain an intermediate sequence, and then summing up the values ​​in the intermediate sequence according to the second preset number until two sum values ​​are obtained; A modulo operation is performed on the two sum values ​​respectively, and the modulo values ​​are summed to obtain a first operation result.

15. The device according to claim 12, characterized in that The first misalignment selection unit is specifically used to: Read the correspondence table between preset time slots and selection coefficients, determine the starting sampling point of the first operation result in different time slots according to the correspondence between the sampling time slot identifier, the time slot and the selection coefficient, and obtain the branch data in the corresponding time slot.

16. The device according to claim 10, characterized in that The rough filling confirmation module includes: A second frequency offset compensation unit, configured to compensate a second received signal of the input signal stream by using the initial frequency offset estimation value to obtain a compensated second received signal; A second quantization unit is used to perform quantization processing on the compensated second received signal to generate a second received signal sequence; the second received signal sequence includes a plurality of data packets, each of which includes a sampling time slot identifier; A second operation unit, configured to operate the second received signal sequence and the local sequence to obtain a second operation result; the second operation result includes a sampling time slot identifier; A second staggered selection unit, configured to perform staggered selection on the second operation result based on the sampling time slot identifier and the correspondence between the preset time slot and the selection coefficient, and select corresponding branch data; A second peak search unit, used for performing accumulation operation and peak search on the branch data corresponding to a plurality of time slots to obtain a cumulative correlation peak; The synchronization code position determination unit is used to determine the candidate synchronization code position based on the position of the maximum peak value in the cumulative correlation peak.

17. The device according to claim 16, characterized in that The second peak search unit is specifically used for: For the branch data in each time slot, the data in each branch data is added point by point to obtain a cumulative sum value; A peak search is performed on the cumulative sum value to obtain a cumulative correlation peak.

18. The device according to claim 10, characterized in that The search and frequency measurement module is specifically used for: Based on the candidate synchronization code position, determine the starting position, sliding window spacing and number of sliding windows of the sliding window of the synchronization code data in each time slot; Based on the starting position, the sliding window spacing and the number of sliding windows, for the synchronization code data in each time slot, the data in each sliding window is operated to obtain a plurality of third operation results; Calculate the cumulative sum of the third operation results in multiple time slots corresponding to each sliding window to obtain a cumulative result; A peak search is performed on the accumulated results corresponding to each sliding window, and a candidate frequency offset estimation value is determined according to the maximum peak value in the peak search result.

19. A synchronization code detection system in a low-orbit satellite communication system, characterized in that: The system comprises: Central processing unit CPU, used for initializing and starting the synchronization code detection module; A synchronization code detection module, used to execute the method described in any one of claims 1 to 9 above.

20. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, for implementing any of the methods described in claims 1-9 when executing a program stored in a memory.

21. A readable storage medium, characterized in that: The readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.

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