Method and system for quickly searching optimal phase of Ethernet based on FPGA (Field Programmable Gate Array) and FPGA

Abstract

The invention belongs to the technical field of embedded development, and particularly discloses a method and a system for quickly searching an optimal Ethernet phase based on an FPGA (Field Programmable Gate Array) and the FPGA. According to the invention, the FPGA Ethernet engineering is constructed, so that the FPGA Ethernet engineering works in different data delay units and clock delay units; finding out a data boundary delay unit and a clock boundary delay unit from packet loss and error packet to stable data receiving and transmitting without packet loss and error packet through an FPGA Ethernet engineering packet loss test; and calculating the taps of the reference clock delay during the phase instability period, and superposing the taps to the data boundary delay unit and the clock boundary delay unit to obtain the optimal phase of the data and the optimal phase of the clock in Ethernet data communication. According to the invention, the boundary phase (the data boundary delay unit and the clock boundary delay unit) is found through the packet loss test, then the optimal phase is determined, the precision requirement on a measuring instrument is not high, and the cost is reduced to a hundred thousand level.

Description

Technical Field

[0001] The present application belongs to the field of embedded development technology, and more specifically, relates to a method, system and FPGA for quickly finding the best phase of Ethernet based on FPGA. Background Art

[0002] Ethernet transmission interface is widely used in network communication, industrial control, data transmission and other fields. It has the characteristics of simple interface, high communication speed, long transmission distance and stable working performance. It can also be freely defined and configured to complete the required functions and realize remote high-speed communication. However, in daily hardware design and development, there are problems such as unequal length of PCB traces and low clock quality, which lead to the problem of clock phase deviation between the Ethernet receiving end clock and data.

[0003] The prior art is to use an oscilloscope to directly measure the deviation between the two clocks. However, this method requires extremely high accuracy of the measuring instrument and is costly. Summary of the invention

[0004] In view of the defects of the prior art, the purpose of this application is to provide a method, system and FPGA based on FPGA to quickly find the optimal phase of Ethernet, aiming to solve the problem that the existing method for measuring the phase deviation between data and clock in Ethernet data communication has high equipment accuracy requirements and high costs.

[0005] To achieve the above objectives, in a first aspect, the present application provides a method for quickly finding the best phase of Ethernet based on FPGA, the method comprising:

[0006] Build FPGA Ethernet projects to work in different data delay units and clock delay units;

[0007] Through the FPGA Ethernet engineering packet loss test, find out the data boundary delay unit and clock boundary delay unit from packet loss to stable data reception and transmission without packet loss and error;

[0008] The taps of reference clock delay during phase instability are calculated and added to the data boundary delay unit and the clock boundary delay unit to obtain the optimal data phase and the optimal clock phase in Ethernet data communication.

[0009] Preferably, the construction of the FPGA Ethernet project is as follows:

[0010] Call the IDELAYE2 primitive and set the delay mode IDELAY_TYPE in IDELAYE2 to "VAR_LOAD";

[0011] Connect port IDATAIN of IDELAYE2 to external clock rgmii_rxc, port DATAOUT to rgmii_rxc in Ethernet IP to output rgmii_rxc_dly, port CNTVALUEIN to delay_clk_cnt in VIO IP, and port LD to delay_en in VIO IP;

[0012] Connect rgmii_rx_data in Ethernet IP to external rgmii_rx_data.

[0013] Preferably, the operation is made to work in different data delay units and clock delay units, specifically as follows:

[0014] Duplicate the FPGA Ethernet project three times, constrain the Ethernet receiving clock delay to 0 units, 12 units, and 31 units respectively, and obtain projects with data delays of 0 units, 12 units, and 31 units;

[0015] After power-on, download the engineering firmware with data delay of 0 units, 12 units, and 31 units to the FPGA respectively, set different delay_clk_cnt on the VIO IP visualization interface of the FPGA, and trigger delay_en after setting to perform packet loss test.

[0016] Preferably, when the data delay unit is fixed, a binary method is used to change delay_clk_cnt.

[0017] Preferably, the data boundary delay unit and the clock boundary delay unit for determining the stable data transmission and reception from packet loss or error packet to no packet loss or error packet are based on:

[0018] If Tdelay_clk_cnt, Tdelay_clk_cnt-1 packet loss, Tdelay_clk_cnt-2 packet loss, Tdelay_clk_cnt+1 no packet loss, Tdelay_clk_cnt+2 no packet loss, then Tdata_delay and Tdelay_clk_cnt are the data boundary delay unit and clock boundary delay unit of Ethernet.

[0019] Preferably, the taps for calculating the reference clock delay during phase instability are specifically as follows:

[0020] Calculate the delay resolution delay_resolution = 1 / (32*2*f)*1000000(ps)

[0021] Calculate the reference clock delay during phase instability Wherein, f represents the reference clock frequency, and the safety distance value range is [3taps, 5taps].

[0022] Preferably, the optimal phase of data and the optimal phase of clock in Ethernet data communication are obtained by superimposing the data boundary delay unit and the clock boundary delay unit, as follows:

[0023] If the value is within the range of 0 to 31 after being superimposed on the data boundary delay unit and the clock boundary delay unit, the sum of the superimposed values ​​is the optimal data phase and the optimal clock phase; otherwise, a certain value is subtracted from the sum of the superimposed values ​​so that the value is within the range of 0 to 31, and the value after subtracting the certain value is the optimal data phase and the optimal clock phase.

[0024] Preferably, the method further comprises:

[0025] In the FPGA Ethernet project constraint document, fix the optimal phase constraints of the clock and data, and set the IDELAY_TYPE in IDELAYE2 from the variable delay "VAR_LOAD" to "FIXED".

[0026] To achieve the above-mentioned purpose, in a second aspect, the present application provides an FPGA, wherein the FPGA includes an FPGA Ethernet engineering constraint file, and the optimal phase of data and the optimal phase of clock in the PGA Ethernet engineering constraint file are obtained by the method described in the first aspect.

[0027] To achieve the above-mentioned purpose, in a third aspect, the present application provides a system for quickly finding the best phase of Ethernet based on FPGA, comprising: FPGA, ETHERNET PHY, RJ45 connector and network tester;

[0028] The FPGA controls the ETHERNET PHY, and the other end of the PHY is connected to the RJ45 connector; the other end of the RJ45 connector is connected to the network tester;

[0029] The FPGA is provided with IDELAYE2, VIO IP and Ethernet IP, and the delay between data and clock is dynamically adjusted through VIO and IDELAYE2;

[0030] The network tester performs high-flow full-load data transmission with the FPGA and performs a packet loss test on the FPGA at the same time;

[0031] The system determines the optimal Ethernet phase according to the method according to the first aspect.

[0032] It can be understood that the beneficial effects of the second to third aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0033] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the prior art:

[0034] The present application provides a method for quickly finding the best phase of Ethernet based on FPGA. By constructing an FPGA Ethernet project, it works in different data delay units and clock delay units; through the packet loss test of the FPGA Ethernet project, the data boundary delay unit and clock boundary delay unit for stable data reception and transmission from packet loss and error packet to no packet loss and error packet are found; the taps of the reference clock delay during the phase instability are calculated and superimposed on the data boundary delay unit and the clock boundary delay unit to obtain the best phase of data and the best phase of clock in Ethernet data communication. The present application finds the boundary phase (data boundary delay unit and clock boundary delay unit) through packet loss test, and then determines the best phase. The accuracy requirements for measuring instruments are not high, and the cost is reduced to the level of one hundred thousand. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a flow chart of a method for quickly finding the optimal phase of Ethernet based on FPGA provided in an embodiment of the present application.

[0036] Figure 2 It is a block diagram of the hardware system structure required for the implementation provided by the embodiment of the present application.

[0037] Figure 3 It is a workflow diagram of the preparation phase provided in an embodiment of the present application.

[0038] Figure 4 This is a test phase workflow diagram provided in an embodiment of the present application.

[0039] Figure 5 This is a flowchart of the process of calculating and fixing the optimal phase provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0041] The term "and / or" in this article is a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The symbol " / " in this article indicates that the associated objects are in an or relationship, for example, A / B means A or B.

[0042] The terms "first" and "second" in the specification and claims herein are used to distinguish different objects rather than to describe a specific order of the objects. For example, a first response message and a second response message are used to distinguish different response messages rather than to describe a specific order of the response messages.

[0043] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0044] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more than two. For example, multiple processing units refer to two or more processing units, etc.; multiple elements refer to two or more elements, etc.

[0045] First, the technical terms involved in the embodiments of the present application are introduced.

[0046] IDELAYE2 primitive: IDELAYE2 is a built-in primitive in Xilinx FPGAs that provides precise input signal delay control. It has 31 programmable delay taps, suitable for fine-tuning high-speed digital signals to meet timing requirements. IDELAYE2 can work independently on each pin of the FPGA and supports multiple operating modes such as fixed delay, variable delay, variable loading and pipeline mode. In addition, IDELAYE2 can be automatically calibrated through the IDELAYCTRL module to reduce the impact of process, voltage and temperature changes.

[0047] IDELAY_TYPE is set to "VAR_LOAD": IDELAY2 timing is in loadable variable delay mode. When IDELAY_TYPE is set to "FIXED", it means that the delay is fixed and will not change at runtime. This mode is suitable for scenes that do not need to adjust the delay dynamically.

[0048] IDATAIN: One of the data input ports of IDELAYE2, IDELAY data input from IBUF.

[0049] DATAOUT: One of the output ports of IDELAYE2, delayed data from one of the two data input ports.

[0050] Port CNTVALUEIN: Calculator value from FPGA logic used to dynamically load the wiper value.

[0051] Port LD: In VAR_LOAD mode, loads the value of CNTVALUEIN.

[0052] tri_mac IP, or Tri-Mode Ethernet MAC IP, is a hardware module for Ethernet communication interface of FPGA. It supports different Ethernet rates, including 10 / 100Mb / s, 1Gb / s, 2.5Gb / s, or 10 / 100 / 1000Mb / s adaptive type. Tri-Mode Ethernet MAC IP core is usually embedded in FPGA to implement Ethernet communication function. It is responsible for data encapsulation and decapsulation of MAC layer, as well as data transmission with PHY layer.

[0053] FPGA Ethernet engineering usually refers to the design and development process of implementing Ethernet communication functions on FPGA (Field Programmable Gate Array). Ethernet is a local area network technology widely used in data communication. It follows the IEEE 802.3 standard and supports multiple rates, such as 10Mbit / s, 100Mbit / s, 1000Mbit / s (Gigabit Ethernet), and even higher. Implementing Ethernet functions on FPGA usually involves the following key parts: MAC (Media Access Control) layer, PHY (Physical layer) layer, interface circuit, communication protocol, and debugging and testing.

[0054] The VIO (Virtual Input / Output) IP core is a very useful debugging tool. It allows designers to monitor and drive signals inside the FPGA in real time through the JTAG interface. The VIO IP core can configure the number and bit width of input and output ports to suit different debugging requirements. Since the VIO core is synchronized with the design being monitored and driven, the clock constraints applied to the design will also be applied to the VIO.

[0055] Next, the technical solutions provided in the embodiments of the present application are introduced.

[0056] like Figure 1 As shown, the present application provides a method for quickly finding the best phase of Ethernet based on FPGA, the method comprising:

[0057] Build FPGA Ethernet projects to work in different data delay units and clock delay units;

[0058] Through the FPGA Ethernet engineering packet loss test, find out the data boundary delay unit and clock boundary delay unit from packet loss to stable data reception and transmission without packet loss and error;

[0059] The taps of reference clock delay during phase instability are calculated and added to the data boundary delay unit and the clock boundary delay unit to obtain the optimal data phase and the optimal clock phase in Ethernet data communication.

[0060] Preferably, the construction of the FPGA Ethernet project is as follows:

[0061] Call the IDELAYE2 primitive and set the delay mode IDELAY_TYPE in IDELAYE2 to "VAR_LOAD";

[0062] Connect port IDATAIN of IDELAYE2 to external clock rgmii_rxc, port DATAOUT to rgmii_rxc in Ethernet IP to output rgmii_rxc_dly, port CNTVALUEIN to delay_clk_cnt in VIO IP, and port LD to delay_en in VIO IP;

[0063] Connect rgmii_rx_data in Ethernet IP to external rgmii_rx_data.

[0064] Preferably, the operation is performed in different data delay units and clock delay units, specifically as follows:

[0065] Duplicate the FPGA Ethernet project three times, constrain the Ethernet receiving clock delay to 0 units, 12 units, and 31 units respectively, and obtain projects with data delays of 0 units, 12 units, and 31 units;

[0066] After power-on, download the engineering firmware with data delay of 0 units, 12 units, and 31 units to the FPGA respectively, set different delay_clk_cnt on the VIO IP visualization interface of the FPGA, and trigger delay_en after setting to perform packet loss test.

[0067] In addition to delays of 0 units, 12 units, and 31 units, this application also supports other combinations as long as the front section, middle section, and back section are covered at the same time, for example, 1 unit, 15 units, and 30 units.

[0068] Preferably, when the data delay unit is fixed, a binary method is used to change delay_clk_cnt.

[0069] Preferably, the data boundary delay unit and the clock boundary delay unit for determining the stable data transmission and reception from packet loss or error packet to no packet loss or error packet are based on:

[0070] If Tdelay_clk_cnt, Tdelay_clk_cnt-1 packet loss, Tdelay_clk_cnt-2 packet loss, Tdelay_clk_cnt+1 no packet loss, Tdelay_clk_cnt+2 no packet loss, then Tdata_delay and Tdelay_clk_cnt are the data boundary delay unit and clock boundary delay unit of Ethernet.

[0071] Preferably, the taps for calculating the reference clock delay during phase instability are specifically as follows:

[0072] Calculate the delay resolution delay_resolution = 1 / (32*2*f)*1000000(ps)

[0073] Calculate the reference clock delay during phase instability Wherein, f represents the reference clock frequency, and the safety distance value range is [3taps, 5taps].

[0074] Preferably, the optimal phase of data and the optimal phase of clock in Ethernet data communication are obtained by superimposing the data boundary delay unit and the clock boundary delay unit, as follows:

[0075] If the value is within the range of 0 to 31 after being superimposed on the data boundary delay unit and the clock boundary delay unit, the sum of the superimposed values ​​is the optimal data phase and the optimal clock phase; otherwise, a certain value is subtracted from the sum of the superimposed values ​​so that the value is within the range of 0 to 31, and the value after subtracting the certain value is the optimal data phase and the optimal clock phase.

[0076] Preferably, the method further comprises:

[0077] In the FPGA Ethernet project constraint document, fix the optimal phase constraints of the clock and data, and set the IDELAY_TYPE in IDELAYE2 from the variable delay "VAR_LOAD" to "FIXED".

[0078] The present application provides an FPGA, which includes an FPGA Ethernet engineering constraint file, and the optimal phase of data and the optimal phase of clock in the PGA Ethernet engineering constraint file are obtained by the above method.

[0079] The present application provides a system for quickly finding the best phase of Ethernet based on FPGA, including: FPGA, ETHERNET PHY, RJ45 connector and network tester;

[0080] The FPGA controls the ETHERNET PHY, and the other end of the PHY is connected to the RJ45 connector; the other end of the RJ45 connector is connected to the network tester;

[0081] The FPGA is provided with IDELAYE2, VIO IP and Ethernet IP, and the delay between data and clock is dynamically adjusted through VIO and IDELAYE2;

[0082] The network tester performs high-flow full-load data transmission with the FPGA and performs a packet loss test on the FPGA at the same time;

[0083] The system determines the optimal Ethernet phase according to the above method.

[0084] Example

[0085] This embodiment uses the VIO IP in FPGA CHIPSICOPE to modify the delay parameter delay_clk_cnt in the primitive IDELAY2 on the computer interface, and then the network tester determines the optimal delay time through Ethernet communication with large traffic and full load, thereby calculating the optimal phase. Specifically, the data received by Ethernet is fixed at the positions of three different delay units 0, 12, and 31, and then the primitive IDELAYE2 provided by FPGA is used to implement the delay of the Ethernet receiving clock rgmii_rxc, and the IDELAY_TYPE is set to the "VAR_LOAD" mode, and the delayed rgmii_rxc_dly is connected to the Ethernet IP (tri_mac). The delay parameter delay_clk_cnt and the delay switch delay_en in the primitive are connected to the VIO of CHIPSCOPE, and the Ethernet data transmission and reception are tested by setting different delay units from 0 to 31 on the CHIPSCOPE interface. In this way, the boundary delay unit for stable data transmission and reception from packet loss and error to no packet loss and error is found. Then, the optimal phase is calculated by combining the delay resolution of the chip itself, delay_resolution, and the delay unit (boundary phase) of the data and clock for stable communication. Finally, the optimal phase between the Ethernet receiving end data and clock calculated can be executed in the FPGA constraint file through commands. Through CHIPSCOPE VIO and IDELAYE2, the delay between data and clock can be dynamically adjusted to improve stability, reliability, flexibility and monitorability.

[0086] like Figure 2As shown, the hardware system required for implementation provided by this embodiment includes: FPGA, ETHERNET PHY, RJ45 connector and network tester. Among them, FPGA controls ETHERNET PHY, and the other end of the PHY is connected to the RJ45 connector; the other end of the RJ45 connector is connected to the network tester. This embodiment uses 88E1111 as ETHERNET PHY. After the hardware is ready, the specific implementation of the solution is divided into the following steps:

[0087] Step 1: Build FPGA Ethernet Project

[0088] like Figure 3 As shown, in the FPGA Ethernet project, the IDELAYE2 primitive is instantiated (called), and the delay mode IDELAY_TYPE in IDELAYE2 is set to "VAR_LOAD".

[0089] Connect the data port IDATAIN of IDELAYE2 to the external clock rgmii_rxc, the output port DATAOUT of IDELAYE2 to the rgmii_rxc_dly of FPGA, the port CNTVALUEIN of IDELAYE2 to the delay_clk_cnt in VIO, the port LD of IDELAYE2 to the delay_en of VIO, and at the same time, the rgmii_rxc_dly in FPGA is connected to the rgmii_rxc in tri_macIP.

[0090] After completing the FPGA project, copy the FPGA Ethernet project three times and constrain the clock delay of Ethernet reception to 0 units, 12 units, and 31 units respectively.

[0091] Step 2: Find the boundary phase

[0092] like Figure 4 As shown in the figure, use a Gigabit Ethernet cable to connect the RJ45 to the test port of the network tester, and use a Gigabit Ethernet cable to connect the control port of the network tester to the computer network port. After the preparation is completed, you can power on the board (including the FPGA hardware system) and the network tester.

[0093] After power-on, the engineering firmware with data delay of 0 units is downloaded to the SRAM in the FPGA, and then the delay_clk_cnt is set on the CHIPSCOPE interface of the FPGA using the binary method, and delay_en is triggered after the setting.

[0094] The binary method is as follows: IDELAYE2 has 31 delay taps. First, set the delay at 16 delay taps and perform a packet loss test. If there is no packet loss, calculate the tap value for no packet loss near 16. If there is packet loss, set the delay at 8 or 24 and perform a packet loss test. If there is no packet loss, calculate the tap value for no packet loss. If there is packet loss, set it at 4 or 28... and so on. Using the binary method to calculate the clock delay range is faster.

[0095] Then use the network tester to send and receive data and observe whether there is packet loss: if there is still packet loss or error after searching all 31 delay units of the clock in the project with data delay of 0 units, change the project with data delay of 12 delay units or 31 delay units. And so on, until the clock phase Tdelay_clk_cnt, Tdelay_clk_cnt-1 packet loss, Tdelay_clk_cnt-2 packet loss, Tdelay_clk_cnt+1 no packet loss, Tdelay_clk_cnt+2 no packet loss are found in the Ethernet transceiver communication without packet loss. Then the Ethernet data delay units Tdata_delay and Tdelay_clk_cnt are the boundary phases of Ethernet.

[0096] Step 3: Calculate the best phase

[0097] After finding the boundary phase of Ethernet, it is necessary to deduce the optimal phase for Ethernet to achieve stable communication. Figure 5 As shown, since the rgmii_rxc clock of Gigabit Ethernet is 125MHz, one cycle is 8ns, and half a cycle is 4ns. The phase instability is generally around the middle of the half cycle, that is, 2ns for a quarter cycle.

[0098] Calculate the delay resolution delay_resolution. The calculation formula is as follows:

[0099] delay_resolution=1 / (32*2*f)*1000000(ps)

[0100] The reference clock frequency f is in MHz.

[0101] When f=200MHz, delay_resolution=78ps (Note: the calculated value is 78.125ps, but it will be rounded to 78ps); when f=300MHz, delay_resolution=52ps.

[0102] The calculated tap value between them (2ns / 78ps) is 25.64. The safety distance range is 3-5 taps, which is rounded to 22 taps after removing the instability at the beginning and end (including the safety distance).

[0103] Add 22 taps to the boundary values ​​Tdata_delay and Tdelay_clk_cnt tested in step 2. If the range of Tdata_delay_tap and Tdelay_clk_cnt_tap values ​​after adding is within the range of 0 to 31, then the values ​​of Tdata_delay_tap and Tdelay_clk_cnt_tap are the best phases Tdata_delay_best and Tdelay_clk_cnt_best. If the range of Tdata_delay_tap and Tdelay_clk_cnt_tap values ​​after adding exceeds the range of 0 to 31, subtract a certain value from Tdata_delay_tap and Tdelay_clk_cnt_tap at the same time, so that the values ​​of Tdata_delay_tap and Tdelay_clk_cnt_tap are within the range of 0 to 31, and the value after subtracting a certain value is the best range Tdata_delay_best and Tdelay_clk_cnt_best.

[0104] Fourth, fixed phase

[0105] In the FPGA Ethernet project constraint file, fix the optimal phase constraints of the clock and data, and set the IDELAY_TYPE in IDELAYE2 from variable delay "VAR_LOAD" to "FIXED". Regenerate a new project file. In this way, the optimal phase is found, and the network can communicate stably and reliably.

[0106] It can be understood that the detailed functional implementation of each of the above-mentioned units / modules can be found in the introduction of the aforementioned method embodiment, and will not be repeated here.

[0107] It should be understood that the above-mentioned device is used to execute the method in the above-mentioned embodiment. The implementation principle and technical effect of the corresponding program module in the device are similar to those described in the above-mentioned method. The working process of the device can refer to the corresponding process in the above-mentioned method, which will not be repeated here.

[0108] Based on the method in the above embodiment, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on a processor, the processor executes the method in the above embodiment.

[0109] Based on the method in the above embodiment, an embodiment of the present application provides a computer program product. When the computer program product runs on a processor, the processor executes the method in the above embodiment.

[0110] It is understandable that the processor in the embodiment of the present application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0111] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0112] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions may be transmitted from a website site, a computer, a server or a data center to another website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0113] It should be understood that the various numerical numbers involved in the embodiments of the present application are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application.

[0114] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A method for quickly finding the best phase of Ethernet based on FPGA, characterized in that: The method includes: Build FPGA Ethernet projects to work in different data delay units and clock delay units; Through the FPGA Ethernet engineering packet loss test, find out the data boundary delay unit and clock boundary delay unit from packet loss to stable data reception and transmission without packet loss and error; The taps of reference clock delay during phase instability are calculated and added to the data boundary delay unit and the clock boundary delay unit to obtain the optimal data phase and the optimal clock phase in Ethernet data communication.

2. The method according to claim 1, characterized in that The construction of the FPGA Ethernet project is as follows: Call the IDELAYE2 primitive and set the delay mode IDELAY_TYPE in IDELAYE2 to "VAR_LOAD"; Connect port IDATAIN of IDELAYE2 to external clock rgmii_rxc, port DATAOUT to rgmii_rxc in Ethernet IP to output rgmii_rxc_dly, port CNTVALUEIN to delay_clk_cnt in VIO IP, and port LD to delay_en in VIO IP; Connect rgmii_rx_data in Ethernet IP to external rgmii_rx_data.

3. The method according to claim 2, characterized in that The operation is performed in different data delay units and clock delay units, as follows: Duplicate the FPGA Ethernet project three times, constrain the Ethernet receiving clock delay to 0 units, 12 units, and 31 units respectively, and obtain projects with data delays of 0 units, 12 units, and 31 units; After power-on, download the engineering firmware with data delay of 0 units, 12 units, and 31 units to the FPGA respectively, set different delay_clk_cnt on the VIO IP visualization interface of the FPGA, and trigger delay_en after setting to perform packet loss test.

4. The method according to claim 3, characterized in that When the data delay unit is fixed, the binary method is used to change delay_clk_cnt.

5. The method according to claim 1, characterized in that The judgment basis of the data boundary delay unit and the clock boundary delay unit from packet loss to stable data reception and transmission without packet loss and error is: If Tdelay_clk_cnt, Tdelay_clk_cnt-1 packet loss, Tdelay_clk_cnt-2 packet loss, Tdelay_clk_cnt+1 no packet loss, Tdelay_clk_cnt+2 no packet loss, then Tdata_delay and Tdelay_clk_cnt are the data boundary delay unit and clock boundary delay unit of Ethernet.

6. The method according to claim 1, characterized in that The taps for calculating the reference clock delay during phase instability are as follows: Calculate the delay resolution delay_resolution = 1 / (32*2*f)*1000000(ps) Calculate the reference clock delay during phase instability Wherein, f represents the reference clock frequency, and the safety distance value range is [3taps, 5taps].

7. The method according to claim 1, characterized in that The optimal phase of data and the optimal phase of clock in Ethernet data communication are obtained by superimposing the data boundary delay unit and the clock boundary delay unit, as follows: If the value is within the range of 0 to 31 after being superimposed on the data boundary delay unit and the clock boundary delay unit, the sum of the superimposed values ​​is the optimal data phase and the optimal clock phase; otherwise, a certain value is subtracted from the sum of the superimposed values ​​so that the value is within the range of 0 to 31, and the value after subtracting the certain value is the optimal data phase and the optimal clock phase.

8. The method according to any one of claims 1 to 7, characterized in that The method further includes: In the FPGA Ethernet project constraint document, fix the optimal phase constraints of the clock and data, and set the IDELAY_TYPE in IDELAYE2 from variable delay "VAR_LOAD" to "FIXED".

9. An FPGA, characterized in that: The FPGA includes an FPGA Ethernet engineering constraint file, and the optimal phase of data and the optimal phase of clock in the PGA Ethernet engineering constraint file are obtained by the method described in any one of claims 1 to 8.

10. A system for quickly finding the best phase of Ethernet based on FPGA, characterized in that: include: FPGA, ETHERNETPHY, RJ45 connector and network tester; The FPGA controls the ETHERNET PHY, and the other end of the PHY is connected to the RJ45 connector; the other end of the RJ45 connector is connected to the network tester; The FPGA is provided with IDELAYE2, VIO IP and Ethernet IP, and the delay between data and clock is dynamically adjusted through VIO and IDELAYE2; The network tester performs high-flow full-load data transmission with the FPGA and performs a packet loss test on the FPGA at the same time; The system determines the optimal Ethernet phase according to the method according to any one of claims 1 to 8.

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