Plasma doping of gap fill materials

Abstract

This application relates to plasma doping of gap fill materials. In a variety of processes for forming electronic devices using spin-on dielectric materials, the properties of the spin-on dielectric materials can be enhanced by curing these materials using plasma doping. For example, the hardness and Young's modulus of the cured materials can be increased. Other properties can be enhanced. The plasma doping that cures the spin-on dielectric materials uses a mechanism that is a combination of plasma ions associated with ionized species and high-energy radiation. In addition, the physical properties of the spin-on dielectric materials can be modified along the length of the spin-on dielectric materials by selecting the implant energy and the dopant dose of the particular dopant used corresponding to a selected variation in length.

Description

[0001] Related application information

[0002] This application is a divisional application of the application for patent application number 202011582142.5, filed on December 28, 2020, entitled “Plasma doping of gap fill material,” having a filing date of December 28, 2020.

[0003] Priority application

[0004] This application claims the benefit of priority to U.S. Provisional Application Serial No. 62 / 955,814, filed December 31, 2019, which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0005] Embodiments of the present disclosure generally relate to the fabrication of electronic devices and fabricated electronic devices, and more specifically, to electronic devices and forming electronic devices using plasma doping. BACKGROUND

[0006] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memories. Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can retain stored data when unpowered and includes flash memory, read only memory (ROM), electrically TM erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistive variable memory (such as phase change random access memory (PCRAM)), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or three-dimensional (3D) XPoint memory, among others. 3D X-Point memory is a non-volatile memory (NVM) technology with a stackable cross-point data access array, where bit storage is based on changes in bulk resistance.

[0007] Flash memory is used in various electronic applications as non-volatile memory. Flash memory devices typically include one or more groups of single transistor, floating gate, or charge trap memory cells that allow for high memory density, high reliability, and low power consumption. Two common types of flash memory array architectures include NAND and NOR architectures, named after the logical form in which the basic memory cell configuration of each is arranged. The memory cells of a memory array are typically arranged in a matrix. In an example, the gates of each floating gate memory cell in a row of the array are coupled to an access line (e.g., a word line). In a NOR architecture, the drains of each memory cell in a column of the array are coupled to a data line (e.g., a bit line). In a NAND architecture, the drains of each memory cell in a string of the array are coupled together in series (source to drain) between a source line and a bit line. SUMMARY

[0008] One embodiment of the present disclosure provides a method comprising: forming a spin-on dielectric as a dielectric to provide electrical isolation in an electronic device; and curing the spin-on dielectric by plasma doping (PLAD) the spin-on dielectric.

[0009] Another embodiment of the present disclosure provides a method comprising: forming a carbon-rich spin-on dielectric (C-SOD) as a dielectric to provide electrical isolation in an electronic device; and curing the C-SOD by subjecting the C-SOD to a combination of a plasma ion implant providing a photon energy greater than 10 eV and species of the plasma ion implant.

[0010] Yet another embodiment of the present disclosure provides a memory device comprising: a three-dimensional memory array; and a dielectric film providing electrical isolation in the memory array, the dielectric film including a spin-on dielectric (SOD) as a dielectric between stacks of memory cells of the memory array, wherein the SOD includes carbon and plasma implant ions. BRIEF DESCRIPTION OF DRAWINGS

[0011] The drawings, which are not necessarily drawn to scale, generally illustrate the various embodiments discussed herein by way of example and not by way of limitation.

[0012] Figure 1 is a block diagram representing an arrangement of vertical 3D stacks of X-Point memory devices according to various embodiments.

[0013] Figure 2 is a representation of a portion of two stacks in a 3D X-Point device having two stacks separated and covered by a dielectric gap filler according to various embodiments.

[0014] Figure 3is another representation of two stacked portions of a two stacked 3D X-Point device separated and covered by a dielectric gap filler, according to various embodiments.

[0015] Figure 4 is a representation of multiple stacked portions of a multiple stacked 3D X-Point device separated and covered from each other by a dielectric gap filler, according to various embodiments.

[0016] Figure 5 is a representation of an apparatus for plasma doping of a wafer, according to various embodiments.

[0017] Figure 6 shows a table of experimental results of curing C-SOD using a conventional method and different PLAD methods, according to various embodiments.

[0018] Figure 7 shows a table of experimental results of curing C-SOD using a conventional method and different PLAD methods, according to various embodiments.

[0019] Figure 8 shows a table of density profiles from X-ray reflectometry (XRR) measurements on SiOC SOD, according to various embodiments.

[0020] Figures 9A to 9C shows three cases associated with a set of parameters for PLAD of C-SOD, according to various embodiments.

[0021] Figure 10 shows stopping and range of ions in matter (SRIM) simulations of He concentration profiles, according to various embodiments.

[0022] Figure 11 is a flowchart of features of an example method of preparing a dielectric film in an electronic device, according to various embodiments.

[0023] Figure 12 is a flowchart of features of an embodiment of an example method of preparing a dielectric film in an electronic device, according to various embodiments.

[0024] Figure 13 shows a block diagram of an example system including memory structured with a three-dimensional memory array structure such that a dielectric film in the memory array includes a PLAD cured SOD, according to various embodiments. DETAILED DESCRIPTION

[0025] The following detailed description relates to the accompanying drawings that illustrate various embodiments by way of illustration. The detailed description is sufficiently detailed to enable one of ordinary skill in the art to practice the embodiments, and variations of the embodiments. Other embodiments can be utilized, and structural, logical, mechanical, and electrical changes can be made without departing from the scope of the embodiments. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. Accordingly, the following detailed description is not to be taken in a limiting sense.

[0026] Spin-on deposition in electronic device manufacturing is a process of applying a material to a wafer, where the material is initially dispensed on the wafer in liquid form and the wafer is spun to achieve uniform distribution of the material and then the material is solidified by low temperature (e.g., <200°C) thermal curing. Spin-on materials are used as dielectric gap fillers for narrow and high aspect ratio trench fill in both shallow trench isolation (STI) and metal pre-dielectric application in electronic devices for their good gap filling properties. For example, in several three-dimensional (3D) memories, there are columns of memory cells where there are gaps between the columns at the time of manufacturing that electrically isolate each of the columns, although in some architectures, conductive plate-like structures can connect portions of some of the columns based on the respective architecture. The gaps are filled with a dielectric material, where this dielectric material is referred to as a dielectric gap filler or gap filler. Spin-on dielectric (SOD) of the gap filler can include materials such as silicates, siloxanes, silazanes, or silsesquioxanes. SOD also includes spin-on-glass (SOG) and spin-on-dielectric polymers. For example, cross-point (X-Point) memory components use a carbon-rich spin-on-dielectric (C-SOD) film to fill the gaps between stacks at access lines such as word lines WL and at data lines such as bit lines BL for better fill by eliminating voids. This C-SOD film can provide sufficient density at low temperature. For the purposes of this description, low carbon (C atomic %) SOD is SOD with 10 to 30% C content, and carbon-rich SOD is SOD with 30 to 60% C content. Content is in atomic percent, where C% is the atomic percent of carbon content, which can be detected by X-ray photoelectron spectroscopy (XPS). For example, in a SiOC composition, the atomic percent of C, Si, and O add up to 100% total.

[0027] One organic low-k dielectric C-SOD material for X-Point WL or BL trench fill includes SiO xApproximately 50% carbon (C) plus porosity (silsesquioxane derivative). Low-k dielectrics are dielectrics with a dielectric constant lower than that of Si02(k < 3.9), and high-k dielectrics are dielectrics with a dielectric constant greater than that of Si02(k > 3.9). Organic SODs (C-based) can have k values ranging from 2.65 to 3.1, while C-free inorganic SODs have k values ranging from 5.6 to 7.9. C-SOD films can vary due to the percentage of carbon, stoichiometry of silicon oxide, and porosity.

[0028] Additionally, SOD fill materials have exhibited tunable thermal conductivity, where this thermal conductivity is approximately 0.14 Wm -1 K -1 1.3 Wm -1 K -1 . Compared to conventional SiO x fillers such as tetraethyl orthosilicate (TEOS), this relatively low thermal conductivity of SOD fill materials reduces thermal disturbance (TD) issues during cell operations by providing a balanced thermal barrier among the nearest neighboring cells. Tunability can be provided through selection of material and processing parameters.

[0029] However, deposited or thermally cured SODs (e.g., C-SODs with approximately 50% carbon along with SiO x , where x > 1) generally present integration challenges in chemical mechanical polishing (CMP) and etching when devices are processed. The challenges include weak mechanical strength with a modulus of approximately 6 GPa. Adhesion and cohesive failures have been observed, such as CMP cracks (cracks are broken material during the CMP process, which can include sharp tip geometry). Furthermore, deposited or thermally cured SODs are generally susceptible to chemical attack and have poor selectivity with respect to carbon, which makes them susceptible to post processing, such as post processing that results in porous materials. Curing is a process during which a chemical reaction, such as polymerization, or a physical action, such as evaporation, occurs that results in stronger, tougher, or more stable bonds (or substances). In polymer chemistry and process design, curing is a chemical process that toughens or hardens a polymeric material through cross-linking of polymer chains. Cross-linking is a linkage that bonds a polymer chain to another polymer chain. Additionally, C-SOD stacks using tetramethylammonium hydroxide (TMAH) processing present significant or direct adhesion failures during CMP.

[0030] Another challenge is damage to alignment marks at CMP. Bottom fill issues of post C-SOD fill to alignment marks are more severe due to surface topography. C-SOD fill can be lower than the alignment marks of the array height. Alignment mark surface topography of feature width can result in C-SOD bottom fill. Bottom fill is worse for C-SOD films that are TMAH processed and ultraviolet (UV) processed.

[0031] In addition to process issues, C-SOD films are generally believed to be the root cause of cell program window reduction and performance degradation. Hydrogen (H), moisture, or vapor poisoning on phase change (PM) regions is believed to be the mechanism of these process issues. As an example, PM regions, which can be implemented as chalcogenide-based phase change regions, can be arranged as memory elements of a phase change memory (PCM) device; and other memory storage technologies, such as variable resistance memory technologies, can have memory elements (sometimes again including chalcogenide materials), which can be subject to such damage or degradation.

[0032] Mitigation of integration issues can be achieved with improvements in C-SOD physical stability including mechanical strength and adhesion, and chemical stability including dry or wet etch properties. Solidification in a current furnace at 200 °C in N2 environment for two hours, total process time can be greater than an hour at greater than 3 minutes / wafer throughput rate. This furnace solidification can provide adequate cross-linking with H2O removal (dehydration). However, this solidification results in a material with insufficient mechanical strength, with a Young's modulus of 6 GPa. In addition, furnace solidification has low T-put and high cost. In contrast, in the most well-known method for ultraviolet (UV) solidification under non-oxidizing and oxidizing conditions, a process time of 4 minutes / wafer is achieved. UV solidification provides enhanced cross-linking with mechanical strength improved to a Young's modulus of approximately 7.5 GPa. This can still be insufficient mechanical strength. UV solidification has low T-put and high tool set cost.

[0033] In various embodiments, a method for enhancing mechanical properties and selective densification of organosilicate SOD materials by a plasma doping (PLAD) process is provided. As an example, SOD materials can be formed as an array gap fill material, although other applications are contemplated. Selective densification can be achieved as a selectivity of surface densification versus bulk densification. The PLAD process is an implantation process that is different from conventional beamline implantation. Solidification of SOG or SOD by implantation in a post-coating or sintering process can improve its mechanical strength and modulate its chemical composition, providing a balanced Si / C / O ratio. Mechanical strength can be exhibited by its Young's modulus (E) and hardness (H). Improving mechanical strength and balancing cost ratio can provide successful integration of SOD gap fillers in any memory device with respect to mitigating process-related challenges such as CMP and etching. In addition, improving mechanical strength and balancing cost ratio can restore cycling performance of device cells, providing enhanced reliability or durability, improving PM film quality and durability by removing hydride.

[0034] The PLAD process taught herein can provide high throughput, low cost, low temperature, e.g., room temperature (RT), processing, and can be used to cure C-SOD by a mechanism of combination of plasma ions associated with the species of ion dopant used and high energy radiation. This approach using the PLAD process provides a novel way of crosslinking C-SOD films to improve mechanical, electrical, and chemical properties. Selective modification of the surface relative to the bulk can be implemented by tuning implant energy and ion density in the PLAD process.

[0035] Helium (He) can be used as an implant in the PLAD process to cure SOD films. Using He plasma provides processing under soft x-ray radiation. The extended ultraviolet (EUV) radiation spectrum provides much higher photon energies 40.81 eV (for He II) and 21.22 eV (for He I) than the normal UV radiation and photon energies of other plasmas less than 10 eV. He I and He II refer to two different ionized states of He. Using higher photon energies significantly improves C-SOD and cell film properties. At the same time, in-situ He plasma low energy ion bombardment enhances C-SOD curing and further improves C-SOD film properties.

[0036] Curing C-SOD by PLAD shows significant C-SOD improvements, including much higher near-surface mechanical strength (hardness and Young's modulus), tunable electrical properties, and enhanced chemical and thermal stability, with less volume shrinkage. Based on these property improvements, current problems of CMP and dry etching processes are minimized and greatly improved.

[0037] Curing SOD by He PLAD can facilitate H removal by high energy radiation to improve cell reliability / durability. This PLAD processing can provide significantly higher T-put and low cost, since the associated process time is only 1 minute compared to more than three minutes to several hours needed using conventional processes. Curing by PLAD is not only limited to helium implants, but is applicable to other PLAD implants, including H, nitrogen (N), boron (B), diborane (B2H6), fluoride (F), boron trifluoride (BF3), C, germanium (Ge), etc., as shown in Table 640 of Figure 6

[0038] ​As taught herein, SOD solidification by PLAD is not only limited to one type of SOD, such as C-SOD, but can also be applied to other SOD materials, including SOG materials and polymers used in shallow trench isolation (STI) gap fill. These materials include, for example, but are not limited to, organic SODs with different carbon content from about 10% to 60% by atomic percent and photoimageable SODs. SODs solidified by PLAD are suitable for DRAM structures with low-k SOD fill and NAND large area gap (LAG) fill films, including photo-definable UV-sensitive gap fill.

[0039] PLAD solidification of SOD can be applied before or after CMP planarization of SOD in integrated flow in integrated circuit fabrication. PLAD can be implemented without any additional integration changes or architecture changes in the process. PLAD processing of SOD gap fill materials can be performed as a low temperature process that is viable for integration in low thermal budget memory devices. Further, the PLAD process of SOD gap fill materials can be tuned by ion density (dose), bias energy, and exposure time. The tunable process can include selecting a dose, bias energy, or exposure time to modify physical properties of the formed SOD gap fill material. The selection can be made according to a functional or tabular relationship of process parameters and physical properties of the SOD gap fill material as a function of length of the formed SOD gap fill material.

[0040] Figure 1 is a block diagram representing an arrangement 100 of a vertical 3D stack of X-Point memory devices. X-Point memory devices are non-volatile memory with relatively high endurance because they are not significantly affected by a number of write cycles performed. X-Point memory devices have thin regions of memory cells in a number of columns, where the thin regions are stacked to provide increased density of memory cells. The arrangement 100 has a cross-point structure with vertical electrodes connecting sub-microscopic columns. Individual memory cells 105 can be addressed by selecting a top electrode 115 and a bottom electrode 110 coupled to the individual memory cells 105. As shown in Figure 1 The top electrode 115 is an electrode coupled to more than one memory cell, where the memory cells are coupled to different bottom electrodes, as shown in the middle. Thus, each memory cell can be addressed by activating one assigned top electrode and one assigned bottom electrode. Each memory cell can store a single bit of data. The arrangement 100 shows a column of two memory cells in a stack, where the top electrode of the memory cells, such as the top electrode 115, is the bottom electrode of the memory cell at the top of the stack of two memory cells.

[0041] Each memory cell, such as memory cell 105, can be coupled to one of its assigned electrodes via a selector 120. Selector 120 can be implemented without a transistor to enable its associated memory cell to be written or read. Selector 120 can be arranged as a bidirectional threshold switch (OTS). An OTS is a two-terminal symmetric voltage sensitive switching device. An OTC can be implemented as a glass switch that returns to a relatively high resistance state in response to a current through the switch falling below a hold current value after transitioning from the relatively high resistance state to a conductive state.

[0042] In arrangement 100, there are gaps between columns of stacked memory cells, which are presented for ease of discussion. These gaps can be filled with a dielectric gap fill using SOD during the manufacturing process. Several SODs can be used, including but not limited to SOG. The SOD can be a PLAD cured SOD.

[0043] Figure 2 is a representation 200 of two stacks 201-1 and 201-2 that are part of a 3D X-Point device, where the two stacks 201-1 and 201-2 are separated and covered by a dielectric gap fill 202. Each of the stacks is structured in the same way. The dielectric gap fill 202 can be a PLAD cured SOD. Several SODs can be used, including but not limited to SOG. The dielectric gap fill 202 can be used in an array trench in a 3D X-Point device. The stack 201-1 and thus the stack 201-2 can further include segments stacked on the part shown in Figure 2

[0044] ​Stack 201-1 and thus stack 201-2 is a type of stack that includes a PM region 205 and a selector device (SD) 220. Stack 201-1 can be arranged perpendicular to an access line 210, such as a word line, on a bottom, with a bottom electrode 212 on the access line 210, the SD 220 on the bottom electrode 212, and a middle electrode 214 on the SD 220. The PM region 205 is arranged over the middle electrode 214 and separated from the middle electrode 214 by a sheet region 204. The PM can be a chalcogenide-based PM. Another sheet region 206 can be disposed on the PM region 205, with a top electrode 215 disposed on the sheet region 206. A hard mask (HM) 218 can optionally be disposed over the top electrode 215, where the HM 218 can typically be silicon nitride. Stack 201-1 can include a first seal region 216 and a second seal region 217. The bottom, middle, and top electrodes can be implemented using different electrode materials or the same material. The electrode material can include, but is not limited to, carbon. The sheets 204 and 206 can include tungsten. The first seal region 216 can be silicon nitride 216, and the second seal region 217 can be silicon nitride. Other dielectric seal materials can be used.

[0045] Figure 3 is a representation 300 of two stacks 301-1 and 301-2 in a 3D X-Point device, where the two stacks 301-1 and 301-2 are separated and covered by a dielectric gap filler 302. Each of the stacks is structured in the same way. The dielectric gap filler 302 can be a PLAD cured SOD. Several SODs can be used, including, but not limited to, SOG. The dielectric gap filler 302 can be used in array trenches in a 3D X-Point device. Stack 301-1 and thus stack 301-2 can further include segments stacked on the portions shown in Figure 3

[0046] Stack 301-1 and thus stack 301-2 is a type of stack that includes a SD 320, in which there is no PM region. Stack 301-1 can be arranged perpendicular to an access line 310, such as a word line, on a bottom, with a bottom electrode 312 on the access line 310, the SD 320 on the bottom electrode 312, and a top electrode 315 on the SD 320. A HM 318 can optionally be disposed on the top electrode 315, where the HM 318 can typically be silicon nitride. Stack 301-1 can include a first seal region 316 and a second seal region 317. The bottom and top electrodes can be implemented using different electrode materials or the same material. The electrode material can include, but is not limited to, carbon. The first seal region 316 can be silicon nitride 316, and the second seal region 317 can be silicon nitride. Other dielectric seal materials can be used.

[0047] ​Figure 4 is a representation 400 of a portion of a plurality of stacks 401-1,... 401-7 in a 3D X-Point device, where the plurality of stacks are separated and covered by a dielectric gap filler 402. Each of the stacks is structured in the same way. The dielectric gap filler 402 can be a PLAD cured SOD. A number of SODs can be used including, but not limited to, SOG. The dielectric gap filler 402 can be used in an array trench in a 3D X-Point device. Although seven stacks are shown, 3D X-Point can have more than seven or less than seven stacks.

[0048] Stack 401-1 and thus the other stacks of the 3D X-Point device can be structured similarly to stack 201-1 of Figure 2 . Stack 401-1 includes a PM region 405 and a SD 420. Stack 401-1 can be arranged perpendicular to an access line 410, e.g., a word line, on a bottom with a bottom electrode 412 on the access line 410, the SD 420 on the bottom electrode 412, and a middle electrode 414 on the SD 420. The PM region 405 is arranged above the middle electrode 414 and separated from the middle electrode 414 by a sheet region 404. The PM region 405 can be a chalcogenide based PM. Another sheet region 406 can be disposed on the PM region 405 with a top electrode 415 disposed on the sheet region 406. A HM structured as regions 419 and 418 can optionally be disposed above the top electrode 415, where the HM can generally be silicon nitride. Stack 201-1 can include a sealing region 417. The bottom, middle, and top electrodes can be implemented using different electrode materials or the same material. The electrode materials can include, this is but not limited to, carbon. The sheets 404 and 406 can include tungsten. The sealing region 417 can be a nitride region. Other dielectric sealing materials can be used.

[0049] Although Figures 1 to 4To demonstrate the implementation of PLAD cured SOD as a dielectric gap filler in a 3D X-Point device, the PLAD cured SOD can be implemented as a dielectric that provides electrical isolation in several other electronic devices. For example, the PLAD cured SOD can be used in DRAM memory and NAND type memory. In a 3D memory array of SRAM devices, a low-k SOD can be used to provide electrical isolation. In a NAND type memory array, the PLAD cured SOD can be implemented as a SOG disposed in regions with high aspect ratio. In a NAND type memory array, the PLAD cured SOD can be implemented as a SOG disposed in regions with low aspect ratio. Low aspect ratio structures have a height to width (h / w) ratio less than 10 / 1 and high aspect ratio structures have a h / w ratio greater than 10 / 1. For use in DRAM devices, NAND type memory devices, and other electronic devices, PLAD cured SODs other than PLAD cured SOG can be used, such as PLAD cured carbon rich SODs.

[0050] Figure 5 is a representation of a device 500 for plasma doping of a wafer 503. The device 500 includes a chamber 530 with a showerhead 534 coupled to a gas line 532. A precursor flows through the gas line 532 and the showerhead 534 into the chamber 530. The device 500 includes a radio frequency (RF) generator 536 for forming a plasma 538 above the wafer 503 mounted on a platform that can be configured as a heater 535. The heater can be coupled to a negative potential source 537. Excess gas from the process can be pumped out of the chamber 530 through an exhaust or exit port 538.

[0051] When the RF generator 536 coupled to the showerhead 534 is turned on, the RF power ionizes the dopant gas flowing from the gas line 532 through the showerhead 534. Positive ions are attracted to the negative potential provided by the negative potential source 537 and accelerated toward the wafer 503. The RF signal is used to dissociate the dopant molecules ionized in the plasma. These ions are accelerated by the negative bias potential provided by the negative potential source 537. The RF generator 536 can provide pulsed plasma doping in a PLAD process. This type of doping can provide high dose, low energy doping, which can be used for ultra-shallow junctions, such as 10 16 cm -2 or greater levels of dose and implant energies less than 500 eV. As compared to beam line ion implantation, the entire wafer can be doped in one step. The PLAD process can provide conformal doping for 3D structures as a non-line-of-sight process that can be adapted for a variety of structures, such as, but not limited to, deep trench sidewalls and FinFet structures. The device 500 can be used for PLAD curing of SOD materials in a wide variety of electronic devices.

[0052] In various embodiments, SOD can be cured using PLAD with He as the dopant ion (this is referred to as He PLAD). He PLAD can be implemented in different formats with respect to one or more of dose, implant energy, pressure, temperature, and exposure time. He PLAD irradiation in different scenarios is considered. Low pressure of 4 mTorr, which is the pressure of the most well-known conventional method, can provide radiation from soft X-ray to EUV with violet-blue plasmas. High pressure of 10 mTorr, which is 2.5 times higher than 4 mTorr, can provide far-infrared (IR) radiation with micro-red plasmas. Low energy of 100 V, which is 80 times lower than the most well-known conventional method energy of 8 KV operation, can help a “radiation-dominant” process. The combination of PLAD with the radiation provided by using He can be varied in the PLAD energy range between 8 kV and 100 V to find the optimal process conditions. He II provides a photon energy of 40.81 eV, which is in the soft X-ray range, and He I provides a photon energy of 21.22 eV (He I), which is in the EUV range.

[0053] For example, H + and He + High energy light ion implantation of low dose ions can be used to improve cross-linking of organosiloxanes, formation of Si-O-Si bonding of organosiloxanes to improve mechanical strength. Implanted ions cause homolytic bond breakage, allowing -Si-O-Si- cross-link formation. Homolytic bond breakage is the dissociation of a molecule’s chemical bond, where each of the fragments retains one of the originally bonded electrons. It is expected that the lighter the ion used, for example, H + and He + The effect is stronger. It should be noted that in contrast, the oxy radical plasma is damaging the C-SOD and in some cases can remove most of the carbon from the SOD by oxidation. This oxidation condition is also damaging the chalcogenide memory cells and the sealing dielectric layer. Using the oxy radical plasma also makes the C-SOD more porous so that it will act as a reservoir for etch contaminants, post-CMP slurry particles, or aqueous solutions.

[0054] Figure 6 Table 640 shows experimental results of curing C-SOD using conventional methods and different PLAD methods. Only the furnace process did not use an implant tool or implant species. Processes that used implanted beam lines are identified with BL as the implant tool. Implant species are defined by the type of dopant, implant energy, and dose. For example, line 7 of beam line implant tool F8k3E15 is an implant species of fluoride with a dose of 3E15 at an implant energy of 8 KeV. Group 642 is the He PLAD results, which are explicitly the best results of the group with respect to hardness and Young’s modulus. The PLAD process can be extended to Ge, B, C, F, and other dopants.

[0055] Figure 7 Table 740 shows experimental results of curing C-SOD using conventional methods and different PLAD methods. UV BKM refers to the most well-known method for UV treatment. Values for hardness and Young's modulus are averaged at about 250 nm, and values in parentheses are at the surface within 20 nm. Dry etch rates are at the PMME layer. High energy (8 keV) He PLAD can make C-SOD too hard such that the etch rate is about zero, and also has degraded electrical properties. Low energy (E) and very low energy (VLE) He PLAD processes, which can be defined as between 1 kV and 250 V, show most improvements. Note that ultra-low energy is defined as 250 eV and lower. These improvements include better near-surface hardness or Young's modulus properties, better electrical properties, reduced etch rates, and acceptable volume shrinkage. These improvements over just furnace and UV treatment can provide better near-surface mechanical strength to improve CMP and dry etching issues, and maintain bulk regions with good chemical or thermal stability.

[0056] Figure 8 Table 840 shows density profiles from X-ray reflectometry (XRR) measurements of SiOC SOD. Such measurements provide information for tuning SOD. Tuning can be performed by selecting parameters from a set of parameters for PLAD curing of SOD. Tuning by using a selected set of parameters can be based on surface modification versus bulk modification of SOD films associated with different sets of parameters. In Table 840, G1 through G7 are sets of parameters for He PLAD, where each set includes parameters of implant energy, dose, time, and pressure. In Table 840, POR means recorded process and p is density. The region of SOD from 0 to 1 nm of SOD from the vertical end of SOD above and opposite the substrate is the surface region, and the region from 1 to 4 nm from the vertical end is the near-surface region, and more than 4 nm from the vertical end is the bulk region of SOD.

[0057] Using He PLAD of set G1 or set G2 results in densification of the volume of SiOC by He PLAD with the parameters of the respective set. Using He PLAD of parameters of any of sets G4, G5, G6, and G7 results in densification of the surface of SiOC by He PLAD for the respective set, with the bulk remaining in a non-densified state. Using He PLAD of parameters of set G3 is a borderline result between the two groups of sets.

[0058] Figures 9A to 9C Three scenarios are shown associated with the sets of parameters for PLAD of C-SOC shown in Table 840, such as Figure 8 Figure 9A ​A high energy implant 944 is shown where the surface region (0 to 1 nm) and near surface region (1 to 4 nm) are softened while the bulk region is densified. Figure 9B A low energy, high dose implant 946 is shown where the surface region (0 to 1 nm), near surface region (1 to 4 nm), and bulk region are virtually unaltered. Figure 9C A low and medium energy implant 948 is shown where the surface region (0 to 1 nm) and near surface region (1 to 4 nm) are densified while the bulk region is not densified.

[0059] Figure 10 A stopping and range of ions in matter (SRIM) simulation of He concentration profile is shown. Curve 1047 shows He concentration versus depth of C-SOD for surface region used for CMP. The parameter set (also referred to as recipe) for He PLAD of C-SOD used in the simulation is He dopant species at 1 KeV implant energy for a dose of 1E16, which is written in as HE1K1E16 in Figure 10 Additionally, He concentration measurements by secondary ion mass spectroscopy (SIMS) and nuclear reaction analysis (NRA) can be done directly at wafer level of final product and can be completely non-destructive. Non-destructive process does not include cross-section process, does not include assembly process, and does not include sample preparation. In He concentration can be as high as 1E21 / cm 3 and can be detected by SIMS measurement. According to the X-Point process flow, the top surface of the He-PLAD treated C-SOD region can be removed by CMP planarization by about 200 to

[0060] Figure 11 A flowchart is a feature of an embodiment of an example method 1100 of preparing a dielectric film in an electronic device. At 1110, a spin-on dielectric is formed as a dielectric to provide electrical isolation in an electronic device. The spin-on dielectric can be formed as one of a number of different materials. The spin-on dielectric can be provided as a spin-on glass. The spin-on dielectric can be a carbon-containing spin-on dielectric. The spin-on dielectric can be a carbon-rich spin-on dielectric. The spin-on dielectric can include, but is not limited to, one or more of the following: an organic spin-on dielectric, an organic SOD with varying carbon content from about 10% to 60% by atomic percent, and a photoimageable SOD.

[0061] At 1120, while fabricating an electronic device, the spin-on dielectric is cured by plasma doping the spin-on dielectric. The PLAD process can be implemented as an oxygen-free PLAD process. The PLAD process can be implemented using one or more dopant species. The PLAD can be implemented with a dopant that is an oxygen-free dopant. The PLAD can include doping with helium. The PLAD can include, but is not limited to, doping with one or more of: hydrogen, nitrogen, boron, diborane, fluoride, boron trifluoride, carbon, and germanium. The PLAD can include using a dopant that provides a photon energy greater than 10 eV.

[0062] Variations of the method 1100, or methods similar to the method 1100, can include several different embodiments that can be combined depending on the application of such a method or the architecture or process flow of an integrated circuit in which such a method is implemented. Such a method can include selectively modifying physical properties of the spin-on dielectric by applying implant energies and implant doses at levels selected according to a relationship of implant energy or implant dose to length of the spin-on dielectric. Selectively modifying the spin-on dielectric of a dielectric gap filler by tuning implant energies and implant doses can allow Si-O-Si crosslinking structures to form. Modification of physical properties of the SOD can include modification of one or more of thermal properties, optical properties, chemical properties, electrical properties, and mechanical properties. Selectively modifying the spin-on dielectric can include modifying a surface region of the spin-on dielectric relative to a bulk region of the spin-on dielectric or modifying a bulk region of the spin-on dielectric relative to a surface region of the spin-on dielectric. Modifying the spin-on dielectric can include densifying a surface region while the bulk region remains undensified or softening the surface region while densifying the bulk region. Optical properties such as, but not limited to, refractive index and absorption coefficient can be modified along the length of the spin-on dielectric. Selectively modifying the spin-on dielectric can include using implant energies ranging from 100 eV to 10 KeV. Additionally, carbon-free SODs or inorganic SODs having a dielectric constant in the range from about 5.6 to about 7.6 can be densified by PLAD curing.

[0063] Variations of the method 1100, or methods similar to the method 1100, can include subjecting the spin-on dielectric to a chemical mechanical polishing (CMP) process after curing. The spin-on dielectric after curing can have a Young's modulus for performing the CMP that exceeds 10 GPa provided by the curing. After curing, the spin-on dielectric can be subjected to a dry etch.

[0064] Figure 12is a flowchart featuring an embodiment of an example method 1200 of preparing a dielectric film in an electronic device. At 1210, a carbon-rich spin-on dielectric (C-SOD) is formed as a dielectric to provide electrical isolation in an electronic device. The C-SOD can be a photo-definable UV-sensitive gapfiller. A UV-sensitive gapfiller is a material that is sensitive to UV light, such as (but not limited to) a photoresist material. At 1220, the C-SOD is cured by subjecting the C-SOD to a combination of plasma ions implants and species of plasma ions implants that provide photon energies greater than 10 eV. The selected ion implant dose of species and implant energy can be selected to provide mechanical strength, such as film hardness and Young's modulus, to assist in integrating the film in an electronic device. The species can include one or more of the following: helium, hydrogen, nitrogen, boron, diborane, fluoride, boron trifluoride, carbon, and germanium.

[0065] Variations of the method 1200 or methods similar to the method 1200 can include several different embodiments that can be combined depending on the application of such methods and / or the architecture or process flow of the integrated circuit for which such methods are implemented. Such methods can include subjecting the C-SOD to a combination of plasma ions implants and species of plasma ions implants for one minute or less than one minute. The C-SOD is subjected to a combination of plasma ions implants and species of plasma ions implants at room temperature.

[0066] Variations of the method 1200 or methods similar to the method 1200 can include selectively modifying physical properties of the C-SOD by applying implant energy and implant dose at levels selected according to a relationship of implant energy or implant dose to length of the C-SOD. The physical properties of the C-SOD can include modification of one or more of thermal properties, optical properties, chemical properties, electrical properties, and mechanical properties. Selectively modifying the C-SOD can include densifying a surface region while the bulk region remains non-densified or softening the surface region while densifying the bulk region. The physical properties can include optical properties of the C-SOD modified along a length of the C-SOD.

[0067] In various embodiments, a memory device can include a three-dimensional memory array and a dielectric film providing electrical isolation in the memory array, where the dielectric film includes a spin-on dielectric (SOD) as a dielectric between stacks of memory cells of the memory array, where the SOD includes carbon and plasma implant ions. The SOD including carbon and plasma implant ions can be implemented from several different material compositions. For example, the SOD can be a carbon-rich SOD. The plasma implant ions can include (but are not limited to) one or more of the following: helium, hydrogen, nitrogen, boron, diborane, fluoride, boron trifluoride, carbon, and germanium.

[0068] Variations of such memory devices may include several different embodiments depending on the application of such memory devices or the combination of memory device architectures. Such memory devices may contain an SOD having physical properties that vary vertically along the SOD. The varying physical property may be density. Other physical properties of the SOD that may vary are one or more of thermal, optical, chemical, electrical, and mechanical properties. Furthermore, the SOD may have a porosity in the range of about 10% to about 50%, wherein the pore size is between about 0.6 nm and 0.7 nm.

[0069] Variations of such memory devices may include three-dimensional memory arrays structured as chalcogenide-based phase change memory arrays. The three-dimensional memory array structure may include an OTS selector device located between access lines and data lines in a stack. In the three-dimensional memory array structure, SOD containing carbon and plasma-implanted ions may have tunable thermal conductivity provided by PLAD curing between array cells, and a balanced thermal barrier among nearest-neighbor cells. The three-dimensional memory array may be a DRAM memory array, and the SOD may be a low-k SOD. The three-dimensional memory array may be a NAND-type memory array in which the SOD is disposed in a region with a high aspect ratio. The three-dimensional memory array may be a NAND-type memory array in which the SOD is disposed in a region with a low aspect ratio.

[0070] Figure 13 A block diagram illustrating an embodiment of Example System 1300 is provided. Example System 1300 includes a memory 1363, which is structured to have a three-dimensional memory array such that a dielectric film providing electrical isolation within the memory array contains SOD as a dielectric between stacks of memory cells in the memory array. The SOD may be structured to include carbon and plasma-implanted ions cured by PLAD from the SOD. PLAD-cured SOD may be implemented according to the various embodiments discussed herein.

[0071] System 1300 may include a controller 1362 operatively coupled to memory 1363. System 1300 may also include electronic device 1367 and peripheral device 1369. One or more of the controller 1362, memory 1363, electronic device 1367 or peripheral device 1369 may be in the form of one or more ICs.

[0072] Bus 1366 provides electrical conductivity between and / or among the various components in system 1300. In embodiments, bus 1366 can include an address bus, a data bus, and a control bus, each of which is independently configured. In alternative embodiments, bus 1366 can provide one or more combined buses, using a common conductive line, which is regulated by controller 1362. Bus 1366 can operate as a network communication structure. Controller 1362 can be in the form of one or more processors.

[0073] Electronic device 1367 can include additional memory. Memory in system 1300 can be structured as one or more types of memory, such as (but not limited to) X-Point memory devices, NAND memory devices, DRAM, static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), synchronous graphics random access memory (SGRAM), double data rate dynamic ram (DDR), double data rate SDRAM, magnetic-based memory, and other types of memory.

[0074] Peripheral devices 1369 can include displays, imaging devices, printing devices, wireless devices, additional storage memory, and control devices that can operate in conjunction with controller 1362. In various embodiments, system 1300 includes (but is not limited to) fiber optic systems or devices, optoelectronic systems or devices, optical systems or devices, imaging systems or devices, and information handling systems or devices, such as wireless devices, wireless systems or devices, telecommunication systems or devices, and computers.

[0075] The following are example embodiments of systems and methods in accordance with the teachings herein.

[0076] Example method 1 can include forming a spin-on dielectric as a dielectric to provide electrical isolation in an electronic device; and curing the spin-on dielectric by plasma doping (PLAD) the spin-on dielectric.

[0077] Example method 2 can include features of example method 1 and can include that the spin-on dielectric is a spin-on glass.

[0078] Example method 3 can include features of any of the preceding example methods and can include selectively modifying a physical property of the spin-on dielectric by applying an implant energy and an implant dosage at a level selected according to a relationship of implant energy or implant dosage to a length of the spin-on dielectric.

[0079] Example method 4 can include features of example method 3 and any of the preceding example methods and can include selectively modifying the spin-on dielectric includes modifying a surface region of the spin-on dielectric relative to a bulk region of the spin-on dielectric or modifying a bulk region of the spin-on dielectric relative to a surface region of the spin-on dielectric.

[0080] Example method 5 can include features of example method 4 and any of the preceding example methods and can include modifying the spin-on dielectric includes densifying a surface region while the bulk region remains undensified or softening the surface region while densifying the bulk region.

[0081] Example method 6 can include features of example method 3 and any of the preceding example methods and can include selectively modifying the spin-on dielectric includes using an implant energy ranging from 100 eV to 10 KeV.

[0082] Example method 7 can include features of any of the preceding example methods and can include the PLAD includes using a dopant that provides a photon energy greater than 10 eV.

[0083] Example method 8 can include features of any of the preceding example methods and can include the PLAD includes doping with helium.

[0084] Example method 9 can include features of any of the preceding example methods and can include the PLAD includes doping with one or more of: hydrogen, nitrogen, boron, diborane, fluoride, boron trifluoride, carbon, and germanium.

[0085] Example method 10 can include features of any of the preceding example methods and can include the spin-on dielectric includes one or more of an organic spin-on dielectric and a photo- imageable spin-on dielectric having a different carbon content from about 10% to 60% by atomic percent.

[0086] Example method 11 can include features of any of the preceding example methods and can include subjecting the spin-on dielectric to a chemical mechanical polishing (CMP) process after curing.

[0087] Example method 12 can include features of example method 11 and any of the preceding example methods and can include the spin-on dielectric has a Young’s modulus for performing the CMP in excess of 10 GPa provided by the curing after curing.

[0088] Example method 13 can include features of any of the preceding example methods and can include subjecting the spin-on dielectric to a dry etch after curing.

[0089] Example method 14 can include forming a carbon-rich spin-on dielectric (C-SOD) as a dielectric to provide electrical isolation in an electronic device; and curing the C-SOD by subjecting the C-SOD to a combination of a plasma ion implant and species of the plasma ion implant that provides a photon energy greater than 10 eV.

[0090] Example method 15 can include the features of example method 14 and can include subjecting the C-SOD to the combination for one minute or less.

[0091] Example method 16 can include the features of either of example methods 14 and 15 and can include subjecting the C-SOD to the combination at room temperature.

[0092] Example method 17 can include the features of any of the preceding example methods 14-16 and can include selectively modifying a physical property of the C-SOD by applying an implant energy and an implant dose at a level selected according to a relationship of the implant energy or implant dose to a length of the C-SOD.

[0093] Example method 18 can include the features of example method 17 and any of the preceding example methods 14-16 and can include selectively modifying the C-SOD includes densifying a surface region while the bulk region remains undensified or softening the surface region while densifying the bulk region.

[0094] Example method 19 can include the features of example method 17 and any of the preceding example methods 14-16 and 18 and can include the physical property includes an optical property of the C-SOD modified along a length of the C-SOD.

[0095] Example method 20 can include the features of any of the preceding example methods 14-19 and can include the species includes one or more of: helium, hydrogen, nitrogen, boron, diborane, fluoride, boron trifluoride, carbon, and germanium.

[0096] Example memory device 1 can include a three-dimensional memory array; and a dielectric film providing electrical isolation in the memory array, the dielectric film including a spin-on dielectric (SOD) as a dielectric between stacks of memory cells of the memory array, wherein the SOD includes carbon and plasma implant ions.

[0097] Example memory device 2 can include the features of example memory device 1 and can include the SOD is a carbon-rich SOD.

[0098] Example memory device 3 can include the features of any of the preceding example memory devices and can include the SOD has a physical property that changes vertically along the SOD.

[0099] Example memory device 4 can include features of example memory device 3 and any of the foregoing example memory devices and can include that the physical property is density.

[0100] Example memory device 5 can include features of any of the foregoing example memory devices and can include that the plasma implant ions include one or more of: helium, hydrogen, nitrogen, boron, diborane, fluoride, boron trifluoride, carbon, and germanium.

[0101] Example memory device 6 can include features of any of the foregoing example memory devices and can include that the three-dimensional memory array is a chalcogenide-based phase change memory array.

[0102] Example memory device 7 can include features of any of the foregoing example memory devices and can include that the three-dimensional memory array is a dynamic random access memory (DRAM) memory array and the SOD is a low-k SOD.

[0103] Example memory device 8 can include features of any of the foregoing example memory devices and can include that the three-dimensional memory array is a NAND-type memory array, where the SOD is disposed in a region having a high aspect ratio.

[0104] Example memory device 9 can include features of any of the foregoing example memory devices and can include that the three-dimensional memory array is a NAND-type memory array, where the SOD is disposed in a region having a low aspect ratio.

[0105] Example memory device 10 can include features of any of the foregoing example memory devices and can include that the SOD has a porosity in a range from about 10% to about 50%, where the pore size is between about 0.6 nm and 0.7 nm.

[0106] In example memory device 11, any of the memory devices of example memory devices 1-10 can include a memory device incorporated into an electronic system that further comprises a host processor and a communication bus extending between the host processor and the memory device.

[0107] In example memory device 12, any of the memory devices of example memory devices 1-11 can be modified to include any of the structures present in another example memory device 1-11.

[0108] In example memory device 13, any of the devices of any of the memory devices of example memory devices 1-12 can further include a machine-readable storage configured to store instructions as physical states, wherein the instructions are usable to perform one or more operations of the device.

[0109] In example memory device 14, any of example memory devices 1-13 can be adapted and operated to perform operations in accordance with any of the following example methods 1-20.

[0110] As taught herein, for example, H + , He + and other high energy light ions can be used for low dose implantation to improve cross-linking of organosiloxanes to improve mechanical strength. The cross-linking can include formation of Si-O-Si bonds. Such techniques using He PLAD processes can increase hardness by greater than 22 times and increase Young's modulus by greater than 10 times. Implanted ions cause homolytic bond breakage allowing -Si-O-Si- cross-link formation and thus mechanical property enhancement. These increased mechanical properties include hardness, Young's modulus, increase, and densification. The lighter the ion used, the stronger the effect.

[0111] SOD region solidification by PLAD can be used to selectively densify the surface or bulk of gapfill films by tuning ion dose and energy. The tuning can be provided by selecting PLAD process parameters (e.g., implant energy and ion dose) that match the desired density modification of the SOD region. In addition to density modification, other physical properties of the SOD region can be modified along the length of the SOD region.

[0112] He PLAD processes are high throughput, low cost, low temperature processes that can be used to solidify C-SOD films by the combination of high energy radiation and plasma ions implants. He and species other than He can be used to solidify SOD in structures that can have a wide variety of aspect ratios, depths, and functions when forming electronic devices.

[0113] Additionally, PLAD solidification is not only limited to a particular type of SOD (e.g., C-SOD), but also applicable to any other SOD or SOG materials and polymers used in STI gapfill. Other SOD materials can include organic SODs with different carbon content from about 10% to 60% atomic percent and photoimageable SODs and others. Due to the applicability to a range of SOD materials and structures, PLAD solidification can be applicable to 3D X-Point memory devices. DRAM devices include using low k SOD fill, NAND memory includes NAND devices with gapfill films of larger area, and other electronic devices.

[0114] While particular embodiments have been illustrated and described herein, it will be appreciated that any arrangement according to the principles of the application will be within the scope of the application. Various embodiments use arrangements of and / or combinations of the embodiments described herein. The foregoing description is intended to be illustrative only and not limiting of the application. The words or terminology employed are used for descriptive purposes only and are not intended to limit the scope of the application. Additionally, in the preceding detailed description, it is to be understood that all the features disclosed in the foregoing description and / or shown in the accompanying drawings are meant to be methods of possible implementations of the application. It is to be understood that the foregoing description is intended to be illustrative only and not limiting of the scope of the application.

Claims

1. A memory device comprising: Three-dimensional memory array; and A dielectric film that provides electrical isolation in the memory array, the dielectric film comprising spin-coated dielectric SOD as a dielectric between stacks of memory cells in the memory array, wherein the SOD comprises carbon and plasma-implanted ions, the SOD having a carbon content that varies along the length of the SOD.

2. The memory device according to claim 1, wherein the SOD is carbon-rich SOD.

3. The memory device according to claim 1, wherein the SOD has a physical property that changes vertically along the SOD.

4. The memory device according to claim 3, wherein the physical property is density.

5. The memory device of claim 1, wherein the plasma implanted ion comprises one or more of the following: helium, hydrogen, nitrogen, boron, diborane, fluoride, carbon, and germanium.

6. The memory device of claim 5, wherein the plasma-implanted ions comprise boron trifluoride.

7. The memory device according to claim 1, wherein the three-dimensional memory array is a chalcogenide-based phase change memory array.

8. The memory device of claim 1, wherein the three-dimensional memory array is a dynamic random access memory (DRAM) array, and the SOD is a low-k SOD.

9. The memory device of claim 1, wherein the three-dimensional memory array is a NAND-type memory array, and wherein the SOD is disposed in a region having a high aspect ratio.

10. The memory device of claim 1, wherein the three-dimensional memory array is a NAND-type memory array, and wherein the SOD is disposed in a region having a low aspect ratio.

11. The memory device of claim 1, wherein the SOD has a porosity in the range of 10% to 50%, wherein the pore size is between 0.6 nm and 0.7 nm.

12. An electronic device comprising: integrated circuit; as well as Spin-coated dielectric SOD that provides electrical isolation in the integrated circuit, wherein the SOD comprises carbon and plasma-implanted ions, the SOD having a carbon content that varies along the length of the SOD and one or more additional properties that vary with the length of the SOD.

13. The electronic device of claim 12, wherein the one or more additional properties that vary with the length include properties based on the dosage of the plasma implanted ions.

14. The electronic device of claim 12, wherein the SOD comprises spin-coated glass.

15. The electronic device of claim 12, wherein the plasma-implanted ion comprises one or more of the following: nitrogen, boron, diborane, fluoride, carbon, or germanium.

16. The electronic device of claim 15, wherein the plasma-implanted ion comprises boron trifluoride.

17. The electronic device of claim 12, wherein the SOD comprises one or more of an organic spin-coated dielectric or a photoimageable spin-coated dielectric having a carbon content ranging from 10% to 60% in atomic percentage.

18. The electronic device of claim 12, wherein the SOD comprises a carbon-rich spin-coated dielectric C-SOD.

19. The electronic device of claim 18, wherein the C-SOD comprises SiOx, wherein x>1, plus 50% carbon for porosity.

20. The electronic device of claim 12, wherein the integrated circuit is a three-dimensional cross-point memory device.

21. The electronic device of claim 12, wherein the SOD comprises a densified surface region and an undensified body region.

22. The electronic device of claim 12, wherein the SOD is a gap filler in the gaps between columns of stacked memory cells in a memory device.

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