Single diffusion isolation method of fin field effect transistor

Abstract

The invention provides a single diffusion isolation method of a fin type field effect transistor. The method comprises the following steps: forming an annular semiconductor fin body on a substrate; forming a single-diffusion isolation groove in the annular semiconductor fin body through an etching process to isolate a plurality of semiconductor fin body units; forming a protection layer on the top surface, the peripheral side surfaces and the surface of the substrate of the semiconductor fin body unit; removing the semiconductor fin body unit needing to be cut off through etching, removing the second photoetching mask and cleaning the semiconductor fin body unit; removing the edge of the semiconductor fin body unit through etching; removing the protective layer; depositing an insulating dielectric layer on the substrate; and carrying out planarization processing on the insulating dielectric layer. According to the invention, the uniformity and consistency of the fin body structure on the whole chip can be ensured, and the overall performance of the chip is improved. Meanwhile, by means of the manufacturing process, the problem of boundary photoresist height difference caused by the fin body area and the non-fin body area on the surface of the substrate can be avoided, defects in the manufacturing process are reduced, and the product yield is improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a single diffusion isolation method for a fin field effect transistor. Background Art

[0002] Single Diffusion Block (SDB) is a process technology widely used in the field of semiconductor manufacturing, mainly used to form isolation areas in integrated circuits. In the process of FinFET, after the fin is formed, the unnecessary fin needs to be removed by a cutting process (Fin cut). For FinFET, the current common process of single diffusion isolation is to perform the process after the fin is formed and the fin removal process is completed.

[0003] At present, the critical dimension (CD) in the SDB process has reached the limit of photolithography technology. At the same time, due to the presence of the fin area and the non-fin area on the silicon wafer surface, the thickness difference between the two areas will occur during the photoresist coating process, resulting in the following problems:

[0004] 1) Difficulty in exposure and development: Due to the non-uniformity of photoresist thickness, the exposure and development process becomes more difficult, which not only affects the precise transfer of the pattern, but also makes it more difficult to control the critical dimension (CD) of the device.

[0005] 2) Boundary area defects: At the junction of the fin area and the non-fin area, the etching is uneven due to the difference in photoresist thickness, which is prone to defects. These defects may affect the performance and reliability of the device, and even cause device failure.

[0006] 3) During the photoresist removal and cleaning process, the cleaning solution corrodes the fin body, which can easily affect the critical dimension (CD) of the device.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a single diffusion isolation method for a fin field effect transistor, which is used to solve the problem that the key dimensions of the device are difficult to control and defects are easily generated due to the difference in photoresist thickness during the preparation process of the fin field effect transistor in the prior art.

[0009] To achieve the above-mentioned purpose and other related purposes, the present invention provides a single diffusion isolation method for a fin field effect transistor, the single diffusion isolation method comprising: providing a substrate, forming an annular semiconductor fin on the substrate; defining a single diffusion isolation groove area on the annular semiconductor fin by a first photolithography mask, and forming a single diffusion isolation groove in the semiconductor fin by an etching process to isolate a plurality of semiconductor fin units, and removing the first photolithography mask; forming a protective layer on the top surface, the surrounding side surfaces and the substrate surface between the semiconductor fin units; defining the semiconductor fin unit area to be removed by a second photolithography mask, and The semiconductor fin unit to be removed is removed by etching, the second photolithography mask is removed and the semiconductor fin unit is cleaned; the edge area of ​​the semiconductor fin unit to be removed is defined by a third photolithography mask, and the edge of the semiconductor fin unit to be removed is removed by etching to form a plurality of independent semiconductor fin strips, the third photolithography mask is removed and the semiconductor fin strips are cleaned; the protective layer is removed; an insulating dielectric layer is deposited on the substrate, the insulating dielectric layer at least fills the gaps between adjacent semiconductor fin strips and the single diffusion isolation trench and covers the semiconductor fin strips; and the insulating dielectric layer is planarized.

[0010] Optionally, a hard mask layer is further formed on the top of the annular semiconductor fin, and the hard mask layer includes a stack of a silicon nitride layer and a silicon oxide layer.

[0011] Optionally, when the insulating dielectric layer is planarized, the planarization stops at the surface of the silicon nitride layer.

[0012] Optionally, the protective layer includes a titanium nitride layer, and the thickness of the titanium nitride layer is 2 nanometers to 50 nanometers.

[0013] Optionally, the method for forming the protective layer includes one of a sputtering process, an evaporation process and a chemical vapor deposition process.

[0014] Optionally, defining a single diffusion isolation groove area by a first photolithography mask includes the steps of: forming a spin-coated carbon layer on the substrate, wherein the spin-coated carbon layer completely fills the gaps between the annular semiconductor fins and has a thickness greater than the height of the annular semiconductor fins; forming an anti-reflective layer on the surface of the spin-coated carbon layer; forming a photoresist layer on the anti-reflective layer; exposing and developing the photoresist layer to define a single diffusion isolation groove area in the photoresist layer.

[0015] Optionally, a semiconductor fin unit area to be removed is defined by a second photolithography mask, comprising the steps of: forming a spin-coated carbon layer on the substrate, the spin-coated carbon layer completely filling the gaps between the semiconductor fin units and the single diffusion isolation trench, and having a thickness greater than the height of the semiconductor fin unit; forming an anti-reflective layer on the surface of the spin-coated carbon layer; forming a photoresist layer on the anti-reflective layer; exposing and developing the photoresist layer to define the semiconductor fin unit area to be removed in the photoresist layer.

[0016] Optionally, removing the semiconductor fin units to be removed includes: defining all semiconductor fin unit regions to be removed at one time through a second photolithography mask, and removing all semiconductor fin units to be removed at one time through etching.

[0017] Optionally, removing the semiconductor fin unit to be cut off includes: defining a portion of the semiconductor fin unit area to be cut off through a second photolithography mask, and removing the portion of the semiconductor fin unit to be cut off by etching, removing the second photolithography mask and cleaning the semiconductor fin unit; repeating the above steps until all the semiconductor fin units to be cut off are removed.

[0018] Optionally, the edge region of the semiconductor fin unit to be removed is defined by a third photolithography mask, comprising the steps of: forming a spin-coated carbon layer on the substrate, the spin-coated carbon layer completely filling the gaps between the semiconductor fin units and the single diffusion isolation trench, and having a thickness greater than the height of the semiconductor fin unit; forming an anti-reflective layer on the surface of the spin-coated carbon layer; forming a photoresist layer on the anti-reflective layer; exposing and developing the photoresist layer to define the edge region of the semiconductor fin unit to be removed in the photoresist layer.

[0019] Optionally, removing the edges of the semiconductor fin units to be cut off includes: defining all the edge regions of the semiconductor fin units to be cut off at one time through a third photolithography mask, and removing all the edges of the semiconductor fin units to be cut off at one time by etching to form multiple independent semiconductor fin strips.

[0020] Optionally, removing the edge of the semiconductor fin unit that needs to be cut off includes: defining a portion of the semiconductor fin unit edge area that needs to be cut off through a third photolithography mask, and removing a portion of the semiconductor fin unit edge that needs to be cut off by etching, removing the third photolithography mask and cleaning the semiconductor fin unit; repeating the above steps until all the semiconductor fin unit edges that need to be cut off are removed to form a plurality of independent semiconductor fin strips.

[0021] Optionally, when cleaning the semiconductor fin unit, the cleaning solution used has a high etching selectivity ratio between the object to be cleaned and the protective layer, and the high etching selectivity ratio is greater than or equal to 10:1.

[0022] Optionally, when removing the protective layer, the etchant used has a high etching selectivity ratio between the protective layer and the semiconductor fin body strip, and the high etching selectivity ratio is greater than or equal to 10:1.

[0023] As described above, the single diffusion isolation method of the fin field effect transistor of the present invention has the following beneficial effects:

[0024] The present invention first etches the single diffusion isolation groove before removing the semiconductor fin body, which can avoid the single diffusion isolation groove etching process, the problem of uneven exposure caused by the inconsistent height of the photoresist due to the presence of the fin body area and the non-fin body area, and can ensure the uniformity and consistency of the fin body structure on the entire chip, thereby improving the overall performance of the chip. At the same time, through the manufacturing process of the present invention, the problem of the height difference of the boundary photoresist caused by the presence of the fin body area and the non-fin body area on the substrate surface can be avoided, the generation of defects in the manufacturing process can be reduced, and the yield of the product can be improved.

[0025] Since the semiconductor fin surface is covered with titanium nitride after SDB preparation, the present invention has good corrosion resistance, so in the subsequent debonding and cleaning process, the loss of critical dimensions of the semiconductor fin (Fin CD loss) can be reduced, thereby ensuring the design accuracy of the semiconductor fin unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0027] Figures 1 to 16 It is a schematic structural diagram showing each step of the single diffusion isolation method of the fin field effect transistor according to an embodiment of the present invention, wherein: Figures 1 to 4 , Figure 6 to Figure 9 and Figure 13 to Figure 15 Contains a first cross-sectional view (left) and a second cross-sectional view (right) of the device, wherein the first cross-sectional view and the second cross-sectional view are cross-sectional views in two directions perpendicular to each other. Figure 5 , 10 , 11, 12 and Fig.16 Shown are schematic diagrams of the top view structure of the device.

[0028] Component number description

[0029] 101 Substrate

[0030] 102 Ring-shaped semiconductor fin

[0031] 1021 semiconductor fin unit

[0032] 1022 semiconductor fin strips

[0033] 103 Silicon nitride layer

[0034] 104 Silicon oxide layer

[0035] 105 Spin-on carbon layer

[0036] 106 Anti-reflection layer

[0037] 107 Photoresist layer

[0038] 108 Single Diffusion Isolation Trench

[0039] 109 protective layer

[0040] 110 Spin-on carbon layer

[0041] 111 Anti-reflective layer

[0042] 112 Photoresist layer

[0043] 113 The semiconductor fin unit area to be removed

[0044] 114 Insulation dielectric layer

[0045] 115 Third photolithography mask DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0048] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0049] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0050] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0051] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0052] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0053] like Figures 1 to 16 As shown, this embodiment provides a single diffusion isolation method for a fin field effect transistor, and the single diffusion isolation method includes the following steps:

[0054] like Figure 1 As shown, step 1) is first performed to provide a substrate 101 and to form a ring-shaped semiconductor fin 102 on the substrate 101 .

[0055] In some embodiments, the substrate 101 may be, for example, a silicon substrate, a germanium substrate, a germanium silicon substrate, a silicon carbide substrate, etc., and is not limited to the examples listed here. In this embodiment, the substrate 101 is a single crystal silicon substrate.

[0056] In one embodiment, forming an annular semiconductor fin 102 on a substrate 101 includes the following steps:

[0057] Step 1-1), forming a single crystal epitaxial layer, such as a single crystal silicon epitaxial layer, on the substrate 101 through an epitaxial process;

[0058] Step 1-2), etching the single crystal epitaxial layer through a photolithography process and an etching process to form a plurality of semiconductor fins 102 arranged at intervals. The semiconductor fins 102 can be, for example, a rectangular ring, and the rectangular ring includes opposite two side edges and opposite two end edges, wherein the spacing between two adjacent rectangular rings is preferably equal, and the spacing between the opposite two side edges in the same rectangular ring is preferably equal to the spacing between two adjacent rectangular rings.

[0059] In one embodiment, a hard mask layer is retained or formed on the top of the annular semiconductor fin 102, and the hard mask layer includes a stack of a silicon nitride layer 103 and a silicon oxide layer 104. The silicon nitride layer 103 can be used as a process stop layer for a subsequent planarization process.

[0060] like Figure 2 to Figure 5 As shown, step 2 is then performed to define a single diffusion isolation trench area on the annular semiconductor fin 102 through a first photolithography mask, and to form a single diffusion isolation trench 108 in the annular semiconductor fin 102 through an etching process to isolate a plurality of semiconductor fin units 1021, and then remove the first photolithography mask.

[0061] In one embodiment, defining a single diffusion isolation trench region by a first photolithography mask comprises the following steps:

[0062] Step 2-1), forming a spin-on carbon layer 105 on the substrate 101, wherein the spin-on carbon layer 105 completely fills the gaps between the annular semiconductor fins 102, and the thickness of the spin-on carbon layer 105 is greater than the height of the annular semiconductor fins 102;

[0063] Step 2-2), forming an anti-reflection layer 106 on the surface of the spin-coated carbon layer 105;

[0064] Step 2-3), forming a photoresist layer 107 on the anti-reflection layer 106;

[0065] Step 2-4), exposing and developing the photoresist layer 107 to define a single diffusion isolation trench region in the photoresist layer 107, such as Figure 2 shown.

[0066] Then, the spin-on carbon layer 107 and the annular semiconductor fin 102 in the single diffusion isolation trench region may be etched in sequence by a dry etching process to form a single diffusion isolation trench 108 in the annular semiconductor fin 102 to isolate a plurality of semiconductor fin units 1021. Figure 3 As shown, the first photolithography mask is finally removed by wet cleaning or dry process, as shown in FIG. Figure 4 and Figure 5 shown.

[0067] The present invention etches the single diffusion isolation groove 108 before removing the annular semiconductor fin 102, which can avoid the problem of uneven exposure caused by the inconsistent height of the photoresist due to the presence of the fin area and the non-fin area during the etching process of the single diffusion isolation groove 108, and can ensure the uniformity and consistency of the fin structure on the entire chip, thereby improving the overall performance of the chip. At the same time, through the manufacturing process of the present invention, the problem of the height difference of the boundary photoresist caused by the presence of the fin area and the non-fin area on the surface of the substrate 101 can be avoided, the generation of defects in the manufacturing process can be reduced, and the yield of the product can be improved.

[0068] like Figure 6 As shown, step 3) is then performed to form a protective layer 109 on the top surface, the surrounding side surfaces of the semiconductor fin unit 1021 and the surface of the substrate 101 between the semiconductor fin unit 1021. The protective layer 109 is used to protect the surrounding side surfaces of the semiconductor fin unit 1021 from being corroded during the subsequent cleaning process (such as cleaning photoresist residues, etc.), thereby ensuring the stability of the key dimensions of the semiconductor fin unit 1021.

[0069] In one embodiment, the protective layer 109 preferably includes a titanium nitride layer. The thickness of the protective layer 109 is preferably sufficient to ensure its protective function and to ensure that it can be efficiently removed later. Therefore, the thickness of the titanium nitride layer is preferably between 2 nanometers and 50 nanometers, for example, 2 nanometers, 3 nanometers, 5 nanometers, 10 nanometers, 50 nanometers, etc., and is not limited to the examples listed here.

[0070] In one embodiment, the protective layer 109 is formed by a method comprising a sputtering process, an evaporation process, and a chemical vapor deposition process.

[0071] like Figure 7 to Figure 10 As shown, step 4 is then performed, the semiconductor fin unit region 113 to be removed is defined by a second photolithography mask, and the semiconductor fin unit 1021 to be removed is removed by etching, the second photolithography mask is removed, and the semiconductor fin unit 1021 is cleaned;

[0072] In one embodiment, defining the semiconductor fin unit region 113 to be removed by a second photolithography mask includes the following steps:

[0073] Step 4-1), forming a spin-on carbon layer 110 on the substrate 101, wherein the spin-on carbon layer 110 completely fills the gaps between the semiconductor fins 1021 and the single diffusion isolation trenches 108, and has a thickness greater than the height of the semiconductor fins 1021;

[0074] Step 4-2), forming an anti-reflection layer 111 on the surface of the spin-coated carbon layer 110; forming a photoresist layer 112 on the anti-reflection layer 111;

[0075] Step 4-3), exposing and developing the photoresist layer 112 to define the semiconductor fin unit region 113 to be removed in the photoresist layer 112 .

[0076] In one embodiment, removing the semiconductor fin unit 1021 that needs to be cut off includes: defining all the semiconductor fin unit areas 113 that need to be cut off at one time through a second photolithography mask, and removing all the semiconductor fin unit 1021 that needs to be cut off at one time by etching. This method can effectively improve the removal efficiency of the semiconductor fin unit 1021.

[0077] In another embodiment, removing the semiconductor fin unit 1021 that needs to be cut off includes: defining a portion of the semiconductor fin unit area 113 that needs to be cut off through a second photolithography mask, and removing the portion of the semiconductor fin unit 1021 that needs to be cut off by etching, removing the second photolithography mask and cleaning the semiconductor fin unit 1021; repeating the above steps until all the semiconductor fin units 1021 that need to be cut off are removed. This method can effectively improve the removal accuracy of the semiconductor fin unit 1021.

[0078] After removing the second photolithography mask, since some mask material will remain on the device, the semiconductor fin unit 1021 will be cleaned in this embodiment. During cleaning, the surface of the semiconductor fin 102 of the present invention is covered with titanium nitride, which has good corrosion resistance. Therefore, during the cleaning process, the loss of key dimensions of the semiconductor fin unit 1021 can be reduced, and the design accuracy of the semiconductor fin 102 can be maintained.

[0079] In one embodiment, when cleaning the semiconductor fin unit 1021, the cleaning solution used has a high etching selectivity between the object to be cleaned and the protective layer 109, and the high etching selectivity is greater than or equal to 10:1. Preferably, the high etching selectivity is greater than or equal to 50:1.

[0080] like Figure 11-12 As shown, then step 5) is performed, the semiconductor fin unit edge 1021 edge region to be removed is defined by a third photolithography mask 115, and the semiconductor fin unit 1021 edge to be removed is removed by etching to form a plurality of independent semiconductor fin strips 1022, the third photolithography mask is removed and the semiconductor fin strips 1022 are cleaned.

[0081] In one embodiment, the edge region of the semiconductor fin unit 1021 to be removed is defined by a third photolithography mask 115, comprising the steps of: forming a spin-coated carbon layer on the substrate, the spin-coated carbon layer completely filling the gaps between the semiconductor fin units 1021 and the single diffusion isolation trench 108, and having a thickness greater than the height of the semiconductor fin unit 1021; forming an anti-reflective layer on the surface of the spin-coated carbon layer; forming a photoresist layer on the anti-reflective layer; exposing and developing the photoresist layer to define the edge region of the semiconductor fin unit 1021 to be removed in the photoresist layer.

[0082] In one embodiment, removing the edges of the semiconductor fin unit 1021 that need to be cut off includes: defining all the edge areas of the semiconductor fin unit 1021 that need to be cut off at one time through a third photolithography mask 115, and removing all the edges of the semiconductor fin unit 1021 that need to be cut off at one time by etching to form multiple independent semiconductor fin strips 1022.

[0083] In one embodiment, removing the edge of the semiconductor fin unit 1021 that needs to be cut off includes: defining a portion of the edge area of ​​the semiconductor fin unit 1021 that needs to be cut off through a third photolithography mask 115, and removing a portion of the edge of the semiconductor fin unit 1021 that needs to be cut off by etching, removing the third photolithography mask 115 and cleaning the semiconductor fin unit 1021; repeating the above steps until all the edges of the semiconductor fin unit 1021 that need to be cut off are removed to form a plurality of independent semiconductor fin strips 1022.

[0084] like Fig.13 As shown, step 6) is then performed to remove the protection layer 109.

[0085] For example, when removing the protective layer 109 , the etchant used has a high etching selectivity between the protective layer 109 and the semiconductor fin strip 1022 , and the high etching selectivity is greater than or equal to 10:1. Preferably, the high etching selectivity is greater than or equal to 50:1.

[0086] like Fig.14 As shown, step 7 is then performed to deposit an insulating dielectric layer 114 on the substrate 101 . The insulating dielectric layer 114 at least fills the gaps between adjacent semiconductor fin strips 1022 and the single diffusion isolation trenches 108 and covers the semiconductor fin strips 1022 .

[0087] In one embodiment, the insulating dielectric layer 114 may be deposited on the substrate 101 by a chemical vapor deposition (CVD) process. The material of the insulating dielectric layer 114 may be, for example, silicon dioxide.

[0088] like Figure 15-16As shown, step 8) is finally performed to planarize the insulating dielectric layer 114 .

[0089] In one embodiment, a chemical mechanical polishing (CMP) process may be used to planarize the insulating dielectric layer 114 . When the planarization process is performed on the insulating dielectric layer 114 , the planarization process stops at the surface of the silicon nitride layer 103 .

[0090] As described above, the single diffusion isolation method of the fin field effect transistor of the present invention has the following beneficial effects:

[0091] The present invention first etches the single diffusion isolation groove before removing the semiconductor fin body, which can avoid the single diffusion isolation groove etching process, the problem of uneven exposure caused by the inconsistent height of the photoresist due to the presence of the fin body area and the non-fin body area, and can ensure the uniformity and consistency of the fin body structure on the entire chip, thereby improving the overall performance of the chip. At the same time, through the manufacturing process of the present invention, the problem of the height difference of the boundary photoresist caused by the presence of the fin body area and the non-fin body area on the substrate surface can be avoided, the generation of defects in the manufacturing process can be reduced, and the yield of the product can be improved.

[0092] Since the semiconductor fin surface is covered with titanium nitride after SDB preparation, the present invention has good corrosion resistance, so in the subsequent debonding and cleaning process, the loss of critical dimensions of the semiconductor fin (Fin CD loss) can be reduced, thereby ensuring the design accuracy of the semiconductor fin unit.

[0093] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0094] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A single diffusion isolation method for a fin field effect transistor, characterized in that: The single diffusion isolation method comprises: Providing a substrate, and forming a ring-shaped semiconductor fin on the substrate; Defining a single diffusion isolation trench region on the annular semiconductor fin body by a first photolithography mask, and forming a single diffusion isolation trench in the semiconductor fin body by an etching process to isolate a plurality of semiconductor fin body units, and removing the first photolithography mask; forming a protective layer on the top surface, surrounding side surfaces of the semiconductor fin unit and the surface of the substrate between the semiconductor fin units; Defining a semiconductor fin unit region to be removed by a second photolithography mask, removing the semiconductor fin unit to be removed by etching, removing the second photolithography mask and cleaning the semiconductor fin unit; Defining the edge area of ​​the semiconductor fin unit to be removed by a third photolithography mask, and removing the edge of the semiconductor fin unit to be removed by etching to form a plurality of independent semiconductor fin strips, removing the third photolithography mask and cleaning the semiconductor fin strips; removing the protective layer; Depositing an insulating dielectric layer on the substrate, wherein the insulating dielectric layer at least fills the gaps between adjacent semiconductor fin strips and the single diffusion isolation trench and covers the semiconductor fin strips; The insulating dielectric layer is planarized.

2. The single diffusion isolation method of the fin field effect transistor according to claim 1, characterized in that: A hard mask layer is also formed on the top of the annular semiconductor fin, and the hard mask layer includes a stack of a silicon nitride layer and a silicon oxide layer.

3. The single diffusion isolation method of the fin field effect transistor according to claim 2, characterized in that: When the insulating dielectric layer is planarized, the planarization stops at the surface of the silicon nitride layer.

4. The single diffusion isolation method of the fin field effect transistor according to claim 1, characterized in that: The protective layer includes a titanium nitride layer, and the thickness of the titanium nitride layer is 2 nanometers to 50 nanometers.

5. The single diffusion isolation method of the fin field effect transistor according to claim 1, characterized in that: The method for forming the protective layer includes one of a sputtering process, an evaporation process and a chemical vapor deposition process.

6. The single diffusion isolation method of the fin field effect transistor according to claim 1, characterized in that: Defining a single diffusion isolation trench region by a first photolithography mask comprises the steps of: Forming a spin-on carbon layer on the substrate, wherein the spin-on carbon layer completely fills the gaps between the annular semiconductor fins and has a thickness greater than the height of the annular semiconductor fins; forming an anti-reflection layer on the surface of the spin-on carbon layer; forming a photoresist layer on the anti-reflective layer; The photoresist layer is exposed and developed to define a single diffusion isolation trench region in the photoresist layer.

7. The single diffusion isolation method of the fin field effect transistor according to claim 1, characterized in that: Defining the semiconductor fin unit area to be removed by a second photolithography mask includes the following steps: Forming a spin-on carbon layer on the substrate, wherein the spin-on carbon layer completely fills the gaps between the semiconductor fin units and the single diffusion isolation trench, and has a thickness greater than the height of the semiconductor fin unit; forming an anti-reflection layer on the surface of the spin-on carbon layer; forming a photoresist layer on the anti-reflective layer; The photoresist layer is exposed and developed to define a semiconductor fin unit region to be removed in the photoresist layer.

8. The single diffusion isolation method of the fin field effect transistor according to claim 1, characterized in that: The semiconductor fin units to be removed include: All semiconductor fin unit regions to be removed are defined at one time through the second photolithography mask, and all semiconductor fin unit regions to be removed are removed at one time through etching.

9. The single diffusion isolation method of the fin field effect transistor according to claim 1, characterized in that: The semiconductor fin units to be removed include: Defining a portion of the semiconductor fin unit area to be removed by a second photolithography mask, removing a portion of the semiconductor fin unit to be removed by etching, removing the second photolithography mask and cleaning the semiconductor fin unit; The above steps are repeated until all the semiconductor fin units that need to be cut off are removed.

10. The single diffusion isolation method of the fin field effect transistor according to claim 1, characterized in that: Defining the edge region of the semiconductor fin unit to be removed by a third photolithography mask includes the following steps: Forming a spin-on carbon layer on the substrate, wherein the spin-on carbon layer completely fills the gaps between the semiconductor fin units and the single diffusion isolation trench, and has a thickness greater than the height of the semiconductor fin unit; forming an anti-reflection layer on the surface of the spin-on carbon layer; forming a photoresist layer on the anti-reflective layer; The photoresist layer is exposed and developed to define the edge region of the semiconductor fin unit to be removed in the photoresist layer.

11. The single diffusion isolation method of the fin field effect transistor according to claim 10, characterized in that: Removing the edges of the semiconductor fin units that need to be cut off includes: All the semiconductor fin unit edge regions to be cut off are defined at one time through the third photolithography mask, and all the semiconductor fin unit edges to be cut off are removed at one time through etching to form a plurality of independent semiconductor fin strips.

12. The single diffusion isolation method of the fin field effect transistor according to claim 10, characterized in that: Removing the edges of the semiconductor fin units that need to be cut off includes: Defining a portion of the semiconductor fin unit edge region to be removed by a third photolithography mask, removing a portion of the semiconductor fin unit edge to be removed by etching, removing the third photolithography mask and cleaning the semiconductor fin unit; The above steps are repeated until all edges of the semiconductor fin units to be cut off are removed to form a plurality of independent semiconductor fin strips.

13. The single diffusion isolation method of the fin field effect transistor according to claim 1, characterized in that: When cleaning the semiconductor fin unit, the cleaning solution used has a high etching selectivity ratio between the object to be cleaned and the protective layer, and the high etching selectivity ratio is greater than or equal to 10:

1.

14. The single diffusion isolation method of the fin field effect transistor according to claim 1, characterized in that: When removing the protective layer, the etchant used has a high etching selectivity ratio between the protective layer and the semiconductor fin body strip, and the high etching selectivity ratio is greater than or equal to 10:1.

Images