Display panel and display device

Abstract

The invention relates to a display panel and a display device and relates to the technical field of display, a first display area is located on at least one side of a second display area, a first data line in the first display area is electrically connected with a second connecting line segment through a first connecting line segment, and the narrow frame design of a product can be achieved. The display area comprises first pixel columns and second pixel columns which are alternately arranged in the second direction, and at least two second connecting line segments located between adjacent second data lines in the second display area are connected with the pixel columns of the same type in a one-to-one correspondence mode. Therefore, the voltage signals on the adjacent second connecting line segments are the same, and the coupling difference between at least part of adjacent signal lines is reduced, thereby facilitating the improvement of the accuracy and stability of signals transmitted by the data lines, and facilitating the improvement of the overall display effect of the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] From the CRT (Cathode Ray Tube) era to the LCD (Liquid Crystal Display) era, and now to the OLED (Organic Light-Emitting Diode) era and the LED display era, the display industry has experienced decades of development and has changed with each passing day. The display industry is closely related to our lives, from traditional mobile phones, tablets, TVs and PCs to today's smart wearable devices, VR, car displays and other electronic devices, all of which are inseparable from display technology.

[0003] With the development of display technology, users have higher and higher requirements for display products. How to reduce the signal coupling problem within the display panel has become one of the technical problems that need to be solved urgently at this stage. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a display device for reducing the coupling difference between adjacent signal lines and improving the phenomenon of overloaded screen splitting and uneven brightness.

[0005] In a first aspect, the present disclosure provides a display panel, comprising a display area, wherein the display area comprises a first display area and a second display area, and along a second direction, the first display area is located at least on one side of the second display area;

[0006] The display area includes a plurality of data lines extending along a first direction and arranged along the second direction, the data lines include a plurality of first data lines located in the first display area and a plurality of second data lines located in the second display area, and the first direction and the second direction intersect;

[0007] The display area further includes a plurality of first connection lines, the first connection lines include a first connection line segment and a second connection line segment that are electrically connected, the first connection line segment extends along the second direction and is connected to the first data line; the second connection line segment extends along the first direction;

[0008] The second connecting line segments are arranged in the same layer as the second data lines, and along the second direction, at least two adjacent second data lines include at least two second connecting line segments;

[0009] The display area includes a plurality of pixel columns arranged along the second direction, and the pixel columns include a first pixel column and a second pixel column arranged alternately along the second direction; at least two second connecting line segments located between two adjacent second data lines are both connected to the first pixel column, or are both connected to the second pixel column.

[0010] In a second aspect, based on the same inventive concept, the present disclosure further provides a display device, comprising the display panel as described in the first aspect.

[0011] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0012] In the display panel and display device provided by the present disclosure, along the second direction, the first display area in the display area is located at least on one side of the second display area, and a first connection line connected to the first data line is introduced into the display panel, and the first connection line includes a first connection line segment extending along the second direction and a second connection line segment extending along the first direction, wherein the second connection line segment is located in the second display area, and the two ends of the first connection line segment are respectively connected to the first data line and the second connection line segment, and the display area includes a plurality of pixel columns arranged along the second direction, and the pixel columns include a first pixel column and a second pixel column arranged alternately along the second direction; at least two second connection line segments located between two adjacent second data lines are connected to the first pixel column in a one-to-one correspondence, or are connected to the second pixel column in a one-to-one correspondence. In this way, the voltage signals on the adjacent second connection line segments are the same, and the coupling difference between at least some adjacent signal lines becomes smaller, which is conducive to improving the accuracy and stability of the signal transmitted by the data line, and is conducive to improving the overall display effect of the display panel.

[0013] Of course, any product implementing the present invention does not necessarily need to achieve all of the above-mentioned technical effects at the same time.

[0014] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1FIG. 1 is a top view of a display panel provided by an embodiment of the present disclosure;

[0018] Figure 2 FIG. 1 is a schematic diagram showing a position relationship between a second connecting line segment and a second data line in an embodiment of the present disclosure;

[0019] Figure 3 The figure shows a schematic diagram of a connection relationship between sub-pixels and data lines in an embodiment of the present disclosure;

[0020] Figure 4 The figure shows a connection relationship diagram between the first fan-out line and the sub-pixel in the embodiment of the present disclosure;

[0021] Figure 5 Shown is a schematic diagram of an arrangement of the first fan-out line in an embodiment of the present disclosure;

[0022] Figure 6 Shown is a schematic diagram of an arrangement of the second fan-out line in an embodiment of the present disclosure;

[0023] Figure 7 The figure shows a connection diagram of the first fan-out line and the multi-way distribution unit in the embodiment of the present disclosure;

[0024] Figure 8 The figure shows a schematic diagram of the position relationship between the multiplexing unit and the driving chip in the embodiment of the present disclosure;

[0025] Fig. 9 FIG. 1 is another schematic diagram showing another positional relationship between the multiplexing unit and the driver chip in the embodiment of the present disclosure;

[0026] Fig.10 Shown is Figure 1 A cross-sectional view along the cc direction in the display panel is shown in the figure;

[0027] Fig.11 Shown is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0029] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0030] Figure 1FIG. 1 is a top view of a display panel provided by an embodiment of the present disclosure. Figure 2 FIG. 1 is a schematic diagram showing a position relationship between the second connecting line segment and the second data line in an embodiment of the present disclosure. Figure 1 and Figure 2 The present disclosure provides a display panel 100, including a display area AA, the display area AA includes a first display area AA1 and a second display area AA2, along the second direction D2, the first display area AA1 is located at least on one side of the second display area AA2; optionally, in the embodiment of the present disclosure, the second display area AA2 is located in the middle area of ​​the display panel 100, and the first display area AA1 is located on one side or both sides of the display panel 100 along the second direction D2, Figure 2 An example is given in which the first display area AA1 is disposed on both sides of the second display area AA2.

[0031] The display area AA includes a plurality of data lines 10 extending along a first direction D1 and arranged along a second direction D2, the data lines 10 include a plurality of first data lines 11 located in the first display area AA1 and a plurality of second data lines 12 located in the second display area AA2, the first direction D1 and the second direction D2 intersect; Figure 2 Only some of the data lines 10 included in the display panel 100 are illustrated, and the number of the data lines 10 actually included in the display panel 100 is not limited. Figure 2 The description is made by taking the case where the first data line 11 is located on both sides of the second data line 12 along the second direction D2 as an example.

[0032] The display area AA also includes a plurality of first connection lines L1, the first connection lines L1 include an electrically connected first connection line segment L11 and a second connection line segment L12, the first connection line segment L11 extends along the second direction D2 and is connected to the first data line 11; the second connection line segment L12 extends along the first direction D1; in this way, the first data line 11 located in the first display area AA1 can obtain a signal through the second connection line segment L12 located in the second display area AA2. It should be noted that the extension of the first connection line segment L11 along the second direction D2 means that the overall extension trend of the first connection line segment L11 is the second direction D2, and does not limit the first connection line segment L11 to be a straight line. Similarly, the extension of the second connection line segment L12 along the first direction D1 means that the overall extension trend of the second connection line segment L12 is the second direction D2, and does not limit the second connection line segment L12 to be a straight line.

[0033] The second connecting line segment L12 is arranged in the same layer as the second data line 12, and at least two second connecting line segments L12 are included between at least part of the adjacent two second data lines 12 along the second direction D2; in the second display area AA2, when the second connecting line segment L12 is arranged in the same layer as the second data line 12, there is no need to introduce a new film layer for the second connecting line segment L12, and the second connecting line segment L12 can be formed while manufacturing the second data line 12, which is beneficial to simplifying the overall film layer structure of the display panel 100, saving the number of masks in the manufacturing process, and improving the production efficiency of the display panel 100. Optionally, the first data line 11, the second data line 12, and the second connecting line segment L12 are arranged in the same layer, so that the first data line 11, the second data line 12, and the second connecting line segment L12 can be manufactured in one production process using one mask, which is more beneficial to simplifying the film layer structure of the display panel 100.

[0034] Figure 3 FIG. 1 is a schematic diagram showing a connection relationship between sub-pixels and data lines in an embodiment of the present disclosure. Figures 1 to 3 The display area AA includes a plurality of pixel columns 30 arranged along the second direction D2, and the pixel columns 30 include first pixel columns 31 and second pixel columns 32 alternately arranged along the second direction D2; at least two second connecting line segments L12 located between two adjacent second data lines 12 are both connected to the first pixel columns 31 in a one-to-one correspondence, or are both connected to the second pixel columns 32 in a one-to-one correspondence.

[0035] In this embodiment, please refer to Figure 3, taking the first second connection line segment L121 and the second second connection line segment L122 from left to right as an example, the first second connection line segment L121 is electrically connected to a first pixel column 31, and the second second connection line segment L122 is electrically connected to another first pixel column 31. Along the second direction D2, the first second connection line segment L121 and the second second connection line segment L122 are located between two second data lines 12; since different pixel columns 30 transmit different data signals, coupling occurs between adjacent data lines 10 that transmit different data signals. For example, the second data line 121 located on the left side of the first second connection line segment L121 is electrically connected to the second pixel column 32, and the first second connection line segment L121 is electrically connected to the first pixel column 31. Since the pixel columns 30 connected to the first second connection line segment L121 on the left side are of different types, the first second connection line segment L121 and the second data line 121 on the left side are electrically connected to each other. The voltage signals on the two data lines 121 are different, and coupling will occur between the two. The first second connection line segment L121 is electrically connected to the first pixel column 31, and the second second connection line segment L122 is electrically connected to another first pixel column 31. Since the pixel columns 30 connected to the first second connection line segment L121 and the second second connection line segment L122 are of the same type, the voltage signals on the first second connection line segment L121 and the second second connection line segment L122 are the same, which can reduce the influence of coupling. The second second connection line segment L122 is electrically connected to the first pixel column 31, and the second data line 122 located on the right side of the second second connection line segment L122 is connected to another first pixel column 31. Since the pixel columns 30 connected to the second second connection line segment L122 and the second data line 122 on the right are of the same type, the voltage signals on the second second connection line segment L122 and the second data line 122 on the right are the same, which can reduce the influence of coupling.If the second second connection line segment L122 is electrically connected to the second pixel column 32, since the second second connection line segment L122 and the first second connection line segment L121 are connected to different types of pixel columns 30, and the left second data line 121 is also connected to different types of pixel columns 30 as the first second connection line segment L121, the voltage signals on the first second connection line segment L121 and the second second connection line segment L122 are different, and the voltage signals on the first second connection line segment L121 and the left second data line 121 are also different, and the first second connection line segment L121 is connected to the left second data line 121. 21 will be affected by the dual coupling of different voltage signals on the second second connection line segment L122 and the left second data line 121, resulting in display distortion; if the second second connection line segment L122 is electrically connected to the second pixel column 32, since the second second connection line segment L122 and the first second connection line segment L121 are connected to different types of pixel columns 30, and the right second data line 122 is also connected to a different type of pixel column 30 with the second second connection line segment L122, the second second connection line segment L122 and the first second connection line segment L121 are connected to different types of pixel columns 30. The voltage signals are different, and the voltage signals on the second second connection line segment L122 and the second data line 122 on the right are also different. The second second connection line segment L122 will be affected by the dual coupling of the different voltage signals on the first second connection line segment L121 and the second data line 122 on the right, resulting in display distortion. In addition, among the first second connection line segment L121, the second second connection line segment L122, the adjacent left second data line 121, and the adjacent right second data line 122, three signal lines are connected to different first pixel columns 31 in a one-to-one correspondence. Compared with the case where two second connection line segments L12 located in adjacent second data lines 12 are respectively connected to different types of pixel columns 30, when two adjacent second connection line segments L12 are respectively connected to the same type of pixel columns 30, the coupling effect between some adjacent signal lines can be reduced; in this way, by connecting at least two second connection line segments L12 between two adjacent second data lines 12 to the same type of pixel columns 30 in a one-to-one correspondence, the coupling effect between some adjacent signal lines can be reduced, and the overload split screen and uneven brightness of the display panel 100 can be improved.

[0036] Please continue to refer to Figure 3 In a display panel 100 provided by an embodiment of the present disclosure, a first pixel column 31 includes a first color sub-pixel P1 and a second color sub-pixel P2 arranged along a first direction D1, and a second pixel column 32 includes a third color sub-pixel P3 arranged along the first direction D1.

[0037] Specifically, in the pixel arrangement structure shown in the present embodiment, the first pixel column 31 and the second pixel column 32 are alternately arranged in sequence along the second direction D2, the first pixel column 31 includes sub-pixels of two colors alternately arranged, and the second pixel column 32 includes sub-pixels of only one color. In an optional embodiment provided by the present disclosure, the first color sub-pixel P1 in the first pixel column 31 may be a red sub-pixel, the second color sub-pixel P2 in the first pixel column 31 may be a blue sub-pixel, and the third color sub-pixel P3 in the second pixel column 32 may be a green sub-pixel; or, the first color sub-pixel P1 in the first pixel column 31 may be a blue sub-pixel, the second color sub-pixel P2 in the first pixel column 31 may be a red sub-pixel, and the third color sub-pixel P3 in the second pixel column 32 may be a green sub-pixel; Figure 3 Only some of the sub-pixels included in the display panel 100 are illustrated, and the types and arrangements of the sub-pixels actually included in the display panel 100 are not limited.

[0038] The present embodiment mentions that at least two second connection line segments L12 located between two adjacent second data lines 12 are both connected to the first pixel column 31, which means that at least two second connection line segments L12 located between two adjacent second data lines 12 are connected to at least two first pixel columns 31 in a one-to-one correspondence, and further, the second connection line segment L12 is connected to the first color sub-pixel P1 and the second color sub-pixel P2 in the first pixel column 31; the present embodiment mentions that at least two second connection line segments L12 located between two adjacent second data lines 12 are both connected to the second pixel column 32, which means that at least two second connection line segments L12 located between two adjacent second data lines 12 are connected to at least two second pixel columns 32 in a one-to-one correspondence, and further, the second connection line segment L12 is connected to the third color sub-pixel P3 in the second pixel column 32. In this way, by inserting at least two second connection line segments L12 between adjacent second data lines 12, and the inserted second connection line segments L12 are all connected one-to-one with the same type of pixel columns 30, the voltage signals on adjacent second connection line segments L12 are made the same, thereby reducing the coupling effect and improving the display defects caused by the coupling effect.

[0039] Figure 4 FIG. 1 is a schematic diagram showing a connection relationship between the first fan-out line and the sub-pixel in the embodiment of the present disclosure. Figures 1 to 4 The display panel 100 provided by the present disclosure includes a first non-display area NA, and the first non-display area NA is located on one side of the display area AA along the first direction D1. Figures 1 to 4 An example is given in which the first non-display area NA is disposed below the display area AA.

[0040] The first non-display area NA includes a first fan-out area Q1, and the first fan-out area Q1 includes a plurality of first fan-out lines S1 extending along the first direction D1 and arranged along the second direction D2; Figure 4 Only part of the first fan-out lines S1 included in the first fan-out area Q1 is illustrated, and the number of the first fan-out lines S1 actually included in the first fan-out area Q1 is not limited. Figure 4 An example is taken for description that the first fan-out lines S1 extend along the first direction D1 and are sequentially arranged along the second direction D2 .

[0041] Two first fan-out lines S1 adjacent to any first fan-out line S1 are connected to the first pixel column 31 and the second pixel column 32 respectively. Specifically, the first fan-out area Q1 can be, for example, a bending area of ​​the display panel. The first fan-out area Q1 is located on one side of the display area AA along the first direction D1, and the first fan-out area Q1 includes a plurality of first fan-out lines S1 extending along the first direction D1 and arranged along the second direction D2. In this embodiment, please refer to Figure 4 , taking the second first fan-out line S112 on the left as an example, the first first fan-out line S111 on the left adjacent to the second first fan-out line S112 on the left is electrically connected to the second pixel column 32, and the third first fan-out line S113 on the left adjacent to the second first fan-out line S112 on the left is electrically connected to the first pixel column 31; taking the third first fan-out line S113 on the left as an example, the second first fan-out line S112 on the left adjacent to the third first fan-out line S113 on the left is electrically connected to the first pixel column 31, and the fourth first fan-out line S114 on the left adjacent to the third first fan-out line S113 on the left is electrically connected to the second pixel column 32... They are not listed one by one here. It is only necessary to know that in this embodiment, a first fan-out line S1 located in the first fan-out area Q1 and adjacent to any first fan-out line S1 is connected to the first color sub-pixel P1 and the second color sub-pixel P2 in the first pixel column 31, and adjacent to any first fan-out line S Another first fan-out line S1 adjacent to the first fan-out line 1 is connected to the third color sub-pixel P3 in the second pixel column 32. The voltage signal on the first pixel column 31 is different from the voltage signal on the second pixel column 32. Any first fan-out line S1 is simultaneously affected by the coupling of the voltage signals on the first pixel column 31 and the second pixel column 32 connected to the two adjacent fan-out lines. That is, any first fan-out line S1 in the first fan-out area Q1 will be affected by the coupling of two different voltage signals. Each first fan-out line S1 is affected by the same coupling as other first fan-out lines S1. Each first fan-out line S1 is evenly affected by the coupling, which is beneficial to reducing the coupling difference. In this way, the two first fan-out lines S1 adjacent to any first fan-out line S1 are respectively connected to different types of pixel columns 30 in a one-to-one correspondence, so that any first fan-out line S1 can be evenly affected by the coupling, reducing the coupling difference between different first fan-out lines S1, which is beneficial to improving the display effect.

[0042] Figure 5 FIG. 1 is a schematic diagram showing an arrangement of the first fan-out line in an embodiment of the present disclosure. Please refer to FIG. Figure 5 In a display panel 100 provided by an embodiment of the present disclosure, a first fan-out line S1 includes a first A fan-out line S11 and a first B fan-out line S12, the first A fan-out line S11 is connected to the second data line 12, and the first B fan-out line S12 is connected to the first data line 11 through a second connecting line segment L12; the first fan-out line S1 includes a first group W1 and a second group W2 alternately arranged along a second direction D2, the first group W1 includes at least two first A fan-out lines S11, and the second group W2 includes at least two first B fan-out lines S12; the first A fan-out line S11 and the first B fan-out line S12 are arranged on the same layer.

[0043] In the present embodiment, the first fan-out lines S1 in the first fan-out area Q1 include a first group W1 and a second group W2, and the first group W1 and the second group W2 are alternately arranged in sequence along the second direction D2. The first group W1 includes at least two first A fan-out lines S11, and the first A fan-out lines S11 are connected to the second data line 12. The second group W2 includes at least two first B fan-out lines S12, and the first B fan-out lines S12 are connected to the first data line 11. That is, in the first fan-out area Q1, the first fan-out lines S1 are grouped according to the types of the data lines 10 connected thereto, and the two groups of first A fan-out lines S11 and first B fan-out lines S12 connected to different data lines 10 are alternately arranged in the second direction D2, so that the first fan-out lines S1 in the same group are connected to the data lines 10 of the same type. In this way, crosstalk can be further reduced and the display effect can be improved.

[0044] Optionally, the first A fan-out line S11 and the first B fan-out line S12 are arranged in the same layer. In this way, the first A fan-out line S11 and the first B fan-out line S12 can be manufactured using one mask in one production process, which is more conducive to simplifying the film layer structure of the display panel 100.

[0045] Please refer to Figure 4 In a display panel 100 provided by an embodiment of the present disclosure, the first non-display area NA also includes a second fan-out area Q2 located between the display area AA and the first fan-out area Q1, the second fan-out area Q2 includes a second fan-out line S2, the first fan-out line S1 is connected to the second data line 12 or the second connecting line segment L12 through the second fan-out line S2; at least part of the second fan-out line S2 is arranged in a different layer from the data line 10.

[0046] Specifically, the first non-display area NA in the display panel 100 further includes a second fan-out area Q2. Along the first direction D1, the second fan-out area Q2 is located at one side of the display area AA, and the second fan-out area Q2 is located between the display area AA and the first fan-out area Q1. The second fan-out area Q2 includes a plurality of second fan-out lines S2. An end of the second fan-out line S2 close to the first fan-out area Q1 is connected to the first fan-out line S1. An end of the second fan-out line S2 close to the display area AA is partially connected to the second connecting line segment L12, and partially connected to the second data line 12. At least part of the second fan-out line S2 is arranged in a different layer from the data line 10 of the display area AA. For example, if the data line 10 of the display area AA is located in the second metal layer M2, at least part of the second fan-out line S2 is located in the first metal layer M1, or, The capacitor metal layer MC, or at least one layer of the third metal layer M3, is convenient for winding. The second fan-out line S2 is used to connect the first fan-out line S1 of the first fan-out area Q1, and the second fan-out line S2 is used to connect the second data line 12 of the display area AA and the second connecting line segment L12. Since the arrangement order of the first fan-out line S1, the second data line 12 and the second connecting line segment L12 in the second direction D2 is different, in the direction perpendicular to the display panel 100, multiple second fan-out lines S2 will overlap with each other. When the second fan-out line S2 and the data line 10 are set in the same layer, signal interference will occur between the overlapping second fan-out lines S2, causing display abnormality. In this way, the second fan-out line S2 and the data line 10 are set in different layers, which can facilitate winding and reduce signal interference.

[0047] Figure 6 FIG. 1 is a schematic diagram showing an arrangement of the second fan-out line in an embodiment of the present disclosure. Please refer to FIG. Figure 6 In a display panel 100 provided by an embodiment of the present disclosure, a second fan-out line S2 includes a first end S21 and a second end S22, the first end S21 of at least a portion of the second fan-out line S2 is electrically connected to the second connecting line segment L12, the first end S21 of at least a portion of the second fan-out line S2 is electrically connected to the second data line 12, and the second end S22 of the second fan-out line S2 is connected to the first fan-out line S1; the arrangement order of the first end S21 of the second fan-out line S2 is different from the arrangement order of the second end S22 of the second fan-out line S2.

[0048] Specifically, please combine Figure 5 and Figure 6In an optional embodiment provided by the present disclosure, in the display area AA near the second fan-out area Q2, some of the adjacent second data lines 12 include at least two second connecting line segments L12. Since the first ends S21 of at least some of the second fan-out lines S2 are connected to the second data lines 12, at least some of the first ends S21 of the second fan-out lines S2 are connected to the second connecting line segments L12, that is, along the second direction D2, the arrangement order of the first ends S21 of the second fan-out lines S2 is the same as the arrangement order of the second data lines 12 and the second connecting line segments L12 in the display area AA. The arrangement order of the first ends S21 of the second fan-out lines S2 is the same as the arrangement order of the second data lines 12 and the second connecting line segments L12 in the display area AA. At least part of the second fan-out lines S2 connected to the second connecting line segments L12 is located between the second fan-out lines S2 connected to the two adjacent second data lines 12; the first fan-out area Q1 close to the second fan-out area Q2 includes a plurality of first fan-out lines S1, the first fan-out lines S1 include a first group W1 and a second group W2 alternately arranged along the second direction D2, the first group W1 includes at least two first A fan-out lines S11, the first A fan-out lines S11 are connected to the second data lines 12, the second group W2 includes at least two first B fan-out lines S12, the first B fan-out lines S12 are connected to the first data lines 11, that is, in the first fan-out area Q1, the first A fan-out line S1 includes two groups alternating in sequence along the second direction D2, the first group W1 is connected to the second data line 12, and the second group W2 is connected to the first data line 11. Since the first data line 11 is connected to the first connecting line segment L11, and the first connecting line segment L11 is connected to the second connecting line segment L12, it is equivalent to that the first group W1 connected to the second data line 12 and the second group W2 connected to the second connecting line segment L12 in the first fan-out line S1 are alternately arranged in sequence in the second direction D2. That is, the arrangement order of the second end S22 of the second fan-out line S2 is the same as the arrangement order of the first fan-out line S1 in the second direction D2. The second ends S22 of the second fan-out lines S2 are arranged in the second direction D2 such that the second ends S22 of at least some of the second fan-out lines S2 arranged alternately in sequence are connected to the second data line 12, and the second ends S22 of at least some of the second fan-out lines S2 arranged alternately in sequence are connected to the second connection line segment L12. It can be seen that the first ends S21 and the second ends S22 of the second fan-out lines S2 are arranged in a different order in the second direction D2. In the direction perpendicular to the plane where the display panel 100 is located, the second fan-out lines S2 are at least partially wound. The winding means that at least some of the second fan-out lines S2 are arranged in different layers and the extension direction intersects with other second fan-out lines S2. In this embodiment, by winding the second fan-out lines S2, the first fan-out lines S1 can be grouped while reducing the signal coupling between adjacent data lines 10 in the display area AA, and the coupling influence on any first fan-out line S1 in the first fan-out area Q1 is uniform, thereby improving the overload screen splitting and uneven brightness.

[0049] Figure 7FIG. 1 is a schematic diagram showing a connection between the first fan-out line and the multiplex distribution unit in the embodiment of the present disclosure. Figure 7 The display panel 100 provided by the present disclosure includes a plurality of multiplexing units 20, each of which includes at least two switching elements T; the switching element T includes a control terminal 21, an input terminal 22 and an output terminal 23, the input terminal 22 is connected to a driving chip 30, the output terminal 23 is connected to at least two first fan-out lines S1, and the control terminal 21 is connected to a switch control line K0. Figure 7 The number of switch elements T in the multiplexing unit 20 is only for illustration and does not represent the actual number of switch elements T in the multiplexing unit 20 .

[0050] Please refer to Figure 7 The multiplexing unit 20 includes two switch elements T; the switch element T includes a control terminal 21, an input terminal 22 and an output terminal 23. The input terminal 22 of the two switch elements T of the same multiplexing unit 20 is electrically connected and connected to the driving chip 30. The output terminals 23 of the two switch elements T of the same multiplexing unit 20 are connected to the two first fan-out lines S1 in a one-to-one correspondence; the control terminals 21 of the two switch elements T of the multiplexing unit 20 are connected to the two switch control lines K0 in a one-to-one correspondence.

[0051] It should be noted that the connection or electrical connection mentioned in the embodiment of the present invention may be a direct connection between two connection bodies, or a signal connection formed by other line segments between the two connection bodies, or a signal connection formed by a switch element T (such as a transistor) between the two connection bodies, etc. For example, the output end 23 of the switch element T is connected to the first data line 11 through the first connection line L1, the second fan-out line S2, and the first fan-out line S1.

[0052] Continue to refer Figure 7 In this embodiment, the multiplexing unit 20 corresponds to two switch control lines K0 respectively. 、 K1, two switch elements T in a multiplexing unit 20 are connected to different switch control lines K0 and K1 respectively, and different switch control lines K0 and K1 are used. 、 K1 controls the switch elements T in the same multiplexer unit 20 to be turned on in time division.

[0053] This embodiment is described by taking a multi-way distribution unit 20 including two switch elements T as an example, but does not limit the number of switch elements T actually included in a multi-way distribution unit 20. In some other embodiments of the present disclosure, a multi-way distribution unit 20 may also include three or more switch elements T.

[0054] Optionally, the switch element T in the multiplexing unit 20 is an NMOS tube. When a high level signal is applied to the control terminal 21 of the NMOS tube, the corresponding switch element T is turned on; conversely, when a low level signal is applied to the control terminal 21 of the NMOS tube, the corresponding switch element T is turned off.

[0055] In some other optional embodiments of the present invention, the switch element T in the multi-way distribution unit 20 can also be selected as a PMOS tube. When a low-level signal is applied to the control end 21 of the PMOS tube, the corresponding switch element T is turned on; conversely, when a high-level signal is applied to the control end 21 of the PMOS tube, the corresponding switch element T is turned off.

[0056] Optionally, the switch elements T in the same multiplexing unit 20 are all NMOS tubes or all PMOS tubes.

[0057] Figure 8 FIG. 1 is a schematic diagram showing a positional relationship between a multiplexing unit and a driver chip in an embodiment of the present disclosure. Fig. 9 FIG. 1 is another schematic diagram of the position relationship between the multiplexing unit and the driver chip in the embodiment of the present disclosure. Figure 8 and Fig. 9 The display panel 100 provided by the present disclosure includes a driving chip 30, the first non-display area NA includes a binding area 40, the driving chip 30 is electrically connected to the binding area 40, the multi-way distribution unit 20 is integrated in the driving chip 30, or the multi-way distribution unit 20 is located on the side of the binding area 40 facing the display area AA.

[0058] Specifically, the display panel 100 further includes a driving chip 30, and the driving chip 30 is electrically connected to the binding area 40 in the first non-display area NA. In an optional embodiment provided in the present disclosure, please refer to Figure 8 , the multiplexing unit 20 is integrated with the driver chip 30, and the 16 first fan-out lines S1 in the first fan-out area Q1 are connected to the 16 terminals on the driver chip 30. In another optional embodiment provided in the present disclosure, please refer to Fig. 9 , along the first direction D1, the multiplexing unit 20 is located on the side of the binding area 40 facing the display area AA, that is, the multiplexing unit 20 is not integrated in the driver chip 30. Taking the multiplexing unit 20 including two switch elements T as an example, the 16 first fan-out lines S1 in the first fan-out area Q1 are connected to the 8 terminals on the driver chip 30 through the multiplexing unit 20. The number of terminals on the driver chip 30 in the figure is only for illustration and does not represent the actual number of terminals in the driver chip 30.

[0059] Fig.10 Shown is Figure 1 A cross-sectional view of the panel along the cc direction is shown in the figure. Figures 1 to 10The display panel 100 provided by the present disclosure includes a substrate 00 and a first metal layer M1, a capacitor metal layer MC, a second metal layer M2 and a third metal layer M3 arranged on one side of the substrate 00. Along the thickness direction of the display panel 100, the capacitor metal layer MC is located on a side of the first metal layer M1 away from the substrate, the second metal layer M2 is located on a side of the capacitor metal layer MC away from the substrate, and the third metal layer M3 is located on a side of the second metal layer M2 away from the substrate;

[0060] The data line 10 and the second connecting line segment L12 are located in the second metal layer M2, and the first connecting line segment L11 is located in at least one layer of the first metal layer M1, the capacitor metal layer MC, and the third metal layer M3; or, the data line 10 and the second connecting line segment L12 are located in the third metal layer M3, and the first connecting line segment L11 is located in at least one layer of the first metal layer M1, the capacitor metal layer MC, and the second metal layer M2;

[0061] At least part of the first fan-out line S1 is located in at least one of the first metal layer M1 and the capacitor metal layer MC; at least part of the first fan-out line S1 is located in the second metal layer M2;

[0062] The second fan-out line S2 is located at least one of the first metal layer M1 , the capacitor metal layer MC, the second metal layer M2 , and the third metal layer M3 .

[0063] Optionally, the display panel 100 provided in this embodiment can be a display panel 100 using organic light-emitting diode display technology, that is, an OLED (Organic Light-Emitting Diode) display panel 100, and the basic structure of the light-emitting functional layer of the OLED display panel 100 includes an anode 201, a light-emitting material layer 202 and a cathode 203. When the power supply supplies an appropriate voltage, the holes of the anode 201 and the electrons of the cathode 203 will combine in the light-emitting material layer to produce bright light. Compared with a thin film field effect transistor liquid crystal display, the OLED display device 200 has the characteristics of high visibility and high brightness, and is more power-saving, light in weight and thin in thickness. Of course, in some other embodiments of the present invention, the display panel 100 can also be a display panel using inorganic light-emitting diode display technology, such as a Micro LED display panel, or a Mini LED display panel, etc.

[0064] Fig.10Only the OLED display panel 100 is used for illustration. Optionally, an encapsulation layer 60 is further provided on the side of the cathode 203 away from the anode 201, and the display panel 100 includes a substrate 00 and a first metal layer M1, a capacitor metal layer MC, a second metal layer M2 and a third metal layer M3 provided on one side of the substrate 00. Among them, the first metal layer M1 may be, for example, a gate metal layer, and the gate of the transistor in the display panel 100 may be provided on the first metal layer M1; the capacitor metal layer MC is used to form a capacitor structure with the first metal layer M1 or the second metal layer M2. The source electrode s and the drain electrode d of the transistor T0 in the display panel 100 may be located in the second metal layer M2, and the semiconductor layer poly includes a source region and a drain region, and the source region and the drain region are formed by doping N-type impurity ions or P-type impurity ions. The source electrode s of the transistor is electrically connected to the source region of the semiconductor layer poly through a contact hole, and the drain electrode d of the transistor is electrically connected to the drain region of the semiconductor layer poly through a contact hole. Optionally, the encapsulation layer 50 is a thin film encapsulation layer, including a first inorganic layer 61, an organic layer 62 and a second inorganic layer 63, for isolating water and oxygen to prevent external moisture and oxygen from affecting the luminescent material layer.

[0065] When the second connecting line segment L12 and the data line 10 are set in the second metal layer M2, and the first connecting line segment L11 is set in at least one of the first metal layer M1, the capacitor metal layer MC and the third metal layer M3, the existing film layer of the display panel 100 can be used to set the second connecting line segment L12 and the first connecting line segment L11, and there is no need to add a new film layer in the display panel 100 to set the first connecting line segment L11 and the second connecting line segment L12. This is beneficial to simplify the film layer structure of the display panel 100 and reduce the number of mask plates in the display panel 100 process, thereby saving production costs.

[0066] Similarly, when the second connecting line segment L12 and the data line 10 are set in the third metal layer M3, and the first connecting line segment L11 is set in at least one of the first metal layer M1, the capacitor metal layer MC and the second metal layer M2, the second connecting line segment L12 and the first connecting line segment L11 can be set using the existing film layer of the display panel 100. There is no need to add a new film layer in the display panel 100 to set the first connecting line segment L11 and the second connecting line segment L12. This is also beneficial to simplify the film layer structure of the display panel 100 and reduce the number of mask plates in the display panel 100 manufacturing process, thereby also helping to save production costs.

[0067] In an optional embodiment provided by the present disclosure, at least part of the second fan-out line S2 is located in one of the first metal layer M1, the capacitor metal layer MC, the second metal layer M2, and the third metal layer M3. The second fan-out line S2 is used to connect the first fan-out line S1 of the first fan-out area Q1. The second fan-out line S2 is used to connect the second data line 12 and the second connecting line segment L12 of the display area AA. When the data line 10 and the second connecting line segment L12 are located in the second metal layer M2 or the third metal layer M3, at least part of the second fan-out line S2 and the data line 10 are located in different film layers. At least part of the second fan-out line S2 is located in at least one of the first metal layer M1 and the capacitor metal layer MC. This facilitates winding and reduces signal interference caused by winding the second fan-out line S2 on the same layer. At least part of the second fan-out line S2 is located in at least one layer of the capacitor metal layer MC, the capacitor metal layer MC, the second metal layer M2, and the third metal layer M3, so that it is convenient to wind and reduce the signal interference caused by the second fan-out line S2 winding on the same layer; at least part of the first fan-out line S1 is located in the second metal layer M2, and the first fan-out line S1 located on the same layer is convenient for connection with the terminal of the driver chip 30, and further convenient for connection with the multi-way distribution unit 20 integrated in the driver chip 30. In this way, when the second fan-out line S2 and the first fan-out line S1 are introduced into the display panel 100, there is no need to add a new film layer in the display panel 100, and the second fan-out line S2 and the first fan-out line S1 can be made using the existing film layer, which is also beneficial to reduce the number of masks in the process and save production costs.

[0068] Fig.11 FIG. 1 is a schematic diagram of a display device structure provided by an embodiment of the present disclosure. Please refer to FIG. Fig.11 Based on the same inventive concept, the present disclosure provides a display device 200 , comprising the display panel 100 as described above.

[0069] It is understandable that the display device 200 provided in the embodiment of the present invention may be a display device 200 with a display function such as a computer, a mobile phone, or a tablet, and the present invention does not specifically limit this. The display device 200 provided in the embodiment of the present invention has the beneficial effects of the display panel 100 provided in the embodiment of the present invention, and the specific description of the display panel 100 in the above embodiments can be referred to, and this embodiment will not be repeated here.

[0070] Understandably, Fig.11 Only a rounded rectangular structure is used as an example to illustrate one shape of the display device 200. In some other embodiments of the present disclosure, the display device 200 may also be circular, elliptical or any other feasible shape, and the present disclosure does not specifically limit this.

[0071] In summary, the present disclosure provides a display panel and a display device, in which the first display area in the display area is located at least on one side of the second display area along the second direction, a first connection line connected to the first data line is introduced into the display panel, the first connection line includes a first connection line segment extending along the second direction and a second connection line segment extending along the first direction, wherein the second connection line segment is located in the second display area, and the first data line and the second connection line segment are connected at both ends of the first connection line segment, respectively, and the display area includes a plurality of pixel columns arranged along the second direction, and the pixel columns include a first pixel column and a second pixel column arranged alternately along the second direction; at least two second connection line segments located between two adjacent second data lines are connected to the first pixel column one-to-one, or are connected to the second pixel column one-to-one. In this way, the voltage signals on the adjacent second connection line segments are the same, and the coupling difference between at least some adjacent signal lines becomes smaller, which is conducive to reducing the display defects caused by the coupling difference. In addition, in the first fan-out area, by connecting two first fan-out lines adjacent to any first fan-out line to different types of pixel columns one by one, any first fan-out line can be subjected to the same coupling influence of adjacent signal lines, thereby reducing the coupling difference of different first fan-out lines and improving the display effect. The arrangement order of the first end and the second end of the second fan-out line in the second direction is different, the second fan-out line is at least partially wound, and the second fan-out line connects the first fan-out line and the data line of the display area. The second fan-out line and the data line are arranged in different layers, which can facilitate winding and reduce signal interference. The existing film layer of the display panel is used to set the second connecting line segment and the first connecting line segment, the first fan-out line and the second fan-out line, without adding a new film layer, which is conducive to simplifying the film layer structure of the display panel and reducing the number of mask plates in the display panel manufacturing process, and thus is also conducive to saving production costs.

[0072] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: comprising a display area, the display area comprising a first display area and a second display area, and along a second direction, the first display area is located at least on one side of the second display area; The display area includes a plurality of data lines extending along a first direction and arranged along the second direction, the data lines include a plurality of first data lines located in the first display area and a plurality of second data lines located in the second display area, and the first direction and the second direction intersect; The display area further includes a plurality of first connection lines, the first connection lines include a first connection line segment and a second connection line segment that are electrically connected, the first connection line segment extends along the second direction and is connected to the first data line; the second connection line segment extends along the first direction; The second connecting line segments are arranged in the same layer as the second data lines, and along the second direction, at least two adjacent second data lines include at least two second connecting line segments; The display area includes a plurality of pixel columns arranged along the second direction, and the pixel columns include a first pixel column and a second pixel column arranged alternately along the second direction; at least two second connecting line segments located between two adjacent second data lines are both connected to the first pixel column, or are both connected to the second pixel column.

2. The display panel according to claim 1, wherein: The first pixel column includes first color sub-pixels and second color sub-pixels arranged along the first direction, and the second pixel column includes third color sub-pixels arranged along the first direction.

3. The display panel according to claim 1, wherein: The first non-display area includes a first non-display area, the first non-display area is located at one side of the display area along the first direction, the first non-display area includes a first fan-out area, and the first fan-out area includes a plurality of first fan-out lines extending along the first direction and arranged along the second direction; Two first fan-out lines adjacent to any first fan-out line are respectively connected to the first pixel column and the second pixel column.

4. The display panel according to claim 3, wherein: The first fan-out line includes a first A fan-out line and a first B fan-out line, the first A fan-out line is connected to the second data line, and the first B fan-out line is connected to the first data line through the second connecting line segment; The first fan-out lines include a first group and a second group alternately arranged along a second direction, the first group includes at least two of the first A fan-out lines, and the second group includes at least two of the first B fan-out lines; The first A fan-out line and the first B fan-out line are arranged on the same layer.

5. The display panel according to claim 3, wherein: The first non-display area further includes a second fan-out area between the display area and the first fan-out area, the second fan-out area includes a second fan-out line, and the first fan-out line is connected to the second data line or the second connection line segment through the second fan-out line; At least part of the second fan-out lines and the data lines are arranged in different layers.

6. The display panel according to claim 5, wherein: The second fan-out line comprises a first end and a second end, the first end of at least part of the second fan-out line is electrically connected to the second connecting line segment, the first end of at least part of the second fan-out line is electrically connected to the second data line, and the second end of the second fan-out line is connected to the first fan-out line; The arrangement order of the first ends of the second fan-out lines is different from the arrangement order of the second ends of the second fan-out lines.

7. The display panel according to claim 3, wherein: It comprises a plurality of multi-way distribution units, each of which comprises at least two switch elements; the switch element comprises a control end, an input end and an output end, the input end is connected to a driver chip, the output end is connected to at least two of the first fan-out lines, and the control end is connected to a switch control line.

8. The display panel according to claim 7, wherein: It includes a driving chip, the first non-display area includes a binding area, the driving chip is electrically connected to the binding area, the multiplexing unit is integrated in the driving chip, or the multiplexing unit is located on a side of the binding area facing the display area.

9. The display panel according to claim 5, wherein: The display panel comprises a substrate and a first metal layer, a capacitor metal layer, a second metal layer and a third metal layer arranged on one side of the substrate, wherein along the thickness direction of the display panel, the capacitor metal layer is located on a side of the first metal layer away from the substrate, the second metal layer is located on a side of the capacitor metal layer away from the substrate, and the third metal layer is located on a side of the second metal layer away from the substrate; The data line and the second connecting line segment are located in the second metal layer, and the first connecting line segment is located in at least one of the first metal layer, the capacitor metal layer, and the third metal layer; or, the data line and the second connecting line segment are located in the third metal layer, and the first connecting line segment is located in at least one of the first metal layer, the capacitor metal layer, and the second metal layer; At least part of the first fan-out line is located in at least one of the first metal layer and the capacitor metal layer; at least part of the first fan-out line is located in the second metal layer; The second fan-out line is located in at least one of the first metal layer, the capacitor metal layer, the second metal layer, and the third metal layer.

10. A display device, characterized in that: Comprising a display panel as described in any one of claims 1 to 9.

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