Carry chain test circuit and test method

Abstract

The invention discloses a carry chain test circuit and a test method, the test circuit comprises N test units with the same structure, and each test unit is composed of a reconfigurable combinational logic, a carry chain, an output selection circuit and an assembly line. According to the test method, a test process covering fixed faults and element functions of each node of the carry chain is preset and configured, and a general modular test circuit design is adopted, so that when a large number of carry chain units need to be tested, only the test circuits need to be logically copied and then combined into a test link.

Description

Technical Field

[0001] The invention relates to a carry chain test circuit and a test method, belonging to the field of integrated circuit chip testing. Background Art

[0002] Carry Chain is a combinational logic resource integrated in the CLB module of the FPGA chip, which is used to build a carry-lookahead logic structure to assist Silce in performing fast arithmetic and logic operations. In Xilinx 7 series FPGAs, each CLB module consists of two Silce units, and each Silce unit integrates a carry chain logic.

[0003] Each carry chain module consists of four binary selectors (MUXCY), four 2-input exclusive OR gates (XOR), IO ports and internal interconnection lines. Testing it needs to cover the fixed-type faults of all ports and the combinational logic functions of MUXCY and XOR.

[0004] The difficulty of carry chain testing lies mainly in:

[0005] (1) Large number of circuits under test

[0006] The number of Silce in FPGA is related to the logic scale of the specific chip, ranging from thousands to hundreds of thousands. Since each Silce integrates a carry chain module, the number of circuits under test is usually large, and the number of IO ports available in FPGA is limited, so it is impossible to build a test circuit for each carry chain under test.

[0007] (2) It is not possible to directly apply a test signal to the IO port of the carry chain

[0008] The S port of the FPGA carry chain is connected to the output port of the lookup table in the Slice through a multiplexer, and there is no direct connection with the FPGA IO in the hardware line;

[0009] (3) BIST method cannot be used directly

[0010] The traditional BIST method uses CLB to build test stimulus generation and test result judgment circuits, which are generally used for self-testing of logic blocks such as DSP and BRAM inside FPGA. However, since the carry chain exists inside the CLB slice, it cannot be avoided, and only LUT, DFF and other resources are used to build BIST circuits to test the carry chain. Summary of the invention

[0011] The technical problem solved by the present invention is: in view of the defects in the current prior art that traditional testing means cannot avoid carry chain and there are many difficulties in the testing process, a carry chain testing circuit and a testing method are proposed.

[0012] The present invention solves the above technical problems by the following technical solutions:

[0013] A carry chain test circuit includes test units, each test unit has the same structure, and the number is N. The test unit includes a reconfigurable combinational logic, a carry chain, an output selection circuit and a pipeline, wherein:

[0014] The reconfigurable combinational logic receives an external address input signal I and outputs a test signal to a carry chain; the carry chain receives the test signal and external input data signals DI and CIN and generates and transmits a test data signal CO and a test data signal O to an output selection circuit; the output selection circuit receives the test data signal and an external input selection signal OS and outputs a selection result output signal to the pipeline; the pipeline generates and outputs a clock pulse signal Q corresponding to the current test unit to the next test unit according to the selection result output signal and the external input clock signal CLK; and each test unit is connected in series.

[0015] After each test unit is connected in series according to the clock pulse signal Q, the last test unit outputs it to the external test instrument and compares it with the expected data. When abnormal flag data appears in the clock pulse signal, the test unit number corresponding to the abnormal flag data is determined by the clock serial number mark of each clock pulse signal.

[0016] The reconfigurable combinational logic includes 4 lookup tables, the address input signal I of the lookup table includes signal I0, signal I1, signal I2, and signal I3. After receiving the corresponding signal, each lookup table outputs the corresponding output test signal to the S port of the carry chain, and the signal I0, signal I1, signal I2, and signal I3 correspond to the S0 port, the S1 port, the S2 port, and the S3 port respectively;

[0017] The carry chain includes 4 two-to-one selectors and 4 two-input XOR gates. The two-to-one selectors receive the test signal and the external input data signals DI and CIN, and transmit the selection result output signals O0, O1, O2, O3 and the data signals CO0, CO1, CO2, CO3 to the data input ports D0, D1, D2, D3 of the pipeline respectively.

[0018] Each lookup table, two-to-one selector, and two-input XOR gate is provided with a corresponding number.

[0019] The address input signal I, external input data signals DI and CIN, external input selection signal OS, and external input clock signal CLK are all input after being defined and programmed by an external test instrument. The expected data is empirical data. Each lookup table is a single-input lookup table. 2 bits of information are stored by pre-setting the data. The data combinations of the address input signals output by each lookup table include 2'b01 and 2'b10, which respectively realize the functions of a single-input inverter and a single-input phase shifter.

[0020] After the address input signal I is output by each lookup table, the corresponding two-to-one selector and two-input XOR gate circuit combination selected by the carry chain signal input is determined according to the preset data of the lookup table and the corresponding output port to achieve full coverage test of the carry chain.

[0021] The specific circuit combination of the full coverage test of the carry chain is set as:

[0022] The signal flag output by each lookup table is 2'b01, external input data signal DI, no input data signal CIN, no input test data signal CO, used to test the signal input port S, input data signal CIN receiving port, and test data signal CO receiving port of the carry chain;

[0023] The signal flags of the outputs of each lookup table are 2'b01, external input data signal DI, no input data signal CIN, external input test data signal CO, which are used to test the signal input port S, input data signal DI receiving port, and test data signal CO receiving port of the carry chain;

[0024] The signal flags output by each lookup table are 2'b10, no input data signal DI, external input data signal CIN, external input test data signal CO, which are used to test the input data signal CIN receiving port of the carry chain;

[0025] The signal flag output by each lookup table is 2'b10, no input data signal DI, external input data signal CIN, no input test data signal CO, which is used to test the input data signal DI receiving port of the carry chain;

[0026] The signal flag output by each lookup table is 2'b10, no external input data signal DI, no input data signal CIN, no input test data signal O, which is used to test the input port of the test data signal O of the carry chain and the two-input XOR gate function;

[0027] The signal flags of the outputs of each lookup table are 2'b10, external input data signal DI, no input data signal CIN, input test data signal O, used to test the input port of the test data signal O of the carry chain and the two-input XOR gate function;

[0028] The signal flags of the outputs of each lookup table are 2'b01, external input data signal DI, input data signal CIN, and input test data signal O, which are used to test the two-input XOR gate function of the carry chain;

[0029] The signal flags output by each lookup table are 2'b01, external input data signal DI, input data signal CIN, and no input test data signal O, which are used to test the two-input XOR gate function of the carry chain.

[0030] In the specific circuit combination of the full coverage test of the carry chain, if the output clock pulse signal Q is valid, then while outputting the clock pulse signal Q, the address input signal I of the current lookup table input is still output to the next test unit.

[0031] A test method for a carry chain test circuit, comprising:

[0032] Test the signal input port S, input data signal CIN receiving port, and test data signal CO receiving port respectively;

[0033] Perform a test on the input port of the test data signal O and the two-input XOR gate function test;

[0034] Perform input data signal DI receiving port test and input data signal CIN receiving port test to complete the carry chain test;

[0035] The test steps for the signal input port S, the input data signal CIN receiving port, and the test data signal CO receiving port are as follows:

[0036] The steps for testing the signal input port S, the input data signal CIN receiving port, and the test data signal CO receiving port are as follows:

[0037] When the first test unit receives the address input signal I, it sets the data flags to 2'b01;

[0038] According to the definition programming of the external test instrument, set the input port logic state of the address input signal I to 1'b0, the input port logic state of the external input data signal DI to 1'b1, the input port logic state of the input data signal CIN to 1'b0, the S port logic state to 1'b1, and continue to perform signal testing;

[0039] Set the input port logic state of the input selection signal OS to 1'b0, so that the test data signal CO on the first input port of the output selection circuit is input from the input port to the input port D of the pipeline;

[0040] An external test instrument generates a valid clock pulse which is input to the input port D and transmitted to the next test unit through the output port Q and stored in the register at the same time;

[0041] The external test instrument continuously generates N valid clock pulses, and collects N data from the output port Q of the last test unit of the test circuit. If the data mark 1'b1 is detected, the test unit number with abnormal function is located according to the clock number corresponding to the appearance of 1'b1; otherwise, the test is completed;

[0042] The testing of different fault conditions is achieved by adjusting the data flags of each port.

[0043] The method for testing the input port of the data signal O and the function test of the two-input XOR gate is:

[0044] According to the definition programming of the external test instrument, set the input port logic state of the address input signal I to 1'b1, the input port logic state of the external input data signal DI to 1'b1, the input port logic state of the input data signal CIN to 1'b1, the S port logic state to 1'b1, and continue to perform signal testing;

[0045] Set the input port logic state of the input selection signal OS to 1'b1, so that the test data signal O on the second input port of the output selection circuit is input from the input port to the input port D of the pipeline;

[0046] An external test instrument generates a valid clock pulse which is input to the input port D and transmitted to the next test unit through the output port Q and stored in the register at the same time;

[0047] The external test instrument continuously generates N valid clock pulses, and collects N data from the output port Q of the last test unit of the test circuit. If the data mark 1'b0 is detected, the test unit number with abnormal function is located according to the clock number corresponding to the appearance of 1'b0; otherwise, the test is completed;

[0048] The testing of different fault conditions is achieved by adjusting the data flags of each port.

[0049] The test method of the input data signal DI receiving port is:

[0050] According to the definition programming of the external test instrument, set the input port logic state of the address input signal I to 1'b0, the input port logic state of the external input data signal DI to 1'b0, the input port logic state of the input data signal CIN to 1'b1, the S port logic state to 1'b0, and continue to perform signal testing;

[0051] Setting the test data signal O on the second input port of the output selection circuit to be input from the input port to the input port D of the pipeline;

[0052] An external test instrument generates a valid clock pulse which is input to the input port D and transmitted to the next test unit through the output port Q and stored in the register at the same time;

[0053] The external test instrument continuously generates N valid clock pulses, and collects N data from the output port Q of the last test unit of the test circuit. If the data mark 1'b1 is detected, the test unit number with abnormal function is located according to the clock number corresponding to the appearance of 1'b1; otherwise, the test is completed;

[0054] The testing of different fault conditions is achieved by adjusting the data flags of each port.

[0055] The advantages of the present invention compared with the prior art are:

[0056] The present invention provides a carry chain test circuit and a test method, which have a simple structure and are easy to logically replicate and expand. Only the logic resources in the CLB Slice are used to build a chain test structure, and the LUT is used to realize the propagation and control of intermediate data. At the same time, the intervention of the pipeline circuit also has the ability to locate faults, and can cover the fixed faults and component functions of each node of the carry chain through preset configuration. The present invention provides a universal modular test circuit design. When a large number of carry chain units need to be tested, the test circuit only needs to be logically replicated and then combined into a test chain. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 A schematic diagram of the structure of the carry chain test circuit provided by the invention;

[0058] Figure 2 A schematic diagram of a reconfigurable combinational logic structure in a carry chain test circuit provided by the invention;

[0059] Figure 3 A schematic diagram of the carry chain structure in the carry chain test circuit provided by the invention;

[0060] Figure 4 A schematic diagram of the structure of the output selection circuit in the carry chain test circuit provided by the invention;

[0061] Figure 5 A schematic diagram of the pipeline structure in the carry chain test circuit provided by the invention. DETAILED DESCRIPTION

[0062] A carry chain test circuit and test method, the test circuit includes N test units with the same structure, each test unit consists of four parts: reconfigurable combinational logic, carry chain, output selection circuit and pipeline. The test method covers the test flow of fixed faults and component functions of each node of the carry chain through preset configuration. Through the universal modular test circuit design, when a large number of carry chain units need to be tested, it is only necessary to logically copy the test circuit and then combine it into a test chain.

[0063] The carry chain test circuit includes a test unit, each test unit has the same structure, and the number is N. The test unit includes a reconfigurable combinational logic 10, a carry chain 20, an output selection circuit 30 and a pipeline 40, wherein:

[0064] The reconfigurable combinational logic 10 receives an external address input signal I, and outputs a test signal to a carry chain 20; the carry chain 20 receives the test signal and external input data signals DI and CIN, and generates and transmits a test data signal CO and a test data signal O to an output selection circuit 30; the output selection circuit 30 receives the test data signal and an external input selection signal OS, and outputs a selection result output signal to a pipeline 40; the pipeline 40 generates and outputs a clock pulse signal Q corresponding to the current test unit to the next test unit according to the selection result output signal and the external input clock signal CLK; and each test unit is connected in series.

[0065] After each test unit is connected in series according to the clock pulse signal Q, the last test unit outputs it to the external test instrument and compares it with the expected data. When abnormal flag data appears in the clock pulse signal, the test unit number corresponding to the abnormal flag data is determined by the clock serial number mark of each clock pulse signal.

[0066] The reconfigurable combinational logic 10 includes 4 lookup tables, and the address input signal I of the lookup table includes a signal I0, a signal I1, a signal I2, and a signal I3. After receiving the corresponding signal, each lookup table outputs a corresponding output test signal to the S port of the carry chain 20, and the signal I0, the signal I1, the signal I2, and the signal I3 correspond to the S0 port, the S1 port, the S2 port, and the S3 port, respectively;

[0067] The carry chain 20 includes four two-to-one selectors and four two-input XOR gates. The two-to-one selectors receive the test signal and the external input data signals DI and CIN, and transmit the selection result output signals O0, O1, O2, O3 and the data signals CO0, CO1, CO2, CO3 to the data input ports D0, D1, D2, D3 of the pipeline 40 respectively.

[0068] Each lookup table, two-to-one selector, and two-input XOR gate is provided with a corresponding number.

[0069] The address input signal I, external input data signals DI and CIN, external input selection signal OS, and external input clock signal CLK are all input after being defined and programmed by an external test instrument. The expected data is empirical data. Each lookup table is a single-input lookup table. 2 bits of information are stored by pre-setting the data. The data combinations of the address input signals output by each lookup table include 2'b01 and 2'b10, which respectively realize the functions of a single-input inverter and a single-input phase shifter.

[0070] After the address input signal I is output by each lookup table, the corresponding two-to-one selector and two-input XOR gate circuit combination selected by the carry chain 20 signal input is determined according to the preset data of the lookup table and the corresponding output port, so as to realize full coverage test of the carry chain 20.

[0071] The specific circuit combination setting for the full coverage test of carry chain 20 is:

[0072] The signal flag output by each lookup table is 2'b01, external input data signal DI, no input data signal CIN, no input test data signal CO, used to test the signal input port S, input data signal CIN receiving port, and test data signal CO receiving port of the carry chain 20;

[0073] The signal flags output by each lookup table are 2'b01, external input data signal DI, no input data signal CIN, external input test data signal CO, which are used to test the signal input port S, input data signal DI receiving port, and test data signal CO receiving port of the carry chain 20;

[0074] The signal flags output by each lookup table are 2'b10, no input data signal DI, external input data signal CIN, external input test data signal CO, which are used to test the input data signal CIN receiving port of the carry chain 20;

[0075] The signal flags output by each lookup table are 2'b10, no input data signal DI, external input data signal CIN, no input test data signal CO, and are used to test the input data signal DI receiving port of the carry chain 20;

[0076] The signal flag output by each lookup table is 2'b10, no external input data signal DI, no input data signal CIN, no input test data signal O, which is used to test the input port of the test data signal O of the carry chain 20 and the two-input XOR gate function;

[0077] The signal flags of the outputs of each lookup table are 2'b10, external input data signal DI, no input data signal CIN, input test data signal O, used to test the input port of the test data signal O of the carry chain 20, and the two-input XOR gate function;

[0078] The signal flags of the outputs of each lookup table are 2'b01, external input data signal DI, input data signal CIN, and input test data signal O, which are used to test the two-input XOR gate function of the carry chain 20;

[0079] The signal flags output by each lookup table are 2′b01, external input data signal DI, input data signal CIN, and no input test data signal O, which are used to test the two-input XOR gate function of the carry chain 20 .

[0080] In the full coverage test specific circuit combination of the carry chain 20, if the output clock pulse signal Q is valid, then while outputting the clock pulse signal Q, the address input signal I of the current lookup table input is still output to the next test unit.

[0081] The test method of the carry chain test circuit includes three parts:

[0082] Test the signal input port S, input data signal CIN receiving port, and test data signal CO receiving port respectively;

[0083] Perform a test on the input port of the test data signal O and the two-input XOR gate function test;

[0084] Perform input data signal DI receiving port test and complete carry chain test;

[0085] The test steps for the signal input port S, the input data signal CIN receiving port, and the test data signal CO receiving port are as follows:

[0086] The steps for testing the signal input port S, the input data signal CIN receiving port, and the test data signal CO receiving port are as follows:

[0087] When the first test unit receives the address input signal I, it sets the data flags to 2'b01;

[0088] According to the definition programming of the external test instrument, set the input port logic state of the address input signal I to 1'b0, the input port logic state of the external input data signal DI to 1'b1, the input port logic state of the input data signal CIN to 1'b0, the S port logic state to 1'b1, and continue to perform signal testing;

[0089] Set the input port logic state of the input selection signal OS to 1'b0, so that the test data signal CO on the first input port of the output selection circuit 30 is input from the input port to the input port D of the pipeline 40;

[0090] An external test instrument generates a valid clock pulse which is input to the input port D and transmitted to the next test unit through the output port Q and stored in the register at the same time;

[0091] The external test instrument continuously generates N valid clock pulses, and collects N data from the output port Q of the last test unit of the test circuit. If the data mark 1'b1 is detected, the test unit number with abnormal function is located according to the clock number corresponding to the appearance of 1'b1; otherwise, the test is completed;

[0092] The testing of different fault conditions is achieved by adjusting the data flags of each port.

[0093] The method for testing the input port of the data signal O and the function test of the two-input XOR gate is:

[0094] According to the definition programming of the external test instrument, set the input port logic state of the address input signal I to 1'b1, the input port logic state of the external input data signal DI to 1'b1, the input port logic state of the input data signal CIN to 1'b1, the S port logic state to 1'b1, and continue to perform signal testing;

[0095] Setting the input port logic state of the input selection signal OS to 1'b1, so that the test data signal O on the second input port of the output selection circuit 30 is input from the input port to the input port D of the pipeline 40;

[0096] An external test instrument generates a valid clock pulse which is input to the input port D and transmitted to the next test unit through the output port Q and stored in the register at the same time;

[0097] The external test instrument continuously generates N valid clock pulses, and collects N data from the output port Q of the last test unit of the test circuit. If the data mark 1'b0 is detected, the test unit number with abnormal function is located according to the clock number corresponding to the appearance of 1'b0; otherwise, the test is completed;

[0098] The testing of different fault conditions is achieved by adjusting the data flags of each port.

[0099] The test method of the input data signal DI receiving port is:

[0100] According to the definition programming of the external test instrument, set the input port logic state of the address input signal I to 1'b0, the input port logic state of the external input data signal DI to 1'b0, the input port logic state of the input data signal CIN to 1'b1, the S port logic state to 1'b0, and continue to perform signal testing;

[0101] The test data signal O on the second input port of the output selection circuit 30 is configured to be input from the input port to the input port D of the pipeline 40;

[0102] An external test instrument generates a valid clock pulse which is input to the input port D and transmitted to the next test unit through the output port Q and stored in the register at the same time;

[0103] The external test instrument continuously generates N valid clock pulses, and collects N data from the output port Q of the last test unit of the test circuit. If the data mark 1'b1 is detected, the test unit number with abnormal function is located according to the clock number corresponding to the appearance of 1'b1; otherwise, the test is completed;

[0104] The testing of different fault conditions is achieved by adjusting the data flags of each port.

[0105] The following is further described in conjunction with the accompanying drawings and preferred embodiments of the specification:

[0106] In the current embodiment, if Figure 1 As shown, it includes N test units with the same structure, each test unit is connected end to end to form a chain; a single test unit is composed of a reconfigurable combinational logic 10, a carry chain 20, an output selection circuit 30 and a pipeline 40;

[0107] The reconfigurable combinational logic 10 includes four lookup tables (100-103), the address input signal of the lookup table is I (I0-I3); the output signal of the lookup table is connected to the S port (S0-S3) of the carry chain 20;

[0108] The carry chain 20 includes four two-to-one selectors (200-203) and four two-input XOR gates (210-213), the input ports of the carry chain are CIN, S (S0-S3) and DI (DI0-DI3), and the output ports of the carry chain are CO (CO0-CO3) and O (O0-O3), which are connected to the first input port and the second input port of the output selection circuit 30 respectively;

[0109] The output selection circuit 30 includes four two-to-one selectors (300-303), the input ports of the selectors are the selection signal OS, the data signals CO (CO0-CO3) and O (O0-O3), and the output ports are connected to the data input ports D (D0-D3) of the pipeline 40;

[0110] The pipeline 40 includes four registers (400-403), the input ports of the registers are clock CLK and data input D (D0-D3), and the output ports are data input and output Q (Q0-Q3). Q (Q0-Q3) is the output signal of the test unit and is connected to the lookup table address input signal I (I0-I3) of the reconfigurable combinational logic 10 of the next test unit.

[0111] The data input DI (DI0-DI3) and carry input CIN of the carry chain 20 of all test modules are connected in parallel; the selection signal OS of the output selection circuit 30 of all test modules are connected in parallel; the register clock CLK of all pipelines 40 are connected in parallel;

[0112] The input signal I (I0-I3) of the reconfigurable combinational logic 10 of the first test module in the test chain, the DI (DI0-DI3), CIN, OS and CLK of all test modules, and the data output Q (Q0-Q3) of the pipeline 40 of the last test module in the test chain are all connected to the external test instrument;

[0113] The test instrument can be programmed to generate digital signals I (I0 to I3), DI (DI0 to DI3), CIN and OS of a certain frequency, collect Q (Q0 to Q3) and compare it with the expected data;

[0114] The lookup table (100-103) in the reconfigurable combinational logic 10 is a single-input lookup table, which can store 2-bit information by pre-setting data. The settable data combinations include 2'b01 and 2'b10, which respectively realize the functions of a single-input inverter and a single-input phase regulator.

[0115] The reconfigurable combinational logic 10 and its lookup table (100-103), the carry chain 20 and its selector (200-203), the XOR gate (210-213), the output selection circuit 30 and its selector (300-303), the pipeline 40 and its register (400-403) in each test unit of the test circuit all have unique numbers that characterize their physical identities;

[0116] The four two-to-one selectors (300-303) in the output selection circuit 30 in each test unit of the test circuit are implemented by four three-input lookup tables;

[0117] By setting the data in the lookup table (100-103) and the signal states of the input ports I, DI, and CIN, a full coverage test of the carry chain 20 is implemented, as follows:

[0118] Signal input port S, input data signal CIN receiving port, test data signal CO receiving port test:

[0119]

[0120] Input data signal DI receiving port test and input data signal CIN receiving port test:

[0121]

[0122] Test the input port of data signal O and the function test of two-input XOR gate:

[0123]

[0124] I Lookup table data (100~103) DI CIN Test O Test fault content 1 2’b01 1 1 1 XOR gate function 1xor 0 0 2’b01 1 1 0 XOR gate function 1xor 1

[0125] When the input port gives the above signal setting combination, and the clock signal CLK gives a valid pulse, the signal output from the Q port is the same as the signal input from the I port:

[0126] The test method of carry chain includes:

[0127] 1. The following tests cover the S port fixed 1 fault, CIN port fixed 1 fault, CO port fixed 1 fault;

[0128] (a) Set the data in the lookup table (100-103) to 2'b01;

[0129] (b) Use an external instrument to set the logic state of port I to 1'b0, port DI to 1'b1, and port CIN to 1'b0. At this time, the signal of the carry chain S port is 1'b1, and the CO output data should be consistent with CIN;

[0130] (c) Setting the logic state of the OS port to 1'b0 through an external instrument, so that the data CO on the first input port of the output selection circuit 30 is transmitted from the output port to the input port D of the pipeline 40;

[0131] (d) An effective clock pulse is given through an external instrument, so that the data on the input port D of the pipeline 40 is stored in the register (300-301) and transmitted from the output port Q to the next test unit;

[0132] (e) Use an external instrument to continuously give N valid clock pulses and collect N data from the output port Q of the last test unit of the test circuit. The data should all be 1'b0. If 1'b1 is detected, the test unit number with abnormal function can be located according to the clock number corresponding to the appearance of 1'b1.

[0133] 2. The following test covers S port fixed 1 fault, CIN port fixed 0 fault, CO port fixed 0 fault

[0134] (f) Through an external instrument, set the logic state of port I to 1'b1, port DI to 1'b1, and port CIN to 1'b0. At this time, the signal of the carry chain S port is 1'b0, and the CO output data should be consistent with DI;

[0135] (g) providing a valid clock pulse through an external instrument, so that the data on the input port D of the pipeline 40 is stored in the register (300-301) and transmitted from the output port Q to the next test unit;

[0136] (h) Use an external instrument to continuously give N valid clock pulses and collect N data from the output port Q of the last test unit of the test circuit. The data should all be 1'b1. If 1'b0 is detected, the test unit number with abnormal function can be located according to the clock number corresponding to the appearance of 1'b0.

[0137] 3. The following tests cover the O port fixed 0 fault and the 1xor 0 combination function of the XOR gate

[0138] (i) Through an external instrument, set the logic state of port I to 1'b1, port DI to 1'b1, and port CIN to 1'b1. At this time, the signal of the carry chain S port is 1'b0, the CO output data should be consistent with DI, and the output of the O port is S xor Cin (O0) or Sxor CO (CO1-CO3);

[0139] (j) Setting the logic state of the OS port to 1'b1 through an external instrument, so that the data O on the second input port of the output selection circuit 30 is transmitted from the output port to the input port D of the pipeline 40;

[0140] (k) providing a valid clock pulse through an external instrument, so that the data on the input port D of the pipeline 40 is stored in the register (300-301) and transmitted from the output port Q to the next test unit;

[0141] (l) Through an external instrument, N valid clock pulses are continuously given, and N data are collected from the output port Q of the last test unit of the test circuit. The data should all be 1'b1; if 1'b0 is detected, the test unit number with abnormal function can be located according to the clock number corresponding to the appearance of 1'b0;

[0142] 4. The following test covers the O port fixed 1 fault and the 1xor 1 combination function of the XOR gate

[0143] (m) Through an external instrument, set the logic state of port I to 1'b0, port DI to 1'b1, and port CIN to 1'b1. At this time, the signal of the carry chain S port is 1'b1, the CO output data should be consistent with CIN, and the output of the O port is S xor Cin (O0) or Sxor CO (CO1-CO3);

[0144] (n) providing a valid clock pulse through an external instrument, so that the data on the input port D of the pipeline 40 is stored in the register (300-301) and transmitted from the output port Q to the next test unit;

[0145] (o) Through an external instrument, N valid clock pulses are continuously given, and N data are collected from the output port Q of the last test unit of the test circuit. The data should all be 1'b0; if 1'b1 is detected, the test unit number with abnormal function can be located according to the clock number corresponding to the appearance of 1'b1;

[0146] 5. The following tests cover the CIN port fixed 0 fault

[0147] (a) Set the data in the lookup table (100-103) to 2'b10;

[0148] (b) Use an external instrument to set the logic state of port I to 1'b1, port DI to 1'b0, and port CIN to 1'b1. At this time, the signal of the carry chain S port is 1'b1, and the CO output data should be consistent with CIN;

[0149] (c) Setting the logic state of the OS port to 1'b0 through an external instrument, so that the data CO on the first input port of the output selection circuit 30 is transmitted from the output port to the input port D of the pipeline 40;

[0150] (d) An effective clock pulse is given through an external instrument, so that the data on the input port D of the pipeline 40 is stored in the register (300-301) and transmitted from the output port Q to the next test unit;

[0151] (e) Use an external instrument to continuously give N valid clock pulses and collect N data from the output port Q of the last test unit of the test circuit. The data should all be 1'b1. If 1'b0 is detected, the test unit number with abnormal function can be located according to the clock number corresponding to the appearance of 1'b0.

[0152] 6. The following test covers DI port fixed 1 fault

[0153] (f) Use an external instrument to set the logic state of port I to 1'b0, port DI to 1'b0, and port CIN to 1'b1. At this time, the signal of the carry chain S port is 1'b0, and the CO output data should be consistent with DI;

[0154] (g) providing a valid clock pulse through an external instrument, so that the data on the input port D of the pipeline 40 is stored in the register (300-301) and transmitted from the output port Q to the next test unit;

[0155] (h) Use an external instrument to continuously give N valid clock pulses and collect N data from the output port Q of the last test unit of the test circuit. The data should all be 1'b0. If 1'b1 is detected, the test unit number with abnormal function can be located according to the clock number corresponding to the appearance of 1'b1.

[0156] 7. The following test covers the 0xor 0 combination function of the XOR gate

[0157] (i) Through an external instrument, set the logic state of port I to 1'b0, port DI to 1'b0, and port CIN to 1'b0. At this time, the signal of the carry chain S port is 1'b0, the CO output data should be consistent with DI, and the output of the O port is S xor Cin (O0) or Sxor CO (CO1-CO3);

[0158] (j) Setting the logic state of the OS port to 1'b1 through an external instrument, so that the data O on the second input port of the output selection circuit 30 is transmitted from the output port to the input port D of the pipeline 40;

[0159] (k) providing a valid clock pulse through an external instrument, so that the data on the input port D of the pipeline 40 is stored in the register (300-301) and transmitted from the output port Q to the next test unit;

[0160] (l) Use an external instrument to continuously give N valid clock pulses and collect N data from the output port Q of the last test unit of the test circuit. The data should all be 1'b0. If 1'b1 is detected, the test unit number with abnormal function can be located according to the clock number corresponding to the appearance of 1'b1.

[0161] 8. The following test covers the 0xor 1 combination function of the XOR gate

[0162] (m) Through an external instrument, set the logic state of port I to 1'b1, port DI to 1'b1, and port CIN to 1'b0. At this time, the signal of the carry chain S port is 1'b1, the CO output data should be consistent with CIN, and the output of the O port is S xor Cin (O0) or Sxor CO (CO1-CO3);

[0163] (n) providing a valid clock pulse through an external instrument, so that the data on the input port D of the pipeline 40 is stored in the register (300-301) and transmitted from the output port Q to the next test unit;

[0164] (o) Through external instruments, N valid clock pulses are continuously given, and N data are collected from the output port Q of the last test unit of the test circuit. The data should all be 1'b1; if 1'b0 is detected, the test unit number with abnormal function can be located according to the clock number corresponding to the appearance of 1'b0.

[0165] The universal modular test circuit design, when a large number of carry chain units need to be tested, only the test circuit needs to be logically replicated and then combined into a test chain, and the fault location is accurate.

[0166] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

[0167] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A carry chain test circuit, characterized in that: The invention comprises a test unit, each test unit has the same structure, the number of the test units is N, N is a positive integer, the test unit comprises a reconfigurable combinational logic (10), a carry chain (20), an output selection circuit (30) and a pipeline (40), wherein: The reconfigurable combinational logic (10) receives an externally input address input signal I and outputs a test signal to a carry chain (20); the carry chain (20) receives the test signal and externally input data signals DI and CIN and then generates and transmits a test data signal CO and a test data signal O to an output selection circuit (30); the output selection circuit (30) receives the test data signal and an externally input selection signal OS and outputs a selection result output signal to a pipeline (40); the pipeline (40) generates and outputs a clock pulse signal Q corresponding to a current test unit to a next test unit according to the selection result output signal and an externally input clock signal CLK; and each test unit is connected in series.

2. A carry chain test circuit according to claim 1, characterized in that: After each test unit is connected in series according to the clock pulse signal Q, the last test unit outputs it to the external test instrument and compares it with the expected data. When abnormal flag data appears in the clock pulse signal, the test unit number corresponding to the abnormal flag data is determined by the clock serial number mark of each clock pulse signal.

3. A carry chain test circuit according to claim 1, characterized in that: The reconfigurable combinational logic (10) includes four lookup tables, the address input signal I of the lookup table includes a signal I0, a signal I1, a signal I2, and a signal I3, and after receiving a corresponding signal, each lookup table outputs a corresponding output test signal to an S port of a carry chain (20), wherein the signal I0, the signal I1, the signal I2, and the signal I3 correspond to the S0 port, the S1 port, the S2 port, and the S3 port, respectively; The carry chain (20) includes four two-to-one selectors and four two-input XOR gates. The two-to-one selectors receive test signals and external input data signals DI and CIN and transmit selection result output signals O0, O1, O2, O3 and data signals CO0, CO1, CO2, CO3 to data input ports D0, D1, D2, D3 of the pipeline (40) respectively. Each lookup table, two-to-one selector, and two-input XOR gate is provided with a corresponding number.

4. A carry chain test circuit according to claim 1, characterized in that: The address input signal I, external input data signals DI and CIN, external input selection signal OS, and external input clock signal CLK are all input after being defined and programmed by an external test instrument. The expected data is empirical data. Each lookup table is a single-input lookup table. 2 bits of information are stored by pre-setting the data. The data combinations of the address input signals output by each lookup table include 2'b01 and 2'b10, which respectively realize the functions of a single-input inverter and a single-input phase shifter.

5. A carry chain test circuit according to claim 1, characterized in that: After the address input signal I is output by each lookup table, the corresponding two-to-one selector and two-input XOR gate circuit combination selected by the carry chain (20) signal input is determined according to the preset data of the lookup table and the corresponding output port to achieve full coverage test of the carry chain (20).

6. A carry chain test circuit according to claim 5, characterized in that: The specific circuit combination of the full coverage test of the carry chain (20) is set as follows: The signal flag output by each lookup table is 2'b01, external input data signal DI, no input data signal CIN, no input test data signal CO, used to test the signal input port S, input data signal CIN receiving port, and test data signal CO receiving port of the carry chain (20); The signal flags of the outputs of each lookup table are 2'b01, external input data signal DI, no input data signal CIN, external input test data signal CO, and are used to test the signal input port S, input data signal DI receiving port, and test data signal CO receiving port of the carry chain (20); The signal flags output by each lookup table are 2'b10, no input data signal DI, external input data signal CIN, external input test data signal CO, used to test the input data signal CIN receiving port of the carry chain (20); The signal flag output by each lookup table is 2'b10, no input data signal DI, external input data signal CIN, no input test data signal CO, and is used to test the input data signal DI receiving port of the carry chain (20); The signal flag output by each lookup table is 2'b10, no external input data signal DI, no input data signal CIN, no input test data signal O, used to test the input port of the test data signal O of the carry chain (20) and the two-input XOR gate function; The signal mark of each lookup table output is 2'b10, external input data signal DI, no input data signal CIN, input test data signal O, used to test the input port of the test data signal O of the carry chain (20) and the two-input XOR gate function; The signal flag outputted by each lookup table is 2'b01, the external input data signal DI, the input data signal CIN, and the input test data signal O, which are used to test the two-input XOR gate function of the carry chain (20); The signal mark of each lookup table output is 2'b01, external input data signal DI, input data signal CIN, no input test data signal O, which is used to test the two-input XOR gate function of the carry chain (20).

7. A carry chain test circuit according to claim 6, characterized in that: In the full coverage test specific circuit combination of the carry chain (20), if the output clock pulse signal Q is valid, the address input signal I of the current lookup table input is still output to the next test unit while the clock pulse signal Q is output.

8. A test method for a carry chain test circuit according to claim 7, characterized in that include: Test the signal input port S, input data signal CIN receiving port, and test data signal CO receiving port respectively; Perform a test on the input port of the test data signal O and the two-input XOR gate function test; Perform input data signal DI receiving port test and input data signal CIN receiving port test to complete the carry chain test; The test steps for the signal input port S, the input data signal CIN receiving port, and the test data signal CO receiving port are as follows: The steps for testing the signal input port S, the input data signal CIN receiving port, and the test data signal CO receiving port are as follows: When the first test unit receives the address input signal I, it sets the data flags to 2'b01; According to the definition programming of the external test instrument, set the input port logic state of the address input signal I to 1'b0, the input port logic state of the external input data signal DI to 1'b1, the input port logic state of the input data signal CIN to 1'b0, the S port logic state to 1'b1, and continue to perform signal testing; Setting the input port logic state of the input selection signal OS to 1'b0, so that the test data signal CO on the first input port of the output selection circuit (30) is input from the input port to the input port D of the pipeline (40); An external test instrument generates a valid clock pulse which is input to the input port D and transmitted to the next test unit through the output port Q and stored in the register at the same time; The external test instrument continuously generates N valid clock pulses, and collects N data from the output port Q of the last test unit of the test circuit. If the data mark 1'b1 is detected, the test unit number with abnormal function is located according to the clock number corresponding to the appearance of 1'b1; otherwise, the test is completed; The testing of different fault conditions is achieved by adjusting the data flags of each port.

9. A carry chain testing method according to claim 8, characterized in that: The method for testing the input port of the data signal O and the function test of the two-input XOR gate is: According to the definition programming of the external test instrument, set the input port logic state of the address input signal I to 1'b1, the input port logic state of the external input data signal DI to 1'b1, the input port logic state of the input data signal CIN to 1'b1, the S port logic state to 1'b1, and continue to perform signal testing; Setting the input port logic state of the input selection signal OS to 1'b1, so that the test data signal O on the second input port of the output selection circuit (30) is input from the input port to the input port D of the pipeline (40); An external test instrument generates a valid clock pulse which is input to the input port D and transmitted to the next test unit through the output port Q and stored in the register at the same time; The external test instrument continuously generates N valid clock pulses, and collects N data from the output port Q of the last test unit of the test circuit. If the data mark 1'b0 is detected, the test unit number with abnormal function is located according to the clock number corresponding to the appearance of 1'b0; otherwise, the test is completed; The testing of different fault conditions is achieved by adjusting the data flags of each port.

10. A carry chain testing method according to claim 8, characterized in that: The test method of the input data signal DI receiving port is: According to the definition programming of the external test instrument, set the input port logic state of the address input signal I to 1'b0, the input port logic state of the external input data signal DI to 1'b0, the input port logic state of the input data signal CIN to 1'b1, the S port logic state to 1'b0, and continue to perform signal testing; Setting the test data signal O on the second input port of the output selection circuit (30) to be input from the input port to the input port D of the pipeline (40); An external test instrument generates a valid clock pulse which is input to the input port D and transmitted to the next test unit through the output port Q and stored in the register at the same time; The external test instrument continuously generates N valid clock pulses, and collects N data from the output port Q of the last test unit of the test circuit. If the data mark 1'b1 is detected, the test unit number with abnormal function is located according to the clock number corresponding to the appearance of 1'b1; otherwise, the test is completed; The testing of different fault conditions is achieved by adjusting the data flags of each port.

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