Chip layout graph correction method and device, equipment, medium and product

Abstract

The invention discloses a chip layout graph correction method, device and equipment, a medium and a product, and is applied to the technical field of photoetching. The method comprises the following steps: determining a corresponding target etching deviation sequence based on a first initial value; determining a corresponding target etching deviation from the target etching deviation sequence based on the second initial value; and finally, correcting the pattern based on the target etching deviation. The size and the distance are two independent attributes of one side, and the requirements of two parameters need to be met simultaneously in the table look-up process. Therefore, according to the embodiment of the invention, an advanced exit mechanism is set, namely, the two parameters are searched respectively, after the first initial value is found, the corresponding target etching deviation sequence is determined firstly, then other etching deviation sequences are not traversed any more, and only the target etching deviation sequence needs to be searched. Through the mode, the searching time of the selective deviation algorithm table is greatly shortened, the speed of the correction process is further increased, and the chip production efficiency is improved.

Description

Technical Field

[0001] The present application belongs to the field of photolithography technology, and in particular, relates to a method, device, equipment, medium and product for correcting chip layout graphics. Background Art

[0002] After the chip is photolithographically processed, chemical etching is required. Chemical etching will produce deviations. In order to compensate for this etching deviation, the chip layout needs to be corrected (often called retargeting in the process). An important step in the correction is to make different etching bias corrections for the edges of different sizes (width) and / or different spacings (space) on the chip layout based on the selective bias algorithm table (i.e., SSA table). The selective bias algorithm table is a two-dimensional table, where rows and columns represent different sizes and spacings, respectively, and the values ​​in the table represent the amount of etching compensation required. In the actual process, by querying the table, the etching bias values ​​of different edges of the chip layout can be quickly obtained. For the entire chip layout, the existing mechanism will traverse all edges of the graphics on the chip layout, and each edge will traverse this two-dimensional table to search for etching bias values ​​that meet the conditions. Assuming that there are N edges on the chip layout, the selective bias algorithm table is a two-dimensional table of n×n, (n<<N), then the complexity of the current algorithm will reach O(Nn 2 ).

[0003] For large tables of selective bias algorithm tables, the entire correction process will become very slow, which will affect the production and manufacturing of chips. Summary of the invention

[0004] The embodiments of the present application provide a method, device, equipment, medium and product for correcting chip layout graphics, which can reduce the processing time of the selective deviation algorithm table and improve the correction speed of the chip layout graphics.

[0005] On the one hand, an embodiment of the present application provides a method for correcting a chip layout pattern, comprising:

[0006] Obtaining a first initial value corresponding to a first parameter of a sideline of the chip layout pattern and a second initial value corresponding to a second parameter; the first parameter and the second parameter are respectively one of a size and a spacing;

[0007] Based on the first initial value, determining a corresponding target etching deviation sequence from a selectivity deviation algorithm table; the selectivity deviation algorithm table is a two-dimensional table with rows and columns corresponding to sizes and spacings, respectively, the value of each cell in the table is the corresponding etching deviation, and different rows and columns correspond to different sizes and spacings, respectively;

[0008] Based on the second initial value, determining a corresponding target etching deviation from the target etching deviation sequence;

[0009] The chip layout pattern is corrected based on the target etching deviation.

[0010] On the other hand, each row and each column in the selective deviation algorithm table corresponds one-to-one to multiple first parameter intervals and multiple second parameter intervals respectively.

[0011] On the other hand, the rows and columns in the selective deviation algorithm table are arranged in order of the size intervals and spacing intervals corresponding to them.

[0012] On the other hand, determining the corresponding target etching deviation sequence from the selective deviation algorithm table based on the first initial value includes:

[0013] Determine, from the plurality of first parameter intervals, a first target parameter interval to which the first initial value belongs;

[0014] The target etching deviation sequence corresponding to the first target parameter interval is determined from the selective deviation algorithm table.

[0015] On the other hand, determining, from the plurality of first parameter intervals, a first target parameter interval to which the first initial value belongs, includes:

[0016] Obtain all values ​​of the first parameter in the selective deviation algorithm table to obtain a first value range;

[0017] Determine a first middle value of the first value interval to divide the first value interval into two first value sub-intervals;

[0018] Comparing the first initial value with the first intermediate value to obtain a first comparison result;

[0019] Based on the first comparison result, determining a first target value sub-interval to which the first initial value belongs from the two first value sub-intervals;

[0020] The first target value sub-interval is used as the new first value interval, and the first intermediate value of the first value interval is returned to divide the first value interval into two first value sub-intervals, until the first target parameter interval to which the first initial value belongs is determined.

[0021] On the other hand, determining the corresponding target etching deviation from the target etching deviation sequence based on the second initial value includes:

[0022] Determine, from a plurality of second parameter intervals, a second target parameter interval to which the second initial value belongs;

[0023] The target etching deviation corresponding to the second target parameter interval is determined from the target etching deviation sequence.

[0024] On the other hand, determining, from the plurality of second parameter intervals, a second target parameter interval to which the second initial value belongs, includes:

[0025] Obtain all values ​​of the second parameter in the selective deviation algorithm table to obtain a second value range;

[0026] Determine a second middle value of the second value interval to divide the second value interval into two second value sub-intervals;

[0027] Comparing the second initial value with the second intermediate value to obtain a second comparison result;

[0028] Based on the second comparison result, determining the second target value sub-interval to which the second initial value belongs from two second value sub-intervals;

[0029] The second target value sub-interval is used as the new second value interval, and the step of determining the second intermediate value of the second value interval to divide the second value interval into two second value sub-intervals is returned until the second target parameter interval to which the second initial value belongs is determined.

[0030] On the other hand, the embodiment of the present application provides a device for correcting a chip layout pattern, comprising:

[0031] An acquisition module, used to acquire a first initial value corresponding to a first parameter of a sideline of the chip layout pattern and a second initial value corresponding to a second parameter; the first parameter and the second parameter are respectively one of a size and a spacing;

[0032] A first determination module is used to determine a corresponding target etching deviation sequence from a selectivity deviation algorithm table based on the first initial value; the selectivity deviation algorithm table is a two-dimensional table with rows and columns corresponding to sizes and spacings, respectively, and the value of each cell in the table is the corresponding etching deviation, and different rows and columns correspond to different sizes and spacings, respectively;

[0033] A second determination module, configured to determine a corresponding target etching deviation from the target etching deviation sequence based on the second initial value;

[0034] A correction module is used to correct the chip layout pattern based on the target etching deviation.

[0035] In another aspect, an embodiment of the present application provides a chip layout pattern correction device, comprising: a processor and a memory storing computer program instructions;

[0036] When the processor executes the computer program instructions, the method for correcting the chip layout graphics as described above is implemented.

[0037] On the other hand, an embodiment of the present application provides a computer-readable storage medium having computer program instructions stored thereon, and the computer program instructions, when executed by a processor, implement the chip layout graphics correction method as described above.

[0038] On the other hand, an embodiment of the present application provides a computer program product. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the chip layout graphics correction method as described above.

[0039] The embodiment of the present application provides a method for correcting a chip layout graphic. After obtaining a first initial value and a second initial value, the corresponding target etching deviation sequence is first determined from a selective deviation algorithm table based on the first initial value; then the corresponding target etching deviation is determined from the target etching deviation sequence based on the second initial value; finally, the chip layout graphic is corrected based on the target etching deviation. Because the size and spacing are two independent attributes of an edge, and the two parameter requirements need to be met simultaneously during the table lookup process. Therefore, this embodiment sets an early exit mechanism, that is, the two parameters are searched separately, and after finding the first initial value, the corresponding target etching deviation sequence is first determined, and then other etching deviation sequences are no longer traversed, and only the target etching deviation sequence needs to be searched. In the above manner, the search time for the selective deviation algorithm table is greatly reduced, thereby achieving the acceleration of the correction process and improving the chip production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] Figure 1 A schematic diagram showing a flow chart of a method for correcting a chip layout pattern provided by an embodiment of the present application;

[0042] Figure 2 A schematic diagram of a method for determining a first target parameter interval based on a binary search algorithm provided by an embodiment of the present application is shown;

[0043] Figure 3A schematic diagram of a method for determining a second target parameter interval based on a binary search algorithm provided by an embodiment of the present application is shown;

[0044] Figure 4 A schematic diagram showing the structure of a chip layout pattern correction device provided in an embodiment of the present application is shown;

[0045] Figure 5 A schematic diagram of the hardware structure of a chip layout graphics correction device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0046] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0047] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "include..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0048] As the technology node of the chip becomes smaller and smaller, the density of transistors per unit area becomes higher and higher, the size and pitch of transistors become smaller and smaller, and microscopic physical and chemical effects become increasingly important. For size, it refers to the distance from one side of the device to the nearest parallel side inside the device, and the distance between the two sides is the size. For pitch, it refers to the distance from one side of the device to the nearest parallel side outside the device, and the distance between the two sides is the pitch. For example, the diffraction effect of light causes errors during chip lithography, and this error is also called the optical proximity effect. To correct this error, optical proximity correction technology is required. On the other hand, after the chip is lithographed, chemical etching is required, and chemical etching will produce deviations, and this deviation has an increasing impact as the chip node becomes smaller. The embodiments of this application are to correct the pattern of the chip layout to make up for this etching deviation.

[0049] In the actual application process, the selective deviation algorithm used is shown in the following table.

[0050] Table 1 Selective Deviation Algorithm Table

[0051]

[0052] The first row of this table represents different size intervals of the pattern, and the first column represents different pitch intervals. The element value at the corresponding position represents the etching deviation value of the corresponding interval. For example, the value 11 in the second row and the third column represents the etching deviation value corresponding to the side of the pattern that satisfies 100nm <= size < 120nm and pitch < 100nm. After obtaining the etching deviation value, let the sides in the corresponding interval move according to the specified etching deviation value, then the etching deviation compensation of this side can be completed. It should be noted that Table 1 is only one example of the embodiments of this application. In actual applications, the parameters corresponding to the rows and columns of the table are not specifically limited, and the size of the parameter intervals corresponding to each row and each column is also not limited, and can be determined according to the actual situation.

[0053] For the entire chip layout, the existing mechanism will traverse all the sides of the patterns on the chip layout, and each side will traverse this two-dimensional table to search for the etching deviation value that meets the conditions. Assuming there are N sides on the chip layout and the selective deviation algorithm table is a two-dimensional table of n×n, (n << N), then the current complexity of this algorithm will reach O(Nn 2 )). However, the value of N in an actual chip is a very large number (in the order of millions, tens of millions, or even hundreds of millions). When the size n of the two-dimensional table becomes very large, the running time of the algorithm will become very long. Assuming N is 1 million and n = 10, the required amount of calculation is 100 million times. And when n = 100, the required amount of calculation reaches an astonishing 10 billion times. This will lead to a sharp increase in the running time.

[0054] In actual chip manufacturing, the two-dimensional table for metal layer correction is usually large in size. Due to the slow search of the two-dimensional table, the complete correction process may even take several days. Only after the graphic correction is completed can the subsequent process of chip manufacturing be entered. Too slow a correction process will seriously affect the scheduling of chip production, the delivery of chips, and even the launch of new products. Therefore, the rapid correction process of large etching tables is an important technical issue in this field.

[0055] In order to solve the problems of the traditional solution, the embodiment of the present application provides a chip layout pattern correction method, device, equipment, medium and product. The chip layout pattern correction method provided by the embodiment of the present application is first introduced below. Figure 1 FIG. 1 is a flow chart showing a method for correcting a chip layout pattern provided by an embodiment of the present application. Figure 1 As shown, the method comprises the following steps:

[0056] S101: Obtain a first initial value corresponding to a first parameter of an edge line of a chip layout graphic and a second initial value corresponding to a second parameter.

[0057] As mentioned above, the rows and columns in the selective deviation algorithm table correspond to the size and spacing of the edge lines of the graphics, respectively. By determining the values ​​of the size and spacing, the corresponding target etching deviation can be found from the table. Therefore, it is necessary to obtain the first initial value corresponding to the first parameter and the second initial value corresponding to the second parameter. The first parameter and the second parameter are respectively one of the size and the spacing, that is, when the first parameter is the size, the second parameter is the spacing; and vice versa.

[0058] S102: Based on the first initial value, determine a corresponding target etching deviation sequence from a selective deviation algorithm table.

[0059] As shown in Table 1 above, the selective deviation algorithm table is a two-dimensional table in which rows and columns correspond to sizes and spacings respectively. The value of each cell in the table is the corresponding etching deviation, and different rows and columns correspond to different sizes and spacings respectively.

[0060] After obtaining the first initial value and the second initial value, the corresponding target etching deviation sequence is first determined from the selective deviation algorithm table based on the first initial value. Taking Table 1 as an example, when the first parameter is the size, the corresponding column can be found based on the first initial value, and all etching deviations in the column constitute the target etching deviation sequence. Conversely, when the first parameter is the spacing, the corresponding row can be found based on the first initial value, and all etching deviations in the row constitute the target etching deviation sequence.

[0061] S103: Based on the second initial value, determine a corresponding target etching deviation from a target etching deviation sequence.

[0062] After finding the target etching deviation sequence, it is necessary to determine the corresponding target etching deviation from the target etching deviation sequence based on the second initial value. When the first parameter is the size and the second parameter is the spacing, the target etching deviation sequence is a column in Table 1, and the etching deviations in the column constitute the target etching deviation sequence, and based on the second initial value, the target etching deviation can be found from the etching deviations in the column. Conversely, when the first parameter is the spacing and the second parameter is the size, the target etching deviation sequence is a row in Table 1, and the etching deviations in the row constitute the target etching deviation sequence, and based on the second initial value, the target etching deviation can be found from the etching deviations in the row.

[0063] The embodiment of the present application adopts an early exit mechanism, that is, first find the corresponding target etching deviation sequence for one of the parameters, and then find the corresponding target etching deviation from the target etching deviation sequence, thereby speeding up the search speed.

[0064] In conjunction with Table 1, the present embodiment is described with a practical example. If the size of one edge is 155nm and the spacing is 145nm, it belongs to the size interval [150, inf) and the spacing interval [140, inf), and the corresponding target etching deviation is 65nm. According to the traditional solution, 36 checks are required to find the corresponding target etching deviation value.

[0065] However, because size and spacing are two independent attributes of an edge, and the search needs to meet both interval requirements at the same time, an early exit mechanism can be set, such as traversing the size conditions first, doing 6 searches to get the corresponding size interval, and then doing the spacing search, doing 6 searches to get the spacing interval, that is, getting the corresponding target etching deviation value. In this process, a total of 12 searches were performed, which is three times less than the original number of searches.

[0066] S104: Correcting the chip layout pattern based on the target etching deviation.

[0067] After the target etching deviation is determined, the etching deviation compensation value required for each edge of the chip layout pattern is determined, and the chip layout pattern is corrected accordingly. The embodiment of the present application makes full use of the characteristics of the selective deviation algorithm table and makes improvements at the algorithm level, so that the target etching deviation is found faster.

[0068] The embodiment of the present application provides a method for correcting a chip layout graphic. After obtaining a first initial value and a second initial value, the corresponding target etching deviation sequence is first determined from a selective deviation algorithm table based on the first initial value; then the corresponding target etching deviation is determined from the target etching deviation sequence based on the second initial value; finally, the chip layout graphic is corrected based on the target etching deviation. Because the size and spacing are two independent attributes of an edge, and the two parameter requirements need to be met simultaneously during the table lookup process. Therefore, this embodiment sets an early exit mechanism, that is, the two parameters are searched separately, and after finding the first initial value, the corresponding target etching deviation sequence is first determined, and then other etching deviation sequences are no longer traversed, and only the target etching deviation sequence needs to be searched. In the above manner, the search time for the selective deviation algorithm table is greatly reduced, thereby achieving the acceleration of the correction process and improving chip production efficiency.

[0069] The above embodiment does not limit the structure of the selective deviation algorithm table. The embodiment of the present application provides a specific implementation method, that is, each row and each column in the selective deviation algorithm table corresponds one-to-one to multiple first parameter intervals and multiple second parameter intervals.

[0070] Each row and column of the selective deviation algorithm table in the embodiment of the present application corresponds to a parameter range. Because the size and spacing within a certain range can use the same target etching deviation, this method can reduce the specifications of the selective deviation algorithm table and thereby increase the speed of table lookup.

[0071] Furthermore, in the selective deviation algorithm table provided in the embodiment of the present application, each row and each column are arranged in order of the size interval and spacing interval corresponding to each other.

[0072] In the selective deviation algorithm table of the embodiment of the present application, each row and column is arranged in order of the size interval and spacing interval corresponding to each other, so that the table data is ordered, thereby making it easier to use various search algorithms to search for the target etching deviation, such as the binary search method.

[0073] In the solution provided in the above embodiment, the selective bias algorithm table is ordered, and for an ordered table, a faster and more stable search algorithm is a binary search method. Therefore, some specific implementation methods are provided below.

[0074] Based on the first initial value, determining the corresponding target etching deviation sequence from the selective deviation algorithm table includes: determining the first target parameter interval to which the first initial value belongs from multiple first parameter intervals; and then determining the target etching deviation sequence corresponding to the first target parameter interval from the selective deviation algorithm table.

[0075] Figure 2A schematic diagram of a method for determining a first target parameter interval based on a binary search algorithm provided by an embodiment of the present application is shown; Figure 2 As shown, determining a first target parameter interval to which a first initial value belongs from a plurality of first parameter intervals specifically includes the following steps:

[0076] S201: Obtain all values ​​of the first parameter in the selective deviation algorithm table to obtain a first value range.

[0077] S202: Determine a first middle value of a first value interval to divide the first value interval into two first value sub-intervals.

[0078] S203: Compare the first initial value and the first intermediate value to obtain a first comparison result.

[0079] S204: Based on the first comparison result, determine a first target value sub-interval to which the first initial value belongs from the two first value sub-intervals.

[0080] S205: Taking the first target value sub-interval as a new first value interval.

[0081] S206: Determine whether the first target parameter interval to which the first initial value belongs is determined; if so, end the above process; if not, return to S202.

[0082] The embodiment of the present application uses a binary search algorithm to quickly obtain the first target parameter interval to which the first initial value belongs through a smaller number of comparisons, thereby finding the corresponding target etching deviation sequence, thereby speeding up the search speed.

[0083] After determining the target etching deviation sequence, it is necessary to determine the corresponding target etching deviation from the target etching deviation sequence based on the second initial value. First, determine the second target parameter interval to which the second initial value belongs from multiple second parameter intervals; then determine the target etching deviation corresponding to the second target parameter interval from the target etching deviation sequence.

[0084] Figure 3 FIG. 1 shows a schematic diagram of a method for determining a second target parameter interval based on a binary search algorithm provided by an embodiment of the present application; Figure 3 As shown, determining the second target parameter interval to which the second initial value belongs from the plurality of second parameter intervals specifically includes the following steps:

[0085] S301: Obtain all values ​​of the second parameter in the selective deviation algorithm table to obtain a second value range.

[0086] S302: Determine a second middle value of a second value interval to divide the second value interval into two second value sub-intervals.

[0087] S303: Compare the second initial value with the second intermediate value to obtain a second comparison result.

[0088] S304: Based on the second comparison result, determine the second target value sub - interval to which the second initial value belongs from the two second value sub - intervals.

[0089] S305: Take the second target value sub - interval as the new second value interval.

[0090] S306: Determine whether the second target parameter interval to which the second initial value belongs has been determined; if yes, end the above process, if no, return to S302.

[0091] Through the binary search algorithm, the embodiments of the present application can quickly obtain the second target parameter interval to which the second initial value belongs through fewer comparisons, thereby finding the corresponding target etching deviation and accelerating the search speed.

[0092] Taking Table 1 as an example, since the selective deviation algorithm table provided by the embodiments of the present application has orderliness, that is, each row and each column in the table are arranged in the order of the corresponding size interval and spacing interval respectively, we can further reduce the number of operations through the binary search algorithm.

[0093] For the edge with a size of 155nm and a spacing of 145nm in the above example; first, search for the size interval. The binary search will take the middle element, the size interval [120, 130). It is found that the size 155nm of this edge is greater than this interval, so the target interval should be on the right side of the current interval. Next, the middle element of the right interval will be extracted, the size interval [140, 150). After further comparison, it is still larger than this interval. Then the final interval is found. Through binary search, the corresponding size interval can be found with only three operations. Similarly, the spacing interval can also be found with three operations.

[0094] With the help of the binary search algorithm and the early exit mechanism, the corresponding target etching deviation value can be found with only 6 operations. The number of operations is reduced by 6 times.

[0095] Assume that there are N edges on the chip layout, and the SSA table is a two - dimensional table of n×n, (n << N). Theoretically, the time complexity of the new algorithm is O(N(2logn)), and the time complexity is greatly reduced compared with the original algorithm.

[0096] To solve the above technical problems, the embodiments of the present application also provide a correction device for the chip layout pattern, Figure 4 which shows the structural schematic diagram of the correction device for the chip layout pattern provided by the embodiments of the present application. As Figure 4 shown, the device includes the following modules:

[0097] An acquisition module 401 is used to acquire a first initial value corresponding to a first parameter and a second initial value corresponding to a second parameter of a sideline of a chip layout pattern; the first parameter and the second parameter are respectively one of a size and a spacing;

[0098] A first determination module 402 is used to determine a corresponding target etching deviation sequence from a selective deviation algorithm table based on the first initial value; the selective deviation algorithm table is a two-dimensional table with rows and columns corresponding to sizes and spacings, respectively, and the value of each cell in the table is the corresponding etching deviation, and different rows and columns correspond to different sizes and spacings, respectively;

[0099] A second determination module 403 is used to determine a corresponding target etching deviation from a target etching deviation sequence based on a second initial value;

[0100] The correction module 404 is used to correct the chip layout pattern based on the target etching deviation.

[0101] In some embodiments, each row and each column in the selective deviation algorithm table corresponds one-to-one to a plurality of first parameter intervals and a plurality of second parameter intervals, respectively.

[0102] In some embodiments, the rows and columns in the selective deviation algorithm table are arranged in order of the size intervals and spacing intervals corresponding to them.

[0103] In some embodiments, the first determining module 402 is specifically configured to:

[0104] Determine, from a plurality of first parameter intervals, a first target parameter interval to which the first initial value belongs;

[0105] A target etching deviation sequence corresponding to the first target parameter interval is determined from the selective deviation algorithm table.

[0106] In some embodiments, the first determination module 402 is specifically used to: obtain all values ​​of the first parameter in the selective deviation algorithm table to obtain a first value range;

[0107] Determine a first middle value of the first value interval to divide the first value interval into two first value sub-intervals;

[0108] Compare the first initial value and the first intermediate value to obtain a first comparison result;

[0109] Based on the first comparison result, determining, from the two first value sub-intervals, a first target value sub-interval to which the first initial value belongs;

[0110] The first target value sub-interval is used as a new first value interval, and the first intermediate value of the first value interval is determined again to divide the first value interval into two first value sub-intervals, until the first target parameter interval to which the first initial value belongs is determined.

[0111] In some embodiments, the second determination module 403 is specifically configured to: determine, from a plurality of second parameter intervals, a second target parameter interval to which the second initial value belongs;

[0112] A target etching deviation corresponding to the second target parameter interval is determined from the target etching deviation sequence.

[0113] In some embodiments, the second determination module 403 is specifically used to: obtain all values ​​of the second parameter in the selective deviation algorithm table to obtain a second value range;

[0114] Determine a second middle value of the second value interval to divide the second value interval into two second value sub-intervals;

[0115] Compare the second initial value with the second intermediate value to obtain a second comparison result;

[0116] Based on the second comparison result, determining, from the two second value sub-intervals, a second target value sub-interval to which the second initial value belongs;

[0117] The second target value sub-interval is used as a new second value interval, and the second intermediate value of the second value interval is determined again to divide the second value interval into two second value sub-intervals, until the second target parameter interval to which the second initial value belongs is determined.

[0118] The device provided in the embodiment of the present application is the same as the method in the above embodiment, so both have the same embodiments and beneficial effects, which will not be repeated here.

[0119] Figure 5 FIG. 1 is a schematic diagram showing the hardware structure of a chip layout pattern correction device provided in an embodiment of the present application. Figure 5 As shown, the chip layout pattern correction device may include a processor 501 and a memory 502 storing computer program instructions.

[0120] Specifically, the processor 501 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0121] The memory 502 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 502 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 502 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 502 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 502 is a non-volatile solid-state memory.

[0122] The memory 502 may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium device, an optical storage medium device, a flash memory device, an electrical, optical or other physical / tangible memory storage device. Therefore, generally, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to one aspect of the present disclosure.

[0123] The processor 501 reads and executes the computer program instructions stored in the memory 502 to implement any one of the chip layout pattern correction methods in the above embodiments.

[0124] In one example, the chip layout pattern correction device may further include a communication interface 503 and a bus 504. The processor 501, the memory 502, and the communication interface 503 are connected via the bus 504 and communicate with each other.

[0125] The communication interface 503 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0126] The bus 504 includes hardware, software, or both, coupling the components of the chip layout pattern correction device to each other. By way of example and not limitation, the bus may include an Accelerate Graphical Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a Hyper Transport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local Bus (VLB) bus, or other suitable buses or a combination of two or more of the above. Where appropriate, the bus 504 may include one or more buses. Although embodiments of the present application describe and illustrate a particular bus, the present application contemplates any suitable bus or interconnect.

[0127] In addition, in combination with the chip layout graphics correction method in the above embodiment, the embodiment of the present application can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by the processor, any chip layout graphics correction method in the above embodiment is implemented.

[0128] An embodiment of the present application also provides a computer program product, including a computer program, which, when executed, implements any one of the chip layout graphics correction methods in the above embodiments.

[0129] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0130] The functional blocks shown in the block diagram above can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an ASIC, appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (Erasable ROM, EROM), floppy disks, compact disc read-only memory (Compact Disc Read-Only Memory, CD-ROM), optical discs, hard disks, optical fiber media, radio frequency (Radio Frequency, RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0131] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0132] The above reference is made to the flowchart and / or block diagram of a method, device, equipment, medium and product for correcting a chip layout graphic according to an embodiment of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the functions / actions specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0133] The above contents are only specific implementation methods of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application.

Claims

1. A method for correcting a chip layout pattern, characterized in that: include: Obtaining a first initial value corresponding to a first parameter of a sideline of the chip layout graphic and a second initial value corresponding to a second parameter; The first parameter and the second parameter are respectively one of size and spacing; Based on the first initial value, determining a corresponding target etching deviation sequence from a selectivity deviation algorithm table; the selectivity deviation algorithm table is a two-dimensional table with rows and columns corresponding to sizes and spacings, respectively, the value of each cell in the table is the corresponding etching deviation, and different rows and columns correspond to different sizes and spacings, respectively; Based on the second initial value, determining a corresponding target etching deviation from the target etching deviation sequence; The chip layout pattern is corrected based on the target etching deviation.

2. The chip layout pattern correction method according to claim 1, characterized in that: Each row and each column in the selective deviation algorithm table corresponds one-to-one to a plurality of first parameter intervals and a plurality of second parameter intervals.

3. The chip layout pattern correction method according to claim 2, characterized in that: The rows and columns in the selective deviation algorithm table are arranged in order of the size intervals and spacing intervals corresponding to them.

4. The chip layout pattern correction method according to claim 3, characterized in that: The determining, based on the first initial value, a corresponding target etching deviation sequence from the selective deviation algorithm table comprises: Determine, from the plurality of first parameter intervals, a first target parameter interval to which the first initial value belongs; The target etching deviation sequence corresponding to the first target parameter interval is determined from the selective deviation algorithm table.

5. The chip layout pattern correction method according to claim 4, characterized in that: The step of determining, from among the plurality of first parameter intervals, a first target parameter interval to which the first initial value belongs comprises: Obtain all values ​​of the first parameter in the selective deviation algorithm table to obtain a first value range; Determine a first middle value of the first value interval to divide the first value interval into two first value sub-intervals; Comparing the first initial value with the first intermediate value to obtain a first comparison result; Based on the first comparison result, determining a first target value sub-interval to which the first initial value belongs from the two first value sub-intervals; The first target value sub-interval is used as the new first value interval, and the first intermediate value of the first value interval is returned to divide the first value interval into two first value sub-intervals, until the first target parameter interval to which the first initial value belongs is determined.

6. The chip layout pattern correction method according to any one of claims 3 to 5, characterized in that: The determining, based on the second initial value, a corresponding target etching deviation from the target etching deviation sequence comprises: Determine, from a plurality of second parameter intervals, a second target parameter interval to which the second initial value belongs; The target etching deviation corresponding to the second target parameter interval is determined from the target etching deviation sequence.

7. The chip layout pattern correction method according to claim 6, characterized in that: The step of determining, from among the plurality of second parameter intervals, a second target parameter interval to which the second initial value belongs comprises: Obtain all values ​​of the second parameter in the selective deviation algorithm table to obtain a second value range; Determine a second middle value of the second value interval to divide the second value interval into two second value sub-intervals; Comparing the second initial value with the second intermediate value to obtain a second comparison result; Based on the second comparison result, determining the second target value sub-interval to which the second initial value belongs from two second value sub-intervals; The second target value sub-interval is used as the new second value interval, and the step of determining the second intermediate value of the second value interval to divide the second value interval into two second value sub-intervals is returned until the second target parameter interval to which the second initial value belongs is determined.

8. A chip layout pattern correction device, characterized in that: include: An acquisition module, used for acquiring a first initial value corresponding to a first parameter of an edge line of the chip layout graphic and a second initial value corresponding to a second parameter; The first parameter and the second parameter are respectively one of size and spacing; A first determination module is used to determine a corresponding target etching deviation sequence from a selectivity deviation algorithm table based on the first initial value; the selectivity deviation algorithm table is a two-dimensional table with rows and columns corresponding to sizes and spacings, respectively, and the value of each cell in the table is the corresponding etching deviation, and different rows and columns correspond to different sizes and spacings, respectively; A second determination module, configured to determine a corresponding target etching deviation from the target etching deviation sequence based on the second initial value; A correction module is used to correct the chip layout pattern based on the target etching deviation.

9. A chip layout pattern correction device, characterized in that: include: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the method for correcting chip layout graphics according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the method for correcting a chip layout graphic according to any one of claims 1 to 7 is implemented.

11. A computer program product, characterized in that When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the chip layout graphics correction method as described in any one of claims 1 to 7.

Images