A link delay test method of a flexible direct-current valve control system and a related device

Abstract

The application discloses a link delay test method of a flexible direct-current valve control system and a related device, and the method comprises the following steps: determining a link delay type according to a starting point and an ending point of a signal passing through a link; determining a type of a test signal used for testing the link delay, a test starting point for sending the test signal, a link through which the test signal passes, and a test tool used for capturing the test signal after the test signal passes through the link according to the link delay type; recording a time point of a level change when the test tool captures the level change of the test signal; and calculating the link delay of the flexible direct-current valve control system according to the time point of the level change. The method realizes comprehensive and accurate testing of the link delay of the flexible direct-current valve control system, thereby solving the problem that there is no special test method for the link delay of the flexible direct-current valve control system in the prior art.

Description

Technical Field

[0001] This invention relates to the field of flexible DC valve control system technology, and in particular to a link delay testing method and related apparatus for flexible DC valve control systems. Background Technology

[0002] Flexible DC transmission is a DC transmission technology that uses voltage source converters based on fully controlled devices and pulse width modulation (PWM) technology for DC transmission. Flexible DC valve-controlled systems are a key technology in flexible DC transmission. However, link delays exist in flexible DC valve-controlled systems, and different link delays can introduce various risks to the system. Currently, there is no specific testing method for link delays in flexible DC valve-controlled systems. Therefore, there is an urgent need to design a link delay testing method for flexible DC valve-controlled systems. Summary of the Invention

[0003] This invention provides a link delay testing method and related apparatus for a flexible DC valve control system, which solves the problem that there is no specific testing method for link delay of flexible DC valve control systems in the prior art.

[0004] In view of this, the first aspect of this application provides a method for testing the link delay of a flexible DC valve-controlled system, the method comprising:

[0005] Determine the link delay type based on the start and end points of the link through which the signal passes;

[0006] The type of test signal used to test the link delay, the test starting point for emitting the test signal, the link through which the test signal passes, and the test tool used to capture the test signal after the test signal passes through the link are determined based on the link delay type.

[0007] When the testing tool detects a change in the level of the test signal, it records the moment of the level change.

[0008] Calculate the link delay of the flexible DC valve control system based on the timing of the level change.

[0009] Optionally, when the link delay type is valve-controlled downlink link delay, the link delay test method includes:

[0010] Set the type of the test signal to a test modulation wave signal, set the test start point to the communication terminal where the polar controller emits the test modulation wave signal, set the test tool to an operation terminal oscilloscope, and set a beam splitter;

[0011] After the test modulation wave signal is emitted at the communication terminal, the test modulation wave signal is divided into a first test signal and a first auxiliary test signal by the optical splitter. The first test signal passes through the test link of the valve-controlled downlink control link, and the first auxiliary test signal passes through the auxiliary test link of the valve-controlled downlink control link and is connected to the operation terminal oscilloscope.

[0012] When the oscilloscope of the operation terminal captures the level changes of the first measured signal and the first accompanying signal respectively, it records the time of the level change and calculates the delay of the downlink control link of the valve control based on the time of the level change.

[0013] The tested link of the valve-controlled downlink control link is a link consisting of the valve-controlled main control board, the bridge arm operation board, the switching board, the pulse distribution board, the power module control board, and the IGBT driver board in sequence.

[0014] The accompanying test link for the valve-controlled downlink is an optical / electrical signal conversion board.

[0015] Optionally, calculating the delay of the downlink control link of the valve control based on the timing of the level change includes:

[0016] ;

[0017] In the formula, The delay of the downlink control link of the valve control is given. The time of the level step change of the first measured signal is denoted as . The time of the level step of the first test signal. The time required for the first test signal to be converted into an electrical signal in the optical / electrical signal conversion board. This refers to the turn-on / turn-off time of the IGBT device.

[0018] Optionally, when the link delay type is the uplink delay of module voltage, the link delay test method includes:

[0019] Set the type of the test signal to a test voltage signal, set the input port of the sampling circuit of the module control board to the test start point setting, set the test tool to an online logic analyzer, and set two parallel output circuits.

[0020] When the test voltage signal is sent out at the input port of the sampling circuit of the module control board, the test voltage signal is divided into a second test signal and a second auxiliary test signal through the parallel two-circuit output circuit. The second test signal passes through the test link of the module voltage uplink, and the second auxiliary test signal passes through the auxiliary test link of the module voltage uplink, and is connected to the online logic analyzer.

[0021] When the online logic analyzer captures the level changes of the second measured signal and the second accompanying signal respectively, it records the time of the level change and calculates the delay of the module voltage uplink based on the time of the level change.

[0022] The measured link of the module voltage transmission link is: a link consisting of the power module control board sampling circuit, the power module control board chip, the pulse distribution board, the switching board, the bridge arm operation board, and the valve control main control board in sequence.

[0023] The accompanying test link for the module voltage transmission link is: through an optical / electrical signal conversion board.

[0024] Optionally, the step of calculating the delay of the module voltage transmission link based on the timing of the level change includes:

[0025] ;

[0026] In the formula, The delay is the time required for the uplink of the module voltage. The step time of the second measured signal is [time of level change]. This refers to the level step time of the second test signal. The time required for the second test signal to be converted into an optical signal in the optical / electrical signal conversion board.

[0027] Optionally, when the link delay type is valve-controlled fast protection link delay, the link delay test method includes:

[0028] Set the type of the test signal to test bridge arm current signal, set the test start point to the bridge arm current output port of the merging unit, set the test tool to the operation terminal oscilloscope, and set the beam splitter.

[0029] After the test arm current signal is emitted at the bridge arm current output port, the test arm current signal is divided into a third test signal and a third auxiliary test signal by the beam splitter. The third test signal passes through the test link of the valve-controlled fast protection link, and the third auxiliary test signal passes through the auxiliary test link of the valve-controlled fast protection link and is connected to the operation terminal oscilloscope.

[0030] When the oscilloscope of the operation terminal captures the level changes of the third measured signal and the third auxiliary measured signal respectively, it records the time of the level change and calculates the delay of the valve-controlled fast protection link based on the time of the level change.

[0031] The tested link of the valve-controlled fast protection link is: a link consisting of a valve-controlled fast protection board, a three-out-of-two output board, a bridge arm operation board, a switching board, a pulse distribution board, a power module control board, and an IGBT driver board in sequence.

[0032] The valve-controlled fast protection link is an optical / electrical signal conversion board.

[0033] Optionally, calculating the delay of the valve-controlled fast protection link based on the timing of the level change includes:

[0034] ;

[0035] In the formula, The delay of the valve-controlled fast protection link, The step time of the third measured signal. The step time of the third test signal. The time required for the third test signal to be converted into an electrical signal in the optical / electrical signal conversion board. This refers to the turn-off time of the IGBT device.

[0036] A second aspect of this application provides a link delay testing system for a flexible DC valve-controlled system, the system comprising:

[0037] The analysis unit is used to determine the link delay type based on the start and end points of the link through which the signal passes;

[0038] The setting unit is used to determine, based on the link delay type, the type of test signal used to test the link delay, the test starting point for emitting the test signal, the link through which the test signal passes, and the test tool used to capture the test signal after the test signal passes through the link.

[0039] The acquisition unit is used to record the moment of the level change when the test tool captures the level change of the test signal;

[0040] The calculation unit is used to calculate the link delay of the flexible DC valve control system based on the timing of the level change.

[0041] A third aspect of the present invention provides a link delay testing device for a flexible DC valve-controlled system, the device comprising a processor and a memory:

[0042] The memory is used to store program code and transmit the program code to the processor;

[0043] The processor is configured to execute, according to the instructions in the program code, the steps of the link delay test method for the flexible DC valve-controlled system as described in the first aspect above.

[0044] A fourth aspect of the present invention provides a computer-readable storage medium for storing program code for executing the link delay test method for the flexible DC valve control system described in the first aspect above.

[0045] As can be seen from the above technical solutions, the present invention has the following advantages:

[0046] This invention provides a link delay testing method for a flexible DC valve-controlled system, comprising: determining the link delay type based on the start and end points of the link through which the signal passes; determining the type of test signal used to test the link delay, the test start point for emitting the test signal, the link through which the test signal passes, and a test tool for capturing the test signal after it passes through the link; recording the moment when the test tool captures a level change in the test signal; and calculating the link delay of the flexible DC valve-controlled system based on the moment of the level change. This method achieves comprehensive and accurate testing of the link delay of a flexible DC valve-controlled system, thereby solving the problem that there is currently no dedicated testing method for the link delay of a flexible DC valve-controlled system in the prior art. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 A flowchart illustrating a link delay testing method for a flexible DC valve control system provided in an embodiment of the present invention;

[0049] Figure 2 A schematic diagram illustrating the principle of valve-controlled downlink delay testing in an embodiment of the present invention;

[0050] Figure 3 A schematic diagram illustrating the principle of uplink delay testing for module voltage provided in an embodiment of the present invention;

[0051] Figure 4 A schematic diagram illustrating the valve-controlled fast protection link delay test principle provided in an embodiment of the present invention;

[0052] Figure 5 This is a schematic diagram of the link delay test system for a flexible DC valve control system provided in an embodiment of the present invention. Detailed Implementation

[0053] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0054] Example 1:

[0055] Please see Figure 1 The link delay testing method for a flexible DC valve-controlled system provided in this embodiment of the invention includes:

[0056] Step 101: Determine the link delay type based on the start and end points of the link through which the signal passes.

[0057] Step 102: Determine the type of test signal used to test link delay, the test starting point for emitting the test signal, the link through which the test signal passes, and the test tool used to capture the test signal after the test signal passes through the link, based on the link delay type.

[0058] Step 103: When the test tool detects a change in the level of the test signal, record the moment of the level change.

[0059] Step 104: Calculate the link delay of the flexible DC valve control system based on the timing of the level change.

[0060] Example 2, please refer to Figure 3 :

[0061] When the link delay type is valve-controlled downlink control link delay, the link delay test method of the flexible DC valve-controlled system of the present invention includes:

[0062] Set the test signal type to test modulated wave signal, set the test start point to the communication terminal where the polar controller sends out the test modulated wave signal, set the test tool to the operation terminal oscilloscope, and set the beam splitter.

[0063] After the test modulation wave signal is sent from the communication terminal, the test modulation wave signal is split into a first test signal and a first auxiliary test signal by the optical splitter. The first test signal passes through the test link of the valve-controlled downlink control link, and the first auxiliary test signal passes through the auxiliary test link of the valve-controlled downlink control link and is connected to the oscilloscope of the operation terminal.

[0064] When the oscilloscope on the operating terminal captures the level changes of the first measured signal and the first auxiliary measured signal, the time of the level change is recorded, and the delay of the downlink control link of the valve control is calculated based on the time of the level change. The expression is as follows:

[0065] ;

[0066] In the formula, For the delay of the downlink control link of valve control, The moment of the first level step of the measured signal. This is the time of the level step of the first test signal. This is the time required for the first test signal to be converted into an electrical signal in the optical / electrical signal conversion board. This refers to the turn-on / turn-off time of the IGBT device.

[0067] Among them, the tested link of the valve-controlled downlink control link is: a link consisting of the valve-controlled main control board, the bridge arm operation board, the switching board, the pulse distribution board, the power module control board, and the IGBT driver board in sequence.

[0068] The accompanying test link for the valve-controlled downlink is: an optical / electrical signal conversion board.

[0069] The principle of Example 2 is explained as follows:

[0070] It should be noted that the downlink control link delay of valve control... This refers to the time elapsed from the moment the modulated wave is sent from the polarity controller to the flexible DC valve control system, through the processing and generation of the IGBT trigger command (Ton / Toff) for each power module by the valve control system, until the IGBT device in the power module actually completes the execution of the trigger command. However, the downlink control link delay directly affects the control response speed and resonance risk of the flexible DC valve control system. A longer delay results in a slower control response, thus increasing the risk of resonance with the system. Therefore, comprehensive and accurate testing of the downlink control link delay of the valve control system is necessary.

[0071] To address this, the present invention provides a test method for the downlink control link delay of valve-controlled systems, specifically:

[0072] like Figure 2As shown, the test starts at the communication terminal where the polar controller emits the test modulation wave signal. During the test, the polar controller first emits the test modulation wave signal (this signal is a periodic optical signal with a period of T1; 50% of the time in one period is a fixed high-level output signal, and the remaining 50% of the time is a fixed zero-level output signal). This signal is first split into two identical optical signals after passing through a beam splitter (one is called the test signal (first test signal), and the other is called the companion signal (first companion signal)). The test signal passes sequentially through the valve control main control board, bridge arm operation board, switching board, pulse distribution board, power module control board, and IGBT driver board, and is finally output from the IGBT driver board as a drive electrical signal and connected to the terminal oscilloscope. The companion signal is directly output as an electrical signal through the optical / electrical signal conversion board and is also connected to the terminal oscilloscope. The terminal oscilloscope is used to find the moments when the test signal instantly steps from a negative level to a positive level (or from a positive level to a negative level) and when the companion signal instantly steps from a zero level to a high level (or from a high level to a zero level). , Then the downlink control link delay of valve control is:

[0073] ;

[0074] In the formula, For the delay of the downlink control link of valve control, The moment of the first level step of the measured signal. This is the time of the level step of the first test signal. The time required for the first test signal to be converted into an electrical signal in the optical / electrical signal conversion board (determined by the board design, usually around 0.5µs). This refers to the turn-on / turn-off time of the IGBT device (typically around 10µs).

[0075] Example 3, please refer to Figure 4 :

[0076] When the link delay type is the uplink delay of module voltage, the link delay test method of the flexible DC valve-controlled system of the present invention includes:

[0077] Set the test signal type to test voltage signal, set the test start point to the sampling circuit input port of the module control board, set the test tool to an online logic analyzer, and set up two parallel output circuits.

[0078] When the test voltage signal is sent out at the input port of the sampling circuit of the module control board, the test voltage signal is divided into the second test signal and the second auxiliary test signal through two parallel output circuits. The second test signal passes through the test link of the module voltage uplink, and the second auxiliary test signal passes through the auxiliary test link of the module voltage uplink, and is connected to the online logic analyzer.

[0079] When the online logic analyzer detects the level changes of the second measured signal and the second accompanying measured signal, it records the time of the level change and calculates the delay of the module voltage transmission link based on the time of the level change. The expression is as follows:

[0080] ;

[0081] In the formula, This is the delay in the uplink of the module voltage transmission link. The step time of the second measured signal. This is the time of the level step of the second test signal. This is the time required for the second test signal to be converted into an optical signal in the optical / electrical signal conversion board.

[0082] Among them, the measured link of the module voltage uplink is: a link consisting of the power module control board sampling circuit, the power module control board chip, the pulse distribution board, the switching board, the bridge arm operation board, and the valve control main control board in sequence.

[0083] The accompanying test link for the module voltage transmission link is: through the optical / electrical signal conversion board.

[0084] The principle of Example 3 is explained as follows:

[0085] It should be noted that the module voltage uplink delay Tup refers to the time from when the sampling circuit of the flexible DC power module control board acquires the power module voltage value Uc, through the processing of the flexible DC power module control board and its transmission to the flexible DC valve control system, until the flexible DC valve control system completes its processing and sends it to the upper-level control and protection system. However, the magnitude of the module voltage uplink delay directly affects the response speed of the overall overvoltage protection action of the flexible DC valve control system. The longer the delay, the slower the overall overvoltage protection action of the flexible DC valve control system, thus increasing the overvoltage risk of the flexible DC valve. Therefore, a comprehensive and accurate test of the module voltage uplink delay is necessary.

[0086] To address this, the present invention provides a test method for the uplink delay of module voltage, specifically:

[0087] like Figure 3As shown, the test starts at the input port of the sampling circuit on the module control board. During the test, a test voltage signal is first emitted by a controllable voltage source (this voltage signal is a periodic electrical signal with a period of T2; 50% of the time in one period is a fixed high-level output signal, and the remaining 50% of the time is a fixed zero-level output signal). This test voltage signal is split into two identical voltage signals through two parallel output circuits (one is called the measured signal (second measured signal), and the other is called the auxiliary signal (second auxiliary signal)). The measured voltage signal then passes through the power supply... The module control board sampling circuit (where the measured voltage signal is converted into an optical signal), power module control board chip, pulse distribution board, switching board, bridge arm operation board, and valve control main control board are all connected. Finally, the signal is output from the valve control main control board in the form of an optical signal and connected to the terminal test board. The accompanying voltage signal is directly output as an optical signal through the optical / electrical signal conversion board and also connected to the terminal test board. The moment when the measured optical signal and the accompanying optical signal instantly step from zero level to high level (or from high level to zero level) is found from the terminal test board using an online logic analyzer. , Then the uplink delay of the module voltage is: ;

[0088] In the formula, This is the delay in the uplink of the module voltage transmission link. The step time of the second measured signal. This is the time of the level step of the second test signal. The time required for the second test signal to be converted into an optical signal in the optical / electrical signal conversion board (determined by the board design, usually around 0.5µs).

[0089] Example 4, please refer to Figure 5 :

[0090] When the link delay type is valve-controlled fast protection link delay, the link delay test method of the flexible DC valve-controlled system of the present invention includes:

[0091] Set the test signal type to test bridge arm current signal, set the test start point to the bridge arm current output port of the merging unit, set the test tool to the operation terminal oscilloscope, and set the beam splitter.

[0092] After the test arm current signal is emitted at the arm current output port, the test arm current signal is split into a third test signal and a third auxiliary test signal by a beam splitter. The third test signal passes through the test link of the valve-controlled fast protection link, and the third auxiliary test signal passes through the auxiliary test link of the valve-controlled fast protection link and is connected to the operation terminal oscilloscope.

[0093] When the oscilloscope on the operating terminal captures the level changes of the third measured signal and the third auxiliary measured signal respectively, the time of the level change is recorded, and the delay of the valve-controlled fast protection link is calculated based on the time of the level change. The expression is:

[0094] ;

[0095] In the formula, For the delay of the valve-controlled fast protection link, The step time of the third measured signal. This refers to the step time of the third test signal. The time required for the third test signal to be converted into an electrical signal in the optical / electrical signal conversion board. This refers to the turn-off time of the IGBT device.

[0096] Among them, the tested link of the valve-controlled fast protection link is: a link consisting of a valve-controlled fast protection board, a three-out-of-two output board, a bridge arm operation board, a switching board, a pulse distribution board, a power module control board, and an IGBT driver board in sequence.

[0097] The valve-controlled fast protection link is: an optical / electrical signal conversion board.

[0098] The principle of Example 4 is explained as follows:

[0099] It should be noted that the valve-controlled fast protection link has a delay. This refers to the time elapsed from the moment the merging unit (MU) sends the bridge arm current Iarm sample value to the fast protection board of the flexible DC valve control system, through the processing and generation of the IGBT turn-off command for each power module by the flexible DC valve control system, until the power module IGBT device actually completes the execution of the turn-off command. The delay of the valve control fast protection link directly affects the response speed of the flexible DC valve control system's fast protection action. The longer the delay, the slower the response speed of the flexible DC valve control system's fast protection action, which in turn increases the risk of overcurrent damage to the flexible DC valve. Therefore, a comprehensive and accurate test of the valve control fast protection link delay is required.

[0100] To address this, the present invention provides a test method for the delay of a flexible DC valve-controlled fast protection link, specifically:

[0101] like Figure 4As shown, the test starts at the bridge arm current output port of the merging unit (MU). During the test, the merging unit (MU) first sends a test bridge arm current signal (this signal is a periodic optical signal with a period of T3, where 50% of the time is a fixed high-level output signal and the remaining 50% is a fixed zero-level output signal). This signal is first split into two identical optical signals after passing through a beam splitter (one is called the test signal (third test signal), and the other is called the companion signal (third companion signal)). The test optical signal passes sequentially through the valve-controlled fast protection board, the three-out-of-two output board, the bridge arm operation board, the switching board, the pulse distribution board, the power module control board, and the IGBT driver board, and is finally output from the IGBT driver board as a drive electrical signal and connected to the terminal oscilloscope. The companion optical signal is directly output as an electrical signal through the optical / electrical signal conversion board and is also connected to the terminal oscilloscope. The terminal oscilloscope is used to find the moment when the test drive electrical signal steps from a positive level to a negative level and the moment when the companion electrical signal steps from a zero level to a high level. , Then the valve-controlled fast protection link delay is:

[0102] ;

[0103] In the formula, For the delay of the valve-controlled fast protection link, The step time of the third measured signal. This refers to the step time of the third test signal. The time required for the third test signal to be converted into an electrical signal in the optical / electrical signal conversion board (determined by the board design, usually around 0.5µs). This refers to the turn-off time of the IGBT device (typically around 10µs).

[0104] In summary, the embodiments of the present invention provide three types of link delay test methods for flexible DC valve control systems, realizing comprehensive and accurate testing of the three types of link delays in flexible DC valve control systems.

[0105] The above describes a link delay test method for a flexible DC valve control system provided in an embodiment of the present invention. The following describes a link delay test system for a flexible DC valve control system provided in an embodiment of the present invention.

[0106] Please see Figure 5 The link delay test system for a flexible DC valve control system provided in this embodiment of the invention includes:

[0107] Analysis unit 201 is used to determine the link delay type based on the start and end points of the link through which the signal passes.

[0108] The setting unit 202 is used to determine the type of test signal used to test the link delay, the test starting point for emitting the test signal, the link through which the test signal passes, and the test tool used to capture the test signal after the test signal passes through the link delay type.

[0109] The acquisition unit 203 is used to record the moment of level change when the test tool captures the level change of the test signal.

[0110] The calculation unit 204 is used to calculate the link delay of the flexible DC valve control system based on the time of level change.

[0111] Furthermore, this embodiment of the invention also provides a link delay testing device for a flexible DC valve-controlled system, the device including a processor and a memory:

[0112] The memory is used to store program code and transmit the program code to the processor;

[0113] The processor is used to execute the steps of the link delay test method for the flexible DC valve-controlled system as described in the above method embodiments, according to the instructions in the program code.

[0114] Furthermore, this embodiment of the invention also provides a computer-readable storage medium for storing program code, which is used to execute the method described in the above-described method embodiments.

[0115] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0116] In the embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0117] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0118] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0119] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0120] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for testing the link delay of a flexible DC valve-controlled system, characterized in that, include: Determine the link delay type based on the start and end points of the link through which the signal passes; The type of test signal used to test the link delay, the test starting point for emitting the test signal, the link through which the test signal passes, and the test tool used to capture the test signal after the test signal passes through the link are determined based on the link delay type. When the testing tool detects a change in the level of the test signal, it records the moment of the level change. Calculate the link delay of the flexible DC valve control system based on the timing of the level change; When the link delay type is valve-controlled downlink delay, the link delay test method includes: Set the type of the test signal to a test modulation wave signal, set the test start point to the communication terminal where the polar controller emits the test modulation wave signal, set the test tool to an operation terminal oscilloscope, and set a beam splitter; After the test modulation wave signal is emitted at the communication terminal, the test modulation wave signal is divided into a first test signal and a first auxiliary test signal by the optical splitter. The first test signal passes through the test link of the valve-controlled downlink control link, and the first auxiliary test signal passes through the auxiliary test link of the valve-controlled downlink control link and is connected to the operation terminal oscilloscope. When the oscilloscope of the operation terminal captures the level changes of the first measured signal and the first accompanying signal respectively, it records the time of the level change and calculates the delay of the downlink control link of the valve control based on the time of the level change. The tested link of the valve-controlled downlink control link is a link consisting of the valve-controlled main control board, the bridge arm operation board, the switching board, the pulse distribution board, the power module control board, and the IGBT driver board in sequence. The accompanying test link for the valve-controlled downlink control link is: an optical / electrical signal conversion board; The calculation of the downlink delay of the valve-controlled system based on the timing of the level change includes: ； In the formula, The delay of the downlink control link of the valve control is given. The time of the level step change of the first measured signal is denoted as . The time of the level step of the first test signal. The time required for the first test signal to be converted into an electrical signal in the optical / electrical signal conversion board. For IGBT devices, turn-on / turn-off time; The downlink control link delay of the valve control is the time from when the polarity controller sends the modulation wave to the flexible DC valve control system, through the processing of the valve control system to generate and send the IGBT trigger command Ton / Toff for each power module, until the power module IGBT device actually completes the execution of the trigger command.

2. The link delay test method for the flexible DC valve control system according to claim 1, characterized in that, When the link delay type is the module voltage transmission link delay, the link delay test method includes: Set the type of the test signal to a test voltage signal, set the input port of the sampling circuit of the module control board to the test start point setting, set the test tool to an online logic analyzer, and set two parallel output circuits. When the test voltage signal is sent out at the input port of the sampling circuit of the module control board, the test voltage signal is divided into a second test signal and a second auxiliary test signal through the parallel two-circuit output circuit. The second test signal passes through the test link of the module voltage uplink, and the second auxiliary test signal passes through the auxiliary test link of the module voltage uplink, and is connected to the online logic analyzer. When the online logic analyzer captures the level changes of the second measured signal and the second accompanying signal respectively, it records the time of the level change and calculates the delay of the module voltage uplink based on the time of the level change. The measured link of the module voltage transmission link is: a link consisting of the power module control board sampling circuit, the power module control board chip, the pulse distribution board, the switching board, the bridge arm operation board, and the valve control main control board in sequence. The accompanying test link for the module voltage transmission link is: through an optical / electrical signal conversion board.

3. The link delay test method for the flexible DC valve control system according to claim 2, characterized in that, The calculation of the uplink delay of the module voltage based on the timing of the level change includes: ； In the formula, The delay is the time required for the uplink of the module voltage. The step time of the second measured signal is [time of level change]. This refers to the level step time of the second test signal. The time required for the second test signal to be converted into an optical signal in the optical / electrical signal conversion board.

4. The link delay test method for the flexible DC valve control system according to claim 1, characterized in that, When the link delay type is valve-controlled fast protection link delay, the link delay test method includes: Set the type of the test signal to test bridge arm current signal, set the test start point to the bridge arm current output port of the merging unit, set the test tool to the operation terminal oscilloscope, and set the beam splitter. After the test arm current signal is emitted at the bridge arm current output port, the test arm current signal is divided into a third test signal and a third auxiliary test signal by the beam splitter. The third test signal passes through the test link of the valve-controlled fast protection link, and the third auxiliary test signal passes through the auxiliary test link of the valve-controlled fast protection link and is connected to the operation terminal oscilloscope. When the oscilloscope of the operation terminal captures the level changes of the third measured signal and the third auxiliary measured signal respectively, it records the time of the level change and calculates the delay of the valve-controlled fast protection link based on the time of the level change. The tested link of the valve-controlled fast protection link is: a link consisting of a valve-controlled fast protection board, a three-out-of-two output board, a bridge arm operation board, a switching board, a pulse distribution board, a power module control board, and an IGBT driver board in sequence. The valve-controlled fast protection link is: an optical / electrical signal conversion board; The delay of the fast protection link of the valve control is: the time from when the merging unit device sends the bridge arm current sampling value to the fast protection board of the flexible DC valve control system, through the processing of the flexible DC valve control system to generate and issue the IGBT turn-off command of each power module, until the power module IGBT device actually completes the turn-off command.

5. The link delay test method for the flexible DC valve control system according to claim 4, characterized in that, The calculation of the delay of the valve-controlled fast protection link based on the timing of the level change includes: ； In the formula, The delay of the valve-controlled fast protection link, The step time of the third measured signal. The step time of the third test signal. The time required for the third test signal to be converted into an electrical signal in the optical / electrical signal conversion board. This refers to the turn-off time of the IGBT device.

6. A link delay testing system for a flexible DC valve-controlled system, characterized in that, include: The analysis unit is used to determine the link delay type based on the start and end points of the link through which the signal passes; The setting unit is used to determine, based on the link delay type, the type of test signal used to test the link delay, the test starting point for emitting the test signal, the link through which the test signal passes, and the test tool used to capture the test signal after the test signal passes through the link. The acquisition unit is used to record the moment of the level change when the test tool captures the level change of the test signal; The calculation unit is used to calculate the link delay of the flexible DC valve control system based on the timing of the level change; When the link delay type is valve-controlled downlink delay, the link delay test method includes: Set the type of the test signal to a test modulation wave signal, set the test start point to the communication terminal where the polar controller emits the test modulation wave signal, set the test tool to an operation terminal oscilloscope, and set a beam splitter; After the test modulation wave signal is emitted at the communication terminal, the test modulation wave signal is divided into a first test signal and a first auxiliary test signal by the optical splitter. The first test signal passes through the test link of the valve-controlled downlink control link, and the first auxiliary test signal passes through the auxiliary test link of the valve-controlled downlink control link and is connected to the operation terminal oscilloscope. When the oscilloscope of the operation terminal captures the level changes of the first measured signal and the first accompanying signal respectively, it records the time of the level change and calculates the delay of the downlink control link of the valve control based on the time of the level change. The tested link of the valve-controlled downlink control link is a link consisting of the valve-controlled main control board, the bridge arm operation board, the switching board, the pulse distribution board, the power module control board, and the IGBT driver board in sequence. The accompanying test link for the valve-controlled downlink control link is: an optical / electrical signal conversion board; The calculation of the downlink delay of the valve-controlled system based on the timing of the level change includes: ； In the formula, The delay of the downlink control link of the valve control is given. The time of the level step change of the first measured signal is denoted as . The time of the level step of the first test signal. The time required for the first test signal to be converted into an electrical signal in the optical / electrical signal conversion board. This refers to the turn-on / turn-off time of the IGBT device.

7. A link delay testing device for a flexible DC valve-controlled system, characterized in that, The device includes a processor and a memory: The memory is used to store program code and transmit the program code to the processor; The processor is used to execute the link delay test method of the flexible DC valve control system according to any one of the instructions in the program code.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store program code for executing the link delay test method of the flexible DC valve control system according to any one of claims 1-5.

Images