Prefix parallel adder based on dual-gate structure reconfigurable transistor and construction method of prefix parallel adder

Abstract

The invention provides a prefix parallel adder based on a reconfigurable transistor with a double-gate structure and a construction method of the prefix parallel adder, and three 8-bit prefix parallel adders suitable for different application scenes are constructed based on the prefix parallel adder. Through cooperative regulation and control of the top gate and the back gate of the reconfigurable transistor with the double-gate structure, the reconfigurable logic operation function of'and 'and'or' of a single transistor is realized. Under the condition that the number of devices is reduced, the integrated circuit which is universal, low in power consumption, small in size and light in weight is constructed. The prefix parallel adder established by the invention has remarkable data processing parallelism and low delay, reduces the loss of data transmission, and has the advantages of high speed, low power consumption, small size and favorable integration in a digital system. The delay problem in a digital circuit is solved, a complex digital circuit is constructed by adopting fewer elements, the area of an integrated circuit is reduced while the power consumption is reduced, and the circuit has potential application to logical operation and data processing in a microcontroller.

Description

Technical Field

[0001] The present disclosure belongs to the fields of future computing, high performance computing and reconfigurable devices, and more specifically to a prefix parallel adder based on a dual-gate structure reconfigurable transistor and a construction method thereof. Background Art

[0002] Traditional CMOS circuits are built based on transistor Boolean logic gates, such as AND gates and OR gates, to perform various logic functions. The circuits of traditional serial carry adders and carry-lookahead adders are usually built with multiple CMOS transistors. However, with the increase in integration and the reduction in process size, the number of CMOS transistors in traditional adder circuits will increase, which cannot meet the current requirements for high speed, low power consumption, small size and high integration of digital circuits.

[0003] Specifically, in the process of realizing the above-mentioned inventive concept, the inventors found that: due to the increase in the number of CMOS transistors in the related technology, problems such as increased circuit complexity, increased power consumption and expanded layout area are caused; at the same time, the traditional serial carry adder circuit and carry lookahead adder circuit constructed by multiple CMOS transistors have technical problems such as low data processing parallelism, high latency and slow calculation speed. Summary of the invention

[0004] In view of the above problems, the present disclosure provides a prefix parallel adder based on a dual-gate structure reconfigurable transistor and a construction method thereof.

[0005] According to the first aspect of the present disclosure, a prefix parallel adder based on a dual-gate structure reconfigurable transistor is provided, comprising: a prefix parallel adder constructed with a dual-gate structure reconfigurable transistor based on a low-dimensional channel material having an N-layer logic depth, the prefix parallel adder comprising a preprocessing gate-level circuit, a prefix unit circuit and a summing output circuit, wherein each logic gate of the preprocessing gate-level circuit, the prefix unit circuit and the summing output circuit is obtained by modulating the dual-gate structure reconfigurable transistor corresponding to each logic gate; a preprocessing gate-level circuit, the preprocessing gate-level circuit is connected to the prefix unit circuit, the preprocessing gate-level circuit comprises an AND gate and an OR gate, and is used to convert input information of the prefix parallel adder into a carry propagation factor and a carry generation factor; a prefix unit circuit, the prefix unit circuit is connected to the summing output circuit The prefix unit circuit includes a calculation circuit for a carry generation factor and a calculation circuit for a carry propagation factor. The calculation circuit for the carry generation factor includes an AND gate and an OR gate. The calculation circuit for the carry propagation factor includes an AND gate, which is used to merge and propagate the carry propagation factor and the carry generation factor generated by the preprocessing gate-level circuit in the first-level logic level to obtain a new carry propagation factor and a new carry generation factor. The new carry propagation factor and the new carry generation factor generate new nodes in the next-level logic depth until all the carry information is transmitted; a summation output circuit, the summation output circuit includes two NOT gates, two AND gates and an OR gate, which is used to calculate the final sum of the prefix parallel adder according to the new carry propagation factor, the new carry generation factor and the carry information obtained in the Nth level logic depth.

[0006] According to an embodiment of the present disclosure, the calculation circuit of the carry generation factor includes an AND gate and an OR gate, which are characterized as a first AND gate and a first OR gate, and the calculation circuit of the carry transfer factor includes an AND gate, which is characterized as a second AND gate; the output end of the first AND gate is connected to the second input end of the first OR gate, and the first input end of the first AND gate receives G [k-1：j] The carry generation factor, the second input terminal of the first AND gate receives P [i：k] The carry-transfer factor, the first input of the first OR gate receives G [i：k] The carry generation factor, the output of the first OR gate outputs G [i：j] The first input terminal of the second AND gate receives P [i：k] The carry transfer factor, the second input terminal of the second AND gate receives P [k-1：j] The carry transfer factor, the output of the second AND gate outputs P [i：j] Carry-propagation factor.

[0007] According to an embodiment of the present disclosure, a dual-gate structure reconfigurable transistor realizes mutual conversion from AND gate to OR gate of a dual-gate structure reconfigurable transistor in a prefix parallel adder by changing the polarity of the back-gate electric field of the dual-gate structure reconfigurable transistor and combining the coordinated modulation of the top gate of the dual-gate structure reconfigurable transistor by an external electric field, wherein the dual-gate structure reconfigurable transistor has a working environment compatible with CMOS transistors.

[0008] According to an embodiment of the present disclosure, the prefix parallel adder includes: an 8-bit prefix parallel adder with an architecture of 6-level logic depth, the 8-bit prefix parallel adder with an architecture of 6-level logic depth includes 6-level logic gates and 8-bit inputs, the 8-bit prefix parallel adder with an architecture of 6-level logic depth is used to perform parallel calculations on the fourth-bit input and the fifth-bit input, and to expand carry chain branches on the third-bit input and the fifth-bit input, so that while using the 8-bit prefix parallel adder with an architecture of 6-level logic depth for parallel calculations, only 67 dual-gate structure reconfigurable transistors are used to reduce power consumption.

[0009] According to an embodiment of the present disclosure, the prefix parallel adder also includes: an 8-bit prefix parallel adder with an architecture of 5-level logic depth, the 8-bit prefix parallel adder with an architecture of 5-level logic depth includes 5 levels of logic gates and 8-bit inputs, the 8-bit prefix parallel adder with an architecture of 5-level logic depth is used to perform parallel calculations on the second-bit input and the fifth-bit input, and to expand carry chain branches on the first-bit input and the fourth-bit input, so that while using the 8-bit prefix parallel adder with an architecture of 5-level logic depth for parallel calculations, only 67 dual-gate structure reconfigurable transistors are used, so as to improve the calculation speed and parallelism of the prefix parallel adder using 5-level logic depth.

[0010] According to an embodiment of the present disclosure, the prefix parallel adder also includes: an 8-bit prefix parallel adder with an architecture of 4-level logic depth, the 8-bit prefix parallel adder with an architecture of 4-level logic depth includes 4-level logic gates and 8-bit inputs, the 8-bit prefix parallel adder with an architecture of 4-level logic depth is used to parallel calculate the zeroth input, the second input, the fourth input and the sixth input, and expand the carry chain branch at the first input, the third input and the fifth input, so that while using the 8-bit prefix parallel adder with an architecture of 4-level logic depth for parallel calculation, only 70 dual-gate structure reconfigurable transistors are used, so as to improve the calculation speed and parallelism of the prefix parallel adder using 4-level logic depth.

[0011] According to the embodiments of the present disclosure, the architecture of the prefix parallel adder is further expanded, and an inverter is constructed based on a dual-gate reconfigurable device. The dual-gate structure reconfigurable transistor includes a substrate, a back gate electrode, a ferroelectric gate dielectric, a buffer layer, a channel, a source-drain electrode, a top gate dielectric and a top gate electrode designed in sequence along the vertical direction, wherein the channel is prepared from a low-dimensional material, which is a single-layer or multi-layer two-dimensional atomic crystal material, and the gate dielectric is prepared from a ferroelectric or hafnium-based material.

[0012] According to an embodiment of the present disclosure, the prefix parallel adder also includes an inverter, which includes a process construction using a dual-gate structure reconfigurable transistor. The inverter is used to be inserted between logic levels of the prefix parallel adder, thereby reversing the polarity of the signal, speeding up signal transmission over long distances or when signal quality deteriorates, optimizing the amplitude and shape of the signal, balancing the transmission delay of the signal, optimizing the overall system performance, and improving the signal transmission capability of the circuit in the prefix parallel adder.

[0013] The second aspect of the present disclosure provides a method for constructing a prefix parallel adder based on a dual-gate structure reconfigurable transistor, comprising: based on the dual-gate structure reconfigurable transistor, determining the input bits for parallel calculation and the input bits for expanding the carry chain branches in the prefix parallel adders of different logical depths, and building circuits corresponding to the prefix parallel adders of different logical depths; generating a node graph corresponding to the prefix parallel adders of different logical depths according to the circuits corresponding to the prefix parallel adders of different logical depths; based on the node graph, switching the logic state of each dual-gate structure reconfigurable transistor in the circuit of the constructed prefix parallel adder by changing the polarity of the back-gate electric field of the dual-gate structure reconfigurable transistor and combining the coordinated modulation of the top gate of the dual-gate structure reconfigurable transistor with an external electric field, thereby obtaining a prefix parallel adder.

[0014] According to an embodiment of the present disclosure, the logic state of each dual-gate structure reconfigurable transistor in the circuit of the constructed prefix parallel adder is switched, including: applying a regulated back gate voltage and a regulated top gate voltage to the back gate and the top gate of the dual-gate structure reconfigurable transistor, respectively; obtaining a truth table of AND logic and a truth table of OR logic according to the transfer curves of the regulated back gate voltage and the regulated top gate voltage, wherein the transfer curve includes a plurality of operating points representing different logic states; determining the back gate and the top gate voltages for changing the logic function of the dual-gate structure reconfigurable transistor from the transfer curve according to the truth table of the logic and the truth table of the OR logic, and changing the back gate and the top gate voltages of the dual-gate structure reconfigurable transistor to switch the operating points, thereby realizing mutual conversion between the AND gate and the OR gate of the dual-gate structure reconfigurable transistor.

[0015] A third aspect of the present invention provides an electronic device, comprising: one or more processors; and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors execute the above method.

[0016] The fourth aspect of the present invention also provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, causes the processor to execute the above method.

[0017] The fifth aspect of the present invention also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0018] According to the prefix parallel adder based on dual-gate structure reconfigurable transistors and the construction method thereof disclosed in the present invention, a prefix parallel adder with N layers of logic levels is constructed by dual-gate structure reconfigurable transistors based on low-dimensional channel materials. The prefix parallel adder based on the dual-gate structure reconfigurable transistors includes a preprocessing gate-level circuit, a prefix unit circuit and a summing output circuit. By modulating each dual-gate structure reconfigurable transistor of the preprocessing gate-level circuit, the prefix unit circuit and the summing output circuit, the dual-gate structure reconfigurable transistor can switch between the "AND gate" and the "OR gate" to obtain the required logic state in the prefix parallel adder, thereby realizing the reconfigurability of the circuit of the prefix parallel adder based on the dual-gate structure reconfigurable transistor, and while reducing the number of devices, a highly versatile, low-power, miniaturized and lightweight integrated circuit can be constructed.

[0019] According to an embodiment of the present disclosure, a preprocessing gate-level circuit in a prefix parallel adder based on a dual-gate structure reconfigurable transistor is connected to a prefix unit circuit, the preprocessing gate-level circuit includes an AND gate and an OR gate, the prefix unit circuit is connected to a summing output circuit, the prefix unit circuit includes a calculation circuit for a carry generation factor and a calculation circuit for a carry transfer factor, the calculation circuit for the carry generation factor includes an AND gate and an OR gate, the calculation circuit for the carry transfer factor includes an AND gate, and the summing output circuit includes two NOT gates, two AND gates and an OR gate. By inputting information a to each bit of the prefix parallel adder, [i] and b [i] Preprocess it and convert it into a carry transfer factor p i and the carry generation factor g i, and then through the calculation circuit of the carry generation factor and the calculation circuit of the carry propagation factor, the carry propagation factor and the carry generation factor generated by the preprocessing gate-level circuit in the first-level logic level are prefixed and calculated in the second-level logic level to obtain the new carry propagation factor and the new carry generation factor of each bit input. Through the carry chain branch, the new carry propagation factor and the new carry generation factor generate new nodes in the next-level logic level, so as to effectively transfer the carry information of the previous bit to the current bit, and then provide the key and accurate input for the next-level logic, while ensuring that the prefix parallel adder based on the dual-gate structure reconfigurable transistor can efficiently merge the carry information of each bit in the calculation process, while reducing the need for low-bit carry propagation, thereby improving the calculation efficiency. Finally, through the summation output circuit, the new carry propagation factor, the new carry generation factor and the carry information of each bit are summed up to obtain the final sum. While realizing the summation calculation by using the prefix parallel adder based on the dual-gate structure reconfigurable transistor, since the prefix parallel adder can process the addition of multiple bits at the same time, the data processing parallelism of the prefix parallel adder based on the dual-gate structure reconfigurable transistor is high and the delay is low, which reduces the loss of data transmission. It has the advantages of fast speed, low power consumption, small size and easy integration in the digital system, further improves the delay problem in the digital circuit, uses fewer components to build a complex digital circuit, reduces the area of ​​the integrated circuit while reducing power consumption, and has potential application in logic operations and data processing in microcontrollers. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0021] Figure 1a A schematic diagram of a calculation circuit for a carry generation factor of a prefix parallel adder based on a dual-gate structure reconfigurable transistor according to an embodiment of the present disclosure is shown;

[0022] Figure 1b A schematic diagram of a calculation circuit for a carry propagation factor of a prefix parallel adder based on a dual-gate structure reconfigurable transistor according to an embodiment of the present disclosure is shown;

[0023] Figure 2 A schematic diagram of a preprocessing gate-level circuit of a prefix parallel adder based on a dual-gate structure reconfigurable transistor according to an embodiment of the present disclosure is shown;

[0024] Figure 3 A schematic diagram of a summing output circuit of a prefix parallel adder based on a dual-gate structure reconfigurable transistor according to an embodiment of the present disclosure is shown;

[0025] Figure 4 A schematic diagram of the structure of a dual-gate structure reconfigurable transistor according to an embodiment of the present disclosure is shown;

[0026] Figure 5a A schematic diagram schematically shows a transfer curve obtained by setting the top gate voltage and the back gate voltage according to an embodiment of the present disclosure;

[0027] Figure 5b A schematic diagram schematically shows a working point selected by a truth table obtained according to a transfer curve according to an embodiment of the present disclosure;

[0028] Figure 6 A schematic diagram of a prefix parallel adder node based on a dual-gate structure reconfigurable transistor with a logic depth of 6 according to an embodiment of the present disclosure is schematically shown;

[0029] Figure 7 A schematic diagram of a prefix parallel adder node based on a dual-gate structure reconfigurable transistor with a logic depth of 5 according to an embodiment of the present disclosure is schematically shown;

[0030] Figure 8 A schematic diagram of a prefix parallel adder node based on a dual-gate structure reconfigurable transistor with a logic depth of 4 according to an embodiment of the present disclosure is schematically shown;

[0031] Fig. 9 A schematic diagram schematically shows the physical structure of a prefix parallel adder based on a dual-gate structure reconfigurable transistor with a logic depth of 4 according to an embodiment of the present disclosure;

[0032] Fig.10 A schematic diagram schematically shows a topological structure of a prefix parallel adder based on a dual-gate structure reconfigurable transistor with a logic depth of 4 according to an embodiment of the present disclosure;

[0033] Fig.11 The flowchart of the method for constructing a prefix parallel adder based on a dual-gate structure reconfigurable transistor according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0035] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0036] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0037] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0038] In the technical solution of the present invention, the user information (including but not limited to user personal information, user image information, user device information, such as location information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved are all information and data authorized by the user or fully authorized by all parties, and the collection, storage, use, processing, transmission, provision, disclosure and application of the relevant data comply with relevant laws, regulations and standards, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0039] Traditional CMOS circuits are widely used in digital circuits, which are constructed based on transistor-based Boolean logic gates, such as AND gates and OR gates, to perform various logic functions. However, with the increase in integration and the reduction in process size, the number of CMOS transistors will increase, leading to problems such as increased circuit complexity, increased power consumption and larger layout area.

[0040] Traditional adders usually perform addition operations in a serial or parallel manner. However, with the growing computing demand and the emergence of new application scenarios, traditional adders face multiple challenges such as performance, power consumption, area, and flexibility. Traditional serial carry adders have relatively slow computing speed and high power consumption, while carry-lookahead adders face the problems of complex circuits, large area, and poor flexibility.

[0041] During the research and development process, the researchers found that the increase in the number of CMOS transistors in related technologies led to problems such as increased circuit complexity, increased power consumption and expanded layout area. At the same time, the traditional serial carry adder circuit and carry lookahead adder circuit constructed with multiple CMOS transistors had technical problems such as low data processing parallelism, high latency and slow calculation speed.

[0042] In view of this, an embodiment of the present disclosure provides a prefix parallel adder based on a dual-gate structure reconfigurable transistor, including: a prefix parallel adder constructed based on a dual-gate structure reconfigurable transistor of a low-dimensional channel material has N layers of logic depth, the prefix parallel adder includes a preprocessing gate-level circuit, a prefix unit circuit and a summing output circuit, wherein each logic gate of the preprocessing gate-level circuit, the prefix unit circuit and the summing output circuit is obtained by modulating the dual-gate structure reconfigurable transistor corresponding to each logic gate; a preprocessing gate-level circuit, the preprocessing gate-level circuit is connected to the prefix unit circuit, the preprocessing gate-level circuit includes an "AND" gate and an "OR" gate, which are used to convert the input information of the prefix parallel adder into a carry transfer factor and a carry generation factor; a prefix unit circuit, the prefix unit circuit is connected to the summing output circuit, The prefix unit circuit includes a calculation circuit for a carry generation factor and a calculation circuit for a carry propagation factor. The calculation circuit for the carry generation factor includes an AND gate and an OR gate. The calculation circuit for the carry propagation factor includes an AND gate, which is used to merge and propagate the carry propagation factor and the carry generation factor generated by the preprocessing gate-level circuit in the first-level logic level to obtain a new carry propagation factor and a new carry generation factor. The new carry propagation factor and the new carry generation factor generate new nodes in the next level of logic depth until all carry information is transmitted; a summation output circuit, which includes two NOT gates, two AND gates and an OR gate, is used to calculate the final sum of the prefix parallel adder according to the new carry propagation factor, the new carry generation factor and the carry information obtained in the Nth level of logic depth.

[0043] The following will be through Figure 1~ Fig.10 The prefix parallel adder based on the dual-gate structure reconfigurable transistor of the disclosed embodiment is described in detail.

[0044] According to an embodiment of the present disclosure, a prefix parallel adder constructed based on a dual-gate structure reconfigurable transistor of a low-dimensional channel material has N logic layers, and the prefix parallel adder includes a preprocessing gate-level circuit, a prefix unit circuit, and a summing output circuit.

[0045] According to an embodiment of the present disclosure, the prefix parallel adder based on the dual-gate structure reconfigurable transistor is an 8-bit prefix parallel adder, and the N-level logic depth may include 6-level logic depth, 5-level logic depth and 4-level logic depth.

[0046] According to an embodiment of the present disclosure, a circuit of a prefix parallel adder based on a dual-gate structure reconfigurable transistor is constructed by using a plurality of dual-gate structure reconfigurable transistors.

[0047] According to the embodiments of the present disclosure, each logic gate in the preprocessing gate-level circuit, the prefix unit circuit and the summation output circuit is obtained by modulating the dual-gate structure reconfigurable transistor corresponding to each logic gate, and the dual-gate structure reconfigurable transistor in the circuit of the prefix parallel adder based on the dual-gate structure reconfigurable transistor is modulated so that the logic state of the dual-gate structure reconfigurable transistor presents "AND logic" or "OR logic", thereby realizing the reconfiguration of the two logics and the programmability of the circuit of the prefix parallel adder based on the dual-gate structure reconfigurable transistor.

[0048] According to an embodiment of the present disclosure, a preprocessing gate-level circuit is connected to the prefix unit circuit, and the preprocessing gate-level circuit includes an "AND" gate and an "OR" gate, which are used to convert the input information of the prefix parallel adder into a carry propagation factor and a carry generation factor.

[0049] According to an embodiment of the present disclosure, the input of the prefix parallel adder based on the dual-gate structure reconfigurable transistor is a [i] and b [i] , i is an integer, 0≤i≤7. Input a [i] and b [i] First, the input of each bit is converted into a carry generation factor g through the AND gate and OR gate in the preprocessing gate level circuit in the first logic level. i and the carry-propagation factor p i , to realize the preprocessing of the input of the prefix parallel adder based on the dual-gate structure reconfigurable transistor.

[0050] According to an embodiment of the present disclosure, a prefix unit circuit is connected to a summation output circuit, the prefix unit circuit includes a calculation circuit for a carry generation factor and a calculation circuit for a carry propagation factor, the calculation circuit for the carry generation factor includes an AND gate and an OR gate, the calculation circuit for the carry propagation factor includes an AND gate for merging and propagating the carry propagation factor and the carry generation factor generated by the preprocessing gate level circuit in the first logic level to obtain a new carry propagation factor and a new carry generation factor, the new carry propagation factor and the new carry generation factor generate a new node in the next logic depth until all carry information is transmitted.

[0051] According to an embodiment of the present disclosure, after being processed by a preprocessing gate-level circuit in the first-level logic level of a prefix parallel adder based on a dual-gate structure reconfigurable transistor, the carry generation factor g of each bit is obtained. iand the carry-propagation factor p i , input to the calculation circuit of the carry generation factor and the calculation circuit of the carry transfer factor in the prefix unit circuit in the first logical depth to calculate the prefix sum. Then, from the second logical depth to the Nth logical depth, the carry information of the 0th bit is transferred to the higher bit until all the carry information is transferred. In this way, the input information is merged and transferred according to the carry chain branches and prefix sum calculation bits set in the prefix parallel adders with different logical depths.

[0052] According to an embodiment of the present disclosure, a summation output circuit includes two NOT gates, two AND gates and one OR gate, which is used to calculate the final sum of the prefix parallel adder based on the new carry propagation factor, the new carry generation factor and the carry information obtained in the Nth level of logic depth.

[0053] According to an embodiment of the present disclosure, after being processed by the preprocessing gate-level circuit from the second logic depth to the Nth logic depth of the prefix parallel adder based on the dual-gate structure reconfigurable transistor, the new carry propagation factor and the new carry generation factor of each bit are summed and output to realize the output of the prefix parallel adder.

[0054] According to an embodiment of the present disclosure, a prefix parallel adder with N layers of logic depth is constructed by using a dual-gate structure reconfigurable transistor based on a low-dimensional channel material. The prefix parallel adder based on the dual-gate structure reconfigurable transistor includes a preprocessing gate-level circuit, a prefix unit circuit and a summing output circuit. By modulating each dual-gate structure reconfigurable transistor of the preprocessing gate-level circuit, the prefix unit circuit and the summing output circuit, the dual-gate structure reconfigurable transistor can switch between the "AND gate" and the "OR gate" to obtain the required logic state in the prefix parallel adder, thereby realizing the reconfigurability of the circuit of the prefix parallel adder based on the dual-gate structure reconfigurable transistor, and while reducing the number of devices, a highly versatile, low-power, miniaturized and lightweight integrated circuit can be constructed.

[0055] According to an embodiment of the present disclosure, a preprocessing gate-level circuit in a prefix parallel adder based on a dual-gate structure reconfigurable transistor is connected to a prefix unit circuit, the preprocessing gate-level circuit includes an AND gate and an OR gate, the prefix unit circuit is connected to a summing output circuit, the prefix unit circuit includes a calculation circuit for a carry generation factor and a calculation circuit for a carry transfer factor, the calculation circuit for the carry generation factor includes an AND gate and an OR gate, the calculation circuit for the carry transfer factor includes an AND gate, and the summing output circuit includes two NOT gates, two AND gates and an OR gate. By inputting information a to each bit of the prefix parallel adder, [i] and b [i] Preprocess it and convert it into a carry transfer factor pi and the carry generation factor g i , and then through the calculation circuit of the carry generation factor and the calculation circuit of the carry propagation factor, the carry propagation factor and the carry generation factor generated by the preprocessing gate-level circuit in the first-level logic level are prefixed and calculated in the first-level logic depth to obtain the new carry propagation factor and the new carry generation factor of each bit input. Through the carry chain branch, the new carry propagation factor and the new carry generation factor generate new nodes in the next-level logic depth, so as to effectively transfer the carry information of the previous bit to the current bit, and then provide the key and accurate input for the next-level logic, while ensuring that the prefix parallel adder based on the dual-gate structure reconfigurable transistor can efficiently merge the carry information of each bit in the calculation process, while reducing the need for low-bit carry propagation, thereby improving the calculation efficiency. Finally, through the summation output circuit, the new carry propagation factor, the new carry generation factor and the carry information of each bit are summed to obtain the final sum. While realizing the summation calculation by using the prefix parallel adder based on the dual-gate structure reconfigurable transistor, since the prefix parallel adder can process the addition of multiple bits at the same time, the data processing parallelism of the prefix parallel adder based on the dual-gate structure reconfigurable transistor is high and the delay is low, which reduces the loss of data transmission. It has the advantages of fast speed, low power consumption, small size and easy integration in the digital system, further improves the delay problem in the digital circuit, uses fewer components to build a complex digital circuit, reduces the area of ​​the integrated circuit while reducing power consumption, and has potential application in logic operations and data processing in microcontrollers.

[0056] Figure 1a The structure diagram of a calculation circuit of a carry generation factor of a prefix parallel adder based on a dual-gate structure reconfigurable transistor according to an embodiment of the present disclosure is schematically shown. Figure 1b The structure diagram of a calculation circuit of a carry propagation factor of a prefix parallel adder based on a dual-gate structure reconfigurable transistor according to an embodiment of the present disclosure is schematically shown.

[0057] like Figure 1a to Figure 1b As shown, the calculation circuit of the carry generation factor includes an AND gate and an OR gate, represented by a first AND gate 101 and a first OR gate 102 , and the calculation circuit of the carry propagation factor includes an AND gate, represented by a second AND gate 103 .

[0058] According to an embodiment of the present disclosure, the output terminal of the first AND gate is connected to the second input terminal of the first OR gate, and the first input terminal of the first AND gate receives G [k-1：j] The carry generation factor, the second input terminal of the first AND gate receives P [i：k] The carry transfer factor, the first input terminal of the first OR gate receives G [i：k]Carry generation factor, the output terminal of the first "OR" gate outputs G [i：j] Carry generation factor.

[0059] According to an embodiment of the present disclosure, the calculation logic of the calculation circuit of the carry generation factor can be calculated according to formula (1), and formula (1) is shown as follows.

[0060] G [i：j] = G [i：k] + G [k-1：j] P [i：k] (1);

[0061] Wherein, G [i：j] can be characterized as a new carry generation factor including the carry information from the j-th input to the i-th input, G [i：k] can be characterized as a carry generation factor including the carry information from the k-th input to the i-th input, G [k-1：j] can be characterized as a carry generation factor including the carry information from the j-th input to the (k - 1)-th input, P [i：k] can be characterized as a new carry propagation factor including the carry information from the k-th input to the i-th input, j < k < i, i, j, and k are all integers, i usually can be characterized as the high bit of the array, j usually can be characterized as the low bit of the array, 0 ≤ i ≤ 7, 0 ≤ j ≤ 6. In the case of calculating the carry generation factor at different logic depths, according to G [k-1：j] carry generation factor and P [i：k] carry propagation factor to perform an "AND" logic operation, and then perform an "OR" logic operation on the result obtained after the "AND" logic operation and G [i：k] carry generation factor to obtain G [i：j] carry generation factor.

[0062] According to an embodiment of the present disclosure, the first input terminal of the second "AND" gate receives P [i：k] carry propagation factor, the second input terminal of the second "AND" gate receives P [k-1：j] carry propagation factor, and the output terminal of the second "AND" gate outputs P [i：j] carry propagation factor.

[0063] According to an embodiment of the present disclosure, the calculation logic of the calculation circuit of the carry propagation factor can be calculated according to formula (2), and formula (2) is shown as follows.

[0064] P [i：j] = P [i：k] P [k-1：j] (2);

[0065] Wherein, P [i：j]can be characterized as a new carry propagation factor P that contains carry information from the j-th input to the i-th input [i：k] can be characterized as a carry propagation factor P that contains carry information from the k-th input to the i-th input [k-1：j] can be characterized as a carry propagation factor that contains carry information from the j-th input to the (k - 1)-th input, where j < k < i, and i, j, and k are all integers. i is usually characterized as the high bit of the array, and j is usually characterized as the low bit of the array. 0 ≤ i ≤ 7, 0 ≤ j ≤ 6. In the case of calculating the carry propagation factor at different logical depths, according to P [k-1：j] carry propagation factor and P [i：k] carry propagation factor perform an "AND" logic operation to obtain P [i：j] carry propagation factor.

[0066] According to an embodiment of the present disclosure, when using the carry generation factor g i and carry propagation factor p i generated by preprocessing in each bit of the first logic level to calculate the carry generation factor and carry propagation factor in the first logic depth, according to the preset parallel calculation bits, the carry generation factor g i and carry propagation factor p i generated by preprocessing are calculated according to the logic in formulas (1) and (2). For example, parallel calculation is performed between the second bit and the third bit. Using the carry generation factor g2 of the second bit, the carry generation factor g3 of the third bit, and the carry propagation factor p3 of the third bit generated by preprocessing in the first logic level for calculation, to obtain the G [3：2] carry generation factor in the first logic depth. Using the carry propagation factor p2 of the second bit and the carry propagation factor p3 of the third bit generated by preprocessing in the first logic level for calculation, to obtain the P [3：2] carry propagation factor in the first logic depth.

[0067] According to an embodiment of the present disclosure, in the calculation circuit of the carry generation factor, the output terminal of the first "AND" gate is connected to the second input terminal of the first "OR" gate. The first input terminal of the first "AND" gate receives the G [k-1：j] carry generation factor, and the second input terminal of the first "AND" gate receives the P [i：k] carry propagation factor. The first input terminal of the first "OR" gate receives the G [i：k] carry generation factor, and the output terminal of the first "OR" gate outputs the G [i：j] carry generation factor. In the calculation circuit of the carry propagation factor, the first input terminal of the second "AND" gate receives the P [i：k] carry propagation factor, and the second input terminal of the second "AND" gate receives the P [k-1：j]The carry transfer factor, the output of the second AND gate outputs P [i：j] Carry propagation factor. Thus, according to the preset parallel calculation bit, the carry propagation factor g generated by preprocessing in the first layer logic level is used. i and the carry generation factor p i , through the calculation circuit of the carry generation factor and the calculation circuit of the carry propagation factor in the first layer of logic depth, the prefix and parallel calculation are performed. Then, according to the pre-set carry chain branch, the G generated in the previous layer of logic depth is used. [i：k] Carry Generation Factor and P [i：k] The carry propagation factor propagates the carry information of the low bit to the high bit, ensuring that the carry information of the previous bit can be effectively transmitted to the current bit, thus improving the calculation efficiency.

[0068] Figure 2 The structure diagram of the pre-processing gate-level circuit of the prefix parallel adder based on the dual-gate structure reconfigurable transistor according to the embodiment of the present disclosure is schematically shown.

[0069] like Figure 2 As shown, the pre-processing gate-level circuit includes an AND gate and an OR gate, which are represented as a third AND gate 201 and a second OR gate 202 .

[0070] According to an embodiment of the present disclosure, the first input terminal of the third AND gate receives input information a [i] , the second input terminal of the third AND gate receives input information b [i] , the output of the third AND gate outputs the carry transfer factor g of the i-th bit i , the first input terminal of the second OR gate receives input information a [i] The second input terminal of the second OR gate receives input information b [i] , the output of the second OR gate outputs the carry generation factor p of the i-th bit i .

[0071] Figure 3 The structure diagram of the summing output circuit of the prefix parallel adder based on the dual-gate structure reconfigurable transistor according to the embodiment of the present disclosure is schematically shown.

[0072] like Figure 3 As shown, the summing output circuit includes two NOT gates, two AND gates and one OR gate, which are represented by a first NOT gate 301 , a second NOT gate 302 , a fourth AND gate 303 , a fifth AND gate 304 and a third OR gate 305 .

[0073] According to an embodiment of the present disclosure, the output end of the fourth AND gate is connected to the first input end of the third OR gate, the output end of the fifth AND gate is connected to the second input end of the third OR gate, and the first input end of the fourth AND gate receives the new carry propagation factor P obtained after the prefix unit circuit is processed in the Nth logical depth. i , which is equivalent to the new carry-transfer factor P [i：0] The second input terminal of the fourth AND gate receives the carry information C after being processed by the first NOT gate. i-1 The first input terminal of the fifth AND gate is connected to the second input terminal of the fourth AND gate, the second input terminal of the fifth AND gate is connected to the first input terminal of the fourth AND gate, and the first input terminal of the fifth AND gate receives the carry information C i-1 The second input terminal of the fifth AND gate receives the new carry transfer factor P after being processed by the second NOT gate. i The output of the third OR gate outputs the final sum S of the i-th input i .

[0074] According to the embodiment of the present disclosure, the first NOT gate and the second NOT gate can be inverters prepared by CMOS technology, or can be inverters prepared by the technology of dual-gate structure reconfigurable transistors. The dual-gate structure reconfigurable transistors can be modulated to make the logic function of the dual-gate structure reconfigurable transistors present a NOT gate, thereby realizing the function required in the summation processing circuit, that is, the first NOT gate and the second NOT gate are used to input the carry information C i-1 or carry-propagation factor P i Perform a logic flip.

[0075] According to an embodiment of the present disclosure, the summation calculation can be calculated according to formula (3), formula (4) and formula (5), and formula (3), formula (4) and formula (5) are as follows.

[0076] S [i] =P i ~ C i-1 +~P i C i-1 (3);

[0077] Among them, S [i] It can be represented as the final sum of the i-th input, P i It can be represented as the new carry propagation factor obtained after the prefix unit circuit processing in the Nth logic depth, C i-1 It can be represented as the carry information of the i-1th bit.

[0078] C i = G [i：0] (4);

[0079] Among them, C i It can be represented as the carry information of the i-th bit, G [i：0] It can be characterized as a new carry generation factor containing carry information from the 0th input to the i-th input.

[0080] C out = C n-1 (5);

[0081] Among them, C out It can be represented as output carry, C n-1 It can be represented as the carry of the n-1th input.

[0082] According to an embodiment of the present disclosure, when performing a summation calculation, the new carry transfer factor P i and the carry information C after being processed by the first NOT gate i-1 Perform the "AND" logic operation to transfer the new carry factor P after the first NOT gate processing. i and carry information C i-1 The "AND" logic operation is also performed, and the "OR" logic operation is performed on the two results obtained after the "AND" logic operation to obtain the final sum S of the i-th input i .

[0083] According to the embodiment of the present disclosure, the prefix parallel adder based on the dual-gate structure reconfigurable transistor uses a calculation circuit of the carry generation factor and a calculation circuit of the carry transmission factor to add multiple input information, and realizes the logic transmission of the carry chain c by "OR and NOT" (OAI) and "AND and OR NOT" (AOI) by combining with the inverter in the CMOS process. Then, the result s is obtained by generating the final sum operation, realizing the addition operation of the form a + b = s.

[0084] Figure 4 The schematic diagram of the structure of a dual-gate structure reconfigurable transistor according to an embodiment of the present disclosure is shown schematically.

[0085] like Figure 4 As shown, the dual-gate structure reconfigurable transistor includes a substrate 401 , a back gate electrode 402 , a ferroelectric gate dielectric 403 , a buffer layer 404 , a channel 405 , a source-drain electrode 406 , a top gate dielectric 407 and a top gate electrode 408 designed in sequence along a vertical direction.

[0086] According to an embodiment of the present disclosure, the channel of the dual-gate structure reconfigurable transistor can be prepared using low-dimensional materials such as molybdenum disulfide, which is a single-layer or multi-layer two-dimensional atomic crystal material, and the gate dielectric of the dual-gate structure reconfigurable transistor can be prepared using ferroelectric or hafnium-based materials.

[0087] According to the embodiments of the present disclosure, since the channel of the dual-gate structure reconfigurable transistor is prepared using a single layer or multiple layers of low-dimensional materials, electrons may encounter fewer defects or interface scattering when moving in the material, further reducing the static power consumption of the device.

[0088] According to an embodiment of the present disclosure, a dual-gate structure reconfigurable transistor realizes mutual conversion from an AND gate to an OR gate of a dual-gate structure reconfigurable transistor in a prefix parallel adder by changing the polarity of the back-gate electric field of the dual-gate structure reconfigurable transistor and combining the coordinated modulation of the top gate of the dual-gate structure reconfigurable transistor by an external electric field.

[0089] According to an embodiment of the present disclosure, a dual-gate structure reconfigurable transistor has a working environment compatible with a CMOS transistor.

[0090] According to the embodiments of the present disclosure, since the dual-gate structure reconfigurable transistor has both a top gate and a back gate, and different control voltages can be applied to the top gate and the back gate, respectively, there is a gate at a symmetrical position between the source and the drain, and the conductance of the channel is controlled by co-modulating the top gate (TG) and the back gate (BG), thereby controlling the output current. Combined with the modulation of the channel by the dual gate, the output characteristics of the device under different input voltage conditions are obtained, thereby deriving the truth table of the "AND" gate and the "OR" gate, and obtaining the "AND logic" and "OR logic" in the form of a truth table. Therefore, by changing the gate voltage of the top gate and the back gate to switch the working point, the dual-gate structure reconfigurable transistor can be switched from the "AND logic" state to the "OR logic" state, or, the dual-gate structure reconfigurable transistor can be switched from the "OR logic" state to the "AND logic" state, thereby realizing the logic reconfiguration of the dual-gate structure reconfigurable transistor, and enhancing the flexibility of circuit construction.

[0091] Figure 5a The schematic diagram schematically shows a transfer curve obtained by setting the top gate voltage and the back gate voltage according to an embodiment of the present disclosure. Figure 5b A schematic diagram schematically shows a working point selected by a truth table obtained according to a transfer curve according to an embodiment of the present disclosure.

[0092] like Figure 5a to Figure 5b As shown in the figure, by controlling the back gate voltage (BG) and the ferroelectric polarization direction (FG), the conductance of the channel is controlled, and then the output current is controlled. Combined with the control of the top gate on the channel, the transfer curves state0 and state1 of the dual-gate structure reconfigurable transistor are obtained. The transfer curves state0 and state1 of the dual-gate structure reconfigurable transistor provide the output characteristics of the device under different input voltage conditions. According to the predetermined current threshold, multiple operating points are determined from the transfer curves state0 and state1, that is, set as follows Figure 5bThe part with small current in the middle gray area is logic state 0, and the part with large current in the black area is logic state 1. The first four working points realize "AND" logic, and the last four working points realize "OR" logic, and the truth table of "AND" gate and "OR" gate is obtained.

[0093] According to an embodiment of the present disclosure, the truth table of the AND gate may be as shown in Table 1.

[0094] Table 1

[0095]

[0096] According to an embodiment of the present disclosure, the truth table of the “OR” gate may be as shown in Table 2.

[0097] Table 2

[0098]

[0099] According to an embodiment of the present disclosure, the prefix parallel adder includes: an 8-bit prefix parallel adder with an architecture of 6-level logic depth, the 8-bit prefix parallel adder with an architecture of 6-level logic depth includes 6-level logic gates and 8-bit inputs, the 8-bit prefix parallel adder with an architecture of 6-level logic depth is used to perform parallel calculations on the fourth-bit input and the fifth-bit input, and to expand carry chain branches on the third-bit input and the fifth-bit input, so that while using the 8-bit prefix parallel adder with an architecture of 6-level logic depth for parallel calculations, only 67 dual-gate structure reconfigurable transistors are used to reduce power consumption.

[0100] According to an embodiment of the present disclosure, the 67 dual-gate structure reconfigurable transistors used in the process of building an 8-bit prefix parallel adder with an architecture of 6 layers of logic depth do not include the first NOT gate and the second NOT gate (two inverters) in the summation output circuit. The first NOT gate and the second NOT gate can be inverters prepared by CMOS process.

[0101] Figure 6 The diagram schematically shows a prefix parallel adder node based on a dual-gate structure reconfigurable transistor with a logic depth of 6 according to an embodiment of the present disclosure.

[0102] like Figure 6 As shown, Figure 6The efficient carry calculation process of the prefix parallel adder based on the dual-gate structure reconfigurable transistor with a logic depth of 6 is shown. The node can be characterized as a joint operation unit of (G, P), that is, the calculation of the carry generation factor and the calculation of the carry transfer factor are performed, and each node stores the information of the carry generation factor and the carry transfer factor of the node. The prefix sum calculation is performed simultaneously at the 4th and 5th bits and the 5th and 6th bits, which is specifically completed by the calculation circuit of the carry generation factor and the calculation circuit of the carry transfer factor. These nodes store the information of the carry generation factor and the carry transfer factor at the corresponding positions, laying the foundation for the subsequent carry transfer. Further, through the remaining 5 layers of logic depth, according to the carry chain branch expanded at the third input and the fifth input, the carry chain is transferred from the 0th bit to the high bit. The carry information of the previous bit in each layer of logic can be effectively transferred to the current bit, providing a key carry input for the next layer of logic. By passing the information step by step, it is ensured that the input information can be efficiently merged with the carry information in the entire prefix parallel adder based on the dual-gate structure reconfigurable transistor. By calculating the prefix sum at the 4th and 5th bits and the 5th and 6th bits at the same time, the carry information can be effectively merged, reducing the need to transfer the carry at the lower bits, thereby reducing power consumption and effectively merging the carry information while using only 67 dual-gate structure reconfigurable transistors. Furthermore, the carry transfer factor of the i-th bit and its low-bit carry generation factor are subjected to an "exclusive or" operation based on "and" logic and "or" logic, generating an 8-bit parallel addition output.

[0103] According to an embodiment of the present disclosure, the prefix parallel adder also includes: an 8-bit prefix parallel adder with an architecture of 5-level logic depth, the 8-bit prefix parallel adder with an architecture of 5-level logic depth includes 5 levels of logic gates and 8-bit inputs, the 8-bit prefix parallel adder with an architecture of 5-level logic depth is used to perform parallel calculations on the second-bit input and the fifth-bit input, and to expand carry chain branches on the first-bit input and the fourth-bit input, so that while using the 8-bit prefix parallel adder with an architecture of 5-level logic depth for parallel calculations, only 67 dual-gate structure reconfigurable transistors are used, so as to improve the calculation speed and parallelism of the prefix parallel adder using 5-level logic depth.

[0104] According to an embodiment of the present disclosure, the 67 dual-gate structure reconfigurable transistors used in the process of building an 8-bit prefix parallel adder with an architecture with a 5-layer logic depth do not include the first NOT gate and the second NOT gate (two inverters) in the summation output circuit. The first NOT gate and the second NOT gate can be inverters prepared by CMOS process.

[0105] Figure 7The diagram schematically shows a prefix parallel adder node based on a dual-gate structure reconfigurable transistor with a logic depth of 5 according to an embodiment of the present disclosure.

[0106] like Figure 7 As shown, Figure 7 The efficient carry calculation process of the prefix parallel adder based on the dual-gate structure reconfigurable transistor with a logic depth of 5 is shown. The node can be characterized as a joint operation unit of (G, P), that is, the calculation of the carry generation factor and the calculation of the carry transfer factor are performed, and each node stores the information of the carry generation factor and the carry transfer factor of the node. The prefix sum is calculated at the 2nd, 3rd and 5th, 6th bits at the same time, which is specifically completed by the calculation circuit of the carry generation factor and the calculation circuit of the carry transfer factor. These nodes store the information of the carry generation factor and the carry transfer factor at the corresponding positions, laying the foundation for the subsequent carry transfer. Further, through the remaining 4 layers of logic depth, according to the carry chain branch expanded at the first input and the fourth input, the carry chain is transferred from the 0th bit to the higher bit. The carry information of the previous bit in each layer of logic can be effectively transferred to the current bit, providing a key carry input for the next layer of logic. By passing the information step by step, it is ensured that the input information can be efficiently merged with the carry information in the entire prefix parallel adder based on the dual-gate structure reconfigurable transistor. By calculating the prefix sum at the 2nd and 3rd bits and the 5th and 6th bits at the same time, the carry information can be effectively merged, reducing the need to transfer the carry at the lower bits, thereby improving the calculation speed and effectively merging the parallelism of the carry information while using only 67 dual-gate structure reconfigurable transistors. Furthermore, the carry transfer factor of the i-th bit and its low-bit carry generation factor are subjected to an "exclusive OR" operation based on "AND" logic and "OR" logic, generating an 8-bit parallel addition output.

[0107] According to an embodiment of the present disclosure, the prefix parallel adder also includes: an 8-bit prefix parallel adder with an architecture of 4-level logic depth, the 8-bit prefix parallel adder with an architecture of 4-level logic depth includes 4-level logic gates and 8-bit inputs, the 8-bit prefix parallel adder with an architecture of 4-level logic depth is used to parallel calculate the zeroth input, the second input, the fourth input and the sixth input, and expand the carry chain branch at the first input, the third input and the fifth input, so that while using the 8-bit prefix parallel adder with an architecture of 4-level logic depth for parallel calculation, only 70 dual-gate structure reconfigurable transistors are used, so as to improve the calculation speed and parallelism of the prefix parallel adder using 4-level logic depth.

[0108] According to an embodiment of the present disclosure, the 70 dual-gate structure reconfigurable transistors used in the process of building an 8-bit prefix parallel adder with an architecture with a 4-layer logic depth do not include the first NOT gate and the second NOT gate (two inverters) in the summation output circuit. The first NOT gate and the second NOT gate can be inverters prepared by CMOS process.

[0109] Figure 8 The diagram schematically shows a prefix parallel adder node based on a dual-gate structure reconfigurable transistor with a logic depth of 4 according to an embodiment of the present disclosure.

[0110] like Figure 8 As shown, Figure 8 The efficient carry calculation process of the prefix parallel adder based on the dual-gate structure reconfigurable transistor with a logic depth of 4 is shown. The node can be characterized as a joint operation unit of (G, P), that is, the calculation of the carry generation factor and the carry transfer factor are performed, and each node stores the information of the carry generation factor and the carry transfer factor of the node. The prefix sum is calculated at the 0th, 1st, 2nd, 3rd, 4th, 5th and 6th, 7th bits at the same time, which is specifically completed by the calculation circuit of the carry generation factor and the calculation circuit of the carry transfer factor. These nodes store the information of the carry generation factor and the carry transfer factor at the corresponding positions, laying the foundation for the subsequent carry transfer. Further, through the remaining 3 layers of logic depth, according to the carry chain branches expanded at the first input, the third input and the fifth input, the carry chain is transferred from the 0th bit to the higher bit. The carry information of the previous bit in each layer of logic can be effectively transferred to the current bit, providing a key carry input for the next layer of logic. By passing the information step by step, it is ensured that the input information can be efficiently merged with the carry information in the entire prefix parallel adder based on the dual-gate structure reconfigurable transistor. By calculating the prefix sum at the 4th and 5th bits and the 5th and 6th bits at the same time, the carry information can be effectively merged, reducing the need to transfer the carry at the lower bits, thereby maximizing the calculation speed and effectively merging the parallelism of the carry information by using only 70 dual-gate structure reconfigurable transistors. Furthermore, the carry transfer factor of the i-th bit and its low-bit carry generation factor are subjected to the "exclusive OR" operation based on the "AND" logic and the "OR" logic, generating an 8-bit parallel addition output.

[0111] Fig. 9 The physical structure of a prefix parallel adder based on a dual-gate structure reconfigurable transistor with a logic depth of 4 according to an embodiment of the present disclosure is schematically shown.

[0112] like Fig. 9 As shown, Fig. 9 The physical topology diagram shows the Figure 8The example is an 8-bit prefix parallel adder with a logic depth of 4 based on a dual-gate structure reconfigurable transistor. Figure 8 Based on the node graph of [i] and b [i] The carry generation factor G is obtained by calculation in the preprocessing gate level circuit i and carry-propagation factor P i Steps 2 to 6 show that the new carry generation factor G is obtained by calculation in the calculation circuit of the carry generation factor and the calculation circuit of the carry transfer factor. [i：0] and the new carry-propagation factor P [i：0] , the final sum S is obtained by calculation in the summing output circuit through step 7. [i] , describe the process of addition from top to bottom and get the final result.

[0113] Fig.10 The topology diagram of a prefix parallel adder based on a dual-gate structure reconfigurable transistor with a logic depth of 4 according to an embodiment of the present disclosure is schematically shown.

[0114] like Fig.10 As shown, Fig.10 The circuit topology diagram shows the Figure 8 The example of an 8-bit prefix parallel adder based on a dual-gate reconfigurable transistor with a logic depth of 4 is shown. The addition operation is described by the expression s = a + b. Further, by magnifying the contents of s, a, and b, it is explained that s represents the output, a and b are the input data, and both contain 8 bits of data. Furthermore, it is revealed that the carry transfer factor p, the carry generation factor g, and the carry information C from the input data a and b to the output i and finally S i The detailed calculation process of the prefix parallel adder based on the dual-gate structure reconfigurable transistor is emphasized, and the internal structure and operation mechanism of the prefix parallel adder based on the dual-gate structure reconfigurable transistor are emphasized. By enlarging the nodes and edges of the prefix parallel adder topology diagram based on the dual-gate structure reconfigurable transistor, the form and method of internal signal transmission of the prefix parallel adder based on the dual-gate structure reconfigurable transistor are demonstrated, that is, the input signal forms the carry transmission factor p and the carry generation factor g through the logic gate composed of "AND" logic and "OR" logic, and then generates the carry information C through the logic gate. i and finally S i .

[0115] According to the embodiments of the present disclosure, the architecture of the prefix parallel adder is further expanded, and an inverter is constructed based on a dual-gate reconfigurable device. The prefix parallel adder may also include an inverter, and the inverter is constructed using a process of a dual-gate structure reconfigurable transistor. By modulating the dual-gate structure reconfigurable transistor, the energy consumption required by the inverter itself constructed based on the dual-gate reconfigurable device is reduced. The inverter can be inserted between the levels of the N-layer logic depth of the prefix parallel adder. For example, in an 8-bit prefix parallel adder with a 4-layer logic depth architecture, the first row of inverters is inserted in the first layer. The second row of inverters is inserted between the prefix unit circuit of the second logical depth and the prefix unit circuit of the second logical depth, the third row of inverters is inserted between the prefix unit circuit of the third logical depth and the prefix unit circuit of the fourth logical depth, thereby reversing the polarity of the signal, speeding up signal transmission in the case of long-distance transmission or deteriorated signal quality, optimizing the amplitude and shape of the signal, balancing the transmission delay of the signal, optimizing the overall system performance, and improving the signal transmission capability of the circuit in the prefix parallel adder.

[0116] According to an embodiment of the present disclosure, in a prefix parallel adder based on a dual-gate structure reconfigurable transistor, an inverter constructed by the process of a dual-gate structure reconfigurable transistor, which is equivalent to a buffer, is introduced between levels of N logic depths, thereby improving the load capacity of the entire circuit unit.

[0117] Fig.11 The flowchart of the method for constructing a prefix parallel adder based on a dual-gate structure reconfigurable transistor according to an embodiment of the present disclosure is schematically shown.

[0118] like Fig.11 As shown, the method for constructing a prefix parallel adder based on a dual-gate structure reconfigurable transistor in this embodiment includes operations S1110 to S1130.

[0119] In operation S1110, based on the dual-gate structure reconfigurable transistor, the input bits for parallel calculation and the input bits of the carry chain branches in the prefix parallel adders of different logical depths are determined, and circuits corresponding to the prefix parallel adders of different logical depths are built.

[0120] According to an embodiment of the present disclosure, according to an 8-bit prefix parallel adder with an architecture having a 6-level logic depth, it is determined to perform parallel calculations on the fourth input and the fifth input, and to expand the carry chain branch on the third input and the fifth input. According to an AND gate and an OR gate required for the preprocessing operation, the determined parallel calculation bit, an AND gate and an OR gate required for multiple groups of calculations of carry generation factors involved in the carry chain branch, an AND gate required for calculations of carry transfer factors, and two NOT gates, two AND gates and an OR gate required for the summation operation, and an inverter that can be expanded and inserted between circuits of every two levels of logic depth, a plurality of dual-gate structure reconfigurable transistors are used to build a circuit corresponding to a prefix parallel adder based on a dual-gate structure reconfigurable transistor with a 6-level logic depth.

[0121] According to an embodiment of the present disclosure, according to an 8-bit prefix parallel adder with an architecture having a 5-level logic depth, it is determined to perform parallel calculations on the second input and the fifth input, and to expand the carry chain branch on the first input and the fourth input. According to an AND gate and an OR gate required for the preprocessing operation, the determined parallel calculation bit, an AND gate and an OR gate required for multiple groups of calculations of carry generation factors involved in the carry chain branch, an AND gate required for calculations of carry transfer factors, and two NOT gates, two AND gates and an OR gate required for the summation operation, and an inverter that can be expanded and inserted between circuits of every two levels of logic depth, a plurality of dual-gate structure reconfigurable transistors are used to build a circuit corresponding to a prefix parallel adder based on a dual-gate structure reconfigurable transistor with a 5-level logic depth.

[0122] According to the embodiment of the present disclosure, according to the 8-bit prefix parallel adder with a 4-level logic depth architecture, it is determined that the zeroth input, the second input, the fourth input and the sixth input are parallelly calculated, and the carry chain branch is expanded at the first input, the third input and the fifth input. According to an AND gate and an OR gate required for the preprocessing operation, the determined parallel calculation bit, an AND gate and an OR gate required for multiple groups of calculations of carry generation factors involved in the carry chain branch, an AND gate required for calculations of carry transfer factors and two NOT gates, two AND gates and an OR gate required for the summation operation, and an inverter that can be expanded and inserted between circuits of every two levels of logic depth, a plurality of dual-gate structure reconfigurable transistors are used to build a circuit corresponding to the prefix parallel adder based on dual-gate structure reconfigurable transistors with a 4-level logic depth.

[0123] According to an embodiment of the present disclosure, a prefix parallel adder based on a dual-gate structure reconfigurable transistor

[0124] In operation S1120 , a node graph corresponding to prefix parallel adders of different logical depths is generated according to circuits corresponding to prefix parallel adders of different logical depths.

[0125] According to an embodiment of the present disclosure, a node graph corresponding to prefix parallel adders of different logic depths may include the logic functions that each dual-gate structure reconfigurable transistor in the circuit needs to present.

[0126] In operation S1130, based on the node graph, by changing the polarity of the back-gate electric field of the dual-gate structure reconfigurable transistor and combining the coordinated modulation of the top gate of the dual-gate structure reconfigurable transistor by an external electric field, the logic state of each dual-gate structure reconfigurable transistor in the circuit of the constructed prefix parallel adder is switched to obtain a prefix parallel adder.

[0127] According to an embodiment of the present disclosure, based on a dual-gate structure reconfigurable transistor, input bits for parallel calculation and input bits for expanding carry chain branches in prefix parallel adders of different logical depths are determined, and circuits corresponding to prefix parallel adders of different logical depths are constructed. According to the circuits corresponding to the prefix parallel adders of different logical depths, node graphs corresponding to prefix parallel adders of different logical depths are generated. Based on the logic functions that each dual-gate structure reconfigurable transistor marked in the node graph needs to present, the polarity of the back-gate electric field of the dual-gate structure reconfigurable transistor is changed, and the top gate of the dual-gate structure reconfigurable transistor is modulated by the coordinated electric field of the external electric field. The logic state of the tube is switched to obtain a prefix parallel adder, which realizes the requirements of integrated circuits with a small number of devices, high versatility, low power consumption, miniaturization and lightness. A prefix parallel adder with different logic depths that can improve the calculation speed and parallelism is built based on a dual-gate structure reconfigurable transistor. The prefix parallel adder based on the dual-gate structure reconfigurable transistor of the present application has high data processing parallelism and low latency, reduces the loss of data transmission, has the advantages of fast speed, low power consumption, small size and easy integration in digital systems, further improves the delay problem in digital circuits, uses fewer components to build complex digital circuits, reduces the area of ​​integrated circuits while reducing power consumption, and has potential applications in logical operations and data processing in microcontrollers.

[0128] According to an embodiment of the present disclosure, switching the logic state of each dual-gate structure reconfigurable transistor in the constructed prefix parallel adder circuit includes:

[0129] According to an embodiment of the present disclosure, a regulated back-gate voltage and a regulated top-gate voltage are applied to the back-gate and the top-gate of the dual-gate structure reconfigurable transistor, respectively.

[0130] According to the embodiments of the present disclosure, a truth table of “AND” logic and a truth table of “OR” logic are obtained according to the transfer curves of regulating the back gate voltage and regulating the top gate voltage.

[0131] According to an embodiment of the present disclosure, the transfer curve includes a plurality of operating points representing different logic states.

[0132] According to an embodiment of the present disclosure, based on the voltage difference between the "AND" logic and the "OR" logic satisfying a predetermined voltage threshold, multiple operating points can be determined from the transfer curve, and based on the predetermined current threshold of the dual-gate structure reconfigurable transistor, the multiple operating points are divided into a logic state of 0 and a logic state of 1 to obtain multiple operating points of determined logical states, and based on the multiple operating points of determined logical states, a truth table of the "AND" logic and a truth table of the "OR" logic are obtained.

[0133] According to an embodiment of the present disclosure, based on the truth table of "AND" logic and the truth table of "OR" logic, the voltages of the back gate and the top gate used to change the logic function of the dual-gate structure reconfigurable transistor are determined from the transfer curve, and the voltages of the back gate and the top gate of the dual-gate structure reconfigurable transistor are changed to switch the operating point, thereby realizing the mutual conversion between the "AND" gate and the "OR" gate of the dual-gate structure reconfigurable transistor.

[0134] According to an embodiment of the present disclosure, based on the logical function that each dual-gate structure reconfigurable transistor is required to present in advance in the node diagram, the voltages of the back gate and the top gate used to change the logical function of the dual-gate structure reconfigurable transistor are determined from the transfer curve, the voltages of the back gate and the top gate of the dual-gate structure reconfigurable transistor are changed, and the logical state of each dual-gate structure reconfigurable transistor in the circuit of the constructed prefix parallel adder is switched to obtain a prefix parallel adder.

[0135] So far, the embodiments of the present disclosure have been described in detail in conjunction with the accompanying drawings. It should be noted that the implementation methods not shown or described in the drawings or the body of the specification are all forms known to ordinary technicians in the relevant technical field and are not described in detail. In addition, the above definitions of each element and method are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and ordinary technicians in the field can simply change or replace them.

[0136] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations and / or combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways without departing from the spirit and teachings of the present disclosure. All of these combinations and / or combinations fall within the scope of the present disclosure.

Claims

1. A prefix parallel adder based on a dual-gate structure reconfigurable transistor, comprising: The prefix parallel adder constructed based on the dual-gate structure reconfigurable transistor of low-dimensional channel material has N layers of logic depth, and the prefix parallel adder includes a preprocessing gate-level circuit, a prefix unit circuit and a summing output circuit, wherein each logic gate of the preprocessing gate-level circuit, the prefix unit circuit and the summing output circuit is obtained by modulating the dual-gate structure reconfigurable transistor corresponding to each logic gate; The preprocessing gate-level circuit is connected to the prefix unit circuit, and the preprocessing gate-level circuit includes an AND gate and an OR gate, which are used to convert the input information of the prefix parallel adder into a carry-propagation factor and a carry-generation factor; The prefix unit circuit is connected to the summing output circuit, the prefix unit circuit includes a calculation circuit for a carry generation factor and a calculation circuit for a carry transfer factor, the calculation circuit for the carry generation factor includes an AND gate and an OR gate, the calculation circuit for the carry transfer factor includes an AND gate, which is used to merge and transfer the carry transfer factor and the carry generation factor generated by the preprocessing gate level circuit in the first layer of logic level to obtain a new carry transfer factor and a new carry generation factor, the new carry transfer factor and the new carry generation factor generate a new node in the next layer of logic depth until all carry information is transferred; The summation output circuit includes two NOT gates, two AND gates and one OR gate, which is used to calculate the final sum of the prefix parallel adder according to the new carry propagation factor, the new carry generation factor and the carry information obtained in the Nth layer of logic depth.

2. The prefix parallel adder according to claim 1, wherein: The calculation circuit of the carry generation factor includes an AND gate and an OR gate, which are characterized as a first AND gate and a first OR gate, and the calculation circuit of the carry transfer factor includes an AND gate, which is characterized as a second AND gate; The output end of the first AND gate is connected to the second input end of the first OR gate, and the first input end of the first AND gate receives G [k-1：j] The carry generation factor, the second input terminal of the first AND gate receives P [i：k] Carry transfer factor, the first input terminal of the first OR gate receives G [i：k] The carry generation factor, the output terminal of the first OR gate outputs G [i：j] Carry generation factor; The first input terminal of the second AND gate receives P [i：k] The carry transfer factor, the second input terminal of the second AND gate receives P [k-1：j] The carry transfer factor, the output terminal of the second AND gate outputs P [i：j] Carry-propagation factor.

3. The prefix parallel adder according to claim 1, wherein: The dual-gate structure reconfigurable transistor realizes the mutual conversion from AND gate to OR gate of the dual-gate structure reconfigurable transistor in the prefix parallel adder by changing the polarity of the back gate electric field of the dual-gate structure reconfigurable transistor and combining the coordinated modulation of the top gate of the dual-gate structure reconfigurable transistor by an external electric field, wherein the dual-gate structure reconfigurable transistor has a working environment compatible with CMOS transistors.

4. The prefix parallel adder according to claim 1, wherein: The prefix parallel adder includes: an 8-bit prefix parallel adder with an architecture of 6-layer logic depth, the 8-bit prefix parallel adder with an architecture of 6-layer logic depth includes 6 layers of logic gates and 8-bit inputs, the 8-bit prefix parallel adder with an architecture of 6-layer logic depth is used to parallel calculate the fourth input and the fifth input, and expand the carry chain branch at the third input and the fifth input, so that when the 8-bit prefix parallel adder with an architecture of 6-layer logic depth is used for parallel calculation, only 67 of the dual-gate structure reconfigurable transistors are used to reduce power consumption.

5. The prefix parallel adder according to claim 1, wherein: The prefix parallel adder also includes: an 8-bit prefix parallel adder with an architecture of 5-layer logic depth, the 8-bit prefix parallel adder with an architecture of 5-layer logic depth includes 5 layers of logic gates and 8-bit inputs, the 8-bit prefix parallel adder with an architecture of 5-layer logic depth is used to parallel calculate the second bit input and the fifth bit input, and expand the carry chain branch on the first bit input and the fourth bit input, so that when the 8-bit prefix parallel adder with an architecture of 5-layer logic depth is used for parallel calculation, only 67 dual-gate structure reconfigurable transistors are used, so as to improve the calculation speed and parallelism of the prefix parallel adder using 5-layer logic depth.

6. The prefix parallel adder according to claim 1, wherein: The prefix parallel adder also includes: an 8-bit prefix parallel adder with an architecture of 4-layer logic depth, the 8-bit prefix parallel adder with an architecture of 4-layer logic depth includes 4 layers of logic gates and 8-bit inputs, the 8-bit prefix parallel adder with an architecture of 4-layer logic depth is used to parallel calculate the zeroth bit input, the second bit input, the fourth bit input and the sixth bit input, and expand the carry chain branch on the first bit input, the third bit input and the fifth bit input, so that when the 8-bit prefix parallel adder with an architecture of 4-layer logic depth is used for parallel calculation, only 70 dual-gate structure reconfigurable transistors are used, so as to improve the calculation speed and parallelism of the prefix parallel adder using 4-layer logic depth.

7. The prefix parallel adder according to claim 1 further expands the architecture of the prefix parallel adder, and constructs an inverter based on a dual-gate reconfigurable device, wherein the dual-gate structure reconfigurable transistor includes a substrate, a back gate electrode, a ferroelectric gate dielectric, a buffer layer, a channel, a source-drain electrode, a top gate dielectric, and a top gate electrode sequentially designed in a vertical direction, wherein: The channel is made of low-dimensional material, which is a single-layer or multi-layer two-dimensional atomic crystal material, and the gate dielectric is made of ferroelectric or hafnium-based material.

8. The prefix parallel adder according to claim 1, wherein: The prefix parallel adder also includes an inverter, which is constructed using the process of the dual-gate structure reconfigurable transistor. The inverter is used to be inserted between logic levels of the prefix parallel adder, thereby reversing the polarity of the signal, speeding up signal transmission in the case of long-distance transmission or deterioration of signal quality, optimizing the amplitude and shape of the signal, balancing the transmission delay of the signal, optimizing the overall system performance, and improving the signal transmission capability of the circuit in the prefix parallel adder.

9. A method for constructing a prefix parallel adder based on a dual-gate structure reconfigurable transistor, comprising: Based on a dual-gate structure reconfigurable transistor, determine the input bits for parallel calculation and the input bits for expanding the carry chain branches in prefix parallel adders of different logical depths, and build circuits corresponding to the prefix parallel adders of different logical depths; Generate a node graph corresponding to the prefix parallel adders of different logical depths according to the circuits corresponding to the prefix parallel adders of different logical depths; Based on the node graph, by changing the polarity of the back-gate electric field of the dual-gate structure reconfigurable transistor and combining the coordinated modulation of the top gate of the dual-gate structure reconfigurable transistor by an external electric field, the logic state of each dual-gate structure reconfigurable transistor in the circuit of the constructed prefix parallel adder is switched to obtain the prefix parallel adder.

10. The prefix parallel adder according to claim 9, wherein: The switching of the logic state of each dual-gate structure reconfigurable transistor in the constructed prefix parallel adder circuit includes: Applying a regulated back-gate voltage and a regulated top-gate voltage to the back-gate and the top-gate of the dual-gate structure reconfigurable transistor, respectively; Obtaining a truth table of AND logic and a truth table of OR logic according to the transfer curves of the regulated back gate voltage and the regulated top gate voltage, wherein the transfer curves include a plurality of operating points representing different logic states; According to the truth table of the logic and the truth table of the OR logic, the voltages of the back gate and the top gate for changing the logic function of the dual-gate structure reconfigurable transistor are determined from the transfer curve, and the voltages of the back gate and the top gate of the dual-gate structure reconfigurable transistor are changed to switch the operating point to achieve mutual conversion between the AND gate and the OR gate of the dual-gate structure reconfigurable transistor.

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