Intercore GPIO (General Purpose Input / Output) interrupt coordination processing method, electronic equipment and storage medium

Abstract

The invention discloses an inter-core GPIO (General Purpose Input / Output) interrupt coordination processing method, electronic equipment and a storage medium, the method is applied to an embedded multi-core system, and comprises the following steps: setting a global shared variable for each core in the embedded multi-core system, the value of the global shared variable being used for representing the busy degree of the corresponding core; when a certain core processing task is busy, querying global shared variables of other cores; according to the global shared variables of the other cores, the cores for processing the idle tasks are determined, and the global shared variable value of the cores for processing the idle tasks is smaller than the global variable value of the cores for processing the busy tasks; and the GPIO interrupt of the core with the busy processing task is processed by the core with the idle processing task. According to the method, the problem of interruption delay or loss caused by overload of a single core can be avoided, balanced distribution of workloads among multiple cores can be promoted, and hardware resources are fully utilized.

Description

Technical Field

[0001] The present application relates to the field of embedded multi-core systems, and in particular to an inter-core GPIO interrupt coordination processing method, an electronic device and a storage medium. Background Art

[0002] In embedded multi-core systems, task allocation and processing efficiency are key factors to ensure system performance. However, in actual applications, it is often the case that a processor core (referred to as "core") undertakes a much larger amount of tasks than other cores, causing the core to become very busy at certain times while other cores are relatively idle. This phenomenon of unbalanced load between cores not only leads to a waste of resources, but also may affect the stability and real-time response capabilities of the system. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a method, electronic device and storage medium for coordinating GPIO interrupts between cores in an embedded multi-core system, which can effectively coordinate GPIO interrupts between cores in an embedded multi-core system, improve resource utilization efficiency, and ensure system stability and real-time response capabilities.

[0004] In order to achieve the above object, an embodiment of the present application provides an inter-core GPIO interrupt coordination processing method, which is applied to an embedded multi-core system, including:

[0005] A global shared variable is set for each core in the embedded multi-core system, wherein the value of the global shared variable is used to indicate the busyness or idleness of the corresponding core;

[0006] When a core is busy processing tasks, query the global shared variables of other cores;

[0007] Determine a core with idle processing tasks according to the global shared variables of other cores, wherein the value of the global shared variable of the core with idle processing tasks is smaller than the value of the global variable of the core with busy processing tasks;

[0008] The GPIO interrupt of the core with busy processing tasks is handed over to the core with idle processing tasks.

[0009] Optionally, after setting a global shared variable for each core in the embedded multi-core system, the method further includes: initializing each of the global shared variables.

[0010] Optionally, the method further includes: after predicting that a core is busy with a processing task according to the required processing task, adjusting the value of the global shared variable corresponding to the core according to the busyness.

[0011] Optionally, the method further includes: after handing over the GPIO interrupt of the core with busy processing tasks to the core with idle processing tasks for processing, feeding back the processing result of the core with idle processing tasks to the core with busy processing tasks.

[0012] Optionally, the processing result of the core with idle processing tasks is fed back to the core with busy processing tasks through a shared variable or a mailbox.

[0013] Optionally, when the core busy with processing tasks completes processing the current task and the busyness changes, the current value of the global shared variable corresponding to the core busy with processing tasks is adjusted.

[0014] Optionally, the method further includes: setting a local variable for each core in the embedded multi-core system, wherein the value of the local variable is used to indicate whether the GPIO interrupt of the corresponding core has been handed over to other cores for processing.

[0015] Optionally, determining a core with idle processing tasks according to global shared variables of other cores may specifically include:

[0016] The value of the GPIO interrupt sharing register set in the embedded multi-core system is routed to the corresponding interrupt controller, and the interrupt controller determines the core that the GPIO interrupt needs to share.

[0017] Optionally, the routing to the corresponding interrupt controller according to the value of the GPIO interrupt shared register is implemented through a routing circuit, and the routing circuit includes at least one AND circuit, the output end and the GPIO pin of the GPIO interrupt shared register are connected to the input end of the AND circuit, the output end of the AND circuit is connected to the input end of the interrupt controller, and the output end of the interrupt controller is connected to each of the cores.

[0018] An embodiment of the present application further provides an electronic device, including a processor and a memory, wherein an executable program is stored in the memory, and the processor executes the executable program to perform the steps of any one of the above methods.

[0019] An embodiment of the present application further provides a storage medium, which carries one or more computer programs, and when one or more of the computer programs are executed by a processor, the steps of any of the above methods are implemented.

[0020] An embodiment of the present application also provides a chip that adopts an embedded multi-core architecture. The embedded multi-core architecture adopts any of the methods described above to coordinate and control GPIO interrupts between cores in the embedded multi-core architecture.

[0021] The inter-core GPIO interrupt coordination processing method provided in the embodiment of the present application is applied to an embedded multi-core system. By setting a global shared variable for each core to dynamically reflect its current busy and idle status, the system can accurately grasp the workload of each core in real time; when it is detected that a core may affect the response to the GPIO interrupt due to high load, the busy and idle status of other cores is immediately queried, and the interrupt processing task is transferred to a relatively idle core for execution. The inter-core GPIO interrupt coordination processing method provided in the embodiment of the present application can not only avoid the interrupt delay or loss problem caused by the overload of a single core, but also promote the balanced distribution of workload among multiple cores and make full use of hardware resources. In addition, it can also ensure that key tasks are responded to in a timely manner, enhance the real-time performance and reliability of the system, and thus provide strong support for building efficient and stable embedded applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A flowchart of the inter-core GPIO interrupt coordination processing method provided in an embodiment of the present application;

[0023] Figure 2 This is a business flow chart of the inter-core GPIO interrupt coordination processing method used in the embodiment of the present application;

[0024] Figure 3 A schematic diagram of GPIO interrupt routing to each core in the inter-core GPIO interrupt coordination processing method provided in an embodiment of the present application;

[0025] Figure 4 A schematic diagram of a routing circuit in the inter-core GPIO interrupt coordination processing method provided in an embodiment of the present application;

[0026] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] Various schemes and features of the present application are described herein with reference to the accompanying drawings. It should be understood that various modifications may be made to the embodiments of the present application. Therefore, the above description should not be considered as limiting, but only as an example of an embodiment. Other modifications within the scope and spirit of the present application will occur to those skilled in the art.

[0028] In an embedded multi-core system, when a core is executing some tasks with high real-time requirements and high CPU consumption, such as graphics display, camera video recording or sensor data sampling, if it receives a GPIO external interrupt request at this time, especially when the interrupt processing logic is more complex, it may interfere with the important tasks currently in progress, causing problems such as screen refresh delays, image frame rate drops or untimely data collection, seriously affecting user experience and system performance.

[0029] In addition, in control application scenarios, such as motor drive control, the main control core needs to frequently process interrupt signals generated by motor encoders or other feedback mechanisms to ensure accurate speed regulation and position tracking. In this case, a large number of interrupt requests are concentrated on the same core for processing, which may exceed the processing capacity of the core, resulting in the loss of some interrupts, further affecting the reliability and accuracy of the entire system.

[0030] In addition, due to the different requirements of different computing tasks for processor resources and the limitations of application design, it is often difficult to achieve an ideal balance in task scheduling under a multi-core architecture. That is, some cores are in a high-load operation state for a long time, while other cores fail to fully utilize their computing potential, resulting in a situation of low resource utilization efficiency and prone to potential problems.

[0031] Therefore, how to effectively solve the above problems and achieve more reasonable and efficient task allocation and collaboration among processors within the embedded multi-core system has become a technical topic that needs to be studied urgently to improve the overall performance and reliability of the embedded system.

[0032] The inter-core GPIO interrupt coordination processing method provided in the embodiment of the present application is applied to an embedded multi-core system. By setting a global shared variable for each core to dynamically reflect its current busy and idle status, the system can accurately grasp the workload of each core in real time; when it is detected that a core may affect the response to the GPIO interrupt due to high load, the status of other cores is immediately queried, and the interrupt processing task is transferred to a relatively idle core for execution. The inter-core GPIO interrupt coordination processing method provided in the embodiment of the present application can not only avoid the interrupt delay or loss problem caused by the overload of a single core, but also promote the balanced distribution of workload among multiple cores and make full use of hardware resources. In addition, it can also ensure that key tasks are responded to in a timely manner, enhance the real-time performance and reliability of the system, and thus provide strong support for building efficient and stable embedded applications.

[0033] The inter-core GPIO interrupt coordination processing method provided in the embodiment of the present application is described in detail below in conjunction with the accompanying drawings. Figure 1 The flowchart of the inter-core GPIO interrupt coordination processing method provided by the embodiment of the present application is as follows: Figure 1 As shown, the method comprises the following steps:

[0034] S100: Setting a global shared variable for each core in the embedded multi-core system, wherein the value of the global shared variable is used to indicate the busyness or idleness of the corresponding core.

[0035] An embedded multi-core system is a system that integrates multiple processing cores in a single chip or microprocessor. These cores can perform different tasks in parallel, thereby improving the overall performance and responsiveness of the system. An embedded multi-core system can be configured to run the same operating system or different operating systems, depending on the specific application requirements and technical architecture.

[0036] When multiple cores run the same operating system, that is, in the SMP (Symmetric Multi-Processing) working mode, all cores share the same memory space, which can be used to store global shared variables set for each core. Each core can directly read and write this memory space through address mapping. In the SMP working mode, the operating system can dynamically assign tasks to any available core.

[0037] In the AMP (Asymmetric Multi-Processing) working mode, although the memory space between each core is usually isolated, each core can still access the same physical RAM in hardware. Data exchange can be achieved by defining a specific physical memory area as a shared area and ensuring that each core can be mapped to this memory in some way. In addition, part of the physical memory can be configured as I / O memory, so that even if the operating system does not support cross-core memory sharing, this memory can be read and written through I / O operations. In addition, when the cores cannot directly share memory in the AMP working mode, information exchange can be indirectly achieved by establishing a message passing mechanism. For example, use shared hardware registers, mailboxes, or other forms of communication queues for data transmission.

[0038] In the embodiment of the present application, the busyness of the core can be reflected by one or more of the CPU utilization, the task queue length and the interrupt frequency. Specifically, the CPU occupancy rate within the preset time can be calculated, and the occupancy rate can be used to reflect the busyness of the core; the number of tasks waiting to be processed within the preset time can also be counted, and the more tasks, the busier the core; the number of interrupts processed per unit time can also be recorded, and the more interrupts, the busier the core.

[0039] Exemplarily, the value of the global shared variable can be set to 0, 1, 2 and 3 respectively to indicate the busyness or idleness of the corresponding core. For example, 0 means completely idle; 1 means busy but with spare capacity; 2 means busy but with insufficient spare capacity; 3 means heavily loaded and with no time to take care of other things, etc.

[0040] S200: When a core is busy processing tasks, query the global shared variables of other cores.

[0041] In the embodiment of the present application, it is possible to pre-judge based on the required processing tasks or to determine whether a core processing task is busy based on the value of the current global shared variable.

[0042] When judging whether a core is busy based on the required processing task, it is possible to judge whether the corresponding core will enter a busy state next based on the nature of the required processing task and the estimated execution time. If so, query the global shared variables of other cores. Of course, it is also possible to judge whether the corresponding core is currently busy based on the value of the current global shared variable. If so, query the global shared variables of other cores. The busy state can be judged by comparing the preset busy threshold.

[0043] When querying the global shared variables of other cores, you can use polling query mode, that is, traverse the global shared variables of all cores to find the idlest core; you can also use broadcast query mode to send query requests to all cores, and determine the idlest core after obtaining the request results.

[0044] S300 . Determine a core with idle processing tasks according to global shared variables of other cores, wherein the value of the global shared variable of the core with idle processing tasks is smaller than the value of the global variable of the core with busy processing tasks.

[0045] In an embodiment of the present application, the minimum value method can be used to select the core with the smallest global shared variable value as the target core to be determined; the threshold method can also be used to select the core with a value below a preset threshold and the smallest global shared variable value as the target core to be determined. The threshold method can be used to avoid assigning tasks to cores that are already close to full load.

[0046] S400: Hand over the GPIO interrupt of the core that is busy with processing tasks to the core that is idle with processing tasks.

[0047] In an embodiment of the present application, an interrupt controller is configured and an interrupt redirection mechanism is used to hand over the GPIO interrupt of a core that is busy with processing tasks to a core that is idle with processing tasks.

[0048] In one embodiment of the present application, after setting a global shared variable for each core in the embedded multi-core system, the method further includes: initializing each of the global shared variables. The initial value of the global shared variable can be set to 0, indicating that the core is in a completely idle state; or it can be set to a smaller value, for example, 1 or 2, indicating that the core has a small number of basic tasks running but is still in an idle state.

[0049] In one embodiment of the present application, the inter-core GPIO interrupt coordination processing method provided by the embodiment of the present application also includes: after predicting that a core processing task is busy according to the required processing task, adjusting the value of the global shared variable corresponding to the core according to the busyness. It should be noted that for some cores, according to the value of the current global shared variable, it may be in an idle state, but it is predicted by the nature of the required processing task and the estimated execution time that it will enter a busy state next. In this case, it is necessary to adjust the current value of the global shared variable corresponding to the core according to the predicted busyness.

[0050] In one embodiment of the present application, the inter-core GPIO interrupt coordination processing method provided by the embodiment of the present application further includes: after handing over the GPIO interrupt of the core with busy processing tasks to the core with idle processing tasks for processing, feeding back the processing result of the core with idle processing tasks to the core with busy processing tasks, the specific process is:

[0051] The cores that are free from processing tasks can store the processing results in shared memory. At the same time, it is necessary to ensure that the read and write operations on the shared memory are atomic, that is, the read and write access to the memory cannot be interrupted to prevent data competition and inconsistency problems.

[0052] Afterwards, the core with idle processing tasks notifies the core with busy processing tasks through a semaphore or event flag after completing the processing; or, the core with busy processing tasks can periodically query the shared memory to check whether there is a new processing result.

[0053] In the above embodiment, the processing result of the core with idle processing tasks can be fed back to the core with busy processing tasks through a shared variable or a mailbox.

[0054] In the above embodiment, the current value of the global shared variable corresponding to each core can be updated in an event-driven manner. Specifically, when the core that is busy with processing tasks completes the current task and the busyness changes, the current value of the global shared variable corresponding to the core that is busy with processing tasks can be adjusted. Of course, the current value of the global shared variable corresponding to each core can also be updated in a periodic update manner. Specifically, a timer can be set to periodically update the current value of the global shared variable corresponding to each core through a timer interrupt.

[0055] In one embodiment of the present application, the inter-core GPIO interrupt coordination processing method provided by the embodiment of the present application also includes: setting a local variable for each core in the embedded multi-core system, wherein the value of the local variable is used to indicate whether the GPIO interrupt of the corresponding core has been handed over to other cores for processing. When it is decided to hand over the GPIO interrupt of a core to other cores for processing, the local variable of the core is updated. The update of the local variable can be ensured to be thread-safe through atomic operations or lock mechanisms. By setting local variables, the reallocation of interrupts can be effectively tracked and managed.

[0056] The inter-core GPIO interrupt coordination processing method provided in the embodiment of the present application is described in detail below through a specific embodiment.

[0057] like Figure 2 As shown, a global shared variable Ri (i=1, 2, ...) and a local variable Qi (i=1, 2, ...) are set for each core in a certain embedded multi-core system. Assuming that all cores are started, the global shared variable Ri and local variable Qi of each core are initialized, that is, Ri=0, Qi=0.

[0058] When it is determined that core 1 is busy with processing tasks based on the required processing tasks or based on the current value of the global shared variable, adjust the value of the global shared variable of core 1, and set R1 = x. Query the global shared variables of other cores, find core n with the smallest global shared variable value among all cores, and use it as the target core. The current value of the global shared variable of core n is Rn = y.

[0059] The GPIO interrupt that needs to be shared is shared with core n, and the value of the local variable of core 1 is adjusted to set Q1=1. At this time, core 1 is not disturbed by the interrupt; the shared GPIO interrupt is processed by core n, and core n feeds back the processing result to core 1; otherwise, core 1 continues to process the GPIO interrupt.

[0060] When core 1 passes the busy time, its local variable is reset to 0, that is, Q1=0, and the global shared variable R1 is reset to an appropriate value according to the busyness.

[0061] In the above step S300, the core with idle processing tasks is determined based on the global shared variables of other cores, specifically including: setting a GPIO interrupt shared register in the embedded multi-core system, routing to the corresponding interrupt controller according to the value of the GPIO interrupt shared register, and the interrupt controller determines the core that needs to be shared by the GPIO interrupt.

[0062] Specifically, routing to the corresponding interrupt controller according to the value of the GPIO interrupt shared register can be achieved through a routing circuit, which includes at least one AND circuit, the output end of the GPIO interrupt shared register and the GPIO pin are both connected to the input end of the AND circuit, the output end of the AND circuit is connected to the input end of the interrupt controller, and the output end of the interrupt controller is connected to each core.

[0063] The following uses chip E3640 as an example to specifically explain the process of determining the core that needs to be shared by the GPIO interrupt.

[0064] like Figure 3 As shown, the chip E3640 has five cores: SF, SP0, SP1, SX0 and SX1. Each core is equipped with a corresponding interrupt controller VIC. Among them, the interrupt controller of the SF core is VIC_Cluster0, the interrupt controller of the SP0 core is VIC_Cluster1_CORE0, the interrupt controller of the SP1 core is VIC_Cluster1_CORE1, the interrupt controller of the SX0 core is VIC_Cluster2_CORE0, and the interrupt controller of the SX1 core is VIC_Cluster2_CORE1. The chip E3640 can use up to 214 GPIO pins, including 135 GPIO pins in the SAF (Safety Software Framework) domain and 79 GPIO pins in the AP (Application Processor) domain. In the SAF domain and the AP domain, 32 pins are grouped together, using the same core and the control register in the core, and each pin uses 1 bit. All GPIO control registers support atomic read and write operations.

[0065] Each group of 32 GPIO pins triggers a state change, and the corresponding 32 GPIO interrupts share a common interrupt number. Assuming that the SF core's GPIO interrupt numbers are 5 to 9, the following table gives the interrupt names and their corresponding interrupt numbers.

[0066] Interrupt Name Interrupt number GPIO_SF_SYNC_GRP_0_INTR_NUM\GPIO_SF_ASYNC_GRP_0_INTR_NUM 5 GPIO_SF_SYNC_GRP_1_INTR_NUM\GPIO_SF_ASYNC_GRP_1_INTR_NUM 6 GPIO_SF_SYNC_GRP_2_INTR_NUM\GPIO_SF_ASYNC_GRP_2_INTR_NUM 7 GPIO_SF_SYNC_GRP_3_INTR_NUM\GPIO_SF_ASYNC_GRP_3_INTR_NUM 8 GPIO_SF_SYNC_GRP_4_INTR_NUM\GPIO_SF_ASYNC_GRP_4_INTR_NUM 9

[0067] Figure 3 It shows how GPIO interrupts triggered by state changes of 135 GPIO pins, namely GPIO0-31, GPIO32-63, GPIO64-95, GPIO96-127, and GPIO128-134 of the SAF domain are routed to different cores.

[0068] By default, all GPIO interrupts can only be detected by the SF core. The user calls the function sdrv_gpio_interrupt_share_with to set the interrupt sharing register GPIO_INT_SHAREk (0≤k≤134) corresponding to the GPIO interrupt to change which core the GPIO interrupt is routed to. The routing circuit set inside the chip routes the corresponding GPIO interrupt to the interrupt controller VIC of different cores according to the value of the interrupt sharing register, and then the interrupt controller VIC routes it to the corresponding core.

[0069] The interrupt number of each core in chip E3640 is represented by GPIO_SAFETY_IRQz (0≤z≤24). Specifically, the interrupt number of each core and its corresponding external interrupt number are:

[0070] The interrupt numbers of the SF core are GPIO_SAFETY_IRQ0 to GPIO_SAFETY_IRQ4, corresponding to external interrupt numbers 5 to 9 respectively.

[0071] The interrupt numbers of the SP0 core are GPIO_SAFETY_IRQ5 to GPIO_SAFETY_IRQ9, corresponding to external interrupt numbers 5 to 9 respectively.

[0072] The interrupt numbers of the SP1 core are GPIO_SAFETY_IRQ10 to GPIO_SAFETY_IRQ14, corresponding to external interrupt numbers 5 to 9 respectively.

[0073] The interrupt numbers of the SX0 core are GPIO_SAFETY_IRQ15 to GPIO_SAFETY_IRQ19, corresponding to external interrupt numbers 5 to 9 respectively.

[0074] The interrupt numbers of the SX1 core are GPIO_SAFETY_IRQ20 to GPIO_SAFETY_IRQ24, corresponding to external interrupt numbers 5 to 9 respectively.

[0075] For example, for a group of 32 pins of the SAF domain, an AND circuit is set respectively corresponding to the five cores SF, SP0, SP1, SX0 and SX1.

[0076] like Figure 4 As shown, the state changes of the 32 pins GPIO0~31 of the SAF domain trigger interrupts GPIO0~31, where the interrupt number is 5.

[0077] Interrupts GPIO0~31 and the output value 0x01 of the GPIO interrupt shared register are input into the corresponding AND circuit, and the AND circuit outputs the corresponding interrupt number GPIO_SAFETY_IRQ0. The interrupt controller VIC_Cluster0 determines that the core that the GPIO interrupt needs to share is the SF core according to the interrupt number GPIO_SAFETY_IRQ0.

[0078] Interrupts GPIO0~31 and the output value 0x02 of the GPIO interrupt shared register are input into the corresponding AND circuit, and the AND circuit outputs the corresponding interrupt number GPIO_SAFETY_IRQ10. The interrupt controller VIC_Cluster1_CORE0 determines that the core that the GPIO interrupt needs to share is the SP0 core according to the interrupt number GPIO_SAFETY_IRQ10.

[0079] Interrupts GPIO0~31 and the output value 0x04 of the GPIO interrupt shared register are input into the corresponding AND circuit, and the AND circuit outputs the corresponding interrupt number GPIO_SAFETY_IRQ15. The interrupt controller VIC_Cluster1_CORE1 determines that the core that the GPIO interrupt needs to share is the SP1 core according to the interrupt number GPIO_SAFETY_IRQ15.

[0080] Interrupts GPIO0~31 and the output value 0x08 of the GPIO interrupt shared register are input into the corresponding AND circuit, and the AND circuit outputs the corresponding interrupt number GPIO_SAFETY_IRQ20. The interrupt controller VIC_Cluster2_CORE0 determines that the core that the GPIO interrupt needs to share is the SX0 core according to the interrupt number GPIO_SAFETY_IRQ20.

[0081] Interrupts GPIO0~31 and the output value 0x10 of the GPIO interrupt shared register are input into the corresponding AND circuit, and the AND circuit outputs the corresponding interrupt number GPIO_SAFETY_IRQ25. The interrupt controller VIC_Cluster2_CORE1 determines that the core that the GPIO interrupt needs to share is the SX1 core according to the interrupt number GPIO_SAFETY_IRQ25.

[0082] The inter-core GPIO interrupt coordination processing method provided in the embodiment of the present application sets a global shared variable for each core to dynamically reflect its current busy or idle state, and when it is detected that a core may affect the response to the GPIO interrupt due to high load, it immediately queries the state of other cores and transfers the interrupt processing task to a relatively idle core for execution. The inter-core GPIO interrupt coordination processing method provided in the embodiment of the present application can not only avoid the interrupt delay or loss problem caused by the overload of a single core, but also promote the balanced distribution of workload among multiple cores and make full use of hardware resources. In addition, by setting a local variable for each core to indicate whether the GPIO interrupt of the corresponding core has been handed over to other cores for processing, it can prevent the task currently being processed by the core busy with processing tasks from being interrupted by the GPIO interrupt, ensure that key tasks are responded to in a timely manner, enhance the real-time performance and reliability of the system, and thus provide strong support for building efficient and stable embedded applications.

[0083] Based on the same inventive concept, the embodiment of the present application also provides an inter-core GPIO interrupt coordination processing device, which is applied to an embedded multi-core system, including:

[0084] The setting module is configured to set a global shared variable for each core in the embedded multi-core system, wherein the value of the global shared variable is used to indicate the busyness or idleness of the corresponding core.

[0085] The query module is configured to query the global shared variables of other cores when it is determined that a core processing task is busy according to the prediction of the required processing task or according to the value of the current global shared variable.

[0086] The determination module is configured to determine a core with idle processing tasks according to global shared variables of other cores, wherein the global shared variable value of the core with idle processing tasks is smaller than the global variable value of the core with busy processing tasks.

[0087] The coordination module is configured to transfer the GPIO interrupt of the core with busy processing tasks to the core with idle processing tasks.

[0088] An embedded multi-core system is a system that integrates multiple processing cores in a single chip or microprocessor. These cores can perform different tasks in parallel, thereby improving the overall performance and responsiveness of the system. An embedded multi-core system can be configured to run the same operating system or different operating systems, depending on the specific application requirements and technical architecture.

[0089] When multiple cores run the same operating system, that is, in the SMP (Symmetric Multi-Processing) working mode, all cores share the same memory space, which can be used to store global shared variables set for each core. Each core can directly read and write this memory space through address mapping. In the SMP working mode, the operating system can dynamically assign tasks to any available core.

[0090] In the AMP (Asymmetric Multi-Processing) working mode, although the memory space between each core is usually isolated, each core can still access the same physical RAM in hardware. Data exchange can be achieved by defining a specific physical memory area as a shared area and ensuring that each core can be mapped to this memory in some way. In addition, part of the physical memory can be configured as I / O memory, so that even if the operating system does not support cross-core memory sharing, this memory can be read and written through I / O operations. In addition, when the cores cannot directly share memory in the AMP working mode, information exchange can be indirectly achieved by establishing a message passing mechanism. For example, use shared hardware registers, mailboxes, or other forms of communication queues for data transmission.

[0091] In the embodiment of the present application, the busyness of the core can be reflected by one or more of the CPU utilization, the task queue length and the interrupt frequency. Specifically, the CPU occupancy rate within the preset time can be calculated, and the occupancy rate can be used to reflect the busyness of the core; the number of tasks waiting to be processed within the preset time can also be counted, and the more tasks, the busier the core; the number of interrupts processed per unit time can also be recorded, and the more interrupts, the busier the core.

[0092] Exemplarily, the value of the global shared variable can be set to 0, 1, 2 and 3 respectively to indicate the busyness or idleness of the corresponding core. For example, 0 means completely idle; 1 means busy but with spare capacity; 2 means busy but with insufficient spare capacity; 3 means heavily loaded and with no time to take care of other things, etc.

[0093] In the embodiment of the present application, it is possible to predict whether the corresponding core will enter a busy state next according to the nature of the task to be processed and the expected execution time, and if so, query other cores. Of course, it is also possible to judge whether the corresponding core is currently in a busy state according to the value of the current global shared variable, and if so, query other cores. The determination of the busy state can be compared and determined by a preset busy threshold.

[0094] When querying the global shared variables of other cores, you can use polling query mode, that is, traverse the global shared variables of all cores to find the idlest core; you can also use broadcast query mode to send query requests to all cores, and determine the idlest core after obtaining the request results.

[0095] In an embodiment of the present application, the minimum value method can be used to select the core with the smallest global shared variable value as the target core to be determined; the threshold method can also be used to select the core with a value below a preset threshold and the smallest global shared variable value as the target core to be determined. The threshold method can be used to avoid assigning tasks to cores that are already close to full load.

[0096] In an embodiment of the present application, an interrupt controller is configured and an interrupt redirection mechanism is used to hand over the GPIO interrupt of a core that is busy with processing tasks to a core that is idle with processing tasks.

[0097] Based on the same concept, the embodiment of the present application also provides an electronic device, such as Figure 5 As shown, it includes a processor and a memory, wherein an executable program is stored in the memory, and the processor executes the executable program to perform the steps of the method as described above.

[0098] An embodiment of the present application further provides a storage medium, wherein the storage medium carries one or more computer programs, and when the one or more computer programs are executed by a processor, the steps of the above method are implemented.

[0099] An embodiment of the present application further provides a chip, comprising the inter-core GPIO interrupt coordination processing device as described above, wherein the inter-core GPIO interrupt coordination processing device is used to coordinate and control GPIO interrupts between cores in an embedded multi-core system.

[0100] The storage medium in this embodiment may be included in the electronic device / system; or it may exist independently without being assembled into the electronic device / system. The above storage medium carries one or more programs, and when the above one or more programs are executed, the method according to the embodiment of the present application is implemented.

[0101] An embodiment of the present application also provides a vehicle, comprising a processing unit, which is capable of executing the steps of the method described in the above embodiment.

[0102] The vehicle in the embodiments of the present application may be "car", "vehicle" and "entire vehicle" or other similar terms including general motor vehicles, such as sedans, SUVs, MPVs, buses, trucks and other cargo or passenger vehicles, watercraft including various ships and boats, and aircraft, etc., including hybrid vehicles, electric vehicles, fuel vehicles, plug-in hybrid vehicles, fuel cell vehicles and other alternative fuel vehicles. Among them, hybrid vehicles refer to vehicles with two or more power sources, and electric vehicles include pure electric vehicles, extended-range electric vehicles, etc., which are not specifically limited in the present application.

[0103] It should be understood that in the embodiments of the present application, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.

[0104] It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct memory bus random access memory (Direct Rambus RAM, DR RAM).

[0105] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, the memory (storage module) is integrated in the processor.

[0106] It should be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0107] It should also be understood that the first, second, third, fourth and various numerical numbers involved in this document are only distinctions made for the convenience of description and are not intended to limit the scope of the present application.

[0108] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0109] In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or an instruction in the form of software. The steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in a processor for execution. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0110] In various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0111] Those skilled in the art will appreciate that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0112] In the several embodiments provided in the present application, it should be understood that the disclosed inter-core GPIO interrupt coordination processing method, electronic device and storage medium can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units (or modules) is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0113] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0114] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0115] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integration. The available medium can be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk), etc.

[0116] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for coordinating and processing inter-core GPIO interrupts, characterized in that: Applications in embedded multi-core systems, including: A global shared variable is set for each core in the embedded multi-core system, wherein the value of the global shared variable is used to indicate the busyness or idleness of the corresponding core; When a core is busy processing tasks, query the global shared variables of other cores; Determine a core with idle processing tasks according to the global shared variables of other cores, wherein the value of the global shared variable of the core with idle processing tasks is smaller than the value of the global variable of the core with busy processing tasks; The GPIO interrupt of the core with busy processing tasks is handed over to the core with idle processing tasks.

2. The method according to claim 1, characterized in that: After setting a global shared variable for each core in the embedded multi-core system, the method further includes: initializing each of the global shared variables.

3. The method according to claim 1, characterized in that The method further includes: after predicting that a core is busy with a processing task according to the required processing tasks, adjusting the value of the global shared variable corresponding to the core according to the busyness.

4. The method according to claim 1, characterized in that: The method further includes: after handing over the GPIO interrupt of the core with busy processing tasks to the core with idle processing tasks for processing, feeding back the processing result of the core with idle processing tasks to the core with busy processing tasks.

5. The method according to claim 4, characterized in that The processing result of the core with idle processing tasks is fed back to the core with busy processing tasks through a shared variable or a mailbox.

6. The method according to claim 4, characterized in that When the core busy with processing tasks completes processing the current task and the busyness changes, the current value of the global shared variable corresponding to the core busy with processing tasks is adjusted.

7. The method according to claim 1, characterized in that The method further comprises: setting a local variable for each core in the embedded multi-core system, wherein the value of the local variable is used to indicate whether the GPIO interrupt of the corresponding core has been handed over to other cores for processing.

8. The method according to claim 1, characterized in that: The step of determining a core with idle processing tasks according to the global shared variables of other cores specifically includes: The value of the GPIO interrupt sharing register set in the embedded multi-core system is routed to the corresponding interrupt controller, and the interrupt controller determines the core that the GPIO interrupt needs to share.

9. The method according to claim 8, characterized in that The routing to the corresponding interrupt controller according to the value of the GPIO interrupt shared register is implemented through a routing circuit, and the routing circuit includes at least one AND circuit, the output end and the GPIO pin of the GPIO interrupt shared register are both connected to the input end of the AND circuit, the output end of the AND circuit is connected to the input end of the interrupt controller, and the output end of the interrupt controller is connected to each of the cores.

10. An electronic device, characterized in that: The method comprises a processor and a memory, wherein an executable program is stored in the memory, and the processor executes the executable program to perform the steps of the method according to any one of claims 1 to 9.

11. A storage medium, characterized in that: The storage medium carries one or more computer programs, and when the one or more computer programs are executed by the processor, the steps of the method according to any one of claims 1 to 9 are implemented.

12. A chip, characterized in that: An embedded multi-core architecture is adopted, and the embedded multi-core architecture adopts the method according to any one of claims 1 to 9 to coordinate and control GPIO interrupts between cores in the embedded multi-core architecture.

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