Memory management method and device, electronic equipment and medium

Abstract

The invention relates to a memory management method and device, electronic equipment and a medium. The method comprises the following steps: creating a thread buffer area for a target application and a global buffer area for managing the thread buffer area; a to-be-run thread in the target application has a corresponding relationship with the thread buffer area; before the main function of the target application is executed, the global buffer area is initialized; performing memory allocation on each thread buffer area according to a predefined storage space in the initialization process of the global buffer area; wherein the predefined storage space of each thread buffer area is obtained by defining space information required by running of the to-be-run thread; and during the execution of the main function of the target application, the running thread is positioned to the corresponding target thread buffer area by accessing the global buffer area, and a target space matched with the actual running state is applied from the target thread buffer area. The distribution efficiency of multi-thread access memory is improved, the waste of memory space can be reduced, and the memory utilization rate is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of memory allocation, and in particular to a method, device, electronic device and medium for memory management. Background Art

[0002] Dynamic memory management is the dynamic allocation and release of memory according to the needs of the program when it is running. It can flexibly handle data or resources of uncertain size, such as user input, file data or network resources. Generally, memory is requested or released through memory management functions (such as malloc, free, calloc, realloc, reallocarray and other memory management functions in the C language function library libc / glibc).

[0003] With the increase of system complexity and application threads, the use of dynamic memory has become very frequent, and the number and size of memory applications have also increased. In the related art, some solutions use a memory pool to improve memory allocation efficiency, specifically by applying for a piece of memory space as a memory pool, and first allocate memory from the memory pool when a thread applies for memory. Since memory allocation must meet alignment conditions, such as the memory address must be a multiple of 2 to the power of N (N is a positive integer), such as 4, 8 or 16, this will lead to more memory fragments, and the memory space corresponding to the application of the memory pool is generally at the system level, and the size of the memory space application is generally large, resulting in some memory blocks may be idle, thereby causing a waste of memory space. In addition, the memory pool is usually provided with a mutual exclusion lock (such as mutex), and multi-threaded access to the memory pool requires mutual exclusive access, wherein only a single thread can exclusively access the memory pool at the same time, and can only access it after waiting for the thread to release the memory pool, thereby causing the waiting time of the thread, resulting in the slow processing time of the application program, so there are still problems such as poor parallel processing capability and low memory allocation time efficiency in high concurrency scenarios. Summary of the invention

[0004] In order to overcome the problems existing in the related art, the present disclosure provides a memory management method, device, electronic device and medium.

[0005] According to a first aspect of an embodiment of the present disclosure, a method for memory management is provided, comprising: creating a thread buffer for a target application and a global buffer for managing the thread buffer; wherein the to-be-run thread in the target application has a corresponding relationship with the thread buffer; before the main function of the target application is executed, the global buffer is initialized; and during the initialization of the global buffer, memory is allocated to each thread buffer according to a predefined storage space; wherein the predefined storage space of each thread buffer is defined based on the space information required for the to-be-run thread to run; during the execution of the main function of the target application, the running thread locates the corresponding target thread buffer by accessing the global buffer, and applies for a target space matching the actual running state from the target thread buffer.

[0006] In some embodiments, the predefined storage space of each thread buffer includes a preset number of memory blocks, each memory block has a corresponding preset space size and the predefined storage space has a variety of different size specifications; the header file information of the thread buffer includes marking information for marking the usage status of the load cache area in each memory block. Wherein, the above-mentioned application of the target space matching the actual running state from the target thread buffer includes: the above-mentioned running thread determines the memory to be applied according to the actual running state; according to the marking information in the header file information of the target thread buffer, searches for the candidate memory block in the current unoccupied state; determines the available space size of the candidate memory block; compares the available space size of the memory to be applied with the available space size of the candidate memory block, and determines the candidate memory block with the smallest size specification in the first available space size whose size is larger than the corresponding size of the memory to be applied as the target memory block to be applied; locates the target memory block according to the header file information of the thread buffer; determines the allocated load cache area for the memory to be applied in the target memory block, and sets the allocated load cache area to the occupied state; wherein the storage space corresponding to the allocated load cache area in the occupied state is used as the target space.

[0007] In some embodiments, each memory block contains multiple load cache areas, and the load cache areas are dynamically applied and released by threads. The marking information includes: usage status bitmap information of multiple load cache areas in each memory block; or positioning offset information of the first load cache area in the current unoccupied state in each memory block; wherein the positioning offset information indicates the first target offset of the first load cache area from the memory block header file of the memory block where it is located.

[0008] Among them, according to the marking information in the header file information of the above-mentioned target thread buffer, searching for candidate memory blocks in the currently unoccupied state includes: according to the usage status bitmap information or positioning offset information of each memory block, determining the memory block with an idle load cache area as the candidate memory block in the currently unoccupied state.

[0009] The step of determining the available space size of the candidate memory block includes:

[0010] According to the usage status bitmap information of the candidate memory block, determine one or more first load cache areas in the candidate memory block that are currently unoccupied; locate the one or more first load cache areas; obtain the available space size corresponding to the one or more first load cache areas; or,

[0011] According to the positioning offset information, one or more first load cache areas that are currently unoccupied are located; and available space sizes corresponding to the one or more first load cache areas are obtained.

[0012] Among them, determining the allocated load cache area for the above-mentioned memory to be applied in the above-mentioned target memory block includes: in the above-mentioned target memory block, determining the first load cache area that is exactly matched with the above-mentioned memory to be applied or based on a preset approximate interval as the allocated load cache area.

[0013] In some embodiments, the index positioning information contained in each load cache area includes: the first offset of the current load cache area from the memory block header file. Wherein, the above positioning to the above one or more first load cache areas includes: positioning to the corresponding first load cache area according to the first offset corresponding to the one or more first load cache areas.

[0014] In some embodiments, the index positioning information contained in each load cache area includes: a second offset corresponding to the load memory space contained in the current load cache area; wherein the second offset is used to locate the load memory space allocated for storing data in the current load cache area. Wherein, setting the allocated load cache area to an occupied state includes: locating a target load memory space as a target space according to the second offset of the allocated load cache area, and setting the target load memory space to an occupied state, and deeming the allocated load cache area to be in an occupied state.

[0015] In some embodiments, the global buffer stores a mapping relationship between each thread and the thread cache index identifier of the corresponding thread buffer. The index positioning information contained in each load cache area includes: the thread cache index identifier of the thread buffer corresponding to the current load cache area; or, the header file information of the thread buffer includes: the thread cache index identifier corresponding to the current thread buffer. Wherein, during the execution of the main function of the target application, the running thread locates the corresponding target thread buffer by accessing the global buffer, including: during the execution of the main function of the target application, the running thread obtains the target thread cache index identifier corresponding to the target thread buffer indicated by the mapping relationship by accessing the global buffer; based on the target thread cache index identifier, the running thread locates the corresponding target thread buffer by matching in the header file information of the thread buffer or matching in the index positioning information contained in the load cache area.

[0016] In some embodiments, the header file information of the thread buffer includes: a memory block index. Locating the target memory block according to the header file information of the thread buffer includes: obtaining a target memory block index for pointing to the target memory block from the header file information of the thread buffer; and locating the target memory block based on the target memory block index.

[0017] In some embodiments, the method further includes: when an index mismatch or memory address error occurs during the use of the first target space by the first running thread, the first running thread or the second running thread calls a library function to release the first target space corresponding to the first target thread buffer. The first running thread and the second running thread are different threads; in the process of releasing the first target space, the first running thread or the second running thread updates the use status of the first target space to an unoccupied state based on the thread cache index identifier corresponding to the first target thread buffer and the index information in the memory block structure contained in the first target thread buffer.

[0018] In some embodiments, the method further includes: when the target space cannot be applied for from the target thread buffer, calling a memory management function to apply for a target space matching the actual running state.

[0019] According to the second aspect of the embodiment of the present disclosure, a memory management device is provided. The above-mentioned device includes: a creation module, an initialization module and a local memory management module. The above-mentioned creation module is used to create a thread buffer for a target application and a global buffer for managing the above-mentioned thread buffer; wherein the thread to be run in the above-mentioned target application has a corresponding relationship with the above-mentioned thread buffer. The above-mentioned initialization module is used to initialize the above-mentioned global buffer before the main function of the above-mentioned target application is executed; and during the initialization process of the above-mentioned global buffer, memory is allocated to each thread buffer according to a predefined storage space; wherein the predefined storage space of each thread buffer is defined based on the space information required for the operation of the thread to be run. The above-mentioned local memory management module is used for, during the execution of the main function of the above-mentioned target application, the running thread locates the corresponding target thread buffer by accessing the above-mentioned global buffer, and applies for a target space matching the actual running state from the above-mentioned target thread buffer.

[0020] According to a third aspect of an embodiment of the present disclosure, an electronic device is provided, comprising: a processor; a memory for storing executable instructions of the processor; the processor is used to read the executable instructions from the memory and execute the instructions to implement the memory management method provided by the first aspect of the present disclosure.

[0021] According to a fourth aspect of an embodiment of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored. When the program instructions are executed by a processor, the steps of the memory management method provided in the first aspect of the present disclosure are implemented.

[0022] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:

[0023] By creating a thread buffer corresponding to the target application's to-be-running thread, since the to-be-running threads access the corresponding thread buffers independently and do not interfere with each other, there is no need to lock, thereby improving the efficiency of multi-threaded memory access allocation. At the same time, by creating a global buffer for managing thread buffers, and allocating memory to each thread buffer according to the predefined storage space during the initialization of the global buffer, the storage space allocated to each thread buffer matches the running space information required by each corresponding to-be-running thread, thereby realizing customized memory allocation; on the one hand, based on the setting of the global buffer, it can ensure that the running thread can quickly locate the corresponding target thread buffer and apply for the corresponding target space during the actual operation, and the indexing is efficient and fast; on the other hand, since the thread buffer is a customized memory allocation, the memory specifications and quantity that can be allocated in the thread buffer are adapted to the needs of the to-be-running thread, so that in the process of applying for the target space, memory fragmentation can be reduced, and a relatively accurate match with the required memory can be achieved, thereby reducing the waste of memory space and improving memory utilization.

[0024] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0026] Figure 1 The figure is a flowchart of a memory management method according to an exemplary embodiment.

[0027] Figure 2 The present invention is a schematic diagram showing an implementation process of a memory management method according to an exemplary embodiment.

[0028] Figure 3 is a schematic diagram of the structure of a global buffer according to an exemplary embodiment.

[0029] Figure 4 The diagram is a schematic diagram of the composition of a thread buffer according to an exemplary embodiment, wherein (a) is a schematic diagram of the structure of a thread buffer, (b) is a schematic diagram of the structure of a memory block, and (c) is a schematic diagram of the structure of a load cache area.

[0030] Figure 5 The figure is a schematic diagram showing a process of a running thread applying for a target space according to an exemplary embodiment.

[0031] Figure 6 The figure is a schematic diagram of a process of customizing memory allocation for a thread buffer in a development phase according to an exemplary embodiment.

[0032] Figure 7 The present invention is a block diagram of a memory management device according to an exemplary embodiment.

[0033] Figure 8 It is a block diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0034] Exemplary embodiments will be described in detail below with reference to the accompanying drawings.

[0035] It should be pointed out that the relevant embodiments and drawings are only for describing exemplary embodiments provided by the present disclosure, rather than all embodiments of the present disclosure, and it should not be understood that the present disclosure is limited to the relevant exemplary embodiments.

[0036] It should be noted that the terms "first", "second", etc. used in the present disclosure are only used to distinguish different steps, devices or modules, etc. The related terms neither represent any specific technical meanings nor indicate the order or interdependence between them.

[0037] It should be noted that the modifications of the terms "one", "multiple", and "at least one" used in the present disclosure are illustrative rather than restrictive. Unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0038] It should be noted that the term "and / or" used in this disclosure is used to describe the association relationship between associated objects, and generally indicates that there are at least three association relationships. For example, A and / or B can at least indicate the existence of three association relationships: A exists alone, A and B exist at the same time, and B exists alone.

[0039] It should be noted that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. Unless otherwise specified, the scope of the present disclosure is not limited by the order of description of the steps in the relevant embodiments.

[0040] It should be noted that all actions of acquiring signals, information or data in the present disclosure are carried out in compliance with the relevant data protection laws and policies of the country where the device is located and with the authorization given by the owner of the corresponding device.

[0041] Exemplary Methods

[0042] Figure 1 The figure is a flowchart of a memory management method according to an exemplary embodiment. Figure 2 The present invention is a schematic diagram showing an implementation process of a memory management method according to an exemplary embodiment.

[0043] Reference Figure 1 and Figure 2 As shown, the memory management method provided in the embodiment of the present disclosure is used in an electronic device installed with an application, and the method includes the following steps: S110, S120 and S130. The above electronic device can be various terminal devices or servers, and the terminal devices include but are not limited to: smart phones, smart watches, smart bracelets, smart home devices, mobile robots, wearable devices, vehicle terminals, etc. The method provided in the embodiment of the present disclosure is a general method that can be adapted to various operating systems, and the operating systems include but are not limited to: Linux system, Windows, ios, macos, Android system, Hongmeng system, etc. The specific development language can be but is not limited to C, C++, etc.

[0044] In step S110, a thread buffer for the target application and a global buffer for managing the thread buffer are created; wherein the threads to be run in the target application correspond to the thread buffer.

[0045] The target application refers to one or more applications in the electronic device that have memory application requirements. The target application needs to dynamically apply for and release memory during operation in the electronic device. The target application can be various applications, such as but not limited to: smart driving applications, shopping applications, instant messaging applications, video playback applications, etc.

[0046] The to-be-running threads in the above-mentioned target application refer to one or more sub-threads used to complete various tasks created after a task process of the target application is started and the main function (main() function, corresponding to the main thread) of the target application is loaded and executed, such as but not limited to: data acquisition sub-thread, data calculation sub-thread, data analysis sub-thread, graphics processing sub-thread, method or service call sub-thread, timing sub-thread, counting sub-thread, etc.

[0047] Since step S110 is the process of creating and predefining thread buffers and global buffers in the development phase, the threads in the target application are described as waiting-to-run threads. These waiting-to-run threads will present a running state according to the startup situation in the actual running phase, so they are described as running threads in the running phase.

[0048] In an embodiment of the present disclosure, a thread buffer corresponding to the to-be-running thread of the target application is created in an electronic device. Since the to-be-running threads access the corresponding thread buffer independently and do not interfere with each other, there is no need to lock it, thereby avoiding the multi-thread access waiting time caused by the locking mechanism in the traditional memory pool-based memory allocation management scheme, and can effectively improve the allocation efficiency of multi-thread access to memory and the multi-thread parallel processing performance.

[0049] In the embodiment of the present disclosure, the to-be-run threads in the target application and the thread buffer have a corresponding relationship.

[0050] In the above correspondence, a thread to be run can correspond to one or more thread buffers (ThreadCache), and the predefined storage space of each thread buffer includes a preset number of memory blocks, each memory block has a corresponding preset space size, and the above predefined storage space has a variety of different size specifications. In some embodiments, some thread buffers have only one size specification, or some thread buffers can have multiple size specifications. In some embodiments, there is a situation where a thread buffer corresponds to only one thread; there may also be a situation where a thread buffer corresponds to multiple different threads at the same time, and these different threads correspond to specific memory blocks of the thread buffer respectively, and different threads occupy the corresponding memory blocks in sequence according to the memory application order or allocate the corresponding memory blocks when applying at the same time, and there will be no memory interference between each other; therefore, there is no need to adopt a lock mechanism to dynamically allocate and manage memory based on the thread buffers corresponding to each thread.

[0051] As an example, the target application includes three threads to be run, namely thread a, thread b and thread c. The memory space required for thread a to run is: M1 (for example, 32 bytes); the memory space required for thread b in the two processing stages during operation is: M2 (for example, 30 bytes) and M3 (for example, 256 bytes); the memory space required for thread c during operation is M4 (for example, 251 bytes) and M5 (for example, 1024 bytes).

[0052] As an example in which a to-be-run thread corresponds to a thread buffer, three thread buffers are created for the above threads a to c. Thread a corresponds to thread buffer A1, thread b corresponds to thread buffer B1, and thread c corresponds to thread buffer C1.

[0053] The size of the thread buffer A1 is 32 Byte, which is customized based on the memory space M1 required for the thread a to run.

[0054] Thread b corresponds to thread buffer B1. The thread buffer B1 has two sizes, 32 Byte and 256 Byte. These two sizes are customized according to the memory spaces M2 and M3 required during the running of thread b.

[0055] Thread c corresponds to thread buffer C1. The thread buffer C1 has two sizes, 256 Byte and 1024 Byte. These two sizes are customized according to the memory spaces M4 and M5 required during the running of thread c.

[0056] As an example that a to-be-run thread may correspond to multiple thread buffers, two thread buffers are created for the above threads a to c, thread a corresponds to thread buffer A2, thread b corresponds to thread buffers A2 and B2, and thread c corresponds to thread buffer B2.

[0057] Among them, thread buffer A2 contains two memory blocks: memory block A21 and memory block A22. The size specifications of these two memory blocks are both 32 bytes, which are customized according to the memory space M1 required for the operation of thread a and the memory space M2 required for the operation of thread b. Thread buffer B2 contains three memory blocks, namely memory blocks B21, B22 and B23. The size specification of memory block B21 is 256 bytes, which is customized according to the memory space M3 required for the operation of thread b; the size specification of memory block B22 is 256 bytes, which is customized according to the memory space M4 required for the operation of thread c; the size specification of memory block B23 is 1024 bytes, which is customized according to the memory space M5 required for the operation of thread c. The detailed corresponding relationship is: thread a—memory block A21 of thread buffer A2, thread b—memory block A22 of thread buffer A2 + memory block B21 of thread buffer B2, thread c—memory block B22 and memory block B23 of thread buffer B2.

[0058] In some embodiments, when the thread buffer corresponds to the thread, the memory block corresponding to the thread can be pre-specified, that is, the correspondence between the memory block and the thread is predetermined, and when the memory is dynamically applied for during the thread operation, the corresponding memory allocation can be performed according to the predetermined correspondence between the memory block and the thread. In this case, for multiple threads corresponding to different memory blocks in the same thread buffer, different threads can occupy the corresponding memory blocks in sequence according to the memory application order or allocate the corresponding memory blocks when applying at the same time, and there will be no memory interference between each other. Therefore, there is no need to use a lock mechanism to dynamically allocate and manage memory based on the thread buffer corresponding to each thread.

[0059] Alternatively, the memory blocks corresponding to the threads may not be specified in advance, but the correspondence between the threads and the memory blocks may be randomly assigned during the application process. In the case of such random assignment, if multiple threads correspond to different memory blocks in the same thread buffer and the correspondence is uncertain, different threads may occupy the randomly assigned memory blocks in sequence according to the memory application order, and the occupation and allocation processes of different memory blocks according to the timing differences will not cause memory interference. If different threads apply for different memory blocks in the same thread buffer at the same time, the corresponding memory blocks will be allocated to each thread and occupied in a random manner, and memory interference will not occur.

[0060] Therefore, regardless of whether the correspondence between threads and memory blocks is pre-specified or not, based on the solution provided in the embodiments of the present disclosure, after the corresponding thread buffer is created for the thread to be run, when the thread actually runs and applies for memory, there is no need to use a lock mechanism to dynamically allocate and manage memory based on the thread buffer corresponding to each thread.

[0061] Figure 3 is a schematic diagram of the structure of a global buffer according to an exemplary embodiment. Figure 4 The diagram is a schematic diagram of the composition of a thread buffer according to an exemplary embodiment, wherein (a) is a schematic diagram of the structure of a thread buffer, (b) is a schematic diagram of the structure of a memory block, and (c) is a schematic diagram of the structure of a load cache area. Figure 6 The figure is a schematic diagram of a process of customizing memory allocation for a thread buffer in a development phase according to an exemplary embodiment.

[0062] Reference Figure 3 and Figure 6 As shown, the global buffer is used to manage the thread buffer. The global buffer contains storage structures corresponding to the multiple threads it manages. For example, the storage structures corresponding to threads 1 to thread n are respectively illustrated. The storage structures corresponding to these threads 1 to n may include: a pointer to the corresponding thread buffer (for example, a thread cache index identifier (Thread Cache Index) of the thread buffer). The storage space occupied by the global buffer is of a fixed size, and the number n of all threads contained in the global buffer is the length of the global buffer. The global buffer is created and initialized before the main function (main function). For example, taking C language as an example, during the development stage, the keyword _attribute_(constructor) (indicating an extension) can be used to construct a function object for creating and initializing the global buffer, so that the function object modified by the above keyword is automatically called by the program loader before the main function. Refer to Figure 6As shown, at the entry of the main function of the main thread, an index can be created based on the index creation function (pthread_key_create) (for example, including an index ID in the global buffer used to point to each thread buffer), and the thread buffer can also be released based on the callback function. In order to allow each thread to dynamically apply for and release memory during operation, the following execution logic can be constructed at the entry of each sub-thread function body during the development phase: obtain the index ID of the thread buffer corresponding to the thread in the global buffer, and then obtain the corresponding thread buffer, and perform customized memory allocation for the corresponding thread buffer; wherein the customized memory allocation mainly includes: setting the memory block size (specifically, the memory block size can be defined according to the space required for thread operation), setting tag information for indicating the memory block usage status, defining a preset approximate interval value for fuzzy matching, etc. This customized memory allocation is a process in the development phase, which can be understood by referring to the subsequent step S120. In addition, refer to Figure 6 As shown, the method disclosed in the present invention also supports customization of dynamic memory application functions or release functions during the development stage. Based on the execution logic of the above functions, the corresponding thread buffer can be matched during the thread running (in Figure 6 The diagram shows obtaining the corresponding thread buffer) and applying for the corresponding target space. It also supports operations such as adding, modifying, and checking the current thread buffer, such as adding new size specifications or numbers of memory blocks, or adding new load cache areas to existing memory blocks, or real-time adjustment or query of usage status information of existing load cache areas.

[0063] In some embodiments, the global buffer uses linear storage space to facilitate retrieval and achieve time complexity O(1) (indicates constant time complexity, the algorithm execution time does not increase with the increase of input size, regardless of the size of the input data, the algorithm execution time is a constant). For example, the linear storage structure can be but is not limited to: array, linked list, stack, queue, etc. Linear storage is divided into sequential storage (such as array) and linked storage (such as linked list).

[0064] Reference Figure 4 As shown in (a), in some embodiments, the predefined storage space of each thread buffer includes a preset number of memory blocks (Slot Buffer), each memory block has a corresponding preset space size, and the predefined storage space of multiple thread buffers has a variety of different size specifications. Figure 4 In (a), a thread buffer containing memory blocks of various sizes is used as an example. The sizes (units may be various units of memory allocation, such as bytes) are 128, 256, 512, 1024, etc. Multiple load cache areas within a memory block may have the same size.

[0065] The existence of multiple different sizes of predefined storage spaces of multiple thread buffers includes the following situations: one or more thread buffers have multiple different sizes, or the size of one or some thread buffers is different from the size of other thread buffers; the above situation can be understood by referring to the above examples about threads a to c and corresponding thread buffers. Among them, there may be a situation where a thread buffer has only one size.

[0066] In some embodiments, each memory block includes multiple payload buffer areas (Payload Buffer), and the payload buffer areas are dynamically allocated and released by threads.

[0067] Reference Figure 4 As shown in (b), each memory block (Slot Buffer) includes a memory block header file (Slot Header) and at least one load buffer area (Payload Buffer). In some embodiments, the memory block header file carries the following information: a memory block index, which is used to indicate the identification of different memory blocks. In some embodiments, the memory block header file may also carry: information corresponding to the size specification of the memory block.

[0068] Reference Figure 4 As shown in (c), each payload buffer area (Payload Buffer) includes: a first offset (Slot Header Offset, as index positioning information) of the current payload buffer area from the memory block header file, a second offset (Payload Offset, as index positioning information) corresponding to the payload memory space contained in the current payload buffer area, and a thread cache index identifier (Thread Cache Index) of the corresponding thread buffer. The second offset is used to locate the payload memory space (Payload) allocated for storing data in the current payload buffer area.

[0069] In some embodiments, reference Figure 4 The dotted line indicates the situation: the memory block header file also carries the following information: the thread cache index identifier of the corresponding thread buffer. Correspondingly, the load cache area may not carry the thread cache index identifier. It is sufficient to carry the thread cache index identifier (ThreadCache Index) in one of the memory block header file or the load cache area.

[0070] In some embodiments, the thread buffer is implemented by linear storage space + dynamic application of continuous storage space. The dynamic application of continuous storage space is actually for the dynamic application of memory for the thread, and is located in the heap storage area of ​​the process memory. The use of linear storage space can facilitate retrieval and achieve a time complexity of O(log2N) (indicates base 2, N represents the critical value of jumping out of the loop). The process of dynamically applying for continuous storage space is to customize the memory block size according to the needs of thread operation, specifically the size of the customized load memory space (Payload), such as size specifications (Malloc size) and quantity.

[0071] In some embodiments, the header file information of the thread buffer includes: marking information for marking the usage status of each memory block. For example, this marking information is the usage status bitmap information of the memory block, and the usage status corresponding to a memory block is represented by 0 or 1, 1 indicates that the corresponding memory block is used, and 0 indicates that the corresponding memory block is not used.

[0072] In the above embodiment, there is a corresponding relationship between threads and memory blocks (which can be pre-set in the development stage or randomly allocated in the thread running stage), and the number of load cache areas included in the memory block can be set according to the needs of the corresponding thread.

[0073] In other embodiments, the correspondence between threads and memory blocks is based on the correspondence between threads and smaller internal units - load cache areas. As another example, for the above-mentioned threads a to c, the load cache areas under different memory blocks of the thread buffer A3 correspond. The thread buffer A3 contains three memory blocks: memory block A31, memory block A32 and memory block A33. The size of memory block A31 is 32Byte, including two load cache areas A311 and A312. This size is customized based on the memory space M1 required for the operation of thread a and the memory space M2 required for the operation of thread b. The size of memory block A32 is 256Byte, including two load cache areas A321 and A322. This size is determined based on the memory space M3 required for the operation of thread b and the memory space M4 required for the operation of thread c. Memory block A33 contains a load cache area A331 with a size of 1024Byte, which is determined based on the memory space M5 required for the operation of thread c. The detailed corresponding relationship is: thread a—load cache area A311 of memory block A31 of thread buffer A3 (as an example, the actual corresponding situation can be adjusted, and other corresponding relationships are understood by reference), thread b—load cache area A312 of memory block A31 of thread buffer A3 + load cache area A321 of memory block A32, thread c—load cache area A322 of memory block A32 of thread buffer A3 + load cache area A331 of memory block A33.

[0074] In this case, the marking information may specifically be the usage information of the load cache area in each memory block. Alternatively, the marking information may also be the positioning offset information (not occupied slot's Slot Header offset) of the first load cache area in the current unoccupied state in each memory block; wherein the positioning offset information indicates the first target offset of the first load cache area in the current unoccupied state from the memory block header file of the memory block in which it is located.

[0075] In step S120, before the main function of the target application is executed, the global buffer is initialized; and during the initialization of the global buffer, memory is allocated to each thread buffer according to the predefined storage space; wherein the predefined storage space of each thread buffer is defined based on the space information required for the execution of the thread to be executed.

[0076] The size and amount of memory dynamically requested by each thread during operation can be known or evaluated in advance by developers through a variety of ways. Therefore, the predefined storage space of the corresponding thread buffer is defined in advance based on the space information required for the running thread to be run. This can realize the local memory storage management of the thread, that is, when each thread applies for memory space, it applies to the customized thread buffer corresponding to the thread. Since customized memory allocation is performed for the thread buffer area during the development phase, the corresponding thread buffer will not be full or insufficient when the thread actually runs and applies for memory, and it is highly likely that there is no need to execute the logic of additional memory application by calling memory management library functions such as malloc / realloc (for example, memory management library functions). This helps to reduce frequent calls to library functions such as malloc / realloc.

[0077] By creating a global buffer for managing thread buffers, and allocating memory to each thread buffer according to the predefined storage space during the initialization of the global buffer, the storage space allocated to each thread buffer matches the running space information required by each corresponding thread to be run, thereby realizing customized memory allocation.

[0078] In step S130, during the execution of the main function of the target application, the running thread locates the corresponding target thread buffer by accessing the global buffer, and applies for a target space matching the actual running state from the target thread buffer.

[0079] Figure 5 The figure is a schematic diagram showing a process of a running thread applying for a target space according to an exemplary embodiment.

[0080] In some embodiments, the global buffer stores thread cache index identifiers of each thread and the corresponding thread buffer (in Figure 5 The simplified diagram is shown as the mapping relationship between thread buffer indices).

[0081] Reference Figure 4 As shown in (c), the index positioning information contained in each load cache area includes: the thread cache index identifier of the thread buffer corresponding to the current load cache area. Figure 4 As shown by the dotted line in (c), the header file information of the thread buffer (eg, the memory block index included in the memory block header file) includes: a thread cache index identifier of the corresponding current thread buffer.

[0082] In some cases, if the thread buffer corresponding to a certain thread is insufficient, it is likely that a suitable memory block has not been temporarily allocated or a suitable load cache area in the target memory block has not been temporarily allocated. By traversing the usage bitmap information of the corresponding specification matching the current thread (as an example, it can be replaced with other marking information), other target memory blocks that meet the requirements or other load cache areas in the same target memory block can be found. This processing process has a fast search efficiency, and the processing time has almost no impact on the normal operation of the application, and is imperceptible to users of the target application.

[0083] Combination Figure 3 , Figure 4 (a) to (c) and Figure 5 As shown, in the above step S130, during the execution of the main function of the above target application, the running thread locates the corresponding target thread buffer by accessing the above global buffer, including:

[0084] During the execution of the main function of the target application, the running thread obtains the target thread cache index identifier corresponding to the target thread buffer indicated by the mapping relationship by accessing the global buffer;

[0085] Based on the target thread cache index identifier, the running thread locates the corresponding target thread buffer by matching in the header file information in the thread buffer or matching in the index positioning information included in the load cache area.

[0086] In some embodiments, in the above step S130, after locating the corresponding target thread buffer, the process of applying for a target space matching the actual running state from the above target thread buffer includes:

[0087] The above-mentioned running thread determines the memory to be applied for according to the actual running status;

[0088] According to the tag information in the header file information of the target thread buffer, searching for a candidate memory block that is currently unoccupied; which memory block is in the unoccupied state can be determined by the tag information;

[0089] Determine the available space size of the candidate memory block;

[0090] Compare the available space sizes of the memory to be applied for and the candidate memory blocks, and determine the candidate memory block with the smallest size in the first available space size that is larger than the corresponding size of the memory to be applied for as the target memory block to be applied for; based on this setting, it is possible to match the pre-customized and allocated target memory block and reduce the waste of memory;

[0091] Locate the target memory block according to the header file information of the thread buffer;

[0092] An allocated load cache area for the memory to be applied is determined in the target memory block, and the allocated load cache area is set to an occupied state; wherein the storage space corresponding to the allocated load cache area in the occupied state is used as the target space.

[0093] In some embodiments, each memory block includes multiple load cache areas, and the load cache areas are dynamically allocated and released by threads.

[0094] The above-mentioned marking information includes: usage status bitmap information of multiple load cache areas in each memory block; or, positioning offset information of the first load cache area in each memory block that is currently unoccupied; wherein the above-mentioned positioning offset information represents the first target offset of the above-mentioned first load cache area from the memory block header file of the memory block where it is located.

[0095] Among them, according to the marking information in the header file information of the above-mentioned target thread buffer, searching for candidate memory blocks in the currently unoccupied state includes: according to the usage status bitmap information or positioning offset information of each memory block, determining the memory block with an idle load cache area as the candidate memory block in the currently unoccupied state.

[0096] The step of determining the available space size of the candidate memory block includes:

[0097] According to the usage status bitmap information of the candidate memory block, determine one or more first load cache areas in the candidate memory block that are currently unoccupied; locate the one or more first load cache areas; obtain the available space size corresponding to the one or more first load cache areas; or,

[0098] According to the positioning offset information, one or more first load cache areas that are currently unoccupied are located; and available space sizes corresponding to the one or more first load cache areas are obtained.

[0099] In the above embodiment, based on the usage status bitmap information or the positioning offset information, the candidate memory block in the current unoccupied state can be quickly and accurately located; meanwhile, the size of the available space in the candidate memory block can also be further determined.

[0100] In some embedded operating scenarios, if the above tag information requires mutually exclusive access by each thread, then atomic variables can be used to implement it, because the application and release operations are performed serially, and the memory application phase only needs to read the above tag information, and only when it is released does it need to be written. In this case, the "snapshot" method can be used to obtain the above tag information during the application and then determine the corresponding target thread buffer for memory application. Snapshot technology is a technology based on data replication and mirroring. It can quickly create a copy of a data set, namely a snapshot. Snapshots can provide a consistent data view without affecting the original data, making it convenient for users to perform data backup, recovery, and analysis operations.

[0101] Wherein, determining the allocated load cache area for the above-mentioned memory to be applied in the above-mentioned target memory block includes: in the above-mentioned target memory block, determining the first load cache area that is accurately matched with the above-mentioned memory to be applied or matched based on a preset approximate interval as the allocated load cache area. In the embodiment of the present disclosure, a matching strategy can be pre-set, such as including an accurate matching strategy and a fuzzy matching strategy. In the fuzzy matching strategy, the principle of close and minimum specifications is adopted. For example, the size of the approximate value can be adopted to apply for 10Byte, 20Byte, and 30Byte sizes, so the memory usage of the smallest 32Byte memory block size is uniformly allocated. That is: each block size has an approximate interval, and the approximate interval of this example is 32Byte. In some cases, it can be customized according to the specific thread memory usage, and the approximate interval value of each memory block size is reserved for use during allocation, such as: 1024Byte length, the corresponding preset approximate interval size is 128, then the memory allocation within the range of [1024-128, 1024] is allocated using a memory block of 1024 size.

[0102] The specific implementation logic of step S130 can be pre-defined in the development stage. Figure 6 Description. If the size of the memory block and its interval value are not within the range, and the target space cannot be matched in the pre-built thread buffer according to the fuzzy matching strategy, the thread buffer and the corresponding memory block of the appropriate size will be customized (for example, a new memory block can be added to the corresponding thread buffer), and a traversal search method will be used to determine the updated adaptive size specifications. Since the size specifications of each memory block are not necessarily in order, the size of each thread memory block is limited, so even if the traversal search method is used, the average efficiency of the search is not low, and the time consumption of this memory allocation has a low negative impact on the overall data processing performance of the target application.

[0103] In some embodiments, the index location information contained in each load cache area includes: the first offset (Slot Header Offset) of the current load cache area from the memory block header file, referring to Figure 4 As shown in (c) above, the locating to the one or more first load cache areas includes: locating to the corresponding first load cache area according to the first offset corresponding to the one or more first load cache areas.

[0104] In some embodiments, the index location information contained in each load cache area includes: a second offset (Payload Offset) corresponding to the load memory space contained in the current load cache area, referring to Figure 4 As shown in (c). The above-mentioned allocated load cache area is set to an occupied state, including: locating the target load memory space as the target space according to the second offset of the above-mentioned allocated load cache area, and setting the above-mentioned target load memory space to an occupied state, and the above-mentioned allocated load cache area is regarded as being in an occupied state.

[0105] In the embodiment including the above steps S110 to S130, by creating a thread buffer corresponding to the target application's to-be-run thread, since the to-be-run threads access the corresponding thread buffers independently and do not interfere with each other, no locking is required, thereby improving the allocation efficiency of multi-threaded access to memory. At the same time, by creating a global buffer for managing thread buffers, and in the process of initializing the global buffer, memory allocation is performed for each thread buffer according to the predefined storage space, so that the storage space allocated to each thread buffer matches the running space information required by each corresponding to-be-run thread, thereby realizing customized memory allocation; on the one hand, based on the setting of the global buffer, it can ensure that the running thread can quickly locate the corresponding target thread buffer and apply for the corresponding target space during the actual operation, and the indexing is efficient and fast; on the other hand, since the thread buffer is a customized memory allocation, the memory specifications and quantity that can be allocated in the thread buffer are adapted to the needs of the to-be-run thread, so that in the process of applying for the target space, memory fragmentation can be reduced, and a relatively accurate match with the required memory can be achieved, thereby reducing the waste of memory space and improving memory utilization.

[0106] In some embodiments, the above method further comprises:

[0107] When an index mismatch or a memory address error occurs during the use of the first target space by the first running thread, the first running thread or the second running thread calls a library function to release the first target space corresponding to the first target thread buffer.

[0108] Among them, the above-mentioned first running thread and the above-mentioned second running thread are different threads; in the process of releasing the above-mentioned first target space, the above-mentioned first running thread or the above-mentioned second running thread updates the usage status of the above-mentioned first target space to an unoccupied state based on the thread cache index identifier corresponding to the first target thread buffer and the index information in the memory block structure contained in the above-mentioned first target thread buffer.

[0109] For example, refer to Figure 5 As shown, when releasing memory, you can also use the thread buffer index and the index of all data structures in the thread buffer (for specific indexes, refer to Figure 4 The structure of ( ) performs memory release operation, and updates the marking information used to mark the usage status of each memory block. The search process based on two types of indexes only requires two indirect addressings to quickly find the result, and the search efficiency is very high.

[0110] In some embodiments, the method further includes: when the target space cannot be applied for from the target thread buffer, calling a memory management function to apply for a target space matching the actual running state.

[0111] This embodiment is a bottom-line strategy when the target space cannot be obtained after executing all the aforementioned memory allocation methods. The target space matching the actual running state is applied by calling the memory management function. In most cases, the memory allocation strategy described above can achieve efficient memory allocation, so there is no need to call the memory management function, which can avoid competing with other applications for the system's memory management function in most cases.

[0112] Exemplary Devices

[0113] Figure 7 The present invention is a block diagram of a memory management device according to an exemplary embodiment.

[0114] Reference Figure 7 As shown, the memory management device 700 provided by the embodiment of the present disclosure includes: a creation module 710, an initialization module 720 and a local memory management module 730.

[0115] The creation module 710 is used to create a thread buffer for a target application and a global buffer for managing the thread buffer; wherein the threads to be run in the target application correspond to the thread buffer.

[0116] The above-mentioned initialization module 720 is used to initialize the above-mentioned global buffer before the main function of the above-mentioned target application is executed; and during the initialization process of the above-mentioned global buffer, memory is allocated to each thread buffer according to the predefined storage space; wherein the predefined storage space of each thread buffer is defined based on the space information required for the operation of the thread to be run.

[0117] The local memory management module 730 is used to locate the corresponding target thread buffer by accessing the global buffer during the execution of the main function of the target application, and to apply for a target space matching the actual running state from the target thread buffer.

[0118] In some embodiments, the above-mentioned device 700 also includes: a first function calling module.

[0119] The first function calling module is used to: when an index mismatch or a memory address error occurs during the use of the first target space by the first running thread, the first running thread or the second running thread calls a library function to release the first target space corresponding to the first target thread buffer.

[0120] Among them, the above-mentioned first running thread and the above-mentioned second running thread are different threads; in the process of releasing the above-mentioned first target space, the above-mentioned first running thread or the above-mentioned second running thread updates the usage status of the above-mentioned first target space to an unoccupied state based on the thread cache index identifier corresponding to the first target thread buffer and the index information in the memory block structure contained in the above-mentioned first target thread buffer.

[0121] In some embodiments, the above-mentioned device 700 also includes: a second function calling module.

[0122] The second function calling module is further used to: when the target space cannot be applied for from the target thread buffer, call the memory management function to apply for the target space matching the actual running state.

[0123] For more details and beneficial effects of this embodiment, please refer to the relevant description of the first embodiment, which will not be repeated here.

[0124] Exemplary Electronic Devices

[0125] Figure 8 1 is a block diagram of an electronic device 800 according to an exemplary embodiment. The electronic device 800 may be a vehicle controller, a vehicle terminal, a vehicle computer or other types of electronic devices.

[0126] Reference Figure 8As shown, the electronic device 800 may include at least one processor 810 and a memory 820. The processor 810 may execute instructions stored in the memory 820. The processor 810 is communicatively connected to the memory 820 via a data bus. In addition to the memory 820, the processor 810 may also be communicatively connected to an input device 830, an output device 840, and a communication device 850 via a data bus.

[0127] The processor 810 may be any conventional processor, such as a commercially available CPU. The processor may also include a graphics processor (Graphic Process Unit, GPU), a field programmable gate array (Field Programmable Gate Array, FPGA), a system on chip (System on Chip, SOC), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC) or a combination thereof.

[0128] The memory 820 may be implemented by any type of volatile or nonvolatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0129] In the embodiment of the present disclosure, executable instructions are stored in the memory 820, and the processor 810 can read the executable instructions from the memory 820 and execute the instructions to implement all or part of the steps of the memory management method described in any of the above exemplary embodiments.

[0130] Exemplary computer-readable storage media

[0131] In addition to the above methods and devices, the exemplary embodiments of the present disclosure may also be a computer program product or a computer-readable storage medium storing the computer program product. The computer product includes computer program instructions that can be executed by a processor to implement all or part of the steps described in any method in the above exemplary embodiments.

[0132] The computer program product may be written in any combination of one or more programming languages ​​to write program codes for performing the operations of the embodiments of the present application, including object-oriented programming languages, such as Java, C++, etc., and also conventional procedural programming languages, such as "C" language or similar programming languages ​​and scripting languages ​​(e.g., Python). The program code may be executed entirely on the user computing device, partially on the user computing device, as an independent software package, partially on the user computing device and partially on the remote computing device, or entirely on the remote computing device or server.

[0133] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples of readable storage media include: a static random access memory (SRAM) with one or more wires electrically connected, an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic storage, a flash memory, a magnetic disk or an optical disk, or any suitable combination of the above.

[0134] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the present disclosure. This application is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and examples are to be considered as exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0135] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A memory management method, characterized in that: include: Creating a thread buffer for a target application and a global buffer for managing the thread buffer; wherein the threads to be run in the target application have a corresponding relationship with the thread buffer; Before the main function of the target application is executed, the global buffer is initialized; and during the initialization of the global buffer, memory is allocated to each thread buffer according to a predefined storage space; wherein the predefined storage space of each thread buffer is defined based on the space information required for the running thread to be run; During the execution of the main function of the target application, the running thread locates the corresponding target thread buffer by accessing the global buffer, and applies for a target space matching the actual running state from the target thread buffer.

2. The method according to claim 1, characterized in that The predefined storage space of each thread buffer includes a preset number of memory blocks, each memory block has a corresponding preset space size and the predefined storage space has a plurality of different size specifications; the header file information of the thread buffer includes marking information for marking the use status of the load cache area in each memory block; The step of applying for a target space matching the actual running state from the target thread buffer includes: The running thread determines the memory to be applied according to the actual running state; According to the tag information in the header file information of the target thread buffer, searching for a candidate memory block that is currently unoccupied; Determining the available space size of the candidate memory block; Compare the available space sizes of the memory to be applied for and the candidate memory blocks, and determine the candidate memory block with the smallest size specification in the first available space size that is larger than the corresponding size of the memory to be applied for as the target memory block to be applied for; Locate the target memory block according to the header file information of the thread buffer; An allocated load cache area for the memory to be applied is determined in the target memory block, and the allocated load cache area is set to an occupied state; wherein the storage space corresponding to the allocated load cache area in the occupied state is used as the target space.

3. The method according to claim 2, characterized in that Each memory block contains multiple load cache areas, and the load cache areas are dynamically applied for and released by threads; The marking information includes: usage status bitmap information of multiple load cache areas in each memory block; or positioning offset information of a first load cache area in a currently unoccupied state in each memory block; wherein the positioning offset information indicates a first target offset of the first load cache area from a memory block header file of the memory block in which the first load cache area is located; Wherein, searching for candidate memory blocks in a currently unoccupied state according to the mark information in the header file information of the target thread buffer includes: determining memory blocks with idle load cache areas as candidate memory blocks in a currently unoccupied state according to the usage status bitmap information or positioning offset information of each memory block; Wherein, determining the available space size of the candidate memory block includes: determining one or more first load cache areas in the candidate memory block that are currently unoccupied according to the usage status bitmap information of the candidate memory block; locating the one or more first load cache areas; obtaining the available space size corresponding to the one or more first load cache areas; or, Locate one or more first load cache areas that are currently unoccupied according to the positioning offset information; obtain available space sizes corresponding to the one or more first load cache areas; Wherein, determining the allocated load cache area for the memory to be applied for in the target memory block includes: In the target memory block, a first load cache area that is precisely matched with the memory to be applied or is matched based on a preset approximate interval is determined as an allocated load cache area.

4. The method according to claim 3, characterized in that The index positioning information contained in each load cache area includes: the first offset of the current load cache area from the memory block header file; Wherein, the locating the one or more first load cache areas includes: According to the first offset corresponding to one or more first load cache areas, the corresponding first load cache area is located.

5. The method according to any one of claims 2 to 4, characterized in that: The index positioning information contained in each load cache area includes: a second offset corresponding to the load memory space contained in the current load cache area; wherein the second offset is used to locate the load memory space allocated for storing data in the current load cache area; The step of setting the allocated load cache area to an occupied state includes: According to the second offset of the allocated load cache area, a target load memory space as a target space is located, and the target load memory space is set to an occupied state, and the allocated load cache area is regarded as being in an occupied state.

6. The method according to any one of claims 2 to 4, characterized in that: The global buffer stores a mapping relationship between each thread and the thread cache index identifier of the corresponding thread buffer; The index positioning information contained in each load cache area includes: the thread cache index identifier of the thread buffer corresponding to the current load cache area; or the header file information of the thread buffer includes: the thread cache index identifier corresponding to the current thread buffer; Wherein, during the execution of the main function of the target application, the running thread locates the corresponding target thread buffer by accessing the global buffer, including: During the execution of the main function of the target application, the running thread obtains the target thread cache index identifier corresponding to the target thread buffer indicated by the mapping relationship by accessing the global buffer; Based on the target thread cache index identifier, the running thread locates the corresponding target thread buffer by matching in the header file information in the thread buffer or matching in the index positioning information included in the load cache area.

7. The method according to any one of claims 2 to 4, characterized in that: The header file information of the thread buffer includes: a memory block index; Locating the target memory block according to the header file information of the thread buffer includes: Obtaining a target memory block index for pointing to the target memory block from the header file information of the thread buffer; The target memory block is located based on the target memory block index.

8. The method according to any one of claims 1 to 4, characterized in that Also includes: When an index mismatch or a memory address error occurs during the use of the first target space by the first running thread, the first running thread or the second running thread calls a library function to release the first target space corresponding to the first target thread buffer; Among them, the first running thread and the second running thread are different threads; in the process of releasing the first target space, the first running thread or the second running thread updates the usage status of the first target space to an unoccupied state based on the thread cache index identifier corresponding to the first target thread buffer and the index information in the memory block structure contained in the first target thread buffer.

9. The method according to claim 1, characterized in that: Also includes: In the case that the target space cannot be applied for from the target thread buffer, a memory management function is called to apply for a target space matching the actual running state.

10. A memory management device, characterized in that: include: A creation module, used to create a thread buffer for a target application and a global buffer for managing the thread buffer; wherein the threads to be run in the target application have a corresponding relationship with the thread buffer; An initialization module, used for initializing the global buffer before the main function of the target application is executed; and during the initialization of the global buffer, memory is allocated to each thread buffer according to a predefined storage space; wherein the predefined storage space of each thread buffer is defined based on the space information required for the execution of the thread to be executed; The local memory management module is used to enable the running thread to locate the corresponding target thread buffer by accessing the global buffer during the execution of the main function of the target application, and to apply for a target space matching the actual running state from the target thread buffer.

11. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; The processor is used to read the executable instructions from the memory and execute the instructions to implement the method described in any one of claims 1-9.

12. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the program instructions are executed by a processor, the steps of the method described in any one of claims 1 to 9 are implemented.

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