Processing core binding method and device, storage medium and electronic equipment

Abstract

The embodiment of the invention provides a processing core binding method and device, a storage medium and electronic equipment, and the method comprises the steps: determining a second processing core which is allowed to be divided into a virtual resource pool in a first processing core corresponding to a central processing unit of a server, and the first processing core is a logic processing core; determining a second standard interface which is allowed to be divided into the virtualized resource pool in first standard interfaces used for connecting the high-speed equipment in the server; and binding the second processing core with the second standard interface in the virtualized resource pool, so that the second processing core is only used for providing computing resources for the second standard interface which has a binding relationship with the second processing core. The problem that the performance optimization effect of the server is poor due to the fact that performance optimization of the server is achieved by adjusting and optimizing a single component associated with the server in the related technology is solved.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of server technology, and more specifically, to a method and device for binding a processing core, a storage medium, and an electronic device. Background Art

[0002] Driven by electronic information hardware technology, server products are the computing, storage and intelligent core of social production, and their performance improvement is crucial to meet the needs of various industries. Servers can be divided into computing, storage and computing types according to their main functions, and each has different requirements for resources such as the central processing unit (CPU), memory, storage speed and graphics processing unit (GPU). At present, the technology for optimizing server performance mainly focuses on the tuning of single hardware components, such as peripheral component interconnect express (PCI-E) components, including: non-volatile memory host controller interface solid state drive (NVMe SSD), GPU computing power card, field programmable gate array (FPGA) card and high-performance network card, etc. The tuning of a single hardware component is usually achieved at the operating system level by adjusting its resource allocation strategy.

[0003] However, this single-component tuning method based on the operating system (OS) has limitations. The differences in resource scheduling strategies of different kernels require continuous manual intervention in the tuning process to ensure the maximum performance of the component. The single-component tuning method based on the OS relies on resource collection and scheduling methods at the software level, which not only consumes a lot of manpower and system resources, but also often fails to achieve the expected results in practice. Especially in the large-scale service environment of cluster deployment, the performance improvement effect is limited and it is difficult to fully meet the needs of high-concurrency and high-pressure input / output (I / O) access scenarios.

[0004] Therefore, there is a problem in the related art that the performance optimization of the server is achieved by tuning a single component associated with the server, resulting in poor optimization effect on the performance of the server.

[0005] In the related art, the problem that the performance of the server is optimized by tuning a single component associated with the server, resulting in poor optimization effect on the performance of the server, has not yet been effectively solved. Summary of the invention

[0006] The embodiments of the present application provide a method and device for binding a processing core, a storage medium, and an electronic device, so as to at least solve the problem in the related art that the performance of a server is optimized by tuning a single component associated with the server, resulting in poor optimization effect on the performance of the server.

[0007] According to one embodiment of the present application, a method for binding processing cores is provided, comprising: determining a second processing core in a first processing core corresponding to a central processor of a server that is allowed to be divided into a virtualized resource pool, wherein the first processing core is a logical processing core; and determining a second standard interface in a first standard interface for connecting a high-speed device in the server that is allowed to be divided into a virtualized resource pool; and binding the second processing core to the second standard interface in the virtualized resource pool so that the second processing core is only used to provide computing resources for the second standard interface that has a binding relationship with the second processing core.

[0008] In an exemplary embodiment, determining a second processing core in a first processing core corresponding to a central processor of a server that is allowed to be allocated to a virtualized resource pool includes: determining a third processing core in the first processing core for executing regular business of the server when it is determined that a current state of a basic input / output system of the server satisfies a preset condition; and selecting the second processing core that is allowed to be allocated to the virtualized resource pool from among fourth processing cores, wherein the fourth processing core is a processing core in the first processing core other than the third processing core.

[0009] In an exemplary embodiment, before determining the third processing core in the first processing core for executing the regular business of the server, the method further includes: determining whether a hierarchical switch is pre-deployed in the basic input and output system, wherein the hierarchical switch is used to manage multiple sub-class function items in the basic input and output system, and the multiple sub-class function items are associated with a binding event, and the binding event is used to indicate that the second processing core is bound to the second standard interface; if the hierarchical switch is pre-deployed in the basic input and output system and the server state of the server meets a preset state, starting the hierarchical switch to simultaneously start the multiple sub-class function items, wherein the preset state at least includes: the server performs storage-type services, wherein when the server performs storage-type services, the multiple sub-class function items at least include: CPU turbo acceleration, non-uniform memory access, hyperthreading technology, and Intel virtualization technology; if the hierarchical switch is not pre-deployed in the basic input and output system and the server state of the server meets the preset state, starting the multiple sub-class function items in sequence according to a preset order; when it is detected that the multiple sub-class function items are all in the startup state, determining that the current state of the basic input and output system of the server meets the preset condition.

[0010] In an exemplary embodiment, selecting the second processing core that is allowed to be divided into the virtualized resource pool from the fourth processing core includes: determining a first number of central processing units deployed in the server, and determining a second number of threads supported by the central processing unit; determining a third number of the fourth processing cores by using the first number and the second number, and determining a fourth number of high-speed devices associated with the second standard interface; and determining the second processing core by using the fourth number when the third number is greater than the fourth number, wherein the fourth number and the fifth number of the second processing cores satisfy a preset proportional relationship, and the preset proportional relationship is determined by the performance level of the central processing unit.

[0011] In an exemplary embodiment, determining a fourth number of high-speed devices associated with a second standard interface includes: determining a sixth number of high-speed serial computer expansion bus standard root complexes in the server through a command line tool, wherein the command line tool is used to obtain detailed information of high-speed serial computer expansion bus standard devices in the server; and determining the fourth number of high-speed devices associated with the second standard interface through the sixth number.

[0012] In an exemplary embodiment, binding the second processing core to the second standard interface in the virtualized resource pool includes: determining the interface address of the second standard interface; and allocating to the second standard interface a number of second processing cores that satisfies the preset ratio; and binding the interface address to the number of second processing cores that satisfies the preset ratio.

[0013] In an exemplary embodiment, determining a second standard interface in a first standard interface in a server for connecting a high-speed device that is allowed to be divided into a virtualized resource pool includes: determining a third standard interface corresponding to the central processing unit, wherein the first standard interface includes: the third standard interfaces corresponding to the plurality of central processing units deployed in the server, respectively; determining a fourth standard interface in the third standard interface to which a high-speed device is connected; and determining the second standard interface from the fourth standard interface.

[0014] According to another embodiment of the present application, a processing core binding device is provided, including: a determination module, used to determine a second processing core in a first processing core corresponding to a central processor of a server that is allowed to be divided into a virtualization resource pool, wherein the first processing core is a logical processing core; and determine a second standard interface in a first standard interface for connecting a high-speed device in the server that is allowed to be divided into a virtualization resource pool; a binding module, used to bind the second processing core to the second standard interface in the virtualization resource pool, so that the second processing core is only used to provide computing resources for the second standard interface that has a binding relationship with the second processing core.

[0015] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0016] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0017] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0018] Through this application, first, determine the second processing core in the first processing core (logical processing core) corresponding to the central processing unit of the server that is allowed to be divided into the virtualized resource pool, and determine the second standard interface in the first standard interface for connecting high-speed devices in the server that is allowed to be divided into the virtualized resource pool; secondly, bind the second processing core to the second standard interface in the virtualized resource pool so that the second processing core is only used to provide computing resources for the second standard interface that has a binding relationship with the second processing core. Therefore, the problem in the related art that the performance optimization of the server is achieved by tuning a single component associated with the server, resulting in poor optimization effect on the performance of the server, can be solved. The performance optimization of the server is achieved from the underlying hardware level, thereby improving the optimization effect on the performance of the server. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a hardware structure block diagram of a computer terminal for a method for binding a processing core according to an embodiment of the present application;

[0020] Figure 2 is a flowchart of a method for binding processing cores according to an embodiment of the present application;

[0021] Figure 3 is a schematic diagram of a logical processing core according to a method for binding processing cores in an embodiment of the present application;

[0022] Figure 4 is a schematic diagram of logical processing core division according to a processing core binding method of an embodiment of the present application;

[0023] Figure 5 is an lntel PCl-E topology logic diagram of a method for binding processing cores according to an embodiment of the present application;

[0024] Figure 6 It is a schematic diagram of the logical relationship of PCI-E Port under virtualization according to the method for binding processing cores in an embodiment of the present application;

[0025] Figure 7 is a schematic diagram of query results of a method for binding processing cores according to an embodiment of the present application;

[0026] Figure 8 is a schematic diagram of a binding relationship of a method for binding processing cores according to an embodiment of the present application;

[0027] Fig. 9 It is a structural block diagram of a binding device for a processing core according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or order.

[0030] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 1 1 is a hardware structure block diagram of a computer terminal for a method for binding a processing core according to an embodiment of the present application. Figure 1 As shown, the computer terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned computer terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0031] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for allocating load resources in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, the above method is implemented. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0032] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0033] Figure 2 is a flowchart of a method for binding a processing core according to an embodiment of the present application, such as Figure 2 As shown, the process includes the following steps:

[0034] Step S202, determining a second processing core in a first processing core corresponding to a central processor of a server that is allowed to be divided into a virtualized resource pool, wherein the first processing core is a logical processing core; and determining a second standard interface in a first standard interface for connecting a high-speed device in the server that is allowed to be divided into a virtualized resource pool;

[0035] Step S204: Bind the second processing core to the second standard interface in the virtualized resource pool, so that the second processing core is only used to provide computing resources for the second standard interface that is bound to the second processing core.

[0036] Through the above steps, first, determine the second processing core in the first processing core (logical processing core) corresponding to the central processing unit of the server that is allowed to be divided into the virtualization resource pool, and determine the second standard interface in the first standard interface for connecting high-speed devices in the server that is allowed to be divided into the virtualization resource pool; secondly, bind the second processing core to the second standard interface in the virtualization resource pool so that the second processing core is only used to provide computing resources for the second standard interface that has a binding relationship with the second processing core. Therefore, the problem in the related art that the performance optimization of the server is achieved by tuning a single component associated with the server, resulting in poor optimization effect on the performance of the server can be solved. The performance optimization of the server is achieved from the underlying hardware level, thereby improving the optimization effect on the performance of the server.

[0037] In an exemplary embodiment, determining a second processing core in a first processing core corresponding to a central processor of a server that is allowed to be allocated to a virtualized resource pool includes: determining a third processing core in the first processing core for executing regular business of the server when it is determined that a current state of a basic input / output system of the server satisfies a preset condition; and selecting the second processing core that is allowed to be allocated to the virtualized resource pool from among fourth processing cores, wherein the fourth processing core is a processing core in the first processing core other than the third processing core.

[0038] During server operation, some logical processing cores are specifically allocated to perform routine business, which usually involves the core services and system management of the server. These third processing cores need to be reserved to ensure the stability and responsiveness of the system. Therefore, it is necessary to select the second processing core that is allowed to be divided into the virtualized resource pool from the remaining fourth processing cores. This selection process needs to consider the following factors:

[0039] Factor 1: Performance optimization goal: According to the performance optimization goal of the server (such as I / O intensive, computing intensive, etc.), select the most suitable processing core to divide the virtualization resource pool.

[0040] Factor 2: Resource pool size: Based on the server's hardware configuration and business requirements, determine the size of the virtualization resource pool, that is, how many logical processing cores are required.

[0041] Factor 3: Balanced allocation of hardware resources: Ensure that the logical processing cores allocated to the virtualized resource pool can be evenly distributed among the physical CPUs to avoid bottlenecks caused by excessive concentration of resources.

[0042] Therefore, in the embodiment of the present application, in the process of allocating the second processing core to the virtualized resource pool, factors such as the performance optimization goals of the server and the hardware resource conditions of the server are taken into consideration, so that the performance optimization of the server is carried out while satisfying the basic hardware conditions of the server, thereby achieving a better performance optimization effect on the server.

[0043] In an exemplary embodiment, before determining the third processing core in the first processing core for executing the regular business of the server, the method further includes: determining whether a hierarchical switch is pre-deployed in the basic input and output system, wherein the hierarchical switch is used to manage multiple sub-class function items in the basic input and output system, and the multiple sub-class function items are associated with a binding event, and the binding event is used to indicate that the second processing core is bound to the second standard interface; if the hierarchical switch is pre-deployed in the basic input and output system and the server state of the server meets a preset state, starting the hierarchical switch to simultaneously start the multiple sub-class function items, wherein the preset state at least includes: the server performs storage-type services, wherein when the server performs storage-type services, the multiple sub-class function items at least include: CPU turbo acceleration, non-uniform memory access, hyperthreading technology, and Intel virtualization technology; if the hierarchical switch is not pre-deployed in the basic input and output system and the server state of the server meets the preset state, starting the multiple sub-class function items in sequence according to a preset order; when it is detected that the multiple sub-class function items are all in the startup state, determining that the current state of the basic input and output system of the server meets the preset condition.

[0044] It should be noted that the central processing unit (CPU) turbo acceleration is a processor technology that allows the CPU to increase its clock speed when lightly loaded to provide higher performance when needed. Numa: Non-Uniform Memory Access, a multi-processor computer architecture in which each processor can access all physical memory, but accesses different memory areas at different speeds, usually faster for memory areas closer to itself. Hyper-Threading: Hyper-Threading technology, a feature of Intel processors that allows a physical core to process multiple threads simultaneously, thereby improving the parallel processing capabilities of the processor. VT-intel Intel Virtualization: Intel Virtualization Technology, a hardware-assisted virtualization technology that can improve performance and efficiency in virtualized environments and support better resource isolation and management.

[0045] Before allocating the second processing core to the virtualized resource pool, at least the function items corresponding to the hyperthreading technology and Intel virtualization technology are enabled in the basic input and output system (BIOS). In order to facilitate the unified management of multiple sub-class function items, hierarchical switches can be deployed in the BIOS in advance, and the function item switches corresponding to the multiple sub-class function items are divided and managed through hierarchical switches, and the management at least includes one-click opening or one-click closing of the function item switches of multiple sub-class function items. In the case where the hierarchical switch is not deployed in the BIOS, the function item switches of the multiple sub-class function items need to be turned on in sequence according to the preset order. The preset order is, for example: first turn on the sub-class function item switch related to the division of the second processing core, and then turn on the sub-class function item switch related to the division of the second standard interface, etc.

[0046] Therefore, the embodiment of the present application can realize one-click activation of multiple sub-category function items related to server performance optimization through pre-deployed hierarchical switches, reducing the additional operations required for server performance optimization, thereby saving optimization time.

[0047] In an exemplary embodiment, selecting the second processing core that is allowed to be divided into the virtualized resource pool from the fourth processing core includes: determining a first number of central processing units deployed in the server, and determining a second number of threads supported by the central processing unit; determining a third number of the fourth processing cores by using the first number and the second number, and determining a fourth number of high-speed devices associated with the second standard interface; and determining the second processing core by using the fourth number when the third number is greater than the fourth number, wherein the fourth number and the fifth number of the second processing cores satisfy a preset proportional relationship, and the preset proportional relationship is determined by the performance level of the central processing unit.

[0048] The number of logical processing cores obtained when Intel Virtualization Technology is turned on can be determined by multiplying the first number of CPUs, the second number of threads, and the number of CPU cores, that is, the number of first processing cores in the above embodiment. The third number of fourth processing cores can be obtained by subtracting the number of third processing cores used to process regular business from the number of first processing cores. Optionally, the fourth number and the fifth number of the second processing cores meet a preset ratio relationship, and the preset ratio relationship can generally be selected as: the fifth number is twice the fourth number.

[0049] In an exemplary embodiment, determining a fourth number of high-speed devices associated with a second standard interface includes: determining a sixth number of high-speed serial computer expansion bus standard root complexes in the server through a command line tool, wherein the command line tool is used to obtain detailed information of high-speed serial computer expansion bus standard devices in the server; and determining the fourth number of high-speed devices associated with the second standard interface through the sixth number.

[0050] It should be noted that PCI-E is a high-speed serial computer expansion bus standard used for connecting hardware devices inside a computer, such as graphics processing units (GPUs), network cards, and storage devices. The PCI-E interface has become one of the main interface standards in modern computer systems due to its high bandwidth and scalability.

[0051] In an embodiment of the present application, detailed information of high-speed devices is obtained using command line tools, which can more accurately evaluate the hardware resources of the server and provide a scientific basis for subsequent resource allocation. It is particularly suitable for dynamic business environments that require frequent monitoring and adjustment of hardware resources, and can ensure the accuracy and timeliness of resource allocation, thereby improving the operating efficiency and stability of the server.

[0052] In an exemplary embodiment, binding the second processing core to the second standard interface in the virtualized resource pool includes: determining the interface address of the second standard interface; and allocating to the second standard interface a number of second processing cores that satisfies the preset ratio; and binding the interface address to the number of second processing cores that satisfies the preset ratio.

[0053] Through the embodiment of the present application, each second standard interface is allocated with a corresponding second processing core dedicated to providing computing resources for the high-speed device connected to each second standard interface, thereby enabling the server to manage its hardware resources more intelligently and efficiently, especially when processing business scenarios with high concurrency and large I / O access, which can significantly improve performance. At the same time, manual tuning work at the system level is reduced, maintenance costs are reduced, and system availability and scalability are improved.

[0054] In an exemplary embodiment, determining a second standard interface in a first standard interface in a server for connecting a high-speed device that is allowed to be divided into a virtualized resource pool includes: determining a third standard interface corresponding to the central processing unit, wherein the first standard interface includes: the third standard interfaces corresponding to the plurality of central processing units deployed in the server, respectively; determining a fourth standard interface in the third standard interface to which a high-speed device is connected; and determining the second standard interface from the fourth standard interface.

[0055] Optionally, after binding the second processing core to the second standard interface in the virtualized resource pool so that the second processing core is only used to provide computing resources for the second standard interface that is bound to the second processing core, the method further includes:

[0056] In the case where the target link is overloaded, determining a target processing core and a target standard interface included in the target link, wherein the target link is a resource provision link formed between a second processing core and a second standard interface that are in a binding relationship with each other;

[0057] Determine a first central processing unit corresponding to a target standard interface, or determine a second central processing unit corresponding to a target processing core;

[0058] Determine whether there are any remaining processing cores in the logic processing cores corresponding to the third central processor that do not process conventional services and are not bound to any standard interface;

[0059] In the case where there are remaining processing cores, allocating additional processing cores to the target link from the remaining processing cores;

[0060] The additional processing core is bound to the target standard interface so that the compliance of the target link is in an acceptable state.

[0061] Therefore, the embodiment of the present application provides a solution for adding binding relationships in real time, so that when a binding link of the server is overloaded, the target link can be quickly balanced, further improving the performance of the server.

[0062] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0063] In order to better understand the process of the above-mentioned processing core binding method, the implementation process of the above-mentioned processing core binding method is described below in combination with an optional embodiment, but it is not used to limit the technical solution of the embodiment of the present application.

[0064] With the continuous updating of electronic information hardware technology, faster and less power-consuming products are also being developed and launched. Among them, server products have become an indispensable part of social production, which can continuously provide a large amount of computing, storage, and intelligent power to meet the needs of all walks of life. In terms of basic needs, servers can be basically divided into three categories: computing, storage, and computing power. Computing servers mainly use CPU + memory to perform high-precision and high-performance computing, mainly focusing on the precise calculation of big data, and have relatively low storage requirements. The characteristics of storage servers are that data computing requirements are general but there are high requirements for fast reading and writing and concurrency of data, such as network cloud applications. The main feature of computing power servers is that they have configurations represented by GPU components, which are suitable for a large number of repeated calculations and the deduction of large models, and are widely used in industrial and scientific research fields. Based on the above different types of servers, corresponding hardware performance combination logic support is required to enable the whole machine to provide the best service status.

[0065] In the related art, the performance optimization of the server is mainly achieved by tuning a single component associated with the server. Taking a computing power and multi-PCI-E component server as an example, the PCI-E components that are widely used in PCI-E component servers are NVME SSDs, PCI-E GPU computing power cards, FPGA cards, and high-performance network cards that use PCI-E resources. These PCI-E components have the same requirement while providing services, that is, to request as many system resource model allocations as possible. Based on this, there are methods for optimizing PCIE SSD IO in the related art, which optimize server performance by improving the stability of PCIE SSD; there are methods for optimizing solid-state drives, which optimize server performance by optimizing the performance of solid-state drives; there are also methods for tuning the GPU in the server, which optimize server performance by optimizing the GPU. The above optimization methods all implement targeted tuning of single component types through the operating system OS, which belongs to system-level adjustment in architecture. However, the resource scheduling strategies of different kernels under the OS are different, which leads to the need for continuous human participation in the targeted tuning of single component types, which requires a lot of resource investment. In essence, the underlying logic of performance has not been adjusted to form a synergy, and resources need to be aggregated at the software layer, which often makes the performance effect fail to meet expectations and has limitations, which is not conducive to the cluster deployment of large-scale services.

[0066] Therefore, the optional embodiment of the present application implements different types of server performance tuning based on the hardware performance combination logic of the firmware to accelerate the rapid deployment of services. Specifically including:

[0067] Step 1: The CPU divides the logical CPU core (equivalent to the second processing core in the above embodiment) into a hardware virtualization resource pool (equivalent to the virtualization resource pool in the above embodiment);

[0068] Step 1 specifically includes virtualization logic division and scope generation of CPU Core.

[0069] Among them, step 1.1: execute the precondition to enable the virtualization function. Enable the two function items of Intel Virtualization and Intel Hyper-Threading of the CPU in the BIOS, so that both function items are in an enabled state.

[0070] Step 1.2: After the virtualization function is enabled, the CPU Core is divided into two parts: the logical Core and the physical Core. The logical Core (equivalent to the first processing core in the above embodiment) under each CPU is virtualized and divided as needed.

[0071] Specifically, after the CPU executes the virtualization function, it can generate a corresponding vCPU (equivalent to the first processing core in the above embodiment) according to the number of threads supported, such as Figure 3 The state of the VCPU under the coupling scope is as follows. Figure 4 Based on Figure 3 and Figure 4 It can be seen that the more physical cores a CPU has and with the support of the hyperthreading function, the more logical cores (equivalent to the first processing core in the above embodiment) it has. The calculation formula for logical cores is as follows:

[0072] Number of vCPUs = (threads × CPU cores) × physical CPUs.

[0073] Wherein, physical CPU represents the first number of central processing units in the above embodiment, and thread represents the second number of threads supported by the central processing unit in the above embodiment. The number of first processing cores in the above embodiment can be calculated by this formula.

[0074] Step 2: PCI-E I / O resource allocation port (equivalent to the second standard interface in the above embodiment) address to the hardware resource pool (equivalent to the virtualization resource pool in the above embodiment);

[0075] The I / Oport virtualization logic is mapped to the functional area (equivalent to the virtualization resource pool in the above embodiment). The Intel PCI-E topology logic is shown as follows: Figure 5 The logical relationship of PCI-E Port under virtualization is as follows Figure 6Generally, the number of PCI-E Root Complexes is determined in hardware design, and can be queried through lspci (equivalent to the command line tool in the above embodiment) in the system. The query result is as follows: Figure 7 There will be multiple PCI-E lanes under the PCI-E Root Complex, and the terminal device (equivalent to the high-speed device in the above embodiment) will be hung under the PCI-E lane, and divided into X4, X8 and X16 devices according to the bandwidth of the terminal device.

[0076] The number of PCI-E terminal devices = the number of PCI-E Root Complexes × 16 / 4.

[0077] The number of PCI-E terminal devices is equivalent to the fourth number of high-speed devices in the above embodiment, and the number of PCI-E Root Complexes is equivalent to the sixth number of high-speed serial computer expansion bus standard root complexes in the above embodiment.

[0078] Select the address of the required PCI-E Port (equivalent to the second standard interface in the above embodiment) and divide it into the scope

[0079] Step 3: Logical CPU core and PCI-E Port implement resource binding, use virtualization to implement resource isolation and form a scope, so that each PCI-E Port has a corresponding dedicated CPU to provide computing resource support, and does not accept resource allocation outside the scope.

[0080] Specifically, the logical CPU core and PCI-E port are scoped and bound. According to the CPU performance level, you can choose to divide different numbers of logical CPU cores into the virtual function area. The number of logical CPU cores is determined by the number of terminal devices under the virtual port. The basic quantitative relationship is: the number of logical CPU cores = the number of terminal devices under the virtual port * 2; that is, LCore:EndDevice = 2:1.

[0081] Among them, the number of logical CPU cores is equivalent to the fifth number in the above embodiment, the number of terminal devices under the virtual port is equivalent to the fourth number of high-speed devices associated with the second standard interface in the above embodiment, and 2 here is equivalent to the preset proportional relationship in the above embodiment, but it should be noted that the preset proportional relationship is not limited to 2.

[0082] Therefore, the optional embodiment of the present application binds the CPU and the devices under the PCI-E lane through virtualization, so as to form a recognizable link binding and exclusive device interrupt processing under the system, no longer relying on the processing wait of the CPU core, and more efficiently utilizing the processor resources of the host. Some I / O delays will increase slightly, but the overall delay can be effectively reduced, and the performance will be better in high-concurrency and high-pressure I / O access scenarios. The resource coupling scope association under the final scope is as follows Figure 8 shown.

[0083] It should be noted that before executing step 1, it is necessary to enable conventional performance (equivalent to enabling the multiple sub-category function items in the above embodiment), such as enabling CPU turbo (i.e., central processing unit turbo acceleration), Numa (i.e., non-uniform memory access), Hyper-Threading (i.e., Hyper-Threading technology, or Intel Hyper-Threading), and VT-intelIntelVirtualization (Intel virtualization technology, or Intel virtualization).

[0084] Optionally, the switch and display of the server type B1OS function combination can be defaulted. Specifically, the server performance scope is added in the B1OS function: that is, the storage service function item level switch is added in the BIOS.

[0085] The following CPU performance and virtualization function items can be enabled under storage services. This function can be managed uniformly through hierarchical switches, and can be separately reflected and hierarchically divided in BlOS. The main categories are: Storage EnhanceServer:

[0086] The sub-category functions are:

[0087] CPU turbo-enable;

[0088] Numa--enbale;

[0089] Hyper-Threading-enable;

[0090] VT-intel Intel Virtualization--enable.

[0091] By setting the hierarchical switch, the functional requirements of server types can be divided and reflected in the BIOS in a hierarchical manner. There is no need to search for and enable functional items separately, and sub-category functional items can be started and closed with one click.

[0092] In summary, the optional embodiment of the present application partially divides the logical core of the CPU, retains the CPU core for conventional business processing (equivalent to the third processing core in the above embodiment), and then schedules and binds the remaining logical core (equivalent to the fourth processing core in the above embodiment). The PCI-E Port device is deeply bound to the CPU logical core in a virtualized environment. The deep binding is implemented at the BlOS level. From the underlying hardware deployment, the system level defaults to the scheduling of resources under the hardware binding relationship, and realizes the exclusive processing of interrupts at the hardware level; thus, the system level does not need to manually adjust the CPU performance, realizes the adjustment and optimization of the soft interrupt under the system, and reduces the investment in the implementation of the system kernel and manual optimization methods, realizes the exclusive processing of processing resources, progress, influence, and terminals based on components, and improves the performance of components under high concurrency and large IO.

[0093] Fig. 9 is a structural block diagram of a binding device for a processing core according to an embodiment of the present application, such as Fig. 9 As shown, the device comprises:

[0094] A determination module 92 is used to determine a second processing core in a first processing core corresponding to a central processor of a server that is allowed to be divided into a virtualized resource pool, wherein the first processing core is a logical processing core; and determine a second standard interface in a first standard interface for connecting a high-speed device in the server that is allowed to be divided into a virtualized resource pool;

[0095] The binding module 94 is used to bind the second processing core to the second standard interface in the virtualized resource pool, so that the second processing core is only used to provide computing resources for the second standard interface that is bound to the second processing core.

[0096] Through the above-mentioned device, firstly, determine the second processing core in the first processing core (logical processing core) corresponding to the central processing unit of the server that is allowed to be divided into the virtualized resource pool, and determine the second standard interface in the first standard interface for connecting high-speed devices in the server that is allowed to be divided into the virtualized resource pool; secondly, bind the second processing core to the second standard interface in the virtualized resource pool, so that the second processing core is only used to provide computing resources for the second standard interface that has a binding relationship with the second processing core. Therefore, the problem in the related art that the performance optimization of the server is achieved by tuning a single component associated with the server, resulting in poor optimization effect on the performance of the server can be solved. The performance optimization of the server is achieved from the underlying hardware level, thereby improving the optimization effect on the performance of the server.

[0097] In an exemplary embodiment, the determination module 92 is also used to: determine the third processing core in the first processing core for executing the regular business of the server when it is determined that the current state of the basic input and output system of the server meets the preset conditions; select the second processing core from the fourth processing core that is allowed to be divided into the virtualization resource pool, wherein the fourth processing core is a processing core in the first processing core other than the third processing core.

[0098] In an exemplary embodiment, the device further includes: a startup module, which is used to, before determining the third processing core in the first processing core for executing the regular business of the server: determine whether a hierarchical switch is pre-deployed in the basic input and output system, wherein the hierarchical switch is used to manage multiple sub-class function items in the basic input and output system, and the multiple sub-class function items are associated with a binding event, and the binding event is used to indicate that the second processing core is bound to the second standard interface; if the hierarchical switch is pre-deployed in the basic input and output system and the server status of the server meets the preset status, start the hierarchical switch to simultaneously Start the multiple sub-category function items, wherein the preset state at least includes: the server performs storage-type services, wherein, in the case where the server performs storage-type services, the multiple sub-category function items at least include: CPU turbo acceleration, non-uniform memory access, hyperthreading technology, and Intel virtualization technology; when the hierarchical switch is not pre-deployed in the basic input and output system and the server state of the server meets the preset state, start the multiple sub-category function items in sequence according to a preset order; when it is detected that the multiple sub-category function items are all in the startup state, determine that the current state of the basic input and output system of the server meets the preset conditions.

[0099] In an exemplary embodiment, the determination module 92 is also used to: determine a first number of central processing units deployed in the server, and determine a second number of threads supported by the central processing unit; determine a third number of the fourth processing cores through the first number and the second number, and determine a fourth number of high-speed devices associated with the second standard interface; when the third number is greater than the fourth number, determine the second processing core through the fourth number, wherein the fourth number and the fifth number of the second processing cores satisfy a preset proportional relationship, and the preset proportional relationship is determined by the performance level of the central processing unit.

[0100] In an exemplary embodiment, the determination module 92 is also used to: determine the sixth number of high-speed serial computer expansion bus standard root complexes in the server through a command line tool, wherein the command line tool is used to obtain detailed information of high-speed serial computer expansion bus standard devices in the server; and determine the fourth number of high-speed devices associated with the second standard interface through the sixth number.

[0101] In an exemplary embodiment, the binding module 94 is also used to: determine the interface address of the second standard interface; and allocate a number of second processing cores that satisfy the preset ratio to the second standard interface; and bind the interface address to the number of second processing cores that satisfy the preset ratio.

[0102] In an exemplary embodiment, the determination module 92 is also used to: determine the third standard interface corresponding to the central processing unit, wherein the first standard interface includes: the third standard interfaces respectively corresponding to the multiple central processing units deployed in the server; determine the fourth standard interface in the third standard interface to which a high-speed device is connected; and determine the second standard interface from the fourth standard interface.

[0103] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0104] Optionally, in this embodiment, the storage medium may be configured to store a computer program for performing the following steps:

[0105] S1, determining a second processing core in a first processing core corresponding to a central processor of a server that is allowed to be divided into a virtualized resource pool, wherein the first processing core is a logical processing core; and determining a second standard interface in a first standard interface for connecting a high-speed device in the server that is allowed to be divided into a virtualized resource pool;

[0106] S2: Bind the second processing core to the second standard interface in the virtualized resource pool, so that the second processing core is only used to provide computing resources for the second standard interface that is bound to the second processing core.

[0107] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0108] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0109] Optionally, in this embodiment, the processor may be configured to perform the following steps through a computer program:

[0110] S1, determining a second processing core in a first processing core corresponding to a central processor of a server that is allowed to be divided into a virtualized resource pool, wherein the first processing core is a logical processing core; and determining a second standard interface in a first standard interface for connecting a high-speed device in the server that is allowed to be divided into a virtualized resource pool;

[0111] S2: Bind the second processing core to the second standard interface in the virtualized resource pool, so that the second processing core is only used to provide computing resources for the second standard interface that is bound to the second processing core.

[0112] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0113] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments are implemented.

[0114] Optionally, in this embodiment, the computer program product may be configured to perform the following steps through a computer program:

[0115] S1, determining a second processing core in a first processing core corresponding to a central processor of a server that is allowed to be divided into a virtualized resource pool, wherein the first processing core is a logical processing core; and determining a second standard interface in a first standard interface for connecting a high-speed device in the server that is allowed to be divided into a virtualized resource pool;

[0116] S2: Bind the second processing core to the second standard interface in the virtualized resource pool, so that the second processing core is only used to provide computing resources for the second standard interface that is bound to the second processing core.

[0117] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0118] An embodiment of the present application also provides a computer program, which includes computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps in any one of the above method embodiments.

[0119] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0120] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0121] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for binding a processing core, characterized in that: include: Determine a second processing core in a first processing core corresponding to a central processor of the server that is allowed to be divided into a virtualized resource pool, wherein the first processing core is a logical processing core; and Determine a second standard interface in a server that is used to connect a high-speed device and is allowed to be divided into a virtualized resource pool; The second processing core is bound to the second standard interface in the virtualized resource pool, so that the second processing core is only used to provide computing resources for the second standard interface that is bound to the second processing core.

2. The method according to claim 1, characterized in that Determining a second processing core in a first processing core corresponding to a central processing unit of a server that is allowed to be divided into a virtualized resource pool includes: In the case where it is determined that the current state of the basic input and output system of the server meets a preset condition, determining a third processing core in the first processing core for executing a regular business of the server; The second processing core that is allowed to be divided into the virtualized resource pool is selected from fourth processing cores, wherein the fourth processing core is a processing core among the first processing cores except the third processing core.

3. The method according to claim 2, characterized in that Before determining a third processing core in the first processing core for executing a regular service of the server, the method further includes: determining whether a hierarchical switch is pre-deployed in the basic input and output system, wherein the hierarchical switch is used to manage a plurality of sub-class function items in the basic input and output system, the plurality of sub-class function items are associated with a binding event, and the binding event is used to indicate binding the second processing core to the second standard interface; In the case where the hierarchical switch is pre-deployed in the basic input and output system and the server state of the server satisfies a preset state, the hierarchical switch is started to simultaneously start the multiple sub-category function items, wherein the preset state at least includes: the server performs a storage-type service, wherein, in the case where the server performs a storage-type service, the multiple sub-category function items at least include: CPU turbo acceleration, non-uniform memory access, hyperthreading technology, and Intel virtualization technology; In the case where the hierarchical switch is not pre-deployed in the basic input and output system and the server state of the server satisfies a preset state, starting the multiple sub-category function items in sequence according to a preset order; When it is detected that the plurality of sub-category function items are all in the startup state, it is determined that the current state of the basic input and output system of the server meets a preset condition.

4. The method according to claim 2, characterized in that: Selecting the second processing core that is allowed to be divided into the virtualized resource pool from the fourth processing core includes: Determining a first number of central processing units deployed in the server, and determining a second number of threads supported by the central processing unit; determining a third number of the fourth processing cores and a fourth number of high-speed devices associated with a second standard interface based on the first number and the second number; When the third number is greater than the fourth number, the second processing core is determined by the fourth number, wherein the fourth number and the fifth number of the second processing cores satisfy a preset proportional relationship, and the preset proportional relationship is determined by the performance level of the central processing unit.

5. The method according to claim 4, characterized in that Determining a fourth number of high-speed devices associated with the second standard interface includes: Determining a sixth number of high-speed serial computer expansion bus standard root complexes in the server by using a command line tool, wherein the command line tool is used to obtain detailed information of high-speed serial computer expansion bus standard devices in the server; A fourth number of high-speed devices associated with the second standard interface is determined by the sixth number.

6. The method according to claim 4, characterized in that Binding the second processing core to the second standard interface in the virtualized resource pool includes: determining an interface address of the second standard interface; and Allocating a number of second processing cores satisfying the preset ratio relationship to the second standard interface; The interface address is bound to the second processing cores whose quantity satisfies the preset ratio relationship.

7. The method according to claim 1, characterized in that Determining a second standard interface in a server that is used to connect a high-speed device and is allowed to be divided into a virtualized resource pool includes: Determine a third standard interface corresponding to the central processing unit, wherein the first standard interface includes: the third standard interfaces respectively corresponding to the plurality of central processing units deployed in the server; Determine that a fourth standard interface of the third standard interface is connected to a high-speed device; The second standard interface is determined from the fourth standard interfaces.

8. A binding device for a processing core, characterized in that: include: A determination module, configured to determine a second processing core in a first processing core corresponding to a central processor of a server that is allowed to be divided into a virtualized resource pool, wherein the first processing core is a logical processing core; and to determine a second standard interface in a first standard interface for connecting a high-speed device in the server that is allowed to be divided into a virtualized resource pool; A binding module is used to bind the second processing core to the second standard interface in the virtualized resource pool so that the second processing core is only used to provide computing resources for the second standard interface that is bound to the second processing core.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 7 when executed by a processor.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 7 are implemented.

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