Data transmission system and method, computer equipment and storage medium

Abstract

The invention relates to a data transmission system and method, computer equipment and a storage medium. The system comprises a substrate management controller, a complex programmable logic device, a first multiplexer group, a second multiplexer group, a processor and a plurality of storage chips, the substrate management controller and the processor are respectively connected with the complex programmable logic device; the storage chips at least comprise a first storage chip, a second storage chip, a third storage chip and a fourth storage chip; the first multiplexer group is used for receiving a control signal transmitted by the complex programmable logic device to conduct any data transmission channel between the substrate management controller and the first storage chip, the second storage chip and the third storage chip; and the second multiplexer group is used for receiving the control signal transmitted by the complex programmable logic device and conducting the processor with any data transmission channel in the third storage chip and the fourth storage chip according to the control signal. By adopting the system, the reliability of data transmission can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer security technology, and in particular to a data transmission system, method, computer device and storage medium. Background Art

[0002] The devices that need SPI FLASH (flash memory based on high-speed, full-duplex synchronous serial bus) in existing servers are mainly CPU (central processing unit), BMC (baseboard management controller) and some SW chips (switch chips). These devices need to read the information in FLASH (flash memory) when starting up to complete initialization. Usually, the information in the first version of FLASH is burned into the chip offline at the factory. When the subsequent debugging is carried out, the updated burning file is mostly burned manually using a burner. When the BMC function development becomes mature, it can support remote refresh of FLASH.

[0003] SPI controller can transfer data between various types of peripheral devices. SPI supports multi-slave mode. In the prior art, multiple NSS (a signal line of SPI) or daisy chain is generally used to connect the host and the slave to enable data transmission between the host and the slave. However, each slave needs a separate NSS line when using the NSS mode. The corresponding NSS signal line is pulled low to communicate with the corresponding slave. However, if two NSS signal lines are pulled low at the same time, the slaves may try to transmit data on the same MISO (a signal line of SPI) line, which may cause garbled received data. When using the daisy chain mode, once a slave in the data link fails, the slaves with lower priority below it cannot be served, which reduces the reliability of the system. Summary of the invention

[0004] Based on this, it is necessary to provide a data transmission system, method, computer device and storage medium that can improve the reliability of the server system in response to the above technical problems.

[0005] In order to solve the above technical problems, in a first aspect, a data transmission system is provided, the system comprising:

[0006] A baseboard management controller, a complex programmable logic device, a multiplexer group, a processor, and a plurality of memory chips;

[0007] The baseboard management controller and the processor are respectively connected to the complex programmable logic device, the baseboard management controller and the processor are both connected to the multiplexer group, and the multiplexer group is connected to a plurality of storage chips;

[0008] The plurality of memory chips include a first memory chip, a second memory chip, a third memory chip and a fourth memory chip;

[0009] The multiplexer group includes a first multiplexer group and a second multiplexer group, the first multiplexer group is used to receive a control signal transmitted by the complex programmable logic device, and conduct a data transmission channel between the baseboard management controller and any one of the first storage chip, the second storage chip, and the third storage chip according to the control signal;

[0010] The second multiplexer group is used to receive a control signal transmitted by the complex programmable logic device, and to conduct a data transmission channel between the processor and any one of the third storage chip and the fourth storage chip according to the control signal.

[0011] In one embodiment, the first multiplexer group includes a first multiplexer, a second multiplexer, a third multiplexer, a fourth multiplexer, a fifth multiplexer, and a sixth multiplexer; the second memory chip also includes a first sub-memory chip and a second sub-memory chip;

[0012] The first interface of the first multiplexer is connected to the baseboard management controller, the second interface of the first multiplexer is connected to the first storage chip, and the third interface of the first multiplexer is connected to the first interface of the second multiplexer; the first interface of the third multiplexer is connected to the second interface of the second multiplexer, the second interface of the third multiplexer is connected to the second interface of the fourth multiplexer, the third interface of the third multiplexer is connected to the second interface of the fifth multiplexer, the first interface of the fourth multiplexer and the first interface of the fifth multiplexer are connected to the first sub-storage chip and the second sub-storage chip respectively, and the third interface of the fourth multiplexer and the third interface of the fifth multiplexer are connected to the first switching chip and the second switching chip respectively;

[0013] The first interface of the sixth multiplexer is connected to the third interface of the second multiplexer, and the second interface of the sixth multiplexer is connected to the third storage chip;

[0014] The control ends of the first multiplexer, the second multiplexer, the third multiplexer, the fourth multiplexer, the fifth multiplexer and the sixth multiplexer are respectively connected to the output ends of the complex programmable logic device.

[0015] In one embodiment, the second multiplexer group includes a seventh multiplexer and an eighth multiplexer, the first interface of the seventh multiplexer is connected to the third interface of the eighth multiplexer, the second interface of the seventh multiplexer is connected to the third storage chip, the first interface of the eighth multiplexer is connected to the processor, and the second interface of the eighth multiplexer is connected to the fourth storage chip; the control ends of the seventh multiplexer and the eighth multiplexer are respectively connected to the output ends of the complex programmable logic device.

[0016] In order to solve the above technical problem, in a second aspect, a data transmission method is provided, applying any one of the above data transmission systems of the claims, the method comprising:

[0017] In response to the baseboard management controller and / or the processor acquiring the target memory chip information, a control instruction is generated according to the target memory chip information, and the control instruction is sent to the complex programmable logic device;

[0018] In response to the complex programmable logic device receiving the control instruction, generating a control signal according to the control instruction, and transmitting the control signal to the first multiplexer group and / or the second multiplexer group;

[0019] In response to the first multiplexer group and / or the second multiplexer group receiving a control signal, the signal value corresponding to the target signal of each multiplexer in the first multiplexer group and / or the second multiplexer group is controlled according to the control signal, thereby realizing data transmission between the baseboard management controller and / or the processor and the target storage chip.

[0020] In one embodiment, the target memory chip is a first memory chip, and the method further includes:

[0021] In response to the baseboard management controller acquiring the first storage chip information, a first control instruction is generated according to the first storage chip information, and the first control instruction is sent to the complex programmable logic device; the first control instruction carries the level signal of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal and the second pin transmits a low-level control signal;

[0022] In response to the complex programmable logic device receiving the first control instruction, generating a first control signal according to the first control instruction, and transmitting the first control signal to the first multiplexer group,

[0023] In response to the first multiplexer group receiving the first control signal, the signal value of the target signal of the first multiplexer of the first multiplexer group is controlled to be the minimum value, thereby connecting the first interface of the first multiplexer and the second interface of the first multiplexer to realize data transmission between the baseboard management controller and the first storage chip.

[0024] In one embodiment, the target memory chip is a first sub-memory chip in a second memory chip, and the method further includes:

[0025] In response to the baseboard management controller acquiring the first sub-storage chip information, a second control instruction is generated according to the first sub-storage chip information, and the second control instruction is sent to the complex programmable logic device; the second control instruction carries the level signal of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal and the second pin transmits a low-level control signal;

[0026] In response to the complex programmable logic device receiving the second control instruction, generating a second control signal according to the second control instruction, and transmitting the second control signal to the first multiplexer group;

[0027] In response to the first multiplexer group receiving the second control signal, controlling the signal value of the target signal of the first multiplexer to be the maximum value, thereby conducting the first interface of the first multiplexer and the third interface of the first multiplexer;

[0028] Controlling the signal value of the target signal of the second multiplexer to be the minimum value, thereby conducting the first interface of the second multiplexer and the second interface of the second multiplexer;

[0029] Controlling the signal value of the target signal of the third multiplexer to be the minimum value, thereby conducting the first interface of the third multiplexer and the second interface of the third multiplexer;

[0030] The signal value of the target signal of the fourth multiplexer is controlled to be the minimum value; thereby connecting the first interface of the fourth multiplexer and the second interface of the fourth multiplexer, thereby realizing data transmission between the baseboard management controller and the first sub-storage chip information.

[0031] In one embodiment, the target memory chip is a second sub-memory chip in the second memory chip, and the method further includes:

[0032] In response to the baseboard management controller acquiring the second sub-storage chip information, a third control instruction is generated according to the second sub-storage chip information, and the third control instruction is sent to the complex programmable logic device; the third control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal and the second pin transmits a high-level control signal;

[0033] In response to the complex programmable logic device receiving a third control instruction, generating a third control signal according to the third control instruction, and transmitting the third control signal to the first multiplexer group;

[0034] In response to the first multiplexer group receiving the third control signal, controlling the signal value of the target signal of the first multiplexer to be the maximum value, thereby conducting the first interface of the first multiplexer and the third interface of the first multiplexer;

[0035] Controlling the signal value of the target signal of the second multiplexer to be the minimum value, thereby conducting the first interface of the second multiplexer and the second interface of the second multiplexer;

[0036] Controlling the signal value of the target signal of the third multiplexer to be the maximum value, thereby conducting the first interface of the third multiplexer and the third interface of the third multiplexer;

[0037] The signal value of the target signal of the fifth multiplexer is controlled to be the minimum value; thereby the first interface of the fifth multiplexer is connected to the second interface of the fifth multiplexer, thereby realizing data transmission between the baseboard management controller and the second sub-storage chip.

[0038] In one embodiment, the target memory chip is a third memory chip, and the method further includes:

[0039] In response to the baseboard management controller acquiring the third storage chip information, a fourth control instruction is generated according to the third storage chip information, and the fourth control instruction is sent to the complex programmable logic device; the fourth control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal and the second pin transmits a high-level control signal;

[0040] In response to the complex programmable logic device receiving a fourth control instruction, generating a fourth control signal according to the fourth control instruction, and transmitting the fourth control signal to the first multiplexer group;

[0041] In response to the first multiplexer group receiving the fourth control signal, the signal value of the target signal of the first multiplexer is controlled to be the maximum value, thereby conducting the first interface of the first multiplexer and the third interface of the first multiplexer;

[0042] Controlling the signal value of the target signal of the second multiplexer to be the maximum value, thereby conducting the first interface of the second multiplexer and the third interface of the second multiplexer;

[0043] The signal value of the target signal of the sixth multiplexer is controlled to be the minimum value, thereby connecting the first interface of the sixth multiplexer and the second interface of the sixth multiplexer; thereby realizing data transmission between the baseboard management controller and the third storage chip.

[0044] In one embodiment, the target memory chip is a third memory chip, and the method further includes:

[0045] In response to the processor acquiring the third storage chip information, a fifth control instruction is generated according to the third storage chip information, and the fifth control instruction is sent to the complex programmable logic device; the fifth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a high-level control signal;

[0046] In response to the complex programmable logic device receiving a fifth control instruction, generating a fifth control signal according to the fifth control instruction, and transmitting the fifth control signal to the second multiplexer group;

[0047] In response to the second multiplexer group receiving the fifth control signal, the signal value of the target signal of the seventh multiplexer is controlled to be the minimum value, thereby conducting the first interface of the seventh multiplexer and the second interface of the seventh multiplexer;

[0048] The signal value of the target signal of the eighth multiplexer is controlled to be the maximum value, thereby connecting the first interface of the eighth multiplexer and the third interface of the eighth multiplexer; thereby realizing data transmission between the processor and the third storage chip.

[0049] In one embodiment, the target memory chip is a fourth memory chip, and the method further includes:

[0050] In response to the processor acquiring the fourth storage chip information, a sixth control instruction is generated according to the fourth storage chip information, and the sixth control instruction is sent to the complex programmable logic device; the sixth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a low-level control signal;

[0051] In response to the complex programmable logic device receiving a sixth control instruction, generating a sixth control signal according to the sixth control instruction, and transmitting the sixth control signal to the second multiplexer group;

[0052] In response to the second multiplexer group receiving the sixth control signal, the signal value of the target signal of the eighth multiplexer is controlled to be the minimum value, thereby turning on the first interface of the eighth multiplexer and the second interface of the eighth multiplexer; thereby realizing data transmission between the processor and the fourth memory chip.

[0053] In order to solve the above technical problem, a third aspect provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program: the processor implements the steps of the above first aspect method when executing the computer program.

[0054] In order to solve the above technical problems, in a fourth aspect, the present application provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the method of the above first aspect are implemented.

[0055] Different from the prior art, the present application provides a data transmission system, the system includes: a baseboard management controller, a complex programmable logic device, a multiplexer group, a processor and a plurality of memory chips; the baseboard management controller and the processor are respectively connected to the complex programmable logic device, the baseboard management controller and the processor are both connected to the multiplexer group, and the multiplexer group is connected to the multiple memory chips; the multiple memory chips include a first memory chip, a second memory chip, a third memory chip and a fourth memory chip; the multiplexer group includes a first multiplexer group and a second multiplexer group, the first multiplexer group is used to receive a control signal transmitted by the complex programmable logic device, and conduct the baseboard management controller with any data transmission channel in the first memory chip, the second memory chip and the third memory chip according to the control signal; the second multiplexer group is used to receive a control signal transmitted by the complex programmable logic device, and conduct the processor with any data transmission channel selector group in the third memory chip and the fourth memory chip according to the control signal. In this way, the interface of the multiplexer can be conducted according to the control instruction, the data interaction between the baseboard management controller and the processor and the multiple memory chips can be realized, and the reliability of data transmission can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 It is a structural block diagram of a data transmission system in the prior art;

[0057] Figure 2 It is a structural block diagram of a data transmission system in the prior art;

[0058] Figure 3 is a structural block diagram of a data transmission system in one embodiment;

[0059] Figure 4 is a schematic diagram of the structure of a data transmission system in another embodiment;

[0060] Figure 5 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0062] See also Figure 1In the prior art, multiple NSS (a signal line of SPI) are used to connect the host and the slave. In the NSS mode, each slave requires a separate NSS line. If you want to communicate with a specific slave, you can pull the corresponding NSS signal line low and keep the state of other NSS signal lines at a high level; if two NSS signal lines are pulled low at the same time, garbled characters may appear, because the slaves may try to transmit data on the same MISO line, which will eventually lead to garbled received data and reduced system reliability.

[0063] See also Figure 2 In the prior art, a daisy chain is used to connect the host and the slave, and the device signal is transmitted from one slave to the next in a serial manner, and the cycle continues until the data reaches the target slave. The biggest disadvantage of the daisy chain is that the signal is transmitted serially. Once a slave in the data link fails, the slaves with lower priorities below it cannot be served. On the other hand, the farther the slave is from the host, the lower the priority of obtaining service. Therefore, the priority of the slaves needs to be arranged, and a bus detector needs to be set. If a slave times out, the slave is short-circuited to prevent the entire link from collapsing due to damage to a single slave, and the maintenance cost is high.

[0064] In view of the above technical problems, in one embodiment, Figure 3 As shown, the present application provides a data transmission system, which includes a baseboard management controller, a complex programmable logic device, a multiplexer group, a processor, and multiple memory chips.

[0065] Among them, the baseboard management controller (BMC) is located on the board and is a dedicated controller used to monitor and manage the server.

[0066] The complex programmable logic device (CPLD) is located on the mainboard. The complex programmable logic device is connected to the baseboard management controller and the processor through pins. The baseboard management controller has a first pin and a second pin. The first pin and the second pin are located at Figure 3 The GPIO on the BMC also includes the first pin on the processor, and the pin here can be GPIO. The motherboard is essentially a switch board with two CXL SW chips (hereinafter referred to as SW chips) on it. It needs to read the information in FLASH to complete its own initialization. The information in SW0 FLASH0 and SW1 FLASH1 is initially burned offline by the factory, and can be burned manually through a burner later, or remotely burned by the baseboard management controller.

[0067] The processor is located on a processor board, which is located on a mainboard. The processor may be a CPU or an MCPU or other types of processors. The figure takes the MCPU as an example.

[0068] The plurality of memory chips include a first memory chip, a second memory chip, a third memory chip and a fourth memory chip. The plurality of memory chips are respectively located on a baseboard management controller board, a mainboard, a processor board and a processor expansion card (MCPU RISER); the memory chips may be FLASH, PROM, EPROM and the like memory chips. Exemplarily, the plurality of memory chips may include: Figure 3 Shown are the BMC FLASH (first storage chip) on the board, FLASH0 (first sub-storage chip in the second storage chip) on the mainboard, FLASH1 (second sub-storage chip in the second storage chip) on the mainboard, BIOS FLASH0 on the server expansion card, and BIOS FLASH1 on the processor board.

[0069] like Figure 4 As shown in the figure, the processor expansion card is placed on the mainboard, with a BIOS FLASH0 and two multiplexers. BIOS FLASH0 is an external flash memory for the processor. There is also a TYPE7 connector on the processor expansion card, which can be plugged into the mainboard. There is also another flash memory for the MCPU on the processor card - BIOS FLASH1.

[0070] A multiplexer (MUX) group includes a first multiplexer group and a second multiplexer group. The first multiplexer group is used to receive a control signal transmitted by the complex programmable logic device, and to conduct a data transmission channel between the baseboard management controller and any one of the first storage chip, the second storage chip, and the third storage chip according to the control signal; the second multiplexer group is used to receive a control signal transmitted by the complex programmable logic device, and to conduct a data transmission channel selector group between the processor and any one of the third storage chip and the fourth storage chip according to the control signal.

[0071] like Figure 3As shown, the first multiplexer group includes a first multiplexer (MUX1), a second multiplexer (MUX2), a third multiplexer (MUX3), a fourth multiplexer (MUX4), a fifth multiplexer (MUX5) and a sixth multiplexer (MUX6); the second storage chip also includes a first sub-storage chip (FLASH0 located on the mainboard) and a second sub-storage chip (FLASH1 located on the mainboard); the first interface (D) of the first multiplexer is connected to the baseboard management controller (BMC), the second interface (A) of the first multiplexer is connected to the first storage chip, and the third interface (B) of the first multiplexer is connected to the first interface (D) of the second multiplexer.

[0072] The first interface (D) of the third multiplexer is connected to the second interface (A) of the second multiplexer, the second interface (A) of the third multiplexer is connected to the second interface (A) of the fourth multiplexer, the third interface (B) of the third multiplexer is connected to the second interface (A) of the fifth multiplexer, the first interface (D) of the fourth multiplexer and the first interface (D) of the fifth multiplexer are connected to the first sub-storage chip and the second sub-storage chip respectively, and the third interface (B) of the fourth multiplexer and the third interface (B) of the fifth multiplexer are connected to the first switching chip and the second switching chip respectively.

[0073] The sixth multiplexer and the fourth memory chip are located on the processor expansion card, the first interface (D) of the sixth multiplexer is connected to the third interface (B) of the second multiplexer, and the second interface (A) of the sixth multiplexer is connected to the third memory chip.

[0074] Specifically, the baseboard management controller board includes a baseboard management controller, a first multiplexer and a first storage chip. The first interface (D) of the first multiplexer is connected to the baseboard management controller (BMC), the second interface (A) of the first multiplexer (MUX1) is connected to the first storage chip (BMC FLASH), and the third interface (B) of the first multiplexer (MUX1) is connected to the first interface (D) of the second multiplexer. By controlling the conduction between the first interface (D) of the first multiplexer and the second interface (A) of the first multiplexer, data transmission between the baseboard management controller and the first storage chip on the baseboard management controller board can be achieved. By controlling the conduction between the first interface (D) of the first multiplexer and the third interface (B) of the first multiplexer, data transmission between the baseboard management controller and the second multiplexer on the mainboard can be achieved, thereby providing the possibility of realizing data transmission between the baseboard management controller and the storage chip on the mainboard.

[0075] Specifically, the main board includes a second multiplexer, a third multiplexer, a fourth multiplexer and a fifth multiplexer. By conducting the interfaces of the multiple multiplexers, the first interface (D) of the second multiplexer is controlled to be connected to the third interface (B) of the first multiplexer, the second interface (A) of the second multiplexer is controlled to be connected to the first interface (D) of the third multiplexer, the second interface (A) of the third multiplexer is connected to the first end of the first level conversion chip, the second end of the first level conversion chip is connected to the second interface (A) of the fourth multiplexer, and the first interface (D) of the fourth multiplexer is connected to the first sub-storage chip of the second storage chip, thereby realizing the data transmission channel between the baseboard management controller and the second sub-storage chip.

[0076] In another embodiment, by conducting the interfaces of multiple multiplexers, it is possible to control the first interface (D) of the second multiplexer to be connected to the third interface (B) of the first multiplexer, the second interface (A) of the second multiplexer to be connected to the first interface (D) of the third multiplexer, the third interface (B) of the third multiplexer to be connected to the first end of the second level conversion chip, the second end of the second level conversion chip to be connected to the second interface (A) of the fifth multiplexer, and the first interface (D) of the fifth multiplexer to be connected to the second sub-storage chip of the second storage chip, thereby conducting the data transmission channel between the baseboard management controller and the second sub-storage chip.

[0077] In one embodiment, the second multiplexer group also includes a seventh multiplexer and an eighth multiplexer, the seventh multiplexer is located on a processor expansion card, the eighth multiplexer and the fourth memory chip are located on a processor board, the first interface (D) of the seventh multiplexer is connected to the third interface (B) of the eighth multiplexer, the second interface (A) of the seventh multiplexer is connected to the third memory chip, the first interface (D) of the eighth multiplexer is connected to the processor, and the second interface (A) of the eighth multiplexer is connected to the basic input and output system and the fourth memory chip.

[0078] Specifically, the processor expansion card includes a sixth multiplexer, a seventh multiplexer, and a third memory chip. In this embodiment, by connecting the multiplexer interface, the connection between the substrate manager, the first multiplexer, the second multiplexer, the sixth multiplexer, and the third memory chip is controlled, and the data transmission channel of the third memory chip of the substrate management controller is connected. The processor main board includes a substrate input and output system (BIOS), an eighth multiplexer, a processor, and a fourth memory chip. The fourth memory chip is connected to the second interface (A) of the eighth multiplexer. By connecting the first interface (D) of the eighth multiplexer and the second interface (A) of the eighth multiplexer, the data transmission channel between the processor and the fifth memory chip can be connected.

[0079] In another embodiment, the data transmission channel between the processor and the third memory chip can be connected by connecting the first interface (D) of the eighth multiplexer and the second interface (A) of the eighth multiplexer, and the first interface (D) of the seventh multiplexer and the second interface (A) of the seventh multiplexer.

[0080] This application supports connecting multiple slaves (memory chips) under a master device (baseboard management controller, processor), but only one line will be connected in the same time period; it supports the method of remotely burning all memory chips in the system by the baseboard management controller, which is implemented by using multiple multiplexers, and controlling multiple multiplexers through the pin interface of a complex programmable logic device, thereby realizing specific path selection, so as to achieve the function of the baseboard management controller burning the firmware in the memory chip or the device reading the data transmission data in the memory chip.

[0081] This scheme has a total of 8 multiplexers, and the functions of each multiplexer are the same, and they are all two-choice signal selectors. The control end of each multiplexer is connected to the output end of the complex programmable logic device to obtain the control signal transmitted by the complex programmable logic device. The control signal is used to control the signal value of the target signal (SEL signal) in the multiplexer. Figure 1 The SEL signal (target signal) and EN_L (first signal) are not drawn in the figure. The EN_L signal is grounded, indicating that the multiplexer chip is turned on. The SEL signals of all multiplexer chips are connected to the CPLD, and the SEL signal has its own default value.

[0082] In this application, there are 2 GPIOs between CPLD and BMC, and the default values ​​of both GPIOs are low. When BMC wants to burn other FLASH, it will send a GPIO signal to CPLD. CPLD reads the GPIO status, determines the operation that BMC wants to perform, and then controls the SEL signal of each MUX to achieve its function.

[0083] The following table 1 shows the correspondence between BMC functions and two GPIOs, where GPIO0 is the first pin, GPIO1 is the second pin, and the value corresponding to GPIO0 or GPIO1 is 0, which means that the pin transmits a low-level control signal. The value corresponding to GPIO0 or GPIO1 is 1, which means that the pin transmits a high-level control signal:

[0084]

[0085] Table 1

[0086] As shown in the table, when CPLD detects the GPIO sent by BMC, it will control the corresponding interface to output SEL (target signal of the multiplexer) information. The following Table 2 shows the correspondence between BMC functions and the SEL signals of MUX, where MUX1, MUX2, MUX3, MUX4, MUX5, MUX6, MUX7, and MUX8 correspond to the first multiplexer, the second multiplexer, the third multiplexer, the fourth multiplexer, the fifth multiplexer, the sixth multiplexer, the seventh multiplexer, and the eighth multiplexer in this application; each multiplexer corresponds to different values ​​under various conditions, where 0 is the minimum value, representing that the first interface of the corresponding multiplexer is connected to the second interface of the multiplexer, 1 is the maximum value, representing that the first interface of the corresponding multiplexer is connected to the third interface of the multiplexer, and X represents an indeterminate state, and no matter how much the value of X is, it has no effect on the result:

[0087]

[0088] Table 2

[0089] In one embodiment, a data transmission method is provided. Figure 3 Taking the data transmission system in the example as an example, the following steps are included:

[0090] In response to the baseboard management controller and / or the processor acquiring the target memory chip information, a control instruction is generated according to the target memory chip information, and the control instruction is sent to the complex programmable logic device;

[0091] In response to the complex programmable logic device receiving the control instruction, generating a control signal according to the control instruction, and transmitting the control signal to the first multiplexer group and / or the second multiplexer group;

[0092] In response to the first multiplexer group and / or the second multiplexer group receiving a control signal, the signal value corresponding to the target signal of each multiplexer in the first multiplexer group and / or the second multiplexer group is controlled according to the control signal, thereby realizing data transmission between the baseboard management controller and / or the processor and the target storage chip.

[0093] In the present application, a corresponding control instruction may be generated according to which storage chip the baseboard management controller or processor needs to interact with for data, and the control instruction is sent to the CPLD. The CPLD generates a corresponding control signal according to the control instruction. The output end of the CPID is connected to each multiplexer to transmit the control signal to the multiplexer. The generation process here may be generated by looking up the above Table 1 and / or Table 2. For example, when the BMC reads the BMC FLASH, the values ​​of the first pin (GPIO0) and the second pin (GPIO1) on the BMC may be set to 0 according to Table 1, that is, the first pin transmits a low-level control signal, and the second pin transmits a high-level control signal. According to Table 2, when the BMC reads the BMC FLASH, the signal value of the target signal of the first multiplexer is set to 0, and the signal values ​​of the target signals of the remaining multiplexers are X. At this time, the BMC can read the data in the BMC FLASH. In this way, by looking up the table, the control signal can be quickly and accurately obtained to execute the conduction of the interface of the multiplexer.

[0094] In one embodiment, the target memory chip is a first memory chip, and the method further includes: in response to the baseboard management controller acquiring the first memory chip information, generating a first control instruction according to the first memory chip information, and sending the first control instruction to the complex programmable logic device; the first control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal and the second pin transmits a low-level control signal; in response to the complex programmable logic device receiving the first control instruction, generating a first control signal according to the first control instruction, and transmitting the first control signal to the first multiplexer group, in response to the first multiplexer group receiving the first control signal, controlling the signal value of the target signal of the first multiplexer of the first multiplexer group to be the minimum value, thereby turning on the first interface of the first multiplexer and the second interface of the first multiplexer, and realizing data transmission between the baseboard management controller and the first memory chip.

[0095] Specifically, in a specific implementation, when the BMC (baseboard management controller) obtains information in the BMCFLASH (first storage chip) on the BMC board, first, the BMC generates a first control instruction to the CPLD, wherein the first control instruction carries the first pin and the second pin signals, and the values ​​of the control signals transmitted by the first pin and the second pin on the BMC are both 0. When the values ​​of the control signals transmitted by the first pin and the second pin on the BMC are both 0, the control signal transmitted by the first pin and the control signal transmitted by the second pin are both low-level control signals. After the CPLD receives the first control instruction sent by the BMC, the CPLD sends a first control signal. In response to the first multiplexer receiving the first control signal, the signal value of the target signal controlling the first multiplexer is 0, wherein the corresponding first signal of the multiplexer is EN_L, the corresponding target signal of the multiplexer is SEL, the first signal in this application is grounded, and the model value of the first signal defaults to 0. At this time, the first interface (D) of the first multiplexer is connected to the second interface (A) of the first multiplexer. At this time, the BMC can transmit data through the data channel between the BMC and the BMC FLASH formed between the first interface (D) and the second interface (A) of the first multiplexer.

[0096] In the present application, the values ​​of the control signals of the first pin and the second pin corresponding to different control instructions are transmitted to the CPLD through control instructions, so that the CPLD controls the signal value of the target signal of the multiplexer, thereby realizing the selective conduction of the data channel in the multiplexer.

[0097] In one embodiment, the target memory chip is a first sub-memory chip in a second memory chip, and the method further includes: in response to a baseboard management controller acquiring information about the first sub-memory chip, generating a second control instruction according to the information about the first sub-memory chip, and sending the second control instruction to a complex programmable logic device; the second control instruction carries level signals of a first pin and a second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal and the second pin transmits a low-level control signal; in response to the complex programmable logic device receiving the second control instruction, generating a second control signal according to the second control instruction, and transmitting the second control signal to the first multiplexer group; in response to the first multiplexer group receiving the second control signal , control the signal value of the target signal of the first multiplexer to be the maximum value, thereby connecting the first interface of the first multiplexer and the third interface of the first multiplexer; control the signal value of the target signal of the second multiplexer to be the minimum value, thereby connecting the first interface of the second multiplexer and the second interface of the second multiplexer; control the signal value of the target signal of the third multiplexer to be the minimum value, thereby connecting the first interface of the third multiplexer and the second interface of the third multiplexer; control the signal value of the target signal of the fourth multiplexer to be the minimum value; thereby connecting the first interface of the fourth multiplexer and the second interface of the fourth multiplexer, thereby realizing data transmission between the baseboard management controller and the first sub-storage chip information.

[0098] When the BMC needs to remotely burn the information in FLASH0 (the first sub-storage chip) on the motherboard, the BMC will generate a second control instruction to the CPLD, wherein the second control instruction carries the first pin and the second pin signal, the value of the control signal transmitted by the first pin on the BMC is 1, and the value of the control signal transmitted by the second pin is 0, that is, the control signal transmitted by the first pin is a high-level control signal, and the control signal transmitted by the second pin is a low-level control signal. After the CPLD receives the second control instruction, the CPLD will send a second control signal, in response to the first multiplexer, the second multiplexer, the third multiplexer and the fourth multiplexer receiving the second control signal, the signal value of the target signal of the first multiplexer is controlled to be 1. At this time , the first interface (D) of the first multiplexer is connected to the third interface (B) of the first multiplexer; the signal value of the target signal of the second multiplexer is controlled to be 0, at this time, the first interface (D) of the second multiplexer is connected to the second interface (A) of the second multiplexer; the signal value of the target signal of the third multiplexer is controlled to be 0, at this time, the first interface (D) of the third multiplexer is connected to the second interface (A) of the third multiplexer; the signal value of the target signal of the fourth multiplexer is controlled to be 0, at this time, the first interface (D) of the fourth multiplexer is connected to the second interface (A) of the fourth multiplexer, at this time, the BMC can transmit data through the data channel between the BMC and FLASH0 on the mainboard formed by multiple multiplexers.

[0099] In one embodiment, the target memory chip is a second sub-memory chip in the second memory chip, and the method further includes:

[0100] In response to the baseboard management controller acquiring the second sub-storage chip information, a third control instruction is generated according to the second sub-storage chip information, and the third control instruction is sent to the complex programmable logic device; the third control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal and the second pin transmits a high-level control signal; in response to the complex programmable logic device receiving the third control instruction, a third control signal is generated according to the third control instruction, and the third control signal is transmitted to the first multiplexer group; in response to the first multiplexer group receiving the third control signal, the target signal of the first multiplexer is controlled The signal value is the maximum value, thereby connecting the first interface of the first multiplexer and the third interface of the first multiplexer; the signal value of the target signal of the second multiplexer is controlled to be the minimum value, thereby connecting the first interface of the second multiplexer and the second interface of the second multiplexer; the signal value of the target signal of the third multiplexer is controlled to be the maximum value, thereby connecting the first interface of the third multiplexer and the third interface of the third multiplexer; the signal value of the target signal of the fifth multiplexer is controlled to be the minimum value; thereby connecting the first interface of the fifth multiplexer and the second interface of the fifth multiplexer, thereby realizing data transmission between the baseboard management controller and the second sub-storage chip.

[0101] When the BMC needs to remotely burn the information in FLASH1 (the first sub-storage chip) on the motherboard, the BMC will generate a third control instruction to the CPLD. After the CPLD receives the third control instruction, the CPLD will send a third control signal, wherein the second control instruction carries the first pin and the second pin signal, that is, the value of the control signal transmitted by the first pin on the BMC is 0, and the value of the control signal transmitted by the second pin is 1, that is, the control signal transmitted by the first pin is a low-level control signal. In response to the first multiplexer, the second multiplexer, the third multiplexer and the fifth multiplexer receiving the third control signal, the signal value of the target signal of the first multiplexer is controlled to be 1. At this time, the first multiplexer The first interface (D) is connected to the third interface (B) of the first multiplexer; the signal value of the target signal of the second multiplexer is controlled to be 0, at which time, the first interface (D) of the second multiplexer is connected to the second interface (A) of the second multiplexer; the signal value of the target signal of the third multiplexer is controlled to be 1, at which time, the first interface (D) of the third multiplexer is connected to the third interface (B) of the third multiplexer; the signal value of the target signal of the fifth multiplexer is controlled to be 0, at which time, the first interface (D) of the fifth multiplexer is connected to the second interface (A) of the fourth multiplexer, and at this time, the BMC can transmit data through the data channel between the BMC and FLASH1 on the mainboard formed by multiple multiplexers.

[0102] In one embodiment, the target memory chip is a third memory chip, and the method further includes: in response to the baseboard management controller acquiring the third memory chip information, generating a fourth control instruction according to the third memory chip information, and sending the fourth control instruction to the complex programmable logic device; the fourth control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal and the second pin transmits a high-level control signal; in response to the complex programmable logic device receiving the fourth control instruction, generating a fourth control signal according to the fourth control instruction, and transmitting the fourth control signal to the first multiplexer group; in response to the first multiplexer group receiving the fourth control signal, controlling the signal value of the target signal of the first multiplexer to be the maximum value, thereby connecting the first interface of the first multiplexer and the third interface of the first multiplexer; controlling the signal value of the target signal of the second multiplexer to be the maximum value, thereby connecting the first interface of the second multiplexer and the third interface of the second multiplexer; controlling the signal value of the target signal of the sixth multiplexer to be the minimum value, thereby connecting the first interface of the sixth multiplexer and the second interface of the sixth multiplexer; thereby realizing data transmission between the baseboard management controller and the fourth memory chip.

[0103] When the BMC needs to read BIOS FLASH0 (the third storage chip), the BMC will generate a fourth control instruction to the CPLD. After the CPLD receives the fourth control instruction, the CPLD will send a fourth control signal. The second control instruction carries the first pin and the second pin signal, wherein the value of the control signal transmitted by the first pin on the BMC is 1, and the value of the control signal transmitted by the second pin is 1, that is, the control signal transmitted by the first pin is a high-level control signal, and the control signal transmitted by the second pin is a high-level control signal. After the PLD receives the third control instruction, the CPLD will send a third control signal in response to the first multiplexer, the second multiplexer and the third multiplexer. The six multiplexers receive the third control signal, and control the signal value of the target signal of the first multiplexer to be 1. At this time, the first interface (D) of the first multiplexer is connected to the third interface (B) of the first multiplexer; the signal value of the target signal of the second multiplexer is controlled to be 1. At this time, the first interface (D) of the second multiplexer is connected to the second interface (A)(B) of the second multiplexer; the signal value of the target signal of the sixth multiplexer is controlled to be 0. At this time, the first interface (D) of the sixth multiplexer is connected to the second interface (A) of the sixth multiplexer; at this time, the BMC can transmit data through the data channel between the BMC and BIOS FLASH0 formed by multiple multiplexers.

[0104] In one embodiment, the target memory chip is a third memory chip, and the method further includes: in response to the processor acquiring the third memory chip information, generating a fifth control instruction according to the third memory chip information, and sending the fifth control instruction to the complex programmable logic device; the fifth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a high-level control signal;

[0105] In response to the complex programmable logic device receiving the fifth control instruction, a fifth control signal is generated according to the fifth control instruction, and the fifth control signal is transmitted to the second multiplexer group; in response to the second multiplexer group receiving the fifth control signal, the signal value of the target signal of the seventh multiplexer is controlled to be the minimum value, thereby turning on the first interface of the seventh multiplexer and the second interface of the seventh multiplexer; the signal value of the target signal of the eighth multiplexer is controlled to be the maximum value, thereby turning on the first interface of the eighth multiplexer and the third interface of the eighth multiplexer; thereby realizing data transmission between the processor and the third storage chip.

[0106] When the MCPU (microprocessor) obtains the BIOS FLASH0 (the fourth storage chip) on the MCPU RISER, the MCPU generates a fifth control instruction to the CPLD, wherein the fifth control instruction transmits information that the level of the GPIO interface between the MCPU and the CPLD is pulled high. After the CPLD receives the fifth control instruction, the CPLD generates a fifth control signal. In response to the second multiplexer group receiving the fifth control signal, the signal value of the target signal of the seventh multiplexer is controlled to be 0. At this time, the first interface (D) of the seventh multiplexer is connected to the second interface (A) of the seventh multiplexer, and the signal value of the target signal of the eighth multiplexer is 1. At this time, the first interface (D) of the eighth multiplexer is connected to the third interface (B) of the eighth multiplexer; at this time, the MCPU can transmit data through the data channel between the MCPU and the BIOS FLASH0 (the third storage chip) formed between the multiple multiplexers.

[0107] In one embodiment, the target memory chip is a fourth memory chip, and the method further includes: in response to the processor acquiring information about the fourth memory chip, generating a sixth control instruction according to the information about the fourth memory chip, and sending the sixth control instruction to the complex programmable logic device; the sixth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a low-level control signal; in response to the complex programmable logic device receiving the sixth control instruction, generating a sixth control signal according to the sixth control instruction, and transmitting the sixth control signal to the second multiplexer group; in response to the second multiplexer group receiving the sixth control signal, controlling the signal value of the target signal of the eighth multiplexer to be the minimum value, thereby turning on the first interface of the eighth multiplexer and the second interface of the eighth multiplexer; thereby realizing data transmission between the processor and the fourth memory chip.

[0108] When the MCPU (microprocessor) obtains the BIOS FLASH1 (fifth storage chip, not shown) on the MCPU board, the MCPU generates a sixth control instruction to the CPLD, wherein the sixth control instruction transmits the information that the GPIO interface level between the MCPU and the CPLD is pulled low. After the CPLD receives the sixth control instruction, the CPLD generates a sixth control signal, and in response to the second multiplexer group receiving the sixth control signal, controls the signal value of the target signal of the eighth multiplexer to be 0, at which time the first interface (D) of the eighth multiplexer is connected to the second interface (A) of the eighth multiplexer; at this time, the MCPU can transmit data through the data channel between the MCPU and the BIOS FLASH1 (fifth storage chip) formed between the first interface (D) and the second interface (A) of the eighth multiplexer. However, since the first interface (D) in the seventh selector is not connected to the third interface (B) of the seventh multiplexer, the signal here is disconnected.

[0109] From the above description, it can be seen that the present application supports two master devices, BMC and MCPU, to read SPI signals, and supports connecting multiple slaves under one master device; it supports BMC remotely burning all FLASH in the system, using multiple selection switches to achieve this, and controlling the selection switches through the GPIO interface of CPLD, thereby achieving specific path selection, and achieving the function of BMC burning FLASH or device reading FLASH.

[0110] In one embodiment, after a certain storage chip is accessed according to a control instruction, the data transmission data obtained by the data access is verified, and when the verification result is successful, data transmission is performed according to the data transmission data obtained by the data access. Specifically, the data transmission data can be calculated based on a preset verification algorithm to obtain verification data. Among them, the preset verification algorithm can be a message digest algorithm, such as an MD digest algorithm, a one-way hash algorithm (Securi ty Hash Algor i gor i thm, SHA), etc. Exemplarily, after the data transmission file is verified by the message digest algorithm, the verification data obtained includes a message digest, for example, an MD value obtained based on the MD digest algorithm, or a multi-segment message value obtained based on the one-way hash algorithm. The verification data obtained by the calculation can be encrypted together with the upgrade instruction to obtain an encrypted verification data packet, and then the encrypted verification data packet is sent to the main device (baseboard management controller, processor). Before the main device performs data transmission, it can encrypt the data transmission data to obtain encrypted upgrade data, and then transmit the encrypted upgrade data to the main device to improve the security of data transmission.

[0111] For the specific definition of the data transmission system, please refer to the definition of the data transmission method above, which will not be repeated here. Each module in the above data transmission system can be implemented in whole or in part by software, hardware and a combination thereof. The above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0112] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 5 As shown. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a data transmission method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0113] Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0114] In one embodiment, the present application also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the data transmission methods provided by the above methods.

[0115] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program:

[0116] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0117] In response to the baseboard management controller and / or the processor acquiring the target memory chip information, a control instruction is generated according to the target memory chip information, and the control instruction is sent to the complex programmable logic device;

[0118] In response to the complex programmable logic device receiving the control instruction, generating a control signal according to the control instruction, and transmitting the control signal to the first multiplexer group and / or the second multiplexer group;

[0119] In response to the first multiplexer group and / or the second multiplexer group receiving a control signal, the signal value corresponding to the target signal of each multiplexer in the first multiplexer group and / or the second multiplexer group is controlled according to the control signal, thereby realizing data transmission between the baseboard management controller and / or the processor and the target storage chip.

[0120] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0121] The target memory chip is a first memory chip, and the method further includes:

[0122] In response to the baseboard management controller acquiring the first storage chip information, a first control instruction is generated according to the first storage chip information, and the first control instruction is sent to the complex programmable logic device; the first control instruction carries the level signal of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal and the second pin transmits a low-level control signal;

[0123] In response to the complex programmable logic device receiving the first control instruction, generating a first control signal according to the first control instruction, and transmitting the first control signal to the first multiplexer group,

[0124] In response to the first multiplexer group receiving the first control signal, the signal value of the target signal of the first multiplexer of the first multiplexer group is controlled to be the minimum value, thereby connecting the first interface of the first multiplexer and the second interface of the first multiplexer to realize data transmission between the baseboard management controller and the first storage chip.

[0125] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0126] The target memory chip is a first sub-memory chip in the second memory chip, and the method further includes:

[0127] In response to the baseboard management controller acquiring the first sub-storage chip information, a second control instruction is generated according to the first sub-storage chip information, and the second control instruction is sent to the complex programmable logic device; the second control instruction carries the level signal of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal and the second pin transmits a low-level control signal;

[0128] In response to the complex programmable logic device receiving the second control instruction, generating a second control signal according to the second control instruction, and transmitting the second control signal to the first multiplexer group;

[0129] In response to the first multiplexer group receiving the second control signal, controlling the signal value of the target signal of the first multiplexer to be the maximum value, thereby conducting the first interface of the first multiplexer and the third interface of the first multiplexer;

[0130] Controlling the signal value of the target signal of the second multiplexer to be the minimum value, thereby conducting the first interface of the second multiplexer and the second interface of the second multiplexer;

[0131] Controlling the signal value of the target signal of the third multiplexer to be the minimum value, thereby conducting the first interface of the third multiplexer and the second interface of the third multiplexer;

[0132] The signal value of the target signal of the fourth multiplexer is controlled to be the minimum value; thereby connecting the first interface of the fourth multiplexer and the second interface of the fourth multiplexer, thereby realizing data transmission between the baseboard management controller and the first sub-storage chip information.

[0133] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0134] The target memory chip is a second sub-memory chip in the second memory chip, and the method further includes:

[0135] In response to the baseboard management controller acquiring the second sub-storage chip information, a third control instruction is generated according to the second sub-storage chip information, and the third control instruction is sent to the complex programmable logic device; the third control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal and the second pin transmits a high-level control signal;

[0136] In response to the complex programmable logic device receiving a third control instruction, generating a third control signal according to the third control instruction, and transmitting the third control signal to the first multiplexer group;

[0137] In response to the first multiplexer group receiving the third control signal, controlling the signal value of the target signal of the first multiplexer to be the maximum value, thereby conducting the first interface of the first multiplexer and the third interface of the first multiplexer;

[0138] Controlling the signal value of the target signal of the second multiplexer to be the minimum value, thereby conducting the first interface of the second multiplexer and the second interface of the second multiplexer;

[0139] Controlling the signal value of the target signal of the third multiplexer to be the maximum value, thereby conducting the first interface of the third multiplexer and the third interface of the third multiplexer;

[0140] The signal value of the target signal of the fifth multiplexer is controlled to be the minimum value; thereby the first interface of the fifth multiplexer is connected to the second interface of the fifth multiplexer, thereby realizing data transmission between the baseboard management controller and the second sub-storage chip.

[0141] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0142] The target memory chip is a third memory chip, and the method further includes:

[0143] In response to the baseboard management controller acquiring the third storage chip information, a fourth control instruction is generated according to the third storage chip information, and the fourth control instruction is sent to the complex programmable logic device; the fourth control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal and the second pin transmits a high-level control signal;

[0144] In response to the complex programmable logic device receiving a fourth control instruction, generating a fourth control signal according to the fourth control instruction, and transmitting the fourth control signal to the first multiplexer group;

[0145] In response to the first multiplexer group receiving the fourth control signal, the signal value of the target signal of the first multiplexer is controlled to be the maximum value, thereby conducting the first interface of the first multiplexer and the third interface of the first multiplexer;

[0146] Controlling the signal value of the target signal of the second multiplexer to be the maximum value, thereby conducting the first interface of the second multiplexer and the third interface of the second multiplexer;

[0147] The signal value of the target signal of the sixth multiplexer is controlled to be the minimum value, thereby connecting the first interface of the sixth multiplexer and the second interface of the sixth multiplexer; thereby realizing data transmission between the baseboard management controller and the third storage chip.

[0148] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0149] The target memory chip is a third memory chip, and the method further includes:

[0150] In response to the processor acquiring the third storage chip information, a fifth control instruction is generated according to the third storage chip information, and the fifth control instruction is sent to the complex programmable logic device; the fifth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a high-level control signal;

[0151] In response to the complex programmable logic device receiving a fifth control instruction, generating a fifth control signal according to the fifth control instruction, and transmitting the fifth control signal to the second multiplexer group;

[0152] In response to the second multiplexer group receiving the fifth control signal, the signal value of the target signal of the seventh multiplexer is controlled to be the minimum value, thereby conducting the first interface of the seventh multiplexer and the second interface of the seventh multiplexer;

[0153] The signal value of the target signal of the eighth multiplexer is controlled to be the maximum value, thereby connecting the first interface of the eighth multiplexer and the third interface of the eighth multiplexer; thereby realizing data transmission between the processor and the third storage chip.

[0154] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0155] The target memory chip is a fourth memory chip, and the method further includes:

[0156] In response to the processor acquiring the fourth storage chip information, a sixth control instruction is generated according to the fourth storage chip information, and the sixth control instruction is sent to the complex programmable logic device; the sixth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a low-level control signal;

[0157] In response to the complex programmable logic device receiving a sixth control instruction, generating a sixth control signal according to the sixth control instruction, and transmitting the sixth control signal to the second multiplexer group;

[0158] In response to the second multiplexer group receiving the sixth control signal, the signal value of the target signal of the eighth multiplexer is controlled to be the minimum value, thereby turning on the first interface of the eighth multiplexer and the second interface of the eighth multiplexer; thereby realizing data transmission between the processor and the fourth memory chip.

[0159] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0160] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0161] In response to the baseboard management controller and / or the processor acquiring the target memory chip information, a control instruction is generated according to the target memory chip information, and the control instruction is sent to the complex programmable logic device;

[0162] In response to the complex programmable logic device receiving the control instruction, generating a control signal according to the control instruction, and transmitting the control signal to the first multiplexer group and / or the second multiplexer group;

[0163] In response to the first multiplexer group and / or the second multiplexer group receiving a control signal, the signal value corresponding to the target signal of each multiplexer in the first multiplexer group and / or the second multiplexer group is controlled according to the control signal, thereby realizing data transmission between the baseboard management controller and / or the processor and the target storage chip.

[0164] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0165] The target memory chip is a first memory chip, and the method further includes:

[0166] In response to the baseboard management controller acquiring the first storage chip information, a first control instruction is generated according to the first storage chip information, and the first control instruction is sent to the complex programmable logic device; the first control instruction carries the level signal of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal and the second pin transmits a low-level control signal;

[0167] In response to the complex programmable logic device receiving the first control instruction, generating a first control signal according to the first control instruction, and transmitting the first control signal to the first multiplexer group,

[0168] In response to the first multiplexer group receiving the first control signal, the signal value of the target signal of the first multiplexer of the first multiplexer group is controlled to be the minimum value, thereby connecting the first interface of the first multiplexer and the second interface of the first multiplexer to realize data transmission between the baseboard management controller and the first storage chip.

[0169] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0170] The target memory chip is a first sub-memory chip in the second memory chip, and the method further includes:

[0171] In response to the baseboard management controller acquiring the first sub-storage chip information, a second control instruction is generated according to the first sub-storage chip information, and the second control instruction is sent to the complex programmable logic device; the second control instruction carries the level signal of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal and the second pin transmits a low-level control signal;

[0172] In response to the complex programmable logic device receiving the second control instruction, generating a second control signal according to the second control instruction, and transmitting the second control signal to the first multiplexer group;

[0173] In response to the first multiplexer group receiving the second control signal, controlling the signal value of the target signal of the first multiplexer to be the maximum value, thereby conducting the first interface of the first multiplexer and the third interface of the first multiplexer;

[0174] Controlling the signal value of the target signal of the second multiplexer to be the minimum value, thereby conducting the first interface of the second multiplexer and the second interface of the second multiplexer;

[0175] Controlling the signal value of the target signal of the third multiplexer to be the minimum value, thereby conducting the first interface of the third multiplexer and the second interface of the third multiplexer;

[0176] The signal value of the target signal of the fourth multiplexer is controlled to be the minimum value; thereby connecting the first interface of the fourth multiplexer and the second interface of the fourth multiplexer, thereby realizing data transmission between the baseboard management controller and the first sub-storage chip information.

[0177] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0178] The target memory chip is a second sub-memory chip in the second memory chip, and the method further includes:

[0179] In response to the baseboard management controller acquiring the second sub-storage chip information, a third control instruction is generated according to the second sub-storage chip information, and the third control instruction is sent to the complex programmable logic device; the third control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal and the second pin transmits a high-level control signal;

[0180] In response to the complex programmable logic device receiving a third control instruction, generating a third control signal according to the third control instruction, and transmitting the third control signal to the first multiplexer group;

[0181] In response to the first multiplexer group receiving the third control signal, controlling the signal value of the target signal of the first multiplexer to be the maximum value, thereby conducting the first interface of the first multiplexer and the third interface of the first multiplexer;

[0182] Controlling the signal value of the target signal of the second multiplexer to be the minimum value, thereby conducting the first interface of the second multiplexer and the second interface of the second multiplexer;

[0183] Controlling the signal value of the target signal of the third multiplexer to be the maximum value, thereby conducting the first interface of the third multiplexer and the third interface of the third multiplexer;

[0184] The signal value of the target signal of the fifth multiplexer is controlled to be the minimum value; thereby the first interface of the fifth multiplexer is connected to the second interface of the fifth multiplexer, thereby realizing data transmission between the baseboard management controller and the second sub-storage chip.

[0185] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0186] The target memory chip is a third memory chip, and the method further includes:

[0187] In response to the baseboard management controller acquiring the third storage chip information, a fourth control instruction is generated according to the third storage chip information, and the fourth control instruction is sent to the complex programmable logic device; the fourth control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal and the second pin transmits a high-level control signal;

[0188] In response to the complex programmable logic device receiving a fourth control instruction, generating a fourth control signal according to the fourth control instruction, and transmitting the fourth control signal to the first multiplexer group;

[0189] In response to the first multiplexer group receiving the fourth control signal, the signal value of the target signal of the first multiplexer is controlled to be the maximum value, thereby conducting the first interface of the first multiplexer and the third interface of the first multiplexer;

[0190] Controlling the signal value of the target signal of the second multiplexer to be the maximum value, thereby conducting the first interface of the second multiplexer and the third interface of the second multiplexer;

[0191] The signal value of the target signal of the sixth multiplexer is controlled to be the minimum value, thereby connecting the first interface of the sixth multiplexer and the second interface of the sixth multiplexer; thereby realizing data transmission between the baseboard management controller and the third storage chip.

[0192] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0193] The target memory chip is a third memory chip, and the method further includes:

[0194] In response to the processor acquiring the third storage chip information, a fifth control instruction is generated according to the third storage chip information, and the fifth control instruction is sent to the complex programmable logic device; the fifth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a high-level control signal;

[0195] In response to the complex programmable logic device receiving a fifth control instruction, generating a fifth control signal according to the fifth control instruction, and transmitting the fifth control signal to the second multiplexer group;

[0196] In response to the second multiplexer group receiving the fifth control signal, the signal value of the target signal of the seventh multiplexer is controlled to be the minimum value, thereby conducting the first interface of the seventh multiplexer and the second interface of the seventh multiplexer;

[0197] The signal value of the target signal of the eighth multiplexer is controlled to be the maximum value, thereby connecting the first interface of the eighth multiplexer and the third interface of the eighth multiplexer; thereby realizing data transmission between the processor and the third storage chip.

[0198] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0199] The target memory chip is a fourth memory chip, and the method further includes:

[0200] In response to the processor acquiring the fourth storage chip information, a sixth control instruction is generated according to the fourth storage chip information, and the sixth control instruction is sent to the complex programmable logic device; the sixth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a low-level control signal;

[0201] In response to the complex programmable logic device receiving a sixth control instruction, generating a sixth control signal according to the sixth control instruction, and transmitting the sixth control signal to the second multiplexer group;

[0202] In response to the second multiplexer group receiving the sixth control signal, the signal value of the target signal of the eighth multiplexer is controlled to be the minimum value, thereby turning on the first interface of the eighth multiplexer and the second interface of the eighth multiplexer; thereby realizing data transmission between the processor and the fourth storage chip. A person of ordinary skill in the art can understand that the implementation of all or part of the process in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the process of the embodiment of each method as described above. Among them, any reference to memory, storage, database or other medium used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct RAMbus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0203] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0204] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A data transmission system, characterized in that: include: A baseboard management controller, a complex programmable logic device, a multiplexer group, a processor, and a plurality of memory chips; The baseboard management controller and the processor are respectively connected to the complex programmable logic device, the baseboard management controller and the processor are both connected to the multiplexer group, and the multiplexer group is connected to the plurality of memory chips; The plurality of memory chips include a first memory chip, a second memory chip, a third memory chip and a fourth memory chip; The multiplexer group includes a first multiplexer group and a second multiplexer group, the first multiplexer group is used to receive a control signal transmitted by the complex programmable logic device, and conduct a data transmission channel between the baseboard management controller and any one of the first storage chip, the second storage chip, and the third storage chip according to the control signal; The second multiplexer group is used to receive a control signal transmitted by the complex programmable logic device, and to conduct a data transmission channel between the processor and any one of the third storage chip and the fourth storage chip according to the control signal.

2. The system according to claim 1, characterized in that The first multiplexer group includes a first multiplexer, a second multiplexer, a third multiplexer, a fourth multiplexer, a fifth multiplexer and a sixth multiplexer; the second memory chip also includes a first sub-memory chip and a second sub-memory chip; The first interface of the first multiplexer is connected to the baseboard management controller, the second interface of the first multiplexer is connected to the first storage chip, the third interface of the first multiplexer is connected to the first interface of the second multiplexer; the first interface of the third multiplexer is connected to the second interface of the second multiplexer, the second interface of the third multiplexer is connected to the second interface of the fourth multiplexer, and the third interface of the third multiplexer is connected to the second interface of the fifth multiplexer; The first interface of the fourth multiplexer and the first interface of the fifth multiplexer are connected to the first sub-storage chip and the second sub-storage chip respectively, and the third interface of the fourth multiplexer and the third interface of the fifth multiplexer are connected to the first switching chip and the second switching chip respectively; The first interface of the sixth multiplexer is connected to the third interface of the second multiplexer, and the second interface of the sixth multiplexer is connected to the third storage chip; The control ends of the first multiplexer, the second multiplexer, the third multiplexer, the fourth multiplexer, the fifth multiplexer and the sixth multiplexer are respectively connected to the output ends of the complex programmable logic device.

3. The system according to claim 2, characterized in that The second multiplexer group includes a seventh multiplexer and an eighth multiplexer, the first interface of the seventh multiplexer is connected to the third interface of the eighth multiplexer, the second interface of the seventh multiplexer is connected to the third storage chip, the first interface of the eighth multiplexer is connected to the processor, and the second interface of the eighth multiplexer is connected to the fourth storage chip; the control ends of the seventh multiplexer and the eighth multiplexer are respectively connected to the output ends of the complex programmable logic device.

4. A data transmission method, based on the data transmission system according to claim 1, characterized in that: The method comprises: In response to the baseboard management controller and / or the processor acquiring the target memory chip information, a control instruction is generated according to the target memory chip information, and the control instruction is sent to the complex programmable logic device; In response to the complex programmable logic device receiving a control instruction, generating a control signal according to the control instruction, and transmitting the control signal to the first multiplexer group and / or the second multiplexer group; In response to the first multiplexer group and / or the second multiplexer group receiving a control signal, the signal value corresponding to the target signal of each multiplexer in the first multiplexer group and / or the second multiplexer group is controlled according to the control signal, thereby realizing data transmission between the baseboard management controller and / or the processor and the target storage chip.

5. The method according to claim 4, characterized in that The target memory chip is a first memory chip, and the method further includes: In response to the baseboard management controller acquiring the first storage chip information, a first control instruction is generated according to the first storage chip information, and the first control instruction is sent to the complex programmable logic device; the first control instruction carries the level signal of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal, and the second pin transmits a low-level control signal; In response to the complex programmable logic device receiving a first control instruction, generating a first control signal according to the first control instruction, and transmitting the first control signal to the first multiplexer group, In response to the first multiplexer group receiving the first control signal, the signal value of the target signal of the first multiplexer of the first multiplexer group is controlled to be the minimum value, thereby connecting the first interface of the first multiplexer and the second interface of the first multiplexer to realize data transmission between the baseboard management controller and the first storage chip.

6. The method according to claim 4, characterized in that The target memory chip is a first sub-memory chip in the second memory chip, and the method further includes: In response to the baseboard management controller acquiring the first sub-storage chip information, a second control instruction is generated according to the first sub-storage chip information, and the second control instruction is sent to the complex programmable logic device; the second control instruction carries the level signal of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal and the second pin transmits a low-level control signal; In response to the complex programmable logic device receiving a second control instruction, generating a second control signal according to the second control instruction, and transmitting the second control signal to the first multiplexer group; In response to the first multiplexer group receiving the second control signal, controlling the signal value of the target signal of the first multiplexer to be the maximum value, thereby conducting the first interface of the first multiplexer and the third interface of the first multiplexer; Controlling the signal value of the target signal of the second multiplexer to be the minimum value, thereby conducting the first interface of the second multiplexer and the second interface of the second multiplexer; Controlling the signal value of the target signal of the third multiplexer to be the minimum value, thereby conducting the first interface of the third multiplexer and the second interface of the third multiplexer; The signal value of the target signal of the fourth multiplexer is controlled to be the minimum value; thereby connecting the first interface of the fourth multiplexer and the second interface of the fourth multiplexer, thereby realizing data transmission between the baseboard management controller and the first sub-storage chip information.

7. The method according to claim 4, characterized in that The target memory chip is a second sub-memory chip in the second memory chip, and the method further includes: In response to the baseboard management controller acquiring the second sub-storage chip information, a third control instruction is generated according to the second sub-storage chip information, and the third control instruction is sent to the complex programmable logic device; the third control instruction carries the level signals of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a low-level control signal and the second pin transmits a high-level control signal; In response to the complex programmable logic device receiving a third control instruction, generating a third control signal according to the third control instruction, and transmitting the third control signal to the first multiplexer group; In response to the first multiplexer group receiving the third control signal, controlling the signal value of the target signal of the first multiplexer to be the maximum value, thereby conducting the first interface of the first multiplexer and the third interface of the first multiplexer; Controlling the signal value of the target signal of the second multiplexer to be the minimum value, thereby conducting the first interface of the second multiplexer and the second interface of the second multiplexer; Controlling the signal value of the target signal of the third multiplexer to be the maximum value, thereby conducting the first interface of the third multiplexer and the third interface of the third multiplexer; The signal value of the target signal of the fifth multiplexer is controlled to be the minimum value; thereby connecting the first interface of the fifth multiplexer and the second interface of the fifth multiplexer, thereby realizing data transmission between the baseboard management controller and the second sub-storage chip.

8. The method according to claim 4, characterized in that The target memory chip is a third memory chip, and the method further includes: In response to the baseboard management controller acquiring the third storage chip information, a fourth control instruction is generated according to the third storage chip information, and the fourth control instruction is sent to the complex programmable logic device; the fourth control instruction carries the level signal of the first pin and the second pin on the baseboard management controller, wherein the first pin transmits a high-level control signal, and the second pin transmits a high-level control signal; In response to the complex programmable logic device receiving a fourth control instruction, generating a fourth control signal according to the fourth control instruction, and transmitting the fourth control signal to the first multiplexer group; In response to the first multiplexer group receiving the fourth control signal, controlling the signal value of the target signal of the first multiplexer to be the maximum value, thereby conducting the first interface of the first multiplexer and the third interface of the first multiplexer; Controlling the signal value of the target signal of the second multiplexer to be the maximum value, thereby conducting the first interface of the second multiplexer and the third interface of the second multiplexer; The signal value of the target signal of the sixth multiplexer is controlled to be the minimum value, thereby connecting the first interface of the sixth multiplexer and the second interface of the sixth multiplexer; thereby realizing data transmission between the baseboard management controller and the third storage chip.

9. The method according to claim 4, characterized in that The target memory chip is a third memory chip, and the method further includes: In response to the processor acquiring the third storage chip information, generating a fifth control instruction according to the third storage chip information, and sending the fifth control instruction to the complex programmable logic device; the fifth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a high-level control signal; In response to the complex programmable logic device receiving a fifth control instruction, generating a fifth control signal according to the fifth control instruction, and transmitting the fifth control signal to the second multiplexer group; In response to the second multiplexer group receiving the fifth control signal, the signal value of the target signal of the seventh multiplexer is controlled to be the minimum value, thereby conducting the first interface of the seventh multiplexer and the second interface of the seventh multiplexer; The signal value of the target signal of the eighth multiplexer is controlled to be the maximum value, thereby turning on the first interface of the eighth multiplexer and the third interface of the eighth multiplexer; thereby realizing data transmission between the processor and the third storage chip.

10. The method according to claim 4, characterized in that The target memory chip is a fourth memory chip, and the method further includes: In response to the processor acquiring the fourth storage chip information, a sixth control instruction is generated according to the fourth storage chip information, and the sixth control instruction is sent to the complex programmable logic device; the sixth control instruction carries a level signal of a pin on the processor, wherein the pin on the processor transmits a low-level control signal; In response to the complex programmable logic device receiving a sixth control instruction, generating a sixth control signal according to the sixth control instruction, and transmitting the sixth control signal to the second multiplexer group; In response to the second multiplexer group receiving the sixth control signal, the signal value of the target signal of the eighth multiplexer is controlled to be the minimum value, thereby turning on the first interface of the eighth multiplexer and the second interface of the eighth multiplexer; thereby realizing data transmission between the processor and the fourth storage chip.

11. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 4 to 10 are implemented.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 4 to 10 are implemented.

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