DFT / FFT structure and DFT / FFT implementation method based on DFT / FFT structure
By using multiple selector, RAM group and counter chain synchronization technology in the DFT/FFT structure, the problems of complex FFT address mapping and RAM access conflict in the prior art are solved, and efficient ultra-long data DFT/FFT calculation is realized.
Patent Information
- Application Number
- CN202411456499.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-02-14
AI Technical Summary
In the prior art, the input data address mapping of FFT is complex, resulting in the lack of addressing regularity and complex access methods. Especially when the data length is long, RAM access conflicts and address calculation complexity increase, making it difficult to achieve efficient DFT/FFT calculations.
A DFT/FFT implementation structure for efficient RAM access is designed. Through the combination of multiple selectors, RAM groups, split selectors, calculation control units and butterfly operation units, the counter chain is used to synchronize data input and random order. RAM group mapping and adjust the sorting of butterfly operation bases to reduce the complexity of RAM address calculation and improve the regularity of address access.
It effectively avoids RAM access conflicts, simplifies the address calculation process, improves the regularity of address access, and makes DFT/FFT calculation of ultra-long data more efficient and suitable for software and hardware implementation.
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Figure CN119441691A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the fields of communication, chip and digital signal processing, and in particular relates to a DFT / FFT structure and a DFT / FFT implementation method based on the structure. Background Art
[0002] In signal processing and spectrum analysis, Discrete Fourier Transformation (DFT) is a commonly used transformation tool. However, the amount of computation required to directly perform DFT is proportional to the length of the data it processes. When the data length is long, it is difficult to directly use DFT for real-time processing of signal and spectrum analysis. The introduction of Fast Fourier Transformation (FFT) has greatly simplified the calculation of DFT and reduced the amount of computation required for DFT. FFT decomposes a long DFT sequence into a short DFT sequence of multiple basis combinations, and uses short sequence DFT transformation to achieve long sequence transformation. The FFT algorithm based on butterfly operation is currently a universal and effective algorithm.
[0003] At present, there are three ways to implement DFT / FFT: full parallel, serial-parallel combination, and serial. The full parallel method takes up less resources and is suitable for DFT / FFT with fewer points. The serial method saves resources but has a larger delay. The serial-parallel combination is more flexible and can achieve a balance between delay and resources according to actual conditions. FFT algorithms often use time domain extraction and frequency domain extraction calculation methods, such as Figure 1 and 2 As shown, the input data of the butterfly operation extracted in the time domain is out of order, and the output results are in order; while the input data of the butterfly operation extracted in the frequency domain is in order, and the output results are out of order.
[0004] In the master's thesis of Xidian University ("Research and Implementation of High-speed and High-precision FFT Processing Scheme Based on FPGA", Lei Yufei, 2019.6), 4∧M and 4∧M*2 point frequency domain extraction FFT was implemented, using 4 dual-port RAMs, and the data was placed according to the operation rules, so that the FFT calculation can be performed in situ, that is, the address of the data is consistent with the address where the calculation result is to be stored, so as to reduce RAM space. In this scheme, for an FFT with a length of 4∧M points, the valid bits of the address are even, and the valid bits of the address are set to m bits. The RAM serial number (0-3) is obtained by adding the modulo-four of every two bits of the input address. The high m-2 bits represent the address of the current RAM, such as Figure 3 As shown. When the valid bit of the address is an odd number, swap the m-1 and m-2 bits, and then execute the steps when m is an even number. In this scheme, when m is an odd number or an even number, the data addressing is different, and the control logic is complicated.
[0005] Based on the above mapping method, the article also proposes the following Figure 4 The FFT calculation structure shown in the figure, in which RAM1 and RAM2 are ping-pong structures, read or write data in turn, and there are 4 dual-port sub-RAMs in RAM1 and RAM2. At the beginning of the calculation, the input data is mapped to the 4 RAMs in RAM1 according to the address. The control module reads the data from RAM1 and calculates it through the base 4 / 2 multiplexing module, and then writes it back to RAM1 according to the same address. Different data are selected for butterfly operation according to the calculation of different stages of FFT, and finally the entire FFT operation is completed. The output module demaps and outputs according to the data mapping method.
[0006] It can be seen that in the prior art, when performing address mapping on FFT input data, it is necessary to distinguish and consider the parity of the number of effective bits of the address, resulting in a lack of addressing regularity and a complex addressing access method, and its complexity increases with the increase of data length; secondly, the FFT implementation method based on frequency domain extraction and the unreasonable selection of the radix order of the butterfly operation lead to complex addressing and a lack of regularity in the output address. Summary of the invention
[0007] In view of the problems existing in the prior art, the present invention designs a DFTF / FFT implementation structure with efficient RAM access to avoid RAM access conflicts. At the same time, based on the structure, the sorting problem of the butterfly operation basis is proposed for the time domain extraction and frequency domain extraction of DFT / FFT, which reduces the complexity of RAM address calculation in the DFT / FFT calculation process, enhances the regularity of address access, and makes it easier to implement DFT of ultra-long data.
[0008] To solve the above problems, the present invention adopts the following technical solutions:
[0009] A DFT / FFT structure and a DFT / FFT implementation method based on the structure, the structure comprising a multiplexer, a RAM group, a branch selector, a calculation control unit, and a butterfly operation unit; the multiplexer controls the selection of whether to store input data or the calculation intermediate result output by the butterfly operation unit in the RAM group, the branch selector is used to select whether to output the RAM group read data to the butterfly operation unit or directly output it as a DFT operation result, and the butterfly operation unit is configured with more than one butterfly calculation core; the calculation control unit controls the entire DFT calculation process, including a disorder control module, a mapping control module, a butterfly calculation data addressing calculation module, a multiplexer control module, a branch selector control module, and a butterfly operation parameter configuration module;
[0010] The DFT / FFT implementation method based on the structure is an FFT time domain extraction method, and the time domain extraction method includes the following steps:
[0011] Step 1) Assume that the DFT / FFT data length is N, decompose N into a combination of multiple bases, expressed as r max =max(r0,r1,…,r m ), r max Represents the maximum value of all bases;
[0012] Step 2) Create a RAM group max dual-port sub-RAM, assuming r0>r1>…>r m ,During the butterfly operation, the bases are ordered from large to small;
[0013] Step 3) Synchronize data input out of order and RAM group mapping through counter chain: Based on Create n0 counters modulo r0, n1 counters modulo r1, ... n m The module is r m The counter carries from the small-module counter to the large-module counter, counts the number of input data through the counter chain structure, calculates the row and column position in the RAM group corresponding to each data through the counter value, and stores the input data in the corresponding position;
[0014] Step 4) Calculate the access address of the data during DFT / FFT calculation. During calculation, the carry relationship of the counter chain is reversed to become a reverse counter chain, and the carry is carried from the counter with a large base to the counter with a small base. The specific iterative steps are as follows:
[0015] S1, the first iteration directly reads out by column, and in the process of reading data, the starting address of each column of data is calculated by the reverse counter chain, and the read data is cyclically shifted with the row position of the starting address as the offset position and then output to the butterfly operation unit, and the calculation result of the butterfly operation unit is written in situ into the RAM group;
[0016] S2, the second iteration, the DFT / FFT calculation length is r0*r, and each r column in the RAM group is used as a block of data for DFT / FFT calculation, and the execution process is: the data at the 0th position filled in the rth column is read out at the same time, and output to the butterfly operation unit after circular shift, and the calculation result is written in situ into the RAM group; until the data at the r0-1th position filled in the rth column is read out at the same time, the butterfly operation is completed after circular shift, and the butterfly operation result is written in situ;
[0017] S3, in the subsequent iterative processing, if the calculation length is r0*r*r', each r*r' column in the RAM group is used as a block of data for DFT / FFT calculation, and each r column in each block is used as a group. The execution process is as follows: each group in the block reads data from the 0th position filled in the 0th column at the same time, until the last position filled in the 0th column is read, and then the 1st column is read. The reading order of the 1st column is the same as that of the 0th column, and both are read from the 0th position filled to the last position filled in the column; each time the r' data read out at the same time are cyclically shifted with the row position of the data read out in group 0 as the offset position and then output to the butterfly operation unit, and the butterfly operation unit writes the calculation result in situ into the RAM group; the remaining iterative operations read data according to the same idea;
[0018] Step 5) Sequential reading of operation results: After the last butterfly operation is completed, the reverse counter chain is used to read out the data column by column. The order of reading each column of data is the order in which the data is filled in the column.
[0019] Furthermore, the butterfly operation core of the butterfly operation unit of the DFT / FFT structure is implemented by table lookup or cordic method, and the butterfly operation core can perform pipeline processing on data.
[0020] Further, the sub-RAM number, i.e., the row number, of the input data to be stored in step 3) is The address of the sub-RAM where the input data needs to be stored, i.e. the column number, is Where i is the number of counters of different modules, j is the number of different modules, and cnt represents the counter value.
[0021] Furthermore, in step 4), in the first iteration, the row position of the first data in each column of data is determined according to the value in the reverse counter, that is, by calculating the sum of the counts of all counters except the lowest bit counter and performing r max The result after modulo calculation is used as the row address of the first data. The specific process is:
[0022] The row address calculation formula is as follows:
[0023]
[0024] Among them, r max = r0;
[0025] Based on the row address calculation formula, the first data row address is:
[0026]
[0027] The second data row address is:
[0028]
[0029] …
[0030] By analogy, the address of the r0th data row is:
[0031]
[0032] The column addresses are taken in order:
[0033] The data read from the RAM group is output to the butterfly operation unit after circular shifting with the row position corresponding to the first data as the offset position, which is expressed by the following formula:
[0034] data shift (i) = data read (mod(row o +i,r0))
[0035] Among them, data shift Represents the data after circular shift, data read Represents the data read from the RAM group, i=0~r0-1.
[0036] Furthermore, in step 4), the address of the first column of data is calculated in the second iteration, and the addresses of other columns of data are calculated based on the address of the first column of data plus the offset address. The specific calculation process is:
[0037] When n0≥3, the row address is:
[0038]
[0039] Wherein, k=0~r0-1, t=0~r-1, k represents the column number in the block, and t represents the sequence number of the read data;
[0040] When n0=2, the row address is:
[0041]
[0042] Wherein, k=0~r0-1, t=0~r-1, k represents the column number in the block, and t represents the sequence number of the read data;
[0043] When n0=1, the row address is:
[0044]
[0045] Wherein, k=0~r0-1, t=0~r-1, k represents the column number in the block, and t represents the sequence number of the read data;
[0046] The above row address formula means: ignoring the two lowest-order counters, the sum of the counts of the remaining counters and k and t and the result modulo r is the row address;
[0047] The column address of data read is: col = b*r + t, where b represents the block number;
[0048] The above row and column addresses are traversed first according to the column address k, and then the read data sequence number t is traversed.
[0049] Further, in step 4), in the subsequent iterative processing, the data row and column address calculation process is:
[0050] When n0≥3, the row address is:
[0051]
[0052] Wherein, k=0~r-1, t=0~r'-1, k represents the column number in the group, and t represents the sequence number of the read data;
[0053] When n0=2, the row address is:
[0054]
[0055] Wherein, k=0~r-1, t=0~r'-1, k represents the column number in the group, and t represents the sequence number of the read data;
[0056] When n0=1, the row address is:
[0057]
[0058] Wherein, k=0~r-1, t=0~r'-1, k represents the column number in the group, and t represents the sequence number of the read data;
[0059] The above row address formula indicates that: ignoring the two lowest-order counters, the sum of the counts of the remaining counters and k and t and the result modulo r' is the row address;
[0060] The column address for data reading is: col = b*B_size+t*G_size+g, where -1, b represents the block number; B_size = r*r', represents the number of columns in the block; g represents the group number, G_size = r, represents the number of columns in the group;
[0061] The above row and column addresses are traversed first according to the column address k, and then the read data sequence number t is traversed.
[0062] Furthermore, after the last butterfly operation is completed, the data is output column by column. The reverse counter chain is used for output. The row address of the read data is t=0~r0-1; the column address is: Read the data in the RAM group at a time.
[0063] Further, the RAM data mapping method in the time domain extraction method and the data access method in the calculation process are applied to the DFT / FFT frequency domain extraction to realize the DFT / FFT frequency domain extraction based on the structure. The frequency domain extraction steps are as follows:
[0064] Step 1) Assume that the DFT data length is N, decompose N into a combination of multiple bases, expressed as r max =max(r0,r1,…,r m ), r max Represents the maximum value of all bases;
[0065] Step 2) Create a RAM group max sub-RAM, assuming r0>r1>…>r m ,During the butterfly operation, the bases are operated in ascending order;
[0066] Step 3) Synchronize the data input sequence and RAM group mapping through the reverse counter chain, based on Create n0 counters modulo r0, n1 counters modulo r1, ... n m The module is r m The counter is carried from the counter with a larger modulus to the counter with a smaller modulus. The sub-RAM number, i.e., the row number, of the data to be stored is The column address of the sub-RAM where the data needs to be stored is: Its address calculation process is consistent with the address calculation of sequentially reading the operation results in the time domain extraction DFT / FFT calculation;
[0067] Step 4) DFT / FFT calculates the access address of data: the read and write address of data is accessed using the iteration base opposite to the time domain extraction, that is, the execution process of the time domain extraction is the DFT / FFT segment calculation length from r0 to N, and the execution process of the frequency domain extraction is the DFT / FFT segment calculation length from N to r0;
[0068] Step 5) Output of DFT / FFT frequency domain extraction operation results: The DFT / FFT frequency domain extraction calculation results are stored in random order in the RAM group, and the address in the RAM group is calculated using a calculation method consistent with the address calculation of the random order of the input data and the RAM group mapping in the time domain extraction method, and then the data is read out.
[0069] Compared with the prior art, the present invention has the following beneficial effects:
[0070] (1) During the DFT / FFT butterfly operation, the order of the bases is adjusted, and the time bases for time domain extraction are selected from large to small, and the largest base is selected as the number of rows mapped in the RAM group. Based on the above adjustment, the DFT data access conflict problem is solved in a simple and unified manner, and there is no need to distinguish between different processing based on the length of the processed data.
[0071] (2) For large-length DFT / FFT operations, partial data loading operations can be performed, reducing the RAM space requirements;
[0072] If the RAM space in the system cannot accommodate the entire data length, the mapped data needs to be placed in an external storage space, such as DDR. Since the DFT / FFT calculation process is equivalent to a row-column interleaving process, the data accessed sequentially may span multiple rows in DDR, causing DDR to frequently precharge and activate rows, resulting in reduced DDR access efficiency.
[0073] This structure can be used to partially load the mapping data into RAM, and write it into the DDR space after partial calculation, thus reducing frequent access to DDR and improving efficiency;
[0074] (3) The address calculation for accessing data in this structure can be obtained through counter chain calculation. The calculation method is unified and there is no need to distinguish too many situations. It is more suitable for software and hardware implementation.
[0075] (4) The time domain extraction method based on the structure of the present invention is also effective for implementing frequency domain extraction. BRIEF DESCRIPTION OF THE DRAWINGS
[0076] Figure 1 It is an 8-point FFT time-domain extraction butterfly operation diagram in the prior art;
[0077] Figure 2 It is an 8-point FFT frequency domain extraction butterfly operation diagram in the prior art;
[0078] Figure 3 This is the RAM address mapping method with even-numbered address valid bits in the master's thesis of Xidian University;
[0079] Figure 4 This is the internal structure diagram of FFT presented in the master's thesis of Xidian University;
[0080] Figure 5 This is a DFT / FFT structure diagram of the present invention;
[0081] Figure 6 The counter chain structure of the present invention;
[0082] Figure 7 The 250,000-point counter chain of the embodiment of the present invention;
[0083] Figure 8 Schematic diagram of RAM group data mapping according to an embodiment of the present invention;
[0084] Fig. 9 The reverse counter chain structure of the present invention;
[0085] Fig.10 It is a 250,000-point reverse counter chain according to an embodiment of the present invention;
[0086] Fig.11 This is a schematic diagram of data reading for the first iteration according to an embodiment of the present invention;
[0087] Fig.12 This is a schematic diagram of the cyclic shift of the RAM group reading data in the first iteration according to the embodiment of the present invention;
[0088] Fig.13 This is a schematic diagram of data reading for the second iteration of the embodiment of the present invention;
[0089] Fig.14 This is an illustration of the third iteration of data reading in an embodiment of the present invention. DETAILED DESCRIPTION
[0090] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0091] like Figure 5 As shown, a DFT / FFT structure disclosed in the present invention includes a multiplexer, a RAM group, a branch selector, a calculation control unit, and a butterfly operation unit; the multiplexer controls the selection of whether to store the input data or the calculation intermediate result output by the butterfly operation unit in the RAM group, the branch selector is used to select whether to output the RAM group read data to the butterfly operation unit or directly output it as a DFT operation result, and the butterfly operation unit is configured with more than one butterfly calculation core; the calculation control unit controls the entire DFT / FFT calculation process, including a disorder control module, a mapping control module, a butterfly calculation data addressing calculation module, a multiplexer control module, a branch selector control module, and a butterfly operation parameter configuration module;
[0092] The DFT / FFT implementation method based on the structure is an FFT time domain extraction method, and the time domain extraction method includes the following steps:
[0093] Step 1) Assume that the DFT data length is N, decompose N into a combination of multiple bases, expressed as r max =max(r0,r1,…,r m ), r max Represents the maximum value of all bases;
[0094] Step 2) Create a RAM group max sub-RAM, assuming r0>r1>…>r m ,During the butterfly operation, the bases are ordered from large to small;
[0095] Step 3) By Figure 6 The counter chain shown here synchronizes the data input out of order and RAM group mapping: Create n0 counters modulo r0, n1 counters modulo r1, ... n m The module is r m The counter carries from the small-module counter to the large-module counter, counts the number of input data through the counter chain structure, calculates the row and column position in the RAM group corresponding to each data through the counter value, and stores the input data in the corresponding position;
[0096] Step 4) Calculate the access address of the data during DFT / FFT calculation. During calculation, the carry relationship of the counter chain is reversed to become a reverse counter chain, such as Fig. 9 As shown, carry from the counter with a larger modulus to the counter with a smaller modulus. The specific iterative steps are as follows:
[0097] S1, the first iteration directly reads out by column, and in the process of reading data, the starting address of each column of data is calculated by the reverse counter chain, and the read data is cyclically shifted with the row position of the starting address as the offset position and then output to the butterfly operation unit, and the calculation result of the butterfly operation unit is written in situ into the RAM group;
[0098] S2, the second iteration, the DFT / FFT calculation length is r0*r, and each r column in the RAM group is used as a block of data for DFT / FFT calculation. The execution process is: the data at the 0th position filled in the rth column is read out at the same time, and a butterfly operation unit is output after circular shift, and the calculation result is written into the RAM group in situ; until the data at the r0-1th position filled in the rth column is read out at the same time, the butterfly operation is completed after circular shift, and the butterfly operation result is written in situ;
[0099] S3, in the subsequent iterative processing, if the calculation length is r0*r*r', each r*r' column in the RAM group is used as a block of data for DFT / FFT calculation, and each r column in each block is used as a group. The execution process is as follows: each group in the block reads data from the 0th position filled in the 0th column at the same time, until the last position filled in the 0th column is read and then the 1st column is read. The reading order of the 1st column is the same as that of the 0th column, and data is read from the 0th position filled to the last position filled in the column; each time the r' data read out at the same time are cyclically shifted with the row position of the data read out in group 0 as the offset position and then output to the butterfly operation unit, and the butterfly operation unit writes the calculation result in situ into the RAM group; the remaining iterative operations read data according to the same idea;
[0100] Step 5) Sequential reading of operation results: After the last butterfly operation is completed, the reverse counter chain is used to read out the data column by column. The order of reading each column of data is the order in which the data is filled in the column.
[0101] Furthermore, the butterfly operation core of the butterfly operation unit of the DFT / FFT structure is implemented by table lookup or cordic method, and the butterfly operation core can perform pipeline processing on data.
[0102] Further, the sub-RAM number, i.e., the row number, of the input data to be stored in step 3) is The address of the sub-RAM where the input data needs to be stored, i.e. the column number, is Where i is the number of counters of different moduli, j is the number of different moduli, and cnt represents the counter value;
[0103] Further, in step 4), the row position of the first data in each column of data is determined according to the value in the reverse counter, that is, by calculating the sum of the counts of all counters except the lowest bit counter, and r max The result after modulo calculation is used as the row address of the first data. The specific process is:
[0104] The row address calculation formula is as follows:
[0105]
[0106] Among them, r max = r0;
[0107] Based on the row address calculation formula, the first data row address is:
[0108]
[0109] The second data row address is:
[0110]
[0111] …
[0112] By analogy, the address of the r0th data row is:
[0113]
[0114] The column addresses are taken in order:
[0115] The data read from the RAM group is output to the butterfly operation unit after circular shifting with the row position corresponding to the first data as the offset position, which is expressed by the following formula:
[0116] data shift (i) = data read (mod(row o +i,r0))
[0117] Among them, data shift Represents the data after circular shift, data read Represents the data read from the RAM group, i=0~r0-1.
[0118] Furthermore, in step 4), the address of the first column of data is calculated in the second iteration, and the addresses of other columns of data are calculated based on the address of the first column of data plus the offset address. The specific calculation process is:
[0119] When n0≥3, the row address is:
[0120]
[0121] Wherein, k=0~r0-1, t=0~r-1, k represents the column number in the block, and t represents the sequence number of the read data;
[0122] When n0=2, the row address is:
[0123]
[0124] Wherein, k=0~r0-1, t=0~r-1, k represents the column number in the block, and t represents the sequence number of the read data;
[0125] When n0=1, the row address is:
[0126]
[0127] Wherein, k=0~r0-1, t=0~r-1, k represents the column number in the block, and t represents the sequence number of the read data;
[0128] The above row address formula means: ignoring the two lowest-order counters, the sum of the counts of the remaining counters and k and t and the result modulo r is the row address;
[0129] The column address of data read is: col = b*r + t, where b represents the block number;
[0130] The above row and column addresses are traversed first according to the column address k, and then the read data sequence number t is traversed.
[0131] Further, in step 4), in the subsequent iterative processing, the data row and column address calculation process is:
[0132] When n0≥3, the row address is:
[0133]
[0134] Wherein, k=0~r-1, t=0~r'-1, k represents the column number in the group, and t represents the sequence number of the read data;
[0135] When n0=2, the row address is:
[0136]
[0137] Wherein, k=0~r-1, t=0~r'-1, k represents the column number in the group, and t represents the sequence number of the read data;
[0138] When n0=1, the row address is:
[0139]
[0140] Wherein, k=0~r-1, t=0~r'-1, k represents the column number in the group, and t represents the sequence number of the read data;
[0141] The above row address formula indicates that: ignoring the two lowest-order counters, the sum of the counts of the remaining counters and k and t and the result modulo r' is the row address;
[0142] The column address of data read is: col = b*B_size+t*G_size+g, where -1, b represents the block number; B_size = r*r', represents the number of columns in the block; g represents the group number, G_size = r, represents the number of columns in the group;
[0143] The above row and column addresses are traversed first according to the column address k, and then the read data sequence number t is traversed.
[0144] Furthermore, after the last butterfly operation is completed, the data is output column by column. The reverse counter chain is used for output. The row address of the read data is t=0~r0-1; the column address is: Read the data in the RAM group at a time.
[0145] Further, the RAM data mapping method in the time domain extraction method and the data access method in the calculation process are applied to the DFT / FFT frequency domain extraction to realize the DFT / FFT frequency domain extraction based on the structure. The frequency domain extraction steps are as follows:
[0146] Step 1) Assume that the DFT data length is N, decompose N into a combination of multiple bases, expressed as r max =max(r0,r1,…,r m ), r max Represents the maximum value of all bases;
[0147] Step 2) Create a RAM group max sub-RAM, assuming r0>r1>…>r m ,During the butterfly operation, the bases are operated in ascending order;
[0148] Step 3) By Fig. 9 The reverse counter chain shown synchronizes the data input sequence with the RAM bank mapping: Create n0 counters modulo r0, n1 counters modulo r1, ... n m The module is r m The counter is carried from the counter with a larger modulus to the counter with a smaller modulus. The sub-RAM number, i.e., the row number, of the data to be stored is The column address of the sub-RAM where the data needs to be stored is: Its address calculation process is consistent with the address calculation of sequentially reading the operation results in the DFT / FFT time domain extraction method;
[0149] Step 4) DFT / FFT calculates the access address of data: the read and write address of data is accessed using the iteration base opposite to the time domain extraction, that is, the execution process of the time domain extraction is the DFT / FFT segment calculation length from r0 to N, and the execution process of the frequency domain extraction is the DFT / FFT segment calculation length from N to r0;
[0150] Step 5) Output of DFT / FFT frequency domain extraction operation results: The DFT / FFT frequency domain extraction calculation results are stored in random order in the RAM group, and the address in the RAM group is calculated using a calculation method consistent with the address calculation of the random order of the input data and the RAM group mapping in the time domain extraction method, and then the data is read out.
[0151] Example
[0152] Based on Figure 5The DFT / FFT structure shown in the figure implements the 250,000-point DFT / FFT time domain extraction operation, including the following steps:
[0153] Step 1) decompose the data length N into a combination of multiple bases, that is, N=250000=5∧6*4∧2, and the maximum base is 5;
[0154] Step 2) 5 dual-port sub-RAMs are established in the RAM group, each RAM has a depth of 50000, and radix-5 operation is performed first and then radix-4 operation is performed during the butterfly operation process;
[0155] Step 3) By Figure 7 The 250,000-point counter chain shown here synchronously implements data input disorder and RAM group mapping. The specific process is:
[0156] Based on N=5∧6*4∧2, 6 counters with a modulus of 5 and 2 counters with a modulus of 4 are established, and the data is carried from the counter with a smaller modulus to the counter with a larger modulus. The sub-RAM number, i.e., the row number, where the data needs to be stored is:
[0157]
[0158] The address of the sub-RAM where the data needs to be stored, i.e. the column number, is:
[0159]
[0160] pass Figure 7 The counter chain structure shown counts the number of input data, calculates the row and column positions in the RAM group corresponding to each data through the counter value, and stores the input data in the corresponding position, such as Figure 8 As shown, each row represents a dual-port sub-RAM, and each column represents a storage unit corresponding to the dual-port sub-RAM. Figure 8 The number filled in is the serial number corresponding to the input data, which is 0 to 250000-1;
[0161] Step 4) Calculate the access address of the data during DFT / FFT calculation. During calculation, the carry relationship of the counter chain is reversed to become a reverse counter chain, such as Fig.10 As shown, the carry is performed from the counter with a modulus of 5 to the counter with a modulus of 4. The specific iterative steps are as follows:
[0162] S1, the first iteration directly reads out by column, and in the process of reading data Fig.10 The reverse counter chain shown calculates the starting address of each column of data, uses the row position of the starting address as the offset position to perform cyclic shift on the read data, and then outputs it to the butterfly operation unit, and the calculation result of the butterfly operation unit is written in situ into the RAM group;
[0163] like Fig.11 As shown, when reading the data in the 0th column, the data at the 0th position filled in the column is in the 0th row, the data at the 1st position is in the 1st row..., the data at the 4th position is in the 4th row, so the data in the 0th column does not need to be circularly shifted; when reading the data in the 1st column, the data at the 0th position filled in the column is in the 1st row, the data at the 1st position is in the 2nd row..., the data at the 4th position is in the 0th row, so the data in the 1st column needs to be circularly shifted; as long as the row where the first data is located is calculated, the rows where the other data are located can be obtained by superimposing the offset and taking the modulus of 5;
[0164] The calculation is performed by calculating the sum of all counter counts except the lowest bit counter and r max The result after modulo calculation is used as the row address of the first data. The row address of the first data is:
[0165]
[0166] The second data row address is:
[0167]
[0168] The third data row address is:
[0169]
[0170] The address of the fourth data line is:
[0171]
[0172] The address of the fifth data line is:
[0173]
[0174] The column addresses are: 0~50000-1;
[0175] like Fig.12 As shown, the data read from the RAM group is output to the butterfly operation unit after cyclic shift with the row position corresponding to the first data as the offset position, which is expressed by the following formula:
[0176] data shift (i) = data read (mod(row o +i,r0))
[0177] Among them, data shift Represents the data after circular shift, data read Represents the data read from the RAM group, i=0~4.
[0178] According to the above formula, parallel calculation is performed to obtain the row positions of all data in column 0 at the same time. The column addresses are 0 to 50000-1 in sequence. The read data determines the number of cyclic shifts according to the row address corresponding to the first data.
[0179] The DFT / FFT calculation length is r0, and each column of the RAM group is used as a block for DFT / FFT calculation. b represents the current block number, and t represents the read data sequence number. The pseudo code corresponding to the calculation process is:
[0180]
[0181] S2, such as Fig.13 As shown, in the second iteration, the DFT calculation length is r0*r, that is, 5*5, and every 5 columns in the RAM group are used as a block of data for DFT / FFT calculation. The block number is 0~10000-1. The execution process is: the data at the 0th position of the 5 columns of data filled are read out at the same time, and a butterfly operation unit is output after circular shift, and the calculation result is written into the RAM group in situ; until the data at the 4th position filled in the 5th column is read out at the same time, the butterfly operation is completed after circular shift, and the butterfly operation result is written in situ;
[0182] Fig.13 Different shapes of symbols are used to represent the order of reading data in the block, which are triangle, square, hexagon, five-pointed star, circle. The data read out simultaneously for the first time are 0, 10000, 20000, 30000, 40000 represented by triangle; the data read out simultaneously for the second time are 50000, 60000, 70000, 80000 represented by square; and so on.
[0183] The pseudo code for calculating the read data address is:
[0184]
[0185]
[0186] S3, the subsequent iterative processing, the calculation length is r0*r*r', that is, 5*5*5, and each r*r' column in the RAM group, that is, 25 columns, is used as a block of data for DFT calculation. Every 5 columns in each block are used as a group, such as Fig.14As shown, the execution process is as follows: each group in the block reads data from the 0th position filled in the 0th column at the same time, until the last position filled in the 0th column is read and then the 1st column is read. The reading order of the 1st column is the same as that of the 0th column, that is, data is read from the 0th position filled to the last position filled in the column; the 5 data read out at the same time each time are cyclically shifted with the row position of the corresponding data read out in group 0 as the offset position and then output to the butterfly operation unit, and the butterfly operation unit writes the calculation result in situ into the RAM group;
[0187] Fig.14 Different shape symbols are used to represent the order of reading data in the block, which are triangle, square, hexagon, five-pointed star, and circle. The triangle annotation data read from the 0th column of each group is the first group of calculation data, and the first group of calculation data read is 0, 2000, 4000, 6000, 8000; the first data in group 0 is located in row0, so the first group of data does not need to be cyclically shifted; the square annotation data is read from the 0th column of each group as the second group of calculation data, and the second group of calculation data read is 50000, 52000, 54000, 56000, 58000; the second data in the 0th column of group 0 is located in row1, so the second group of data needs to be cyclically shifted with an offset of 1; subsequently, data is read sequentially from the 0th column to the 4th column; the read data is cyclically shifted and input to the butterfly operation unit, and the calculation result is written into the RAM group in situ;
[0188] The pseudo code for calculating the read data address is:
[0189]
[0190]
[0191] The data is read in the same way in the remaining iterative operations;
[0192] Step 5) Sequential reading of the operation results: After the last butterfly operation is completed, the reverse counter chain is used to read the data one column at a time. The order of reading each column of data is the order in which the column data is filled. The row address of the read column data is:
[0193] t is the data reading sequence number, and t=0~4;
[0194] The column address is: 0~50000-1;
[0195] The pseudo code for calculating the read data address is:
[0196]
[0197] Furthermore, the row address calculation by summing the counter chain is also applicable to DFT frequency domain extraction. The difference between the DFT implementation of frequency domain extraction and the DFT implementation of frequency domain extraction is that the frequency domain extraction process is opposite to the time domain extraction implementation process, that is, the data is mapped to the RAM group sequentially; the DFT calculates the data access address, and its segmented operation length is from long to short, and the calculation base is from small to large; the output result is output after the order is adjusted out of order.
[0198] The present invention is based on a designed DFT / FFT structure with efficient RAM access, and proposes the sorting problem of butterfly operation bases according to different DFT / FFT implementation methods, thereby avoiding the RAM access conflict problem in the DFT / FFT implementation process; a counter chain counting and summing method is used to calculate the data reading address in the RAM group, thereby reducing the complexity of address calculation, enhancing the address access rule, and making the DFT / FFT implementation of ultra-long data and data with different base combinations easier.
Claims
1. A DFT / FFT structure and a DFT / FFT implementation method based on the structure, characterized in that: The structure includes a multiplexer, a RAM group, a branch selector, a calculation control unit, and a butterfly operation unit; the multiplexer controls the selection of whether to store the input data or the calculation intermediate result output by the butterfly operation unit in the RAM group, the branch selector is used to select whether to output the RAM group read data to the butterfly operation unit or directly output it as a DFT operation result, and the butterfly operation unit is configured with more than one butterfly calculation core; the calculation control unit controls the entire DFT calculation process, including a disorder control module, a mapping control module, a butterfly calculation data addressing calculation module, a multiplexer control module, a branch selector control module, and a butterfly operation parameter configuration module; The DFT / FFT implementation method based on the structure is an FFT time domain extraction method, and the time domain extraction method includes the following steps: Step 1) Assume that the DFT / FFT data length is N, decompose N into a combination of multiple bases, expressed as r max =max(r0,r1,…,r m ), r max Represents the maximum value of all bases; Step 2) Create a RAM group max dual-port sub-RAM, assuming r0>r1>…>r m ,During the butterfly operation, the bases are ordered from large to small; Step 3) Synchronize data input out of order and RAM group mapping through counter chain: Based on Create n0 counters modulo r0, n1 counters modulo r1, ... n m The module is r m The counter carries from the small-module counter to the large-module counter, counts the number of input data through the counter chain structure, calculates the row and column position in the RAM group corresponding to each data through the counter value, and stores the input data in the corresponding position; Step 4) Calculate the access address of the data during DFT / FFT calculation. During calculation, the carry relationship of the counter chain is reversed to become a reverse counter chain, and the carry is carried from the counter with a large modulus to the counter with a small modulus. The specific iterative steps are as follows: S1, the first iteration directly reads out by column, and in the process of reading data, the starting address of each column of data is calculated by the reverse counter chain, and the read data is cyclically shifted with the row position of the starting address as the offset position and then output to the butterfly operation unit, and the calculation result of the butterfly operation unit is written in situ into the RAM group; S2, the second iteration, the DFT / FFT calculation length is r0*r, and each r column in the RAM group is used as a block of data for DFT / FFT calculation, and the execution process is: the data at the 0th position filled in the rth column is read out at the same time, and output to the butterfly operation unit after circular shift, and the calculation result is written in situ into the RAM group; until the data at the r0-1th position filled in the rth column is read out at the same time, the butterfly operation is completed after circular shift, and the butterfly operation result is written in situ; S3, in the subsequent iterative processing, if the calculation length is r0*r*r', each r*r' column in the RAM group is used as a block of data for DFT / FFT calculation, and each r column in each block is used as a group. The execution process is as follows: each group in the block reads data from the 0th position filled in the 0th column at the same time, until the last position filled in the 0th column is read, and then the 1st column is read. The reading order of the 1st column is the same as that of the 0th column, and both are read from the 0th position filled to the last position filled in the column. Each time the r' data read out at the same time are cyclically shifted with the row position of the data read out in group 0 as the offset position and then output to the butterfly operation unit, and the butterfly operation unit writes the calculation result in situ into the RAM group; the remaining iterative operations read data according to the same idea; Step 5) Sequential reading of operation results: After the last butterfly operation is completed, the reverse counter chain is used to read out the data column by column. The order of reading each column of data is the order in which the data is filled in the column.
2. A DFT processing structure and a data processing method based on the structure according to claim 1, characterized in that: The butterfly operation core of the butterfly operation unit is implemented by table lookup or cordic method, and the butterfly operation core can perform pipeline processing on data.
3. A DFT / FFT structure and a DFT / FFT implementation method based on the structure according to claim 2, characterized in that: In step 3), the sub-RAM number (row number) where the input data needs to be stored is The address of the sub-RAM where the input data needs to be stored, i.e. the column number, is Where i is the number of counters of different modules, j is the number of different modules, and cnt represents the counter value.
4. A DFT / FFT structure and a DFT / FFT implementation method based on the structure according to claim 3, characterized in that: In step 4), in the first iteration, the row position of the first data in each column is determined according to the value in the reverse counter, that is, by calculating the sum of the counts of all counters except the lowest bit counter and r max The result after modulo calculation is used as the row address of the first data. The specific process is: The row address calculation formula is as follows: Among them, r max = r0; Based on the row address calculation formula, the first data row address is: The second data row address is: By analogy, the address of the r0th data row is: The column addresses are taken in order: The data read from the RAM group is output to the butterfly operation unit after circular shifting with the row position corresponding to the first data as the offset position, which is expressed by the following formula: data shift (i)=data read (mod(row o +i,r0)) Among them, data shift Represents the data after circular shift, data read Represents the data read from the RAM group, i=0~r0-1.
5. A DFT / FFT structure and a DFT / FFT implementation method based on the structure according to claim 4, characterized in that: In step 4), the address of the first column of data is calculated in the second iteration, and the addresses of other columns of data are calculated based on the address of the first column of data plus the offset address. The specific calculation process is: When n0≥3, the row address is: Wherein, k=0~r0-1, t=0~r-1, k represents the column number in the block, and t represents the sequence number of the read data; When n0=2, the row address is: Wherein, k=0~r0-1, t=0~r-1, k represents the column number in the block, and t represents the sequence number of the read data; When n0=1, the row address is: Wherein, k=0~r0-1, t=0~r-1, k represents the column number in the block, and t represents the sequence number of the read data; The above row address formula means: ignoring the two lowest-order counters, the sum of the counts of the remaining counters and k and t and the result modulo r is the row address; The column address of data read is: col = b*r + t, where b represents the block number; The above row and column addresses are traversed first according to the column address k, and then the read data sequence number t is traversed.
6. A DFT / FFT structure and a DFT / FFT implementation method based on the structure according to claim 5, characterized in that: In step 4), in the subsequent iterative processing, the data row and column address reading process is: When n0≥3, the row address is: Wherein, k=0~r-1, t=0~r'-1, k represents the column number in the group, and t represents the sequence number of the read data; When n0=2, the row address is: Wherein, k=0~r-1, t=0~r'-1, k represents the column number in the group, and t represents the sequence number of the read data; When n0=1, the row address is: Wherein, k=0~r-1, t=0~r'-1, k represents the column number in the group, and t represents the sequence number of the read data; The above row address formula indicates that: ignoring the two lowest-order counters, the sum of the counts of the remaining counters and k and t and the result modulo r' is the row address; The column address of data read is: col = b*B_size+t*G_size+g, where b represents the block number; B_size = r*r', represents the number of columns in the block; g represents the group number, G_size = r, represents the number of columns in the group; The above row and column addresses are traversed first according to the column address k, and then the read data sequence number t is traversed.
7. A DFT / FFT structure and a DFT / FFT implementation method based on the structure according to claim 6, characterized in that: After the last butterfly operation is completed, the data is output column by column. The reverse counter chain is used for output. The row address of the read data is t=0~r0-1; the column address is: Read the data in the RAM group at a time.
8. A DFT / FFT structure and a DFT / FFT implementation method based on the structure according to claim 1, characterized in that: The RAM data mapping method in the time domain extraction method and the data access method in the calculation process are applied to DFT / FFT frequency domain extraction to realize DFT / FFT frequency domain extraction based on the structure. The frequency domain extraction steps are as follows: Step 1) Assume that the DFT data length is N, decompose N into a combination of multiple bases, expressed as r max =max(r0,r1,…,r m ), r max Represents the maximum value of all bases; Step 2) Create a RAM group max sub-RAM, assuming r0>r1>…>r m ,During the butterfly operation, the bases are operated in ascending order; Step 3) Synchronize the data input sequence and RAM group mapping through the reverse counter chain, based on Create n0 counters modulo r0, n1 counters modulo r1, ... n m The module is r m The counter carries from the counter with a larger modulus to the counter with a smaller modulus, and the address calculation process thereof is consistent with the address calculation of the sequential reading of the operation results in the time domain extraction DFT / FFT calculation; Step 4) DFT / FFT calculates the access address of data: the read and write address of data is accessed using the iteration base opposite to the time domain extraction, that is, the execution process of the time domain extraction is the DFT / FFT segment calculation length from r0 to N, and the execution process of the frequency domain extraction is the DFT / FFT segment calculation length from N to r0; Step 5) Output of DFT / FFT frequency domain extraction operation results: The DFT / FFT frequency domain extraction calculation results are stored in random order in the RAM group, and the address in the RAM group is calculated using a calculation method consistent with the address calculation of the random order of the input data and the RAM group mapping in the time domain extraction, and then the data is read out.