Chip simulation acceleration method and device, electronic equipment and storage medium

Abstract

The invention provides a chip simulation acceleration method and device, electronic equipment and a storage medium, when a simulation program executes memory operation, the simulation program transmits parameters, types and to-be-operated data required by the operation to an executive program, the executive program completes the memory operation, and the executive program is independent of the simulation program and is not used for chip simulation, so that the memory operation is accelerated. According to the method, the real instruction execution process of the SOC does not need to be simulated, the memory operation can be directly carried out, the memory operation process in a simulation environment in the prior art is skipped, and the chip development and design efficiency is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip design, and in particular relates to a chip simulation acceleration method, device, electronic equipment and storage medium. Background Art

[0002] During the early front-end design process of the chip, its design needs to be verified by hardware, so RTL simulation is required to verify the correctness of the SOC chip logic design.

[0003] Taking the simulation program that simulates the actual SOC chip operation process in the RTL environment as an example, a large number of memory operations will be used in the program (such as the assignment operation function memset and the data transfer operation function memcpy), and the amount of data operated is not small. Since the simulation will perform a large number of simulated CPU calculations, such as when assigning values ​​to memory addresses and performing data transfer, the actual instruction execution process of the SOC chip will be simulated. During this period, a large amount of data and events will be generated, which makes the simulation speed very slow. However, the simulation of memory operations is not very meaningful for the verification of chip design. Summary of the invention

[0004] Based on this, in order to solve the above technical problems, a chip simulation acceleration method, device, electronic device and storage medium are provided.

[0005] The technical solution adopted by the present invention is as follows:

[0006] As a first aspect of the present invention, a chip simulation acceleration method is provided, wherein chip simulation is implemented by a simulation program, and the method is characterized by comprising:

[0007] When the simulation program performs a memory operation, the simulation program determines the parameters, type and data to be operated of this operation, wherein the parameters include the address and the length of the data operation, and the type corresponds to the memory operation;

[0008] The simulation program transmits the parameters, types and data to be operated to the execution program;

[0009] The execution program performs corresponding memory operations on the data to be operated according to the parameters and types.

[0010] As a second aspect of the present invention, a chip simulation acceleration device is provided, which implements chip simulation by a simulation program, and is characterized by comprising:

[0011] The first module is used for determining the parameters, type and data to be operated of this operation by the simulation program when the simulation program performs a memory operation, wherein the parameters include the address and the length of the data operation, and the type corresponds to the memory operation;

[0012] The second module is used for the simulation program to pass the parameters, types and data to be operated to the execution program;

[0013] The third module is used for the execution program to perform corresponding memory operations on the data to be operated according to the parameters and types.

[0014] As a third aspect of the present invention, there is provided an electronic device, characterized in that it comprises a storage module, wherein the storage module comprises instructions loaded and executed by a processor, wherein when the instructions are executed, the processor executes a chip simulation acceleration method of the first aspect.

[0015] As a fourth aspect of the present invention, a computer-readable storage medium is provided, which stores one or more programs, and is characterized in that when the one or more programs are executed by a processor, a chip simulation acceleration method of the above-mentioned first aspect is implemented.

[0016] When the simulation program of the present invention executes a memory operation, the simulation program passes the parameters, types and data to be operated required for the operation to the execution program, and the execution program completes the memory operation. Since the execution program is independent of the simulation program and is not used for chip simulation, it does not need to simulate the actual instruction execution process of the SOC chip and can directly perform memory operations, skipping the memory operation process in the simulation environment in the prior art, thereby improving the efficiency of chip development and design. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments:

[0018] Figure 1 A flowchart of a chip simulation acceleration method provided by an embodiment of the present invention;

[0019] Figure 2 A schematic diagram of a chip simulation acceleration device provided by an embodiment of the present invention;

[0020] Figure 3 A schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following will illustrate the implementation methods of the present invention in conjunction with the drawings in the specification. It should be noted that the implementation methods involved in this specification are not exhaustive and do not represent the only implementation methods of the present invention. The following corresponding embodiments are only for the purpose of clearly illustrating the invention content of the patent of the present invention, and are not intended to limit its implementation methods. For ordinary technicians in this field, different forms of changes and modifications can be made on the basis of the description of this embodiment. All obvious changes or modifications that belong to the technical concept and invention content of the present invention are also within the scope of protection of the present invention.

[0022] like Figure 1 As shown, the embodiment of the present application provides a chip simulation acceleration method, and its specific process is as follows:

[0023] S101. When the simulation program executes a memory operation, the simulation program determines the parameters, type and data to be operated of this operation.

[0024] The simulation program is used to implement chip simulation. The parameters include the length of the address and data operation. The type corresponds to the memory operation, that is, it is used to characterize which memory operation this operation is.

[0025] When the memory operation is an assignment operation (memset), the address includes the target address and the type is assignment; when the memory operation is a data transfer operation (memcpy), the address includes the source address and the target address and the type is transfer.

[0026] S102, the simulation program passes the parameters, types and data to be operated to the execution program.

[0027] The execution program is independent of the simulation program and is not used for chip simulation. It does not need to simulate the actual instruction execution process of the SOC chip.

[0028] In this embodiment, the simulation program writes the parameters, types and data to be operated into the target memory area, and the execution program obtains the parameters, types and data to be operated from the target memory area.

[0029] Among them, the size of the target memory area is 8 bytes, which includes a first sub-area for storing a flag value type and a second sub-area for storing information val indicated by the flag value type in the first sub-area, and the sizes of the first sub-area and the second sub-area are both 2 bytes.

[0030] Although the first sub-area and the second sub-area occupy only 4 bytes in total, since the simulation program directly writes 8 bytes of content to a certain memory address each time, 4 bytes of memory are reserved to avoid operating on illegal memory addresses.

[0031] Memory Address byte7 byte6 byte5 byte4 byte3 byte2 byte1 byte0 Storage Content N / A N / A N / A N / A val[15:8] val[7:0] type[15:8] type[7:0]

[0032] Table 1

[0033] As shown in Table 1, in this embodiment, the first sub-area occupies two bytes, byte0 and byte1, the second sub-area occupies two bytes, byte2 and byte3, and bytes4-7 are reserved areas.

[0034] The flag value is a hexadecimal value, and there are 15 types in total, each corresponding to different information.

[0035] In this embodiment, the 15 flag values ​​may be 0x0000-0x000e, and the corresponding relationships with different information are as follows:

[0036] 0x0000-0x0003 correspond to the lower 16-bit data, two middle 16-bit data and upper 16-bit data of the source address respectively.

[0037] 0x0004-0x0007 correspond to the lower 16-bit data, two middle 16-bit data and upper 16-bit data of the target address respectively.

[0038] 0x0008-0x000b correspond to the lower 16-bit data, two middle 16-bit data and the upper 16-bit data of the data to be operated.

[0039] 0x000c and 0x000d correspond to the lower 16 bits and higher 16 bits of the length respectively.

[0040] 0x000e corresponds to type data. Type data can be represented by 0x0 for assignment and 0x10 for transfer.

[0041] It is understandable that the 15 flag values ​​are not limited to 0x0000-0x000e, and the corresponding relationship with different information is not limited to the above relationship.

[0042] Thus, the simulation program writes the flag values ​​and corresponding information into the first sub-area and the second sub-area in batches, thereby writing the parameters, types and data to be operated into the target memory area.

[0043] Taking writing the source address as an example, it consists of the lower 16-bit data, two middle 16-bit data and the upper 16-bit data, a total of 64 bits, so it needs to be written in 4 times:

[0044] 1. Write 0x0000 and lower 16-bit data to the first sub-area and the second sub-area respectively;

[0045] 2. Write 0x0001 and an intermediate 16-bit data to the first sub-area and the second sub-area respectively;

[0046] 3. Write 0x0002 and an intermediate 16-bit data to the first sub-area and the second sub-area respectively;

[0047] 4. Write 0x0003 and high 16-bit data to the first sub-area and the second sub-area respectively.

[0048] Accordingly, the specific process of executing the program to obtain parameters, types, and data to be operated from the target memory area is as follows:

[0049] S21, real-time monitoring of the target memory area;

[0050] S22. When the target memory area is written, the written flag value and information are read.

[0051] S23. Determine the parameters, type and data to be operated according to the flag value.

[0052] Continuing with the above example, the execution program reads from the target memory area four times: 0x0000 and the lower 16-bit data, 0x0001 and an intermediate 16-bit data, 0x0002 and an intermediate 16-bit data, and 0x0003 and the upper 16-bit data. Then, according to 0x0000-0x0003, the corresponding 16-bit data are spliced ​​to obtain the source address.

[0053] Similarly, the executing program can obtain other parameters, types and data to be operated on respectively.

[0054] S103: The executing program performs corresponding memory operations on the data to be operated according to the parameters and types.

[0055] Among them, memory operations are performed in units of 1 byte by default.

[0056] If the type data obtained by executing the program is 0x0, it means an assignment operation is performed, and the data to be operated is assigned to the target address in units of 1 byte each time.

[0057] From the above, it can be seen that an embodiment of the present application provides a chip simulation acceleration method. When the simulation program executes a memory operation, the simulation program passes the parameters, types and data to be operated required for the operation to the execution program, and the execution program completes the memory operation. Since the execution program is independent of the simulation program and is not used for chip simulation, it does not need to simulate the actual instruction execution process of the SOC chip, and can directly perform memory operations, skipping the memory operation process in the simulation environment in the prior art, thereby greatly improving the chip simulation speed and improving the efficiency of chip development and design.

[0058] The chip simulation acceleration device of one or more embodiments of the present invention will be described in detail below. Those skilled in the art will appreciate that these devices can be configured using commercially available hardware components through the steps taught in this solution. Figure 2 A chip simulation acceleration device provided by an embodiment of the present invention is shown. Figure 2 As shown, the device includes a first module 11 , a second module 12 and a third module 13 .

[0059] The first module 11 is used for determining the parameters, type and data to be operated of the operation by the simulation program when the simulation program performs the memory operation.

[0060] The simulation program is used to implement chip simulation. The parameters include the length of the address and data operation. The type corresponds to the memory operation, that is, it is used to characterize which memory operation this operation is.

[0061] When the memory operation is an assignment operation (memset), the address includes the target address and the type is assignment; when the memory operation is a data transfer operation (memcpy), the address includes the source address and the target address and the type is transfer.

[0062] The second module 12 is used for transmitting parameters, types and data to be operated from the simulation program to the execution program.

[0063] The execution program is independent of the simulation program and is not used for chip simulation. It does not need to simulate the actual instruction execution process of the SOC chip.

[0064] In this embodiment, the simulation program writes the parameters, types and data to be operated into the target memory area, and the execution program obtains the parameters, types and data to be operated from the target memory area.

[0065] Among them, the size of the target memory area is 8 bytes, which includes a first sub-area for storing a flag value type and a second sub-area for storing information val indicated by the flag value type in the first sub-area, and the sizes of the first sub-area and the second sub-area are both 2 bytes.

[0066] Although the first sub-area and the second sub-area occupy only 4 bytes in total, since the simulation program directly writes 8 bytes of content to a certain memory address each time, 4 bytes of memory are reserved to avoid operating on illegal memory addresses.

[0067] As shown in Table 1, in this embodiment, the first sub-area occupies two bytes, byte0 and byte1, the second sub-area occupies two bytes, byte2 and byte3, and bytes4-7 are reserved areas.

[0068] The flag value is a hexadecimal value, and there are 15 types in total, each corresponding to different information.

[0069] In this embodiment, the 15 flag values ​​may be 0x0000-0x000e, and the corresponding relationships with different information are as follows:

[0070] 0x0000-0x0003 correspond to the lower 16-bit data, two middle 16-bit data and upper 16-bit data of the source address respectively.

[0071] 0x0004-0x0007 correspond to the lower 16-bit data, two middle 16-bit data and upper 16-bit data of the target address respectively.

[0072] 0x0008-0x000b correspond to the lower 16-bit data, two middle 16-bit data and the upper 16-bit data of the data to be operated.

[0073] 0x000c and 0x000d correspond to the lower 16 bits and higher 16 bits of the length respectively.

[0074] 0x000e corresponds to type data. Type data can be represented by 0x0 for assignment and 0x10 for transfer.

[0075] It is understandable that the 15 flag values ​​are not limited to 0x0000-0x000e, and the corresponding relationship with different information is not limited to the above relationship.

[0076] Thus, the simulation program writes the flag values ​​and corresponding information into the first sub-area and the second sub-area in batches, thereby writing the parameters, types and data to be operated into the target memory area.

[0077] Taking writing the source address as an example, it consists of the lower 16-bit data, two middle 16-bit data and the upper 16-bit data, a total of 64 bits, so it needs to be written in 4 times:

[0078] 1. Write 0x0000 and lower 16-bit data to the first sub-area and the second sub-area respectively;

[0079] 2. Write 0x0001 and an intermediate 16-bit data to the first sub-area and the second sub-area respectively;

[0080] 3. Write 0x0002 and an intermediate 16-bit data to the first sub-area and the second sub-area respectively;

[0081] 4. Write 0x0003 and high 16-bit data to the first sub-area and the second sub-area respectively.

[0082] Accordingly, the specific process of executing the program to obtain parameters, types, and data to be operated from the target memory area is as follows:

[0083] S21, real-time monitoring of the target memory area;

[0084] S22. When the target memory area is written, the written flag value and information are read.

[0085] S23. Determine the parameters, type and data to be operated according to the flag value.

[0086] Continuing with the above example, the execution program reads from the target memory area four times: 0x0000 and the lower 16-bit data, 0x0001 and an intermediate 16-bit data, 0x0002 and an intermediate 16-bit data, and 0x0003 and the upper 16-bit data. Then, according to 0x0000-0x0003, the corresponding 16-bit data are spliced ​​to obtain the source address.

[0087] Similarly, the executing program can obtain other parameters, types and data to be operated on respectively.

[0088] The third module 13 is used for the executing program to perform corresponding memory operations on the data to be operated according to the parameters and types.

[0089] Among them, memory operations are performed in units of 1 byte by default.

[0090] If the type data obtained by executing the program is 0x0, it means an assignment operation is performed, and the data to be operated is assigned to the target address in units of 1 byte each time.

[0091] In summary, the chip simulation acceleration device provided in the above embodiment can execute the chip simulation acceleration method provided in the above embodiments.

[0092] The same as above concept, Figure 2 The structure of the chip simulation acceleration device shown can be implemented as an electronic device. Figure 3 A schematic block diagram of the structure of an electronic device provided by an embodiment of the present invention is shown.

[0093] Exemplarily, the electronic device includes a storage module 21 and a processor 22, the storage module 21 includes instructions loaded and executed by the processor 22, and when the instructions are executed, the processor 22 executes the steps of various exemplary embodiments of the present invention described in the above-mentioned chip simulation acceleration method section of this specification.

[0094] It should be understood that the processor 22 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0095] A computer-readable storage medium is also provided in an embodiment of the present invention. The computer-readable storage medium stores one or more programs. When the one or more programs are executed by a processor, the steps of various exemplary embodiments of the present invention described in the above-mentioned chip simulation acceleration method are implemented.

[0096] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable storage medium, which may include a computer-readable storage medium (or a non-transitory medium) and a communication medium (or a temporary medium).

[0097] As is known to those of ordinary skill in the art, the term computer-readable storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer-readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, it is known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.

[0098] Exemplarily, the computer-readable storage medium may be an internal storage unit of the electronic device of the aforementioned embodiment, such as a hard disk or memory of the electronic device. The computer-readable storage medium may also be an external storage device of the electronic device, such as a plug-in hard disk, a smart memory card (SmartMediaCard, SMC), a secure digital (SecureDigital, SD) card, a flash memory card (FlashCard), etc. equipped on the electronic device.

[0099] The electronic device and computer-readable storage medium provided by the aforementioned embodiments are such that when the simulation program executes a memory operation, the simulation program passes the parameters, type and data to be operated required for the operation to the execution program, and the execution program completes the memory operation. Since the execution program is independent of the simulation program and is not used for chip simulation, it does not need to simulate the actual instruction execution process of the SOC chip and can directly perform memory operations, skipping the memory operation process in a simulation environment in the prior art, thereby greatly improving the chip simulation speed and the efficiency of chip development and design.

[0100] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A chip simulation acceleration method, wherein chip simulation is implemented by a simulation program, characterized in that: include: When the simulation program performs a memory operation, the simulation program determines the parameters, type and data to be operated of this operation, wherein the parameters include the address and the length of the data operation, and the type corresponds to the memory operation; The simulation program transmits the parameters, types and data to be operated to the execution program; The execution program performs corresponding memory operations on the data to be operated according to the parameters and types.

2. A chip simulation acceleration method according to claim 1, characterized in that: When the memory operation is an assignment operation, the address includes a target address, and the type is assignment; when the memory operation is a data transfer operation, the address includes a source address and a target address, and the type is transfer.

3. A chip simulation acceleration method according to claim 2, characterized in that: The simulation program passing the parameters, types and data to be operated to the execution program further comprises: The simulation program writes the parameters, types and data to be operated into a target memory area, and the execution program obtains the parameters, types and data to be operated from the target memory area.

4. A chip simulation acceleration method according to claim 3, characterized in that: The target memory area includes a first sub-area for storing a flag value and a second sub-area for storing information indicated by the flag value in the first sub-area. The sizes of the first sub-area and the second sub-area are both 2 bytes. The flag value is a hexadecimal value, which has 15 types in total and corresponds to the following information one by one: The low 16-bit data of the source address, the high 16-bit data of the source address, an intermediate 16-bit data of the source address, another intermediate 16-bit data of the source address, the low 16-bit data of the target address, the high 16-bit data of the target address, an intermediate 16-bit data of the target address, another intermediate 16-bit data of the target address, the low 16-bit data of the data to be operated, the high 16-bit data of the data to be operated, an intermediate 16-bit data of the data to be operated, another intermediate 16-bit data of the data to be operated, the low 16-bit data of the length, the high 16-bit data of the length and the type data, wherein the type data represents assignment and transfer with different hexadecimal values.

5. A chip simulation acceleration method according to claim 4, characterized in that: 15 flag values ​​are 0x0000-0x000e; in: 0x0000-0x0003 correspond to the lower 16-bit data, two middle 16-bit data and the upper 16-bit data of the source address in sequence; 0x0004-0x0007 correspond to the lower 16-bit data, two middle 16-bit data and the upper 16-bit data of the target address in sequence; 0x0008-0x000b correspond to the lower 16-bit data, two middle 16-bit data and the upper 16-bit data of the data to be operated in sequence; 0x000c and 0x000d correspond to the lower 16 bits and higher 16 bits of the length respectively; 0x000e corresponds to type data, and the type data uses 0x0 to represent assignment and 0x10 to represent transfer.

6. A chip simulation acceleration method according to claim 5, characterized in that: The simulation program writes the parameters, types and data to be operated into the target memory area, further comprising: The flag values ​​and corresponding information are written into the first sub-area and the second sub-area in batches.

7. A chip simulation acceleration method according to claim 6, characterized in that: The executing program obtains the parameter, type and data to be operated from the target memory area, further comprising: monitoring the target memory area in real time; When the target memory area is written, reading the written flag value and information; According to the flag value, the parameter, type and data to be operated are determined.

8. A chip simulation acceleration device, which implements chip simulation by a simulation program, characterized in that: include: The first module is used for determining the parameters, type and data to be operated of this operation by the simulation program when the simulation program performs a memory operation, wherein the parameters include the address and the length of the data operation, and the type corresponds to the memory operation; The second module is used for the simulation program to pass the parameters, types and data to be operated to the execution program; The third module is used for the execution program to perform corresponding memory operations on the data to be operated according to the parameters and types.

9. An electronic device, characterized in that: It comprises a storage module, wherein the storage module comprises instructions loaded and executed by a processor, and when the instructions are executed, the processor executes a chip simulation acceleration method according to any one of claims 1-7.

10. A computer-readable storage medium storing one or more programs, characterized in that: When the one or more programs are executed by the processor, a chip simulation acceleration method as described in any one of claims 1 to 7 is implemented.

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