Apparent defect intelligent detection method for chip test carrier

Abstract

The invention discloses an intelligent detection method for appearance defects of a chip test carrier, and the method comprises the steps: obtaining a plurality of images of the chip test carrier, carrying out the image segmentation based on deep learning, and obtaining a plurality of first images; performing feature extraction on the first image and the spatial structure information of the chip test carrier through a multi-modal feature extraction network to obtain a first image feature; the first image feature is a high-dimensional feature vector fusing space structure information and image information of the chip test carrier; performing defect detection on the first image feature through a defect detection network, and outputting a defect detection result; the defect detection result comprises the defect position, the defect type and the probability of the defect type of the chip test carrier. The whole process from image acquisition to defect identification is automatic, subjective errors of manual detection are avoided, consistency and efficiency are improved, and cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence technology, and in particular to an intelligent detection method for appearance defects of a chip test carrier. Background Art

[0002] Chip test trays (Test Tray) will have defects such as wear and aging during use, which will directly affect the test results of the product, so the Test Tray needs to be regularly inspected for defects.

[0003] 1. Currently, the appearance defect detection of the test tray is mostly carried out manually. Due to individual differences and other reasons, manual detection may result in missed detection and false detection, and the detection efficiency is low.

[0004] 2. The existing traditional visual inspection method has limited detection accuracy for test trays. Although the detection speed is better than manual inspection, the detection rate of irregular defects by traditional algorithms is not high, and there are still problems of missed detection and false detection.

[0005] 3. The existing inspection equipment takes a long time to inspect a test tray because there are many areas to be inspected and the images to be processed are complex. Summary of the invention

[0006] Technical purpose: In response to the defects in the prior art, the present invention discloses an intelligent detection method for the appearance defects of a chip test carrier, which automates the entire process from image acquisition to defect identification, avoids subjective errors in manual detection, improves consistency and efficiency, and reduces costs.

[0007] Technical solution: In order to achieve the above technical objectives, the present invention adopts the following technical solution.

[0008] A method for intelligently detecting appearance defects of a chip test carrier comprises the following steps:

[0009] S1. Acquire several images of a chip test carrier, perform image segmentation based on deep learning, and obtain several first images;

[0010] S2. Extracting features of the first image and the spatial structure information of the chip test carrier through a multimodal feature extraction network to obtain a first image feature; the first image feature is a high-dimensional feature vector that integrates the spatial structure information and image information of the chip test carrier;

[0011] S3. Perform defect detection on the first image feature through a defect detection network and output a defect detection result; the defect detection result includes a defect position, defect type and probability of the defect type of the chip test carrier.

[0012] Beneficial effects:

[0013] 1. The present invention combines deep learning with a multimodal feature extraction network to integrate the spatial structure and image information of the chip test carrier, so that the appearance defect detection method of the present invention can accurately identify complex and irregular defects and significantly reduce missed detections and false detections;

[0014] 2. The defect detection network of the present invention adopts a cascade detection network and a lightweight neural network, which greatly improves the detection speed, and optimizes the calculation through a feature reuse mechanism, reducing unnecessary calculation redundancy;

[0015] 3. The present invention performs image segmentation based on deep learning, can automatically adjust the detection strategy according to the characteristics of different chip test carriers, has wide applicability, and is adaptable to different test scenarios and models;

[0016] 4. The present invention automates the entire process from image acquisition to defect identification, avoiding subjective errors in manual inspection, improving consistency and efficiency, and reducing costs;

[0017] 5. The present invention can not only identify the defect type, but also accurately locate the defect position and perform detailed classification according to the hierarchical structure to ensure higher diagnostic accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a flow chart of the method of the present invention;

[0019] Figure 2 It is a simulation verification schematic diagram of the present invention. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0021] As attached Figure 1 As shown, a method for intelligently detecting appearance defects of a chip test carrier of the present invention comprises the following steps:

[0022] S1. Acquire several images of the chip test carrier, perform image segmentation based on deep learning, and obtain several first images; in view of the feature differences of different models of Test Tray, the present invention designs an adaptive image segmentation algorithm based on deep learning. The algorithm first uses an improved U-Net network to semantically segment the overall structure of the Test Tray and identify various functional areas. Then, a region of interest (ROI) is dynamically generated based on the recognition results, and specific image enhancement and denoising techniques are applied to each ROI. For example, for highly reflective areas, adaptive histogram equalization is used; for shadow areas, a shadow removal algorithm based on guided filtering is applied. This method significantly improves the pertinence and accuracy of subsequent defect detection.

[0023] S2. Extracting features of the first image and the spatial structure information of the chip test carrier through a multimodal feature extraction network to obtain a first image feature; the first image feature is a high-dimensional feature vector that integrates the spatial structure information and image information of the chip test carrier;

[0024] In the multimodal feature extraction network, the 3D CAD model of the chip test vehicle is fused with the first image to extract features and output the first image features; the steps include:

[0025] S21, constructing a multimodal feature extraction network; the multimodal feature extraction network includes a CNN network for extracting features from the first image, a GCN network for extracting features from the spatial structure information of the chip test carrier, and a feature fusion module for fusing features of the first image features and spatial structure features;

[0026] The CNN network for extracting features from the first image uses an existing CNN network, with the first image as input and image features as output. The image features mainly represent the surface texture, illumination and reflection information of the chip test carrier.

[0027] In the GCN network that extracts the spatial structure information of the chip test carrier, the input is the 3D CAD model of the chip test carrier, and the output is the spatial structure feature, which captures the structure and spatial layout of the chip test carrier;

[0028] The construction of the GCN network includes the following steps:

[0029] S211, converting the 3D CAD model of the chip test vehicle into a plurality of 2D projection images through multi-view projection so as to align with the first image. The angle of the projection image is consistent with the angle of the first image to ensure that the geometric information is not distorted. The multi-view projection conversion process includes:

[0030] S2111. Convert the 3D CAD model of the chip test carrier into a 2D projection image, that is, M_2D=Proj(M_3D); wherein M_2D is a two-dimensional projection image converted from M_3D, which retains the geometric information of the original three-dimensional model but has been reduced to a two-dimensional space, M_3D is the 3D CAD model of the chip test carrier, which contains complete three-dimensional structure information, and Proj is a projection operation symbol, which indicates that the three-dimensional model M_3D is converted into a two-dimensional plane image through orthogonal projection;

[0031] S2112, perform image registration on the projection image and the first image through affine transformation, correct the geometric difference between the first image and the projection image by detecting and matching key points, align the two in space, and ensure the consistency of feature extraction. The calculation formula of the affine transformation matrix includes:

[0032] T=arg min||IT(M_2D)|| 2

[0033] Wherein, T is the affine transformation matrix, T(M_2D) is the image of M_2D after being processed by the affine transformation matrix, and I is the first image;

[0034] S212, constructing a 3D CAD model of a graph convolutional network (GCN) processing chip test carrier; comprising the following steps:

[0035] S2121. Construct a graph G, G=(V, E), where V is a key component, i.e., a physical component in a 3D CAD model of a chip test vehicle, and E is a component relationship, i.e., a positional relationship or a functional relationship between physical components;

[0036] S2122. Construct a graph convolutional network GCN based on the graph G. The update rule of GCN is:

[0037]

[0038] Among them, H I+1 is the node feature matrix of the I+1th layer, σ is the activation function, D is the degree matrix, For the adjacency matrix with self-loops added, A is the adjacency matrix, H I is the node feature matrix of layer I, W I is the weight matrix of the Ith layer, which is the trainable parameter of the graph convolutional network GCN;

[0039] The feature fusion module that fuses image features and spatial structure features takes image features and spatial structure features as input and outputs the first image feature F_fused. The calculation formula is:

[0040] F_fused=Concat[F_CNN,F_GCN]

[0041] Among them, F_CNN=CNN(I) represents the image features output by the CNN network; F_GCN=GCN(G) represents the spatial structure features output by the GCN network.

[0042] S22. Train and optimize the multimodal feature extraction network. First, pre-train the CNN network and GCN network:

[0043] CNN network pre-training: Pre-train the CNN network on a large-scale general image dataset to learn common image features such as edges, textures, and shapes. Through transfer learning, the pre-trained CNN is applied to images of chip test vehicles for fast convergence.

[0044] GCN network pre-training: The GCN network is pre-trained on a graph dataset with a similar structure to the chip test vehicle. This process helps the network learn how to propagate and aggregate node information in the graph structure, especially for capturing spatial relationships.

[0045] Secondly, based on pre-training, the CNN network and the GCN network are combined and fine-tuned for specific chip test vehicle data. By minimizing the loss function of multimodal features, the optimal feature fusion method is learned. The loss function is designed, which includes not only the 2D image, that is, the classification loss of the first image, but also the graph convolution loss for the 3DCAD model.

[0046] Thirdly, a phased training method is adopted. First, the CNN and GCN networks are trained to enable them to stably extract 2D and 3D features. Then, the two are fused to jointly train the multimodal feature extraction network. In the early stage of training, some weights of CNN or GCN are frozen to prevent overfitting of the multimodal feature extraction network during the fine-tuning stage. At the same time, during the fusion training process of the multimodal feature extraction network, the weights of each layer are gradually unfrozen for overall optimization.

[0047] Use a learning rate scheduler during training to ensure that the multimodal feature extraction network can converge more smoothly in the later stages of training. To prevent the multimodal feature extraction network from overfitting, use L2 regularization techniques, especially in the CNN part, to prevent the CNN network from over-relying on specific image features. When training deep networks, use gradient clipping to avoid the gradient explosion problem and ensure that the gradient is updated stably during training.

[0048] Finally, the validation set is used to evaluate the multimodal feature extraction network, and the parameters of the multimodal feature extraction network are adjusted by monitoring performance indicators such as accuracy and recall in the actual defect detection task of the chip test vehicle. After completing the initial training, CNN and GCN are fine-tuned to adapt to specific defect detection tasks to ensure the effectiveness of the multimodal feature extraction network for actual application scenarios. In the final deployment stage, the trained multimodal feature extraction network is optimized using model compression technology to reduce the model size and increase the inference speed so that defect detection tasks can be quickly performed in the actual test environment.

[0049] S3, perform defect detection on the first image feature through the defect detection network, and output the defect detection result; the defect detection result includes: 1. defect type and probability of defect type, identifying the specific appearance defect type of the chip test carrier and the probability value of each appearance defect type; 2. defect location, output the location information of the defect. Specifically, it includes the following steps:

[0050] S31. Build a defect detection network. Build a defect hierarchy for the appearance defects of the chip test carrier. Based on the defect hierarchy, build a defect detection network for cascade detection, and introduce feature reuse and soft decision mechanisms in the defect detection network.

[0051] First, based on the physical characteristics and visual similarities of defects, the defects of the Test Tray are defined as the following 14 defect types: Insert buckle breakage, Insert buckle opening and closing angle abnormality, Insert buckle missing, Insert buckle damaged, Insert bottom net detachment, Insert bottom net damaged, Insert body damaged, Insert body deformation, HiFix socket appearance damage, HiFix socket conductive glue damage, HiFix socket dirt attachment, HiFix socket fixing screws, HiFix socket Pin missing, HiFix back connector damaged; the 14 types of defects are organized into a three-layer defect hierarchy. The top layer is the main defect type, including structural defects and surface defects. The middle layer is subdivided into more specific defect categories. Structural defects include Insert-related defects and HiFix-related defects. Insert-related defects correspond to buckle problems, bottom net problems and main body problems. HiFix-related defects correspond to socket problems, connector problems and component problems. Surface defects include appearance defects. The bottom layer is the final 14 types of specific defects. Among Insert-related defects, buckle problems include Insert buckle breakage, Insert buckle opening and closing angle abnormality, Insert buckle missing, and Insert buckle damage. Bottom net problems include Insert bottom net detachment and Insert bottom net damage. Main body problems include Insert main body damage and Insert main body deformation. Among HiFix-related defects, socket problems include HiFix socket appearance damage and HiFix socket conductive glue damage. Connector problems include HiFix back connector damage. Component problems include HiFix socket fixing screws and HiFix socket Pin missing.

[0052] This structure allows the model to learn defect features at different levels, improving classification accuracy and robustness.

[0053] Based on the defect hierarchy, the defect detection network of the present invention is designed as a cascade detection defect detection network. The cascade detection defect detection network includes three stages of detectors, each stage corresponding to a level of the classification system. The first stage quickly identifies the main defect types, the second stage performs more specific defect classification in the selected category, and the last stage performs the underlying defect classification. Each stage uses a specially trained lightweight network, which greatly improves the detection efficiency. At the same time, cross-stage feature reuse and soft decision mechanisms are introduced to ensure high accuracy while maintaining computational efficiency.

[0054] The defect detection network is based on the defect hierarchy. Let x be the input image feature, y i is the output of the i-th stage, i=1,2,3, and its calculation formula is:

[0055] Phase 1: Quickly identify the main defect types:

[0056] P(y1|x), y1∈{structural defect, surface defect}

[0057] Among them, P(y1|x) represents the probability that the main defect type is y1 when the input feature x is given;

[0058] The first stage is designed as a lightweight convolutional neural network (CNN) to quickly identify the main defect types of chip test carriers. The input is the first image feature, that is, the input feature x, and the output is P(y1|x), which is the preliminary prediction result of the main defect category, expressed as the category label of the main defect type; it is used to distinguish large defect categories through rapid classification, so as to facilitate more detailed detection in subsequent stages.

[0059] Phase 2: Identify more specific defect categories within the selected major defect types, i.e. mid-level defect types:

[0060] P(y2|x, y1), y2∈{Insert related defects, HiFix related defects, appearance defects}

[0061] Among them, P(y2|x, y1) represents the probability that the main defect type is y1 and the more specific defect category is y2 when the input feature x is given;

[0062] The second stage is designed as a more complex classification network, which is still a lightweight convolutional network, but adds more levels of convolution and pooling operations to process more detailed information. The input is a feature subset of the main defect categories output by the first stage. The output is a more specific defect category prediction result, which is used to accurately classify into more specific defect categories through step-by-step refinement, providing a basis for accurate classification in the third stage.

[0063] Phase 3: Identify the final 14 specific defects at the bottom level:

[0064] P(y3|x,y1,y2), y3∈{14 types of specific defects}

[0065] Where P(y3|x, y1, y2) represents the probability that the main defect type is y1, the more specific defect category is y2, and the underlying defect type is y3 given the input feature x;

[0066] The output of the defect detection network, that is, the final classification probability, is calculated by the Bayesian rule, and then:

[0067] P(y3|x)=P(y3|x, y1, y2)*P(y2|x, y1)*P(y1|x)

[0068] Among them, P(y3|x) represents the output of the defect detection network, that is, the probability that the underlying defect type is y3 when the input feature x is given; this probability comprehensively considers the classification of all levels and directly predicts the specific defect category.

[0069] The third stage is designed as a cascaded refined detection network, a fully convolutional network with more feature maps; the input is the detailed category prediction results output by the second stage and the regional features in the image. This stage combines specific areas and focuses on the defect areas that have been preliminarily identified; the output is the final 14 categories of specific defects at the bottom layer, and the specific defect locations are marked. In addition, this stage may also output defect confidence, that is, the probability of the defect type.

[0070] Goal: Provide final, detailed classification and precise location detection, ensuring the system outputs the specific defect type and its location in the image.

[0071] In order to improve efficiency and accuracy, the present invention also introduces feature reuse and soft decision mechanism in the defect detection network:

[0072] For feature reuse, feature extraction functions are defined for the three stages: f1(x), f2(x), and f3(x). Feature extraction functions are implemented through feature extraction networks. Each feature extraction function can be represented as a neural network module, which consists of multiple convolutional layers or other deep learning modules. They are specifically used to extract specific features and can be used as input processing modules for each stage in the defect detection network. The calculation formula for feature reuse is:

[0073]

[0074] Among them, g2 and g3 are lightweight feature conversion networks, which are composed of shallow convolution layers, deep separable convolution layers, bottleneck layers, etc., and can maintain low computational overhead in different feature conversion stages. Before the classification task of each stage, lightweight feature conversion networks g2 and g3 are added so that the features output in the previous stage can be effectively compressed or converted, providing efficient input for the classification task of the next stage. Through the feature sharing mechanism, g2 and g3 can reuse some of the features extracted in the previous stage, making the feature transfer between different stages of the network more efficient and avoiding unnecessary repeated calculations.

[0075] For the soft decision mechanism, the first threshold τ1 and the second threshold τ2 are introduced. The judgment process of the soft decision mechanism is as follows:

[0076]

[0077] S32, training and optimizing defect detection network;

[0078] First, the defect detection network is pre-trained, and the underlying feature extraction network, namely the CNN network and GCN network in the multimodal feature extraction network, is pre-trained on a large-scale general dataset, and then fine-tuned using domain-specific data.

[0079] Second, the defect detection network is progressively trained:

[0080] 1. First, train the first-stage network; corresponding to the feature extraction function f1(x), it mainly deals with the preliminary classification task;

[0081] 2. Fix the first-stage parameters and train the second-stage network, corresponding to the feature extraction function f2(x), to handle more fine-grained defect classification;

[0082] 3. Finally, fine-tune the entire defect detection network.

[0083] Thirdly, knowledge distillation is performed on the defect detection network; the integrated model is used as the teacher network and the distillation loss is introduced, where P teacher is the teacher model, P student For the student model, the calculation formula of knowledge distillation is:

[0084] L_dist = KL(P teacher (y|x)||P student (y|x)

[0085] Among them, L_dist is the knowledge distillation loss, KL is the Kullback-Leibler divergence, which is used to measure the difference between two probability distributions, P teacher (y|x) is the probability distribution of the teacher model predicting category y given input x, P student (y|x) is the probability distribution of the student model predicting category y given the input x;

[0086] Finally, the defect detection network is optimized through multi-task learning;

[0087] A multi-task loss function is constructed to optimize all stages of the defect detection network. The calculation formula of the multi-task loss function is:

[0088]

[0089] Among them, L is the total loss function, α1, α2, and α3 are the balance factors of the first stage, the second stage, and the third stage respectively, y1, are the true labels of the first stage, the predicted output of the first stage network, y2, are the true label of the second stage, the predicted output of the second stage network, y3, are the true labels of the third stage and the predicted output of the network of the third stage, respectively. L1, L2, and L3 are the cross entropy loss functions of the first stage, the second stage, and the third stage, respectively. λ is the regularization coefficient, θ is the parameter of the model, and R(θ) is the regularization term.

[0090] S33, performing defect detection on the first image feature according to the trained and optimized defect detection network, and outputting the defect detection result;

[0091] like Figure 2 As shown, compared with existing deep learning methods and traditional visual detection, the method of the present invention has higher accuracy values ​​in multimodal feature extraction, hierarchical cascade detection, feature fusion optimization and final high-precision detection, that is, the method of the present invention is more effective in practical applications.

[0092] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for intelligently detecting appearance defects of a chip test carrier, characterized in that: The following steps are involved: S1. Acquire several images of a chip test carrier, perform image segmentation based on deep learning, and obtain several first images; S2. Extracting features of the first image and the spatial structure information of the chip test carrier through a multimodal feature extraction network to obtain a first image feature; the first image feature is a high-dimensional feature vector that integrates the spatial structure information and image information of the chip test carrier; S3. Perform defect detection on the first image feature through a defect detection network and output a defect detection result; the defect detection result includes a defect position, defect type and probability of the defect type of the chip test carrier.

2. The method for intelligently detecting appearance defects of a chip test carrier according to claim 1, characterized in that: The multimodal feature extraction network in S2 includes a CNN network for extracting features from the first image, a GCN network for extracting features from the spatial structure information of the chip test carrier, and a feature fusion module for fusing features of the first image and the spatial structure features; The CNN network for extracting features from the first image adopts an existing CNN network, with the first image as input and image features as output; In the GCN network that extracts the spatial structure information of the chip test carrier, the input is the 3D CAD model of the chip test carrier, and the output is the spatial structure feature; The feature fusion module performs feature fusion on the image feature and the spatial structure feature, and its input is the image feature and the spatial structure feature, and its output is the first image feature.

3. The method for intelligently detecting appearance defects of a chip test carrier according to claim 2, characterized in that: The construction of the GCN network includes the following steps: Converting the 3D CAD model of the chip test carrier into a plurality of 2D projection images through multi-view projection so as to align with the first image; Construct a GCN network to process the 3D CAD model of the chip test carrier; in the GCN network, first construct a graph G, G = (V, E), where V is the key component, that is, the physical component in the 3D CAD model of the chip test carrier, and E is the component relationship, that is, the positional connection relationship or functional connection relationship between the physical components; then construct a graph convolutional network GCN based on the graph G.

4. The method for intelligently detecting appearance defects of a chip test carrier according to claim 3, characterized in that: The update rule of GCN is: Among them, H I+1 is the node feature matrix of the I+1th layer, σ is the activation function, D is the degree matrix, For the adjacency matrix with self-loops added, A is the adjacency matrix, H I is the node feature matrix of layer I, W I is the weight matrix of the Ith layer.

5. The method for intelligently detecting appearance defects of a chip test carrier according to claim 1, characterized in that: S3 includes the following steps: S31. Build a defect detection network, build a defect hierarchy structure for the appearance defects of the chip test carrier, and build a defect detection network for cascade detection based on the defect hierarchy structure; S32, training and optimizing defect detection network; S33. Perform defect detection on the first image feature according to the trained and optimized defect detection network, and output the defect detection result.

6. The method for intelligently detecting appearance defects of a chip test carrier according to claim 5, characterized in that: The defect hierarchy includes: based on the physical characteristics and visual similarities of the defects, the defects of the Test Tray are defined as 14 types of defects: Insert buckle breakage, abnormal Insert buckle opening and closing angle, Insert buckle missing, Insert buckle damaged, Insert bottom net detachment, Insert bottom net damage, Insert body damage, Insert body deformation, HiFix socket appearance damage, HiFix socket conductive glue damage, HiFix socket dirt attachment, HiFix socket fixing screws, HiFix socket Pin missing, HiFix back connector damage; the 14 types of defects are organized into a three-layer defect hierarchy; the top layer area is the main defect type, including structural defects and surface defects, the middle layer is subdivided into more specific defect categories, structural defects include Insert-related defects and HiFix-related defects, Insert-related defects are Corresponding to the buckle problems, bottom net problems and main body problems, HiFix-related defects correspond to socket problems, connector problems and component problems. Surface defects include appearance defects; the bottom layer is the final 14 types of specific defects; among the Insert-related defects, the buckle problems include the Insert buckle breakage, the Insert buckle opening and closing angle abnormality, the Insert buckle missing, and the Insert buckle damaged. The bottom net problems include the Insert bottom net falling off and the Insert bottom net damaged. The main body problems include the Insert body damaged and the Insert body deformed. Among the HiFix-related defects, the socket problems include the HiFix socket appearance damaged and the HiFix socket conductive glue damaged. The connector problems include the HiFix back connector damaged. The component problems include the HiFix socket fixing screws and the HiFix socket pin missing.

7. The method for intelligently detecting appearance defects of a chip test carrier according to claim 6, characterized in that: The defect detection network is based on the defect hierarchy. Let x be the input image feature, y i is the output of the i-th stage, i=1, 2, 3, and its calculation formula includes: Phase 1: Quickly identify the main defect types: P(y1|x), y1∈{structural defect, surface defect} Among them, P(y1|x) represents the probability that the main defect type is y1 when the input feature x is given; Phase 2: Identify more specific defect categories within the selected major defect types: P(y2|x, y1), y2∈{Insert related defects, HiFix related defects, appearance defects} Among them, P(y2|x, y1) represents the probability that the main defect type is y1 and the more specific defect category is y2 when the input feature x is given; Phase 3: Identify the final 14 specific defects at the bottom level: P(y3|x,y1,y2), y3∈{14 types of specific defects} Where P(y3|x, y1, y2) represents the probability that the main defect type is y1, the more specific defect category is y2, and the underlying defect type is y3 given the input feature x; The output of the defect detection network, that is, the final classification probability, is calculated by the Bayesian rule, and then: P(y3|x)=P(y3|x, y1, y2)*P(y2|x, y1)*P(y1|x) Among them, P(y3|x) represents the result output by the defect detection network, that is, the probability that the underlying defect type is y3 when the input feature x is given.

8. The method for intelligently detecting appearance defects of a chip test carrier according to claim 7, characterized in that: Feature reuse is introduced into the defect detection network, and feature extraction functions are defined for the three stages: f1(x), f2(x), and f3(x). Each feature extraction function is represented by a neural network module as the input processing module of each stage.

9. The method for intelligently detecting appearance defects of a chip test carrier according to claim 7, characterized in that: A soft decision mechanism is introduced into the defect detection network. The judgment process of the soft decision mechanism includes: Among them, τ1 is the first threshold and τ2 is the second threshold.

10. The method for intelligently detecting appearance defects of a chip test carrier according to claim 7, characterized in that: In the training and optimization of the defect detection network of S32, a multi-task loss function is constructed to optimize all stages of the defect detection network. The calculation formula of the multi-task loss function is: Among them, L is the total loss function, α1, α2, and α3 are the balance factors of the first stage, the second stage, and the third stage respectively, y1, are the true labels of the first stage, the predicted output of the first stage network, y2, are the true label of the second stage, the predicted output of the second stage network, y3, are the true labels of the third stage and the predicted output of the third stage network, L1, L2, and L3 are the cross entropy loss functions of the first, second, and third stages, λ is the regularization coefficient, θ is the parameter of the model, and R(θ) is the regularization term.

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