Pixel circuit, display panel and display device

Abstract

The invention relates to a pixel circuit, a display panel and a display device. The pixel circuit comprises a driving transistor, a threshold compensation transistor and a shielding layer, the threshold compensation transistor comprises a first sub-threshold compensation transistor and a second sub-threshold compensation transistor; an active layer of the threshold compensation transistor comprises a first sub-channel region, a second sub-channel region and a first connection region; the first sub-channel region and the second sub-channel region are electrically connected through the first connecting region; in the direction perpendicular to the active layer, the first sub-channel region is at least partially overlapped with the grid electrode of the first sub-threshold compensation transistor, and the second sub-channel region is at least partially overlapped with the grid electrode of the second sub-threshold compensation transistor. And the overlapping area A of the first connecting region and the shielding layer meets # imgabs0 # imgabs1 #. According to the display panel, the stability of the grid potential of the driving transistor can be kept, and the problem of low-frequency flicker of the display panel is solved.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a pixel circuit, a display panel and a display device. Background Art

[0002] In the prior art, the display panel includes a pixel circuit, which is used to drive the light-emitting device to emit light. The light-emitting device can be an organic light-emitting diode (OLED). Compared with the traditional thin-film transistor liquid crystal display panel, the OLED display panel has the characteristics of self-luminescence, fast response speed, wide color gamut, large viewing angle, high brightness and easy application of flexible display technology, and has gradually become the mainstream display technology for mobile phones, televisions, computers and other displays. The OLED display panel has the advantages of low energy consumption, self-luminescence, wide viewing angle, and fast response speed. Since the OLED device is a current-driven device, the OLED display panel can usually be driven by current. When it emits light, it is necessary to control the driving transistor in the pixel circuit to provide a driving current to the OLED device to make it emit light.

[0003] In existing display panels, when some modules are turned off, the potential of the control end of the driving module will be unstable, resulting in changes in the display brightness of the light-emitting module. Especially in low-frequency display, the display screen will have different degrees of flicker, which will affect the display effect of the display panel. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a pixel circuit, a display panel and a display device.

[0005] In a first aspect, the present application provides a pixel circuit, comprising:

[0006] Driver transistor;

[0007] A threshold compensation transistor; the threshold compensation transistor includes a first sub-threshold compensation transistor and a second sub-threshold compensation transistor; a first electrode of the first sub-threshold compensation transistor is electrically connected to a gate electrode of the driving transistor; a second electrode of the first sub-threshold compensation transistor is electrically connected to a first electrode of the second sub-threshold compensation transistor; a second electrode of the second sub-threshold compensation transistor is electrically connected to a first electrode of the driving transistor; a gate electrode of the first sub-threshold compensation transistor and a gate electrode of the second sub-threshold compensation transistor are electrically connected; an active layer of the threshold compensation transistor includes a first sub-channel region, a second sub-channel region and a first connection region; the first sub-channel region and the second sub-channel region are electrically connected via the first connection region;

[0008] Shielding layer;

[0009] Wherein, in a direction perpendicular to the active layer, the first sub-channel region at least partially overlaps with the gate of the first sub-threshold compensation transistor, the second sub-channel region at least partially overlaps with the gate of the second sub-threshold compensation transistor, and an overlapping area A between the first connection region and the shielding layer satisfies:

[0010]

[0011] Among them, C ox1 is the unit area capacitance of the MIS structure of the threshold compensation transistor; V 01 is the gate potential of the driving transistor before the threshold compensation transistor is turned off; d1 is the thickness of the insulating layer between the shielding layer and the first connection area, ε1 is the relative dielectric constant of the insulating layer between the shielding layer and the first connection area; N1 is the gate potential of the driving transistor before the pixel circuit drives the pixel to emit light; V g1 is the gate potential of the threshold compensation transistor after the threshold compensation transistor is turned off; a1 is a preset constant; W1 is the channel width of the first sub-threshold compensation transistor; L1 is the channel length of the first sub-threshold compensation transistor; W2 is the channel width of the second sub-threshold compensation transistor; L2 is the channel length of the second sub-threshold compensation transistor.

[0012] In a second aspect, the present application further provides a display panel, comprising the pixel circuit as described in the first aspect.

[0013] In a third aspect, the present application further provides a display device, comprising the display panel as described in the second aspect.

[0014] Compared with the prior art, the technical solution provided by this application has the following advantages:

[0015] The pixel circuit provided in the present application includes a driving transistor and a threshold compensation transistor, wherein the threshold compensation transistor includes a first sub-threshold compensation transistor and a second sub-threshold compensation transistor, and the active layer of the threshold compensation transistor includes a first sub-channel region, a second sub-channel region and a first connection region; the first sub-channel region and the second sub-channel region are electrically connected through the first connection region, and in a direction perpendicular to the active layer, the first sub-channel region at least partially overlaps with the gate of the first sub-threshold compensation transistor, and the second sub-channel region at least partially overlaps with the gate of the second sub-threshold compensation transistor, and the first connection region overlaps with the shielding layer to form a shielding capacitor. Since the charge at the position where the second pole of the first sub-threshold compensation transistor is electrically connected to the first pole of the second sub-threshold compensation transistor can be stored in the shielding capacitor. In addition, the embodiment of the present application sets the overlapping area A of the first connection region and the shielding layer to satisfy the following formula:

[0016]

[0017] Setting the overlapping area A of the first connection region and the shielding layer according to the above formula can make the absolute value of the difference between the potential at the electrical connection position between the second pole of the first sub-threshold compensation transistor and the first pole of the second sub-threshold compensation transistor and the gate potential of the driving transistor less than a1, thereby reducing the leakage current from the electrical connection position between the second pole of the first sub-threshold compensation transistor and the first pole of the second sub-threshold compensation transistor to the gate of the driving transistor, thereby maintaining the stability of the gate potential of the driving transistor and solving the problem of low-frequency flickering of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0020] Figure 1 A schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application;

[0021] Figure 2 for Figure 1 A schematic diagram of a layout of a threshold compensation transistor in the pixel circuit;

[0022] Figure 3 for Figure 2 A schematic diagram of the layout structure of the active layer of the mid-threshold compensation transistor;

[0023] Figure 4 for Figure 2 A schematic diagram of the layout structure of the film layer where the gate metal of the mid-threshold compensation transistor is located;

[0024] Figure 5 for Figure 2 Schematic diagram of the layout structure of the film layer where the middle shielding layer is located;

[0025] Figure 6 A schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application;

[0026] Figure 7 for Figure 6 A schematic diagram of a layout structure of a pixel circuit shown;

[0027] Figure 8 for Figure 6 A schematic diagram of the layout structure of the active layer of each transistor;

[0028] Fig. 9 for Figure 6 A schematic diagram of the layout structure of the film layer where the gate metal of each transistor is located;

[0029] Fig.10 for Figure 6 Schematic diagram of the layout structure of the film layer where the middle shielding layer is located;

[0030] Fig.11 A schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application;

[0031] Fig.12 A schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0032] Fig.13 A schematic diagram of the structure of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0034] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present application, rather than all of the embodiments.

[0035] Figure 1 A schematic diagram of a pixel circuit provided in an embodiment of the present application is provided. Figure 1 The pixel circuit includes a driving transistor M1 and a threshold compensation transistor M2. The driving transistor M1 is used to provide a driving current for the light emitting element D.

[0036] The threshold compensation transistor M2 of this embodiment is connected to the gate of the driving transistor M1 ( Figure 1 The first node N1 in the figure) and the first electrode of the driving transistor (which can be the drain of the driving transistor, the third node N3 in the figure). It should be noted that the driving transistor also includes a second electrode, such as Figure 1 The second node N2 in the driving transistor is used to receive and transmit the data signal.

[0037] The threshold compensation transistor M2 is used to detect and compensate for the deviation of the threshold voltage of the driving transistor M1 , that is, the threshold compensation transistor M2 can electrically connect the gate of the driving transistor M1 and the first electrode of the driving transistor M1 when it is turned on, thereby capturing the threshold voltage Vth of the driving transistor M1 .

[0038] The threshold compensation transistor M2 in the embodiment of the present application includes a first sub-threshold compensation transistor M21 and a second sub-threshold compensation transistor M22. Among them, the first electrode of the first sub-threshold compensation transistor M21 is electrically connected to the gate of the driving transistor M1. The second electrode of the first sub-threshold compensation transistor M21 is electrically connected to the first electrode of the second sub-threshold compensation transistor M22. The second electrode of the second sub-threshold compensation transistor M22 is electrically connected to the first electrode of the driving transistor M1. The gate of the first sub-threshold compensation transistor M21 and the gate of the second sub-threshold compensation transistor M22 are electrically connected. In the embodiment of the present application, the threshold compensation transistor M2 is a dual-gate transistor, which is conducive to reducing the leakage of the threshold compensation transistor M2 to the gate of the driving transistor M1 to ensure the stability of the gate potential of the driving transistor M1.

[0039] Figure 2 for Figure 1 A schematic diagram of the layout of a threshold compensation transistor in the pixel circuit. Figure 3 for Figure 2 Schematic diagram of the layout structure of the active layer of the mid-threshold compensation transistor. Figure 4 for Figure 2 Schematic diagram of the layout structure of the film layer where the gate metal of the mid-threshold compensation transistor is located. Figure 5 for Figure 2 Schematic diagram of the layout structure of the film layer where the middle shielding layer is located.

[0040] Combination Figures 1 to 5 As shown, the active layer of the threshold compensation transistor M2 includes a first sub-channel region P21, a second sub-channel region P22 and a first connection region P23. The first sub-channel region P21 and the second sub-channel region P22 are electrically connected through the first connection region P23.

[0041] Among them, combined Figure 1-Figure 5 As shown, the first sub-channel region P21 is the channel region of the first sub-threshold compensation transistor M21. In the direction perpendicular to the active layer, the first sub-channel region P21 at least partially overlaps with the gate metal of the threshold compensation transistor, and the area where the gate metal of the threshold compensation transistor overlaps with the first sub-channel region P21 is the gate G21 of the first sub-threshold compensation transistor M21, that is, in the direction perpendicular to the active layer, the first sub-channel region P21 at least partially overlaps with the gate G21 of the first sub-threshold compensation transistor M21.

[0042] Combination Figure 1-Figure 5As shown, the second sub-channel region P22 is the channel region of the second sub-threshold compensation transistor M22. In the direction perpendicular to the active layer, the second sub-channel region P22 at least partially overlaps with the gate metal of the threshold compensation transistor, and the area where the gate metal of the threshold compensation transistor overlaps with the second sub-channel region P22 is the gate G22 of the second sub-threshold compensation transistor M22, that is, in the direction perpendicular to the active layer, the second sub-channel region P22 at least partially overlaps with the gate G22 of the second sub-threshold compensation transistor M22.

[0043] See also Figure 5 The pixel circuit in the embodiment of the present application further includes a shielding layer. In a direction perpendicular to the active layer, the first connection region P23 overlaps with the shielding layer.

[0044] In the direction perpendicular to the active layer, the first connection area P23 is arranged to overlap with the shielding layer MC to form a shielding capacitor C1. The first electrode of the first sub-threshold compensation transistor M21 and the gate of the driving transistor M1 are electrically connected to the scanning line S2. When the level on the scanning line S2 changes, the potential at the position where the second electrode of the first sub-threshold compensation transistor M21 and the first electrode of the second sub-threshold compensation transistor M22 are electrically connected will change ( Figure 1 Since the shielding capacitor C1 is provided, when the level on the scan line S2 changes, the charge of the fourth node N4 can be stored in the shielding capacitor C1, so as to prevent the charge of the fourth node N4 from being injected into the first node N1, thereby facilitating the stability of the gate potential of the driving transistor M1, so as to stabilize the driving current generated by the driving transistor M1, and further facilitating the display uniformity of the display panel.

[0045] In order to avoid the potential difference between the fourth node N4 and the first node N1 caused by the coupling of the level change on the scan line S2, which causes the fourth node N4 potential to affect the stability of the first node N1 potential, thereby affecting the display flicker problem, the embodiment of the present application sets the overlapping area A of the first connection area and the shielding layer to satisfy the following formula:

[0046]

[0047] Among them, C ox1 is the capacitance per unit area of ​​the MIS structure of the threshold compensation transistor; V 01 is the gate potential of the driving transistor before the threshold compensation transistor is turned off; d1 is the thickness of the insulating layer between the shielding layer and the first connection area, ε1 is the relative dielectric constant of the insulating layer between the shielding layer and the first connection area; N1 is the gate potential of the driving transistor before the pixel circuit drives the pixel to emit light; V g1is the gate potential of the threshold compensation transistor after the threshold compensation transistor is turned off; a1 is a preset constant; W1 is the channel width of the first sub-threshold compensation transistor; L1 is the channel length of the first sub-threshold compensation transistor; W2 is the channel width of the second sub-threshold compensation transistor; L2 is the channel length of the second sub-threshold compensation transistor.

[0048] It should be noted that the embodiments of the present application are described by taking each transistor of the pixel circuit as a P-type transistor as an example. In other embodiments, each transistor of the pixel circuit can be selected as a P-type transistor or an N-type transistor according to needs. All transistors of the pixel circuit can be P-type transistors; or all transistors of the pixel circuit can be N-type transistors; or some transistors of the pixel circuit can be P-type transistors and some transistors can be N-type transistors. In the subsequent embodiments, the transistors are all P-type transistors and are turned on under a low-level signal as an example for description.

[0049] The following is a detailed description of the requirements for setting the overlapping area A between the first connection region and the shielding layer.

[0050] Since the threshold compensation transistor is connected to the gate of the driving transistor, the potential of the fourth node N4 in the threshold compensation transistor will affect the gate potential of the driving transistor. Exemplarily, the threshold compensation transistor M2 is a P-type transistor, and when the potential of the scan line S2 is at a low level, the threshold compensation transistor M2 is turned on. When the potential of the scan line S2 jumps from a low level to a high level, the threshold compensation transistor M2 is turned off. The jump of the level signal on the scan line S2 will cause coupling to the potential at the position where the second electrode of the first sub-threshold compensation transistor M21 is electrically connected to the first electrode of the second sub-threshold compensation transistor M22 ( Figure 1 The potential of the scan signal provided by the scan line S2 changes from a low level to a high level, which will increase the potential of the fourth node N4.

[0051] For the fourth node N4, before the threshold compensation transistor M2 is turned off, the gate potential of the driving transistor M1 ( Figure 1 The first node N1) in is Vdata-Vth.

[0052] The scanning signal provided by the scanning line S2 jumps from a low level to a high level, the threshold compensation transistor M2 is turned off, and the jump of the scanning signal of the scanning line S2 pulls the fourth node N4 high. When the threshold compensation transistor M2 is not turned off, the fourth node N4 will not be coupled by the jump of the scanning signal of the scanning line S2. 01 The gate potential of the driving transistor before the initialization transistor is turned off. The voltage range for coupling the fourth node N4 is V 01 To V g1 , V g1After the threshold compensation transistor is turned off, the gate potential of the threshold compensation transistor, that is, the high level of the scan signal corresponding to the scan line S2.

[0053] See Figure 1 , there is a transistor on both the left and right sides of the fourth node N4, namely the first sub-threshold compensation transistor M21 and the second sub-threshold compensation transistor M22. The part of the first sub-threshold compensation transistor M21 close to the fourth node N4 (such as Figure 1 at the dashed box A1 in Figure 1 ) can cause coupling to the fourth node N4, and the part of the second sub-threshold compensation transistor M22 close to the fourth node N4 (such as

[0054] at the dashed box A2 in Figure 1 ) can also cause coupling to the fourth node N4. Figure 1 Therefore, the transistors that can couple to the fourth node N4 include the part of the first sub-threshold compensation transistor M21 close to the fourth node N4 (such as at the dashed box A1 in , half of the first sub-threshold compensation transistor M21) and the part of the second sub-threshold compensation transistor M22 close to the fourth node N4 (such as at the dashed box A2 in p1 *(V g1 -V 01 ). For the total capacitance of the fourth node N4, the voltage change brought by these charges is ΔV1, that is Therefore Then the potential of the fourth node N4 is

[0055] To avoid the potential of the fourth node N4 affecting the gate potential (the potential of the first node N1) of the driving transistor, the embodiment of the present application sets the difference between the potential of the fourth node N4 and the gate potential of the driving transistor within a certain value a1. a1 is a preset constant greater than zero, for example, 1 < a1 ≤ 2. That is Among them, N1 in the formula represents the gate potential of the driving transistor before the pixel circuit drives the pixel to emit light. Through the above formula conversion, the overlapping area A between the first connection area and the shielding layer can be calculated to satisfy:

[0056]

[0057] Since the threshold compensation transistor M2 is used to write the data signal into the gate of the driving transistor M1, the potential of the fourth node N4 is always equal to the gate potential N1 of the driving transistor (the potential of the first node N1) when the threshold compensation transistor M2 is turned on. It should be noted that for the convenience of description, before the pixel circuit drives the pixel to emit light, the gate potential of the driving transistor is also represented by the mark "N1". The subsequent jump of the scanning signal of the scanning line S2 will pull up the fourth node N4, so the potential of the fourth node N4 must be greater than the gate potential N1 of the driving transistor, so the formula is taken In Can get That is, in the embodiment of the present application, the overlapping area A of the first connection area and the shielding layer satisfies: It can be achieved that the difference between the potential of the fourth node N4 after coupling and the potential of the first node N1 is controlled to be smaller than a1, thereby reducing the leakage current from the threshold compensation transistor to the driving transistor.

[0058] It should be noted that the pixel circuit provided in the embodiment of the present application may also include other transistors that support the operation of the circuit, such as Figure 1 The initialization transistor M3, the anode reset transistor M4, the first light emission control transistor M5, the second light emission control transistor M6, and the data writing transistor M7.

[0059] The pixel circuit needs to receive a scan signal provided by the scan line S1, a scan signal provided by the scan line S2, a light control signal provided by the light control line Emit, a data signal provided by the data line Data, a first reset signal provided by the initialization signal line Vref1, a second reset signal provided by the reset signal line Vref2, a positive polarity power supply voltage provided by the first power line PVDD, a negative polarity power supply voltage provided by the second power line PVEE, etc. For the convenience of description, the signal transmitted by the signal line is represented by the same reference numeral as the signal line in this application. Figure 1 In the exemplary setting, the initialization signal line Vref1 and the reset signal line Vref2 receive the same signal, that is, the first reset signal provided by the initialization signal line Vref1 is the same as the second reset signal provided by the reset signal line Vref2. In other feasible implementations, different constant voltage signals may also be provided for the initialization signal line Vref1 and the reset signal line Vref2.

[0060] The gate of the driving transistor M1 is connected to the first node N1, the first electrode is connected to the second node N2, and the second electrode is connected to the third node N3. The first electrode of the initialization transistor M3 is connected to the initialization signal line Vref1, the second electrode of the initialization transistor M3 is connected to the first node N1, and the gate of the initialization transistor M3 is connected to the scan line S1. The first electrode of the data writing transistor M7 is connected to the data line Data, the second electrode of the data writing transistor M7 is connected to the second node N2, and the gate of the data writing transistor M7 is connected to the scan line S2. The gates of the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are both connected to the light-emitting control line Emit, the first electrode of the first light-emitting control transistor M5 is connected to the first power line PVDD, the second electrode of the first light-emitting control transistor M5 is connected to the second node N2, the first electrode of the second light-emitting control transistor M6 is connected to the third node N3, and the second electrode of the second light-emitting control transistor M6 is connected to the anode of the light-emitting element D. The cathode of the light-emitting element D is connected to the second power line PVEE. The first electrode of the anode reset transistor M4 is connected to the reset signal line Vref2, and the second electrode of the anode reset transistor M4 is connected to the anode of the light-emitting element D.

[0061] Below Figure 1 In the example, M1 to M7 are all P-type transistors, and are turned on under a low-level signal to illustrate the working process of the above pixel circuit.

[0062] Within one frame time, the display panel executes a first reset phase t1, a data writing phase t2, and a light emitting phase t3. During the initialization phase t1, the scan line S1 provides a low-level signal to the initialization transistor M3. The initialization transistor M3 is turned on, and the first reset signal provided by the first initialization signal line Vref1 is transmitted to the driving transistor M1 to reset the gate of the driving transistor M1. During the data writing phase t2, the scan line S2 provides a low-level signal to the threshold compensation transistor M2, the anode reset transistor M4, and the data writing transistor M7. The threshold compensation transistor M2, the anode reset transistor M4, and the data writing transistor M7 are turned on, and the data signal provided by the data line Data is written to the gate of the driving transistor M1 (threshold capture is achieved during the phase when the data writing transistor M7 and the threshold compensation transistor M2 are both turned on). The second reset signal provided by the reset signal line Vref2 is transmitted to the anode of the light emitting element D to reset the anode of the light emitting element D. When an effective level signal is transmitted on the scan line S1, the pixel circuit of the previous row enters the data writing phase, and the pixel circuit of the current row enters the reset phase; when an effective level signal is transmitted on the scan line S2, the pixel circuit of the current row enters the data writing phase. During the light emitting phase t3, the light emitting control line Emit provides a low-level signal to the first light emitting control transistor M5 and the second light emitting control transistor M6. The first light emitting control transistor M5 and the second light emitting control transistor M6 are turned on, and the positive power supply voltage provided by the first power supply line PVDD is transmitted to the driving transistor M1. The light emitting element D emits light in response to the driving signal of the driving transistor M1.

[0063] For each transistor in the pixel circuit, it can be a low-temperature polycrystalline silicon thin-film transistor or an indium gallium zinc oxide thin-film transistor. The type of transistor is not limited in this application. It can be understood that in practical applications, the implementation method of the pixel circuit can be selected based on requirements, and it is not limited to Figure 1 the pixel circuit with 7 transistors shown.

[0064] In some embodiments, 0 ≤ a1 ≤ 2.

[0065] In the embodiment of this application, by setting the overlapping area A between the first connection area and the shielding layer to satisfy the above formula conditions, a shielding capacitor C1 is formed, so that the potential difference between the potential of the fourth node N4 after coupling and the potential of the first node N1 can be kept between 0V and 2V, thereby reducing the leakage current between the fourth node N4 and the first node N1, and further maintaining the stability of the gate potential of the driving transistor, and solving the problem of low-frequency flicker of the display panel.

[0066] In some embodiments, the overlapping area A between the first connection area and the shielding layer can also satisfy: A < b1(W1*L1 + W2*L2); where b1 is a preset constant.

[0067] Based on the above embodiments, optionally, the overlapping area A between the first connection region and the shielding layer in the embodiments of the present application satisfies: A < b1(W1*L1 + W2*L2). Since an overly large shielding capacitor plate area is likely to cause an excessively long switching delay time of the transistor, the embodiments of the present application set the overlapping area A between the first connection region and the shielding layer to satisfy A < b1(W1*L1 + W2*L2), so as to avoid the problem of abnormal display caused by an excessively long switching delay time of the threshold compensation transistor.

[0068] In some embodiments, the pixel circuit may further include an initialization transistor. The initialization transistor is configured to transmit the first reset signal provided by the initialization signal line to the gate of the driving transistor during the initialization phase to initialize the gate of the driving transistor.

[0069] Figure 6 FIG. is a schematic structural diagram of another pixel circuit provided by the embodiments of the present application. As Figure 6 shown, the initialization transistor M3 includes a first sub-initialization transistor M31 and a second sub-initialization transistor M32. Among them, the first pole of the first sub-initialization transistor M31 is electrically connected to the initialization signal line Vref1. The second pole of the first sub-initialization transistor M31 is electrically connected to the first pole of the second sub-initialization transistor M32. The second pole of the second sub-initialization transistor M32 is electrically connected to the gate of the driving transistor M1. The gates of the first sub-initialization transistor M31 and the second sub-initialization transistor M32 are electrically connected. In the embodiments of the present application, the initialization transistor M3 is a double-gate transistor, which is beneficial to reducing the leakage current between the gate of the initialization transistor M3 and the gate of the driving transistor M1 to ensure the stability of the gate potential of the driving transistor M1.

[0070] Figure 7 FIG. is Figure 6 a schematic layout structure diagram of the pixel circuit shown. Figure 8 FIG. is Figure 6 a schematic layout structure diagram of the active layers of the transistors in FIG. Fig. 9 FIG. is Figure 6 a schematic layout structure diagram of the film layer where the gate metal of each transistor in FIG. is located. Fig.10 FIG. is Figure 6 a schematic layout structure diagram of the film layer where the shielding layer in FIG. is located.

[0071] Figure 6-Figure 10In the exemplary configuration, the gate of each transistor, the scan line S1 and the scan line S2, and the light control line Emit are located in the same layer; the initialization signal line Vref1, the reset signal line Vref2 (the initialization signal line Vref1 and the reset signal line Vref2 receive the same constant voltage signal), the capacitor metal layer, and the shielding layer are located in the same layer; the source of each transistor, the source and drain of each transistor, the first power line PVDD, and the data line Data are located in the same layer. It should be noted that Figure 6-Figure 10 In the figure, only a film layer relationship of the pixel circuit area is illustrated, and the film layers of different structures in the pixel circuit are not specifically limited. In other feasible implementations, the first power line PVDD and the data line Data can also be set in different layers without short circuit.

[0072] Combination Figures 6 to 10 The active layer of the initialization transistor M3 includes a third sub-channel region P31, a fourth sub-channel region P32 and a second connection region P33. The third sub-channel region P31 and the fourth sub-channel region P32 are electrically connected through the second connection region P33.

[0073] Among them, combined Figures 6 to 10 , as shown, the third sub-channel region P31 is the channel region of the first sub-initialization transistor M31. In the direction perpendicular to the active layer, the third sub-channel region P31 at least partially overlaps with the gate metal of the initialization transistor. The area where the gate metal of the initialization transistor overlaps with the first sub-channel region P21 is the gate G31 of the first sub-initialization transistor M31, that is, in the direction perpendicular to the active layer, the third sub-channel region P31 at least partially overlaps with the gate G31 of the first sub-initialization transistor M31.

[0074] Combination Figure 6-Figure 10 As shown, the fourth sub-channel region P32 is the channel region of the second sub-initialization transistor M32. In the direction perpendicular to the active layer, the fourth sub-channel region P32 at least partially overlaps with the gate metal of the initialization transistor. The area where the gate metal of the initialization transistor overlaps with the fourth sub-channel region P32 is the gate G32 of the second sub-threshold compensation transistor M32, that is, in the direction perpendicular to the active layer, the fourth sub-channel region P32 at least partially overlaps with the gate G32 of the second sub-initialization transistor M32.

[0075] In the embodiment of the present application, in the direction perpendicular to the active layer, the second connection area P33 overlaps with the shielding layer MC to form a shielding capacitor C2. When the level on the scan line S1 changes, the potential at the position where the second electrode of the first sub-initialization transistor M31 and the first electrode of the second sub-initialization transistor M32 are electrically connected will change ( Figure 6Since the shielding capacitor C2 is provided, when the level on the scan line S1 changes, the charge of the fifth node N5 will be stored in the shielding capacitor C2, preventing the charge of the fifth node N5 from being injected into the first node N1, which is beneficial to maintaining the stability of the gate potential of the driving transistor M1, so as to stabilize the driving current generated by the driving transistor M1, and further beneficial to improving the display uniformity of the display panel. Figure 6 The charge of the fifth node N5 can be stored in the shielding capacitor C2, thereby alleviating the leakage phenomenon between the fifth node N5 and the first node N1 to a certain extent.

[0076] In order to avoid the excessive difference in potential between the fifth node N5 and the first node N1 caused by the coupling of the level change on the scan line S1, which causes the potential of the fifth node N5 to affect the stability of the potential of the first node N1, thereby affecting the display flicker problem, the embodiment of the present application sets the overlapping area B of the second connection area and the shielding layer to satisfy the following formula:

[0077]

[0078] Among them, C ox2 is the unit area capacitance of the MIS structure of the initialization transistor; V 02 is the gate potential of the driving transistor before the initialization transistor is turned off; d2 is the thickness of the insulating layer between the shielding layer and the second connection area, ε2 is the relative dielectric constant of the insulating layer between the shielding layer and the second connection area; N1 is the gate potential of the driving transistor before the pixel circuit drives the pixel to emit light; V g2 is the gate potential of the initialization transistor after the initialization transistor is turned off; a2 is a preset constant; W3 is the channel width of the second sub-initialization transistor; L3 is the channel length of the second sub-initialization transistor; W4 is the channel width of the first sub-initialization transistor; L4 is the channel length of the first sub-initialization transistor.

[0079] The following is a detailed description of the requirements for setting the overlapping area B between the second connection region and the shielding layer.

[0080] Exemplarily, the initialization transistor M3 is a P-type transistor, and when the potential of the scan line S1 is low, the initialization transistor M3 is turned on. When the scan signal provided by the scan line S1 jumps from low level to high level, the initialization transistor M3 is turned off, and the jump of the scan signal of the scan line S1 will cause coupling to the potential of the fifth node N5.

[0081] When the initialization transistor M3 is not turned off, the fifth node N5 will not be coupled by the jump of the scan signal on the scan line S1. 02 The gate potential of the driving transistor M1 before the initialization transistor M3 is turned off. The voltage range for coupling the fifth node N5 is V 02 To Vg2 (V g2 After the initialization transistor is turned off, the gate potential of the initialization transistor, that is, the high level of the scan signal corresponding to the scan line S1).

[0082] See Figure 6 , there is a transistor on both the left and right sides of the fifth node N5, that is, the first sub-initialization transistor M31 and the second sub-initialization transistor M32. The part of the first sub-initialization transistor M31 close to the fifth node N5 (such as Figure 6 at the dashed box B1 in Figure 6 ) can cause coupling to the fifth node N5, and the part of the second sub-initialization transistor M32 close to the fifth node N5 (such as

[0083] at the dashed box B2 in Figure 6 ) can also cause coupling to the fifth node N5. Figure 6 Therefore, the transistors that can couple to the fifth node N5 include the part of the first sub-initialization transistor close to the fifth node N5 (such as the shielding capacitance formed by the overlap of the second connection region and the shielding layer in the embodiment of the present application is Then the total capacitance at the fifth node N5 is According to the charge conservation and capacitance coupling principle, the coupling amount brought by the jump of the scan signal of the scan line S1 is C p2 *(V g2 -V 02 ). For the total capacitance of the fifth node N5, the voltage change brought by these charges is ΔV2, that is

[0084] Therefore Then the potential of the fifth node N5 is

[0085] To avoid the potential of the fifth node N5 affecting the gate potential of the driving transistor (the potential of the first node N1), the embodiment of the present application sets the difference between the potential of the fifth node N5 and the gate potential of the driving transistor within a certain value a2, and a2 is a preset constant greater than zero. For example, 1 < a2 ≤ 2. That is N1 in the formula represents the gate potential of the driving transistor before the pixel circuit drives the pixel to emit light. Through the above formula conversion, the overlap area B between the second connection region and the shielding layer can be calculated to satisfy:

[0086]

[0087] In the embodiment of the present application, the overlapping area B between the second connection area and the shielding layer satisfies: It can be achieved that the difference between the potential of the fifth node N5 after coupling and the potential of the first node N1 is controlled to be smaller than a2, thereby reducing the leakage current between the initialization transistor and the driving transistor.

[0088] Table 1 is a test result data table provided by the embodiment of the present application. The shielding layer of the test panel in Table 1 is arranged on the same layer as the capacitor metal layer of the pixel circuit. It can be seen that the overlapping area A of the first connection area and the shielding layer satisfies A>10.85um, and the overlapping area B of the second connection area and the shielding layer satisfies 3.10um. <B<21.69um。

[0089] Table 1: Test results data table

[0090] W1=W2=W3=W4 2um L1=L2=L3=L4 3.4um <![CDATA[V g1 ]]> 6V <![CDATA[V 01 ]]> 2V N1 2V a1 2V <![CDATA[C p1 ]]> 2.00E-15 d1 2.40E-07 ε1 4.43E-11 A A>10.85um <![CDATA[V g2 ]]> 6V <![CDATA[V 02 ]]> -3V N1 2V a2 2V <![CDATA[C p2 ]]> 2.00E-15 d2 2.40E-07 ε2 4.43E-11 B 3.10um<B<21.69um

[0091] In some embodiments, the overlapping area A of the first connection region and the shielding layer, and the overlapping area B of the second connection region and the shielding layer satisfy:

[0092]

[0093] Among them, b2 is a preset constant.

[0094] Since the potential of the fourth node N4 is always greater than the potential of the first node N1, the fourth node N4 leaks positive electricity to the first node N1. To offset the leakage of the fourth node N4 to the first node N1, the embodiment of the present application sets the overlapping area A of the first connection area and the shielding layer, and the overlapping area B of the second connection area and the shielding layer, so that the fifth node N5 leaks negative electricity to the first node N1. That is, the potential difference between the first node N1 and the fifth node N5 is as close as possible to the potential difference between the fourth node N4 and the first node N1.

[0095] Among them, the potential of the fourth node N4 is The potential difference ΔV3 between the fourth node N4 and the first node N1 is The potential of the fifth node N5 is The potential difference ΔV4 between the first node N1 and the fifth node N5 is This application sets

[0096] b2 in the formula is a preset constant greater than or equal to zero. It should be noted that b2 can be set according to the display effect requirements of different panels, and the embodiment of the present application does not limit this. The smaller the b2 value, the better the leakage compensation effect of the fourth node N4 and the fifth node N5 on the first node N1.

[0097] In some embodiments, the pixel circuit may include a third sub-initialization transistor. A first electrode of the third sub-initialization transistor is electrically connected to the initialization signal line. A second electrode of the third sub-initialization transistor is electrically connected to a second electrode of the second sub-threshold compensation transistor.

[0098] Fig.11 A schematic diagram of a structure of another pixel circuit provided in an embodiment of the present application is shown in FIG. Fig.11 As shown, the pixel circuit includes a driving transistor M1, a threshold compensation transistor M2 and a third sub-initialization transistor M33. Different from the above embodiment, the third sub-initialization transistor M33 is a single-gate transistor, the first electrode of the third sub-initialization transistor M33 is electrically connected to the initialization signal line Vref, and the second electrode of the third sub-initialization transistor M33 is electrically connected to the second electrode of the second sub-threshold compensation transistor M22. The gate of the third sub-initialization transistor M33 is connected to the scan line S1.

[0099] Similar to the above embodiments, the threshold compensation transistor M2 includes a first sub-threshold compensation transistor M21 and a second sub-threshold compensation transistor M22. The connection method of the first sub-threshold compensation transistor M21 and the second sub-threshold compensation transistor M22 and other transistors is similar to the above embodiments and will not be repeated here. The structure of the active layer of the first sub-threshold compensation transistor M21 and the second sub-threshold compensation transistor M22 is also similar to the above embodiments, and the overlapping area A of the first connection area and the shielding layer also satisfies:

[0100] In the embodiment of the present application, the second electrode of the third sub-initialization transistor M33 is electrically connected to the second electrode of the second sub-threshold compensation transistor M22. Since the third sub-initialization transistor M33 is no longer directly connected to the gate of the driving transistor, the problem of unstable gate potential of the driving transistor caused by the leakage current of the third sub-initialization transistor M33 can be alleviated to a certain extent.

[0101] In some embodiments, the shielding layer is disposed on the same layer as a capacitor metal layer of the pixel circuit.

[0102] A storage capacitor is generally provided in the pixel circuit. In the embodiment of the present application, the shielding layer can be prepared by using the capacitor metal layer of the capacitor plate of the storage capacitor of the pixel circuit. This arrangement does not require a separate process for the shielding layer, and the shielding layer can be formed simultaneously when the capacitor plate of the original storage capacitor of the pixel circuit is formed.

[0103] In some embodiments, the shielding layer is disposed at the same layer as any one of the source / drain metal layer, the gate metal layer, and the light-shielding metal layer of the pixel circuit.

[0104] In the embodiment of the present application, the shielding layer can also be arranged on the same layer as any one of the source / drain metal layer, the gate metal layer and the light-shielding metal layer of the pixel circuit. That is, while any one of the source / drain metal layer, the gate metal layer and the light-shielding metal layer of the pixel circuit is formed, the shielding layer can be prepared using the same metal film layer in the same process flow, which can also achieve the effect of saving process flow and reducing cost.

[0105] In some embodiments, the shielding layer is disposed on the same layer as the metal layer that is closest to the active layer.

[0106] In the embodiment of the present application, the shielding layer is arranged on the same layer as the metal layer of the nearest active layer, so that the shielding layer and the overlapping active layer are closest to each other. According to the capacitance formula (C is the capacitance value, ε is the relative dielectric constant between the layers, S is the area facing the two plates of the capacitor, and d is the distance between the two plates of the capacitor) It can be seen that the smaller the distance between the two plates of the capacitor, the greater the capacitance value. Therefore, in the embodiment of the present application, the shielding layer is arranged on the same layer as the metal layer of the nearest active layer, and the area of ​​the capacitor plate can be reduced as much as possible on the basis of achieving the target capacitance value of the capacitor formed by the shielding layer and the overlapping active layer, so as to avoid occupying too much pixel circuit space.

[0107] In some embodiments, a storage capacitor is further included; the storage capacitor is connected between the gate of the driving transistor and the first power line.

[0108] See for example Figure 1 , Figure 6 as well as Fig.11 The storage capacitor Cst is connected between the gate of the driving transistor M1 and the first power line PVDD. The first plate of the storage capacitor Cst is connected to the first node N1, and the second plate of the storage capacitor Cst is connected to the first power line PVDD. The storage capacitor Cst is used to store the data signal written into the gate of the driving transistor M1.

[0109] It should be noted that the first power line PVDD can provide a positive polarity power supply voltage. The display panel may also include a second power line PVEE, which can provide a negative polarity power supply voltage. For example, the voltage range of the first power line PVDD can be 3.3V to 4.6V, and the voltage range of the second power line PVEE can be -3.5V to -2V, etc.

[0110] In the related art, the gate potential stability of the driving transistor is generally improved by increasing the storage capacitor. However, since the storage capacitor cannot be increased infinitely, the embodiment of the present application can achieve the stability of the gate potential of the driving transistor by making the overlapping area A of the first connection area and the shielding layer satisfy the formula mentioned in the above embodiments through the above embodiments, thereby solving the problem of low-frequency flicker of the display panel.

[0111] In some embodiments, the shielding layer is used to access a power signal or a reset signal. In the embodiment of the present application, a power signal or a reset signal can be provided for the shielding layer, and a constant voltage signal can be provided for the shielding capacitor plate at the position where the second pole of the first sub-threshold compensation transistor is electrically connected to the first pole of the second sub-threshold compensation transistor (the fourth node N4 in the above embodiments), and the position where the second pole of the first sub-initialization transistor is electrically connected to the first pole of the second sub-initialization transistor (the fifth node N5 in the above embodiments).

[0112] The power signal may be, for example, a positive power voltage transmitted by the first power line PVDD, or a negative power voltage transmitted by the second power line PVEE. The reset signal may be a first reset signal transmitted by an initialization signal line Vref1 connected to an initialization transistor in a pixel circuit, or a second reset signal transmitted by a reset signal line Vref2 connected to an anode reset transistor in a pixel circuit.

[0113] The embodiment of the present application provides a constant voltage signal to the shielding layer by multiplexing the original signal in the pixel circuit, so there is no need to add an additional separate signal line to provide a signal to the shielding layer.

[0114] In some implementations, the shielding layer may be connected to the positive polarity power supply voltage transmitted by the first power line PVDD, the signal transmitted by the initialization signal line Vref1 connected to the initialization transistor, or the signal transmitted by the reset signal line Vref2 connected to the anode reset transistor. Since the first power line PVDD, the initialization signal line Vref1, and the reset signal line Vref2 are all located in the display area, the shielding layer and the first power line PVDD are easily connected, and there is no need to pull the wires to the non-display area.

[0115] In some embodiments, W1 / L1 is less than or equal to W2 / L2.

[0116] W1 is the channel width of the first sub-threshold compensation transistor; L1 is the channel length of the first sub-threshold compensation transistor; W2 is the channel width of the second sub-threshold compensation transistor; L2 is the channel length of the second sub-threshold compensation transistor. Since the leakage current increases with the increase of the channel width-to-length ratio, the first sub-threshold compensation transistor is closer to the gate of the driving transistor than the second sub-threshold compensation transistor. Therefore, in the embodiment of the present application, the channel width-to-length ratio W1 / L1 of the first sub-threshold compensation transistor adjacent to the gate of the driving transistor is set to be less than or equal to the channel width-to-length ratio W2 / L2 of the second sub-threshold compensation transistor away from the gate of the driving transistor, thereby reducing the leakage current of the transistor close to the gate of the driving transistor as much as possible, which is conducive to maintaining the stability of the gate potential of the driving transistor, so as to stabilize the driving current generated by the driving transistor, and further conducive to improving the display uniformity of the display panel.

[0117] In some embodiments, W3 / L3 is less than or equal to W4 / L4.

[0118] W3 is the channel width of the second sub-initialization transistor; L3 is the channel length of the second sub-initialization transistor; W4 is the channel width of the first sub-initialization transistor; L4 is the channel length of the first sub-initialization transistor. Since the leakage current increases with the increase of the channel width-to-length ratio, the second sub-initialization transistor is closer to the gate of the driving transistor than the first sub-initialization transistor. Therefore, in the embodiment of the present application, the channel width-to-length ratio W3 / L3 of the second sub-initialization transistor close to the gate of the driving transistor is set to be less than or equal to the channel width-to-length ratio W4 / L4 of the first sub-initialization transistor far from the gate of the driving transistor, thereby reducing the leakage current of the transistor close to the gate of the driving transistor as much as possible, which is conducive to maintaining the stability of the gate potential of the driving transistor, so as to stabilize the driving current generated by the driving transistor, and further conducive to improving the display uniformity of the display panel.

[0119] The present application also provides a display panel. Fig.12 As shown, the display panel includes the pixel circuit 10 provided in any of the above embodiments. Since the pixel circuit 10 has been described in detail in the above embodiments, it will not be described again here.

[0120] Based on the same inventive concept, the embodiment of the present application further provides a display device, Fig.13 FIG. 1 is a schematic diagram of a structure of a display device provided by an embodiment of the present invention. Please refer to FIG. Fig.13 , the display device includes the display panel 100 provided by any of the above embodiments.

[0121] It is understandable that the display device provided in the embodiment of the present application can be a computer, a mobile phone, a tablet, or other display device with a display function, and the present invention does not specifically limit this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application, and the specific description of the display panel in the above embodiments can be referred to, and this embodiment will not be repeated here.

[0122] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0123] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A pixel circuit, characterized in that: include: Driver transistor; Threshold compensation transistor; The threshold compensation transistor includes a first sub-threshold compensation transistor and a second sub-threshold compensation transistor; The first electrode of the first sub-threshold compensation transistor is electrically connected to the gate of the driving transistor; the second electrode of the first sub-threshold compensation transistor is electrically connected to the first electrode of the second sub-threshold compensation transistor; the second electrode of the second sub-threshold compensation transistor is electrically connected to the first electrode of the driving transistor; the gate of the first sub-threshold compensation transistor and the gate of the second sub-threshold compensation transistor are electrically connected; the active layer of the threshold compensation transistor includes a first sub-channel region, a second sub-channel region and a first connection region; the first sub-channel region and the second sub-channel region are electrically connected through the first connection region; Shielding layer; Wherein, in a direction perpendicular to the active layer, the first sub-channel region at least partially overlaps with the gate of the first sub-threshold compensation transistor, the second sub-channel region at least partially overlaps with the gate of the second sub-threshold compensation transistor, and an overlapping area A between the first connection region and the shielding layer satisfies: Among them, C ox1 is the unit area capacitance of the MIS structure of the threshold compensation transistor; V 01 is the gate potential of the driving transistor before the threshold compensation transistor is turned off; d1 is the thickness of the insulating layer between the shielding layer and the first connection area, ε1 is the relative dielectric constant of the insulating layer between the shielding layer and the first connection area; N1 is the gate potential of the driving transistor before the pixel circuit drives the pixel to emit light; V g1 is the gate potential of the threshold compensation transistor after the threshold compensation transistor is turned off; a1 is a preset constant; W1 is the channel width of the first sub-threshold compensation transistor; L1 is the channel length of the first sub-threshold compensation transistor; W2 is the channel width of the second sub-threshold compensation transistor; L2 is the channel length of the second sub-threshold compensation transistor.

2. The pixel circuit according to claim 1, characterized in that: The overlapping area A between the first connection area and the shielding layer also satisfies: A <b1(W1*L1+W2*L2); Wherein, b1 is a preset constant.

3. The pixel circuit according to claim 1, characterized in that: Also included is initializing the transistor; The initialization transistor includes a first sub-initialization transistor and a second sub-initialization transistor; a first electrode of the first sub-initialization transistor is electrically connected to an initialization signal line; a second electrode of the first sub-initialization transistor is electrically connected to a first electrode of the second sub-initialization transistor; a second electrode of the second sub-initialization transistor is electrically connected to a gate of the driving transistor; a gate of the first sub-initialization transistor and a gate of the second sub-initialization transistor are electrically connected; an active layer of the initialization transistor includes a third sub-channel region, a fourth sub-channel region and a second connection region; the third sub-channel region and the fourth sub-channel region are electrically connected via the second connection region; In a direction perpendicular to the active layer, the third sub-channel region at least partially overlaps with the gate of the first sub-initialization transistor, the fourth sub-channel region at least partially overlaps with the gate of the second sub-initialization transistor, and an overlapping area B between the second connection region and the shielding layer satisfies: Among them, C ox2 is the unit area capacitance of the MIS structure of the initialization transistor; V 02 is the gate potential of the driving transistor before the initialization transistor is turned off; d2 is the thickness of the insulating layer between the shielding layer and the second connection area, ε2 is the relative dielectric constant of the insulating layer between the shielding layer and the second connection area; N1 is the gate potential of the driving transistor before the pixel circuit drives the pixel to emit light; V g2 is the gate potential of the initialization transistor after the initialization transistor is turned off; a2 is a preset constant; W3 is the channel width of the second sub-initialization transistor; L3 is the channel length of the second sub-initialization transistor; W4 is the channel width of the first sub-initialization transistor; L4 is the channel length of the first sub-initialization transistor.

4. The pixel circuit according to claim 1, characterized in that: 0≤a1≤2。 5. The pixel circuit according to claim 3, characterized in that: The overlapping area A between the first connection area and the shielding layer, and the overlapping area B between the second connection area and the shielding layer satisfy: Among them, b2 is a preset constant.

6. The pixel circuit according to claim 1, characterized in that: Also included is a third sub-initialization transistor; The first electrode of the third sub-initialization transistor is electrically connected to the initialization signal line; A second electrode of the third sub-initialization transistor is electrically connected to a second electrode of the second sub-threshold compensation transistor.

7. The pixel circuit according to claim 1, characterized in that: The shielding layer is arranged on the same layer as the capacitor metal layer of the pixel circuit.

8. The pixel circuit according to claim 1, characterized in that: The shielding layer is arranged on the same layer as any one of the source / drain metal layer, the gate metal layer and the light-shielding metal layer of the pixel circuit.

9. The pixel circuit according to claim 1, characterized in that: The shielding layer is arranged on the same layer as the metal layer closest to the active layer.

10. The pixel circuit according to claim 1, characterized in that: It also includes a storage capacitor; the storage capacitor is connected between the gate of the driving transistor and the first power line.

11. The pixel circuit according to claim 1, characterized in that: The shielding layer is used for accessing a power signal or a reset signal.

12. The pixel circuit according to any one of claims 1 to 11, characterized in that: W1 / L1 is less than or equal to W2 / L2.

13. The pixel circuit according to any one of claims 3 to 5, characterized in that: W3 / L3 is less than or equal to W4 / L4.

14. A display panel, characterized in that: Comprising the pixel circuit as described in any one of claims 1-13.

15. A display device, characterized in that: Comprising the display panel as claimed in claim 14.

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