Data transmission method, display device and display module

Abstract

The invention discloses a data transmission method, a display device and a display module. The data transmission method is applied to a host. The host is connected with at least one time schedule controller; the data transmission method comprises the following steps: sending instruction signals to all time schedule controllers; wherein the instruction signal comprises a device address and first verification data, and the first verification data is obtained through operation of at least one kind of data except the first verification data in the instruction signal. According to the technical scheme, the reliability of communication between the host and the time schedule controller is guaranteed, and then the use performance of the display device is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a data transmission method, a display device and a display module. Background Art

[0002] With the development of display technology, organic light emitting diode (OLED) flat display devices have been widely used.

[0003] However, the performance of current OLED display devices needs to be improved. Summary of the invention

[0004] The present invention provides a data transmission method, a display device and a display module to improve the performance of the display device.

[0005] According to one aspect of the present invention, a data transmission method is provided, which is applied to a host; the host is connected to at least one timing controller; the data transmission method comprises:

[0006] A command signal is sent to all the timing controllers; wherein the command signal includes a device address and first verification data, and the first verification data is obtained by calculating at least one data other than the first verification data in the command signal.

[0007] Optionally, the instruction signal is a read instruction or a write instruction; the instruction signal also includes a read-write flag;

[0008] Sending a command signal to all the timing controllers includes:

[0009] Sending the read instruction or the write instruction to all the timing controllers;

[0010] After sending the read instruction to all the timing controllers, the method further includes:

[0011] When a feedback signal sent by a timing controller corresponding to a device address is received, the feedback signal is verified according to second verification data of the feedback signal.

[0012] Optionally, the instruction signal also includes instruction data and a register address;

[0013] Sending a command signal to all the timing controllers includes:

[0014] The instruction data and the register address are operated according to a preset operation mode to obtain the first verification data, and the instruction signal is sent to all timing controllers; wherein the preset operation mode includes at least one of addition, subtraction, multiplication, shift and XOR;

[0015] Alternatively, the device address, the instruction data and the register address are operated according to a preset operation method to obtain the first verification data, and the instruction signal is sent to all timing controllers.

[0016] Optionally, sending the command signal to all timing controllers includes:

[0017] Sending the instruction signal to all the timing controllers in the order of the device address, the instruction data, the register address and the first verification data;

[0018] Alternatively, the instruction signal is sent to all the timing controllers in the order of the device address, the register address, the instruction data and the first verification data.

[0019] Optionally, the instruction data and the register address are operated according to a preset operation mode to obtain the first verification data, including:

[0020] Add the instruction data to the data of the register address to obtain the first verification data;

[0021] Preferably, sending a command signal to all the timing controllers includes:

[0022] The command signal is sent to all the timing controllers through the IIC channel.

[0023] According to another aspect of the present invention, a data transmission method is provided. The data transmission method is applied to a timing controller, and the timing controller is connected to a host. The method comprises:

[0024] When receiving a command signal from the host, if the device address in the command signal is consistent with the address of the timing controller, the command signal is verified according to the first verification data in the command signal; wherein the first verification data is obtained by calculating at least one data other than the first verification data in the command signal.

[0025] Optionally, the instruction signal is a read instruction or a write instruction; the instruction signal also includes a read / write flag; and the method further includes:

[0026] When receiving a read instruction from the host, if the device address in the instruction signal is consistent with the address of the timing controller, and the instruction signal is verified according to the first verification data in the instruction signal, a feedback signal is sent to the host; wherein the feedback signal includes feedback data and second verification data.

[0027] Optionally, sending a feedback signal to the host includes:

[0028] Calculate the feedback data according to a preset calculation method to obtain the second verification data, and send the feedback data and the second verification data to the host; wherein the preset calculation method includes at least one of addition, subtraction, multiplication, shift and XOR;

[0029] Preferably, the feedback data is operated according to a preset operation mode to obtain the second verification data, including:

[0030] Adding each bit of the feedback data to obtain the second verification data;

[0031] Preferably, the data in the feedback signal is arranged in the order of the feedback data and the second verification data;

[0032] Preferably, sending a feedback signal to the host comprises:

[0033] The feedback signal is sent to the host through the IIC channel.

[0034] According to another aspect of the present invention, a display device is provided, the display device comprising: a host and at least one timing controller; the host is connected to at least one timing controller;

[0035] The host is used to send a command signal to all the timing controllers; wherein the command signal includes a device address and a first verification data, and the first verification data is obtained by calculating at least one data other than the first verification data in the command signal;

[0036] The timing controller is used for verifying the instruction signal according to the first verification data if the device address in the instruction signal is consistent with the address of the timing controller.

[0037] According to another aspect of the present invention, a display module is provided. The display module includes the display device described in any embodiment of the present invention.

[0038] The technical solution of the embodiment of the present invention is to set the first verification data in the command signal, and the first verification data is obtained by calculating at least one data other than the first verification data in the command signal, so that the timing controller can verify other data in the command signal according to the first verification data, and ensure that the timing controller performs corresponding actions according to the correct command signal. In addition, after the command signal obtained by the timing controller contains the first verification data, the timing controller will also send a feedback signal to the host in a corresponding format, that is, send a feedback signal with the second verification data to the host, so that the host can verify the feedback signal, thereby ensuring the reliability of communication between the host and the timing controller, and then improving the performance of the display device.

[0039] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 is a flow chart of a data transmission method provided by an embodiment of the present invention;

[0042] Figure 2 is a flow chart of another data transmission method provided by an embodiment of the present invention;

[0043] Figure 3 is a flow chart of another data transmission method provided by an embodiment of the present invention;

[0044] Figure 4 is a flow chart of another data transmission method provided by an embodiment of the present invention;

[0045] Figure 5 is a flow chart of another data transmission method provided by an embodiment of the present invention;

[0046] Figure 6 is a flow chart of another data transmission method provided by an embodiment of the present invention;

[0047] Figure 7 is a flow chart of another data transmission method provided by an embodiment of the present invention;

[0048] Figure 8 is a flow chart of another data transmission method provided by an embodiment of the present invention;

[0049] Fig. 9 is a structural schematic diagram of a display device provided by an embodiment of the present invention;

[0050] Fig.10 It is a structural schematic diagram of a display module provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0053] As mentioned in the background technology, the performance of the existing display device needs to be improved. The inventors have found that the reason for this problem is that the host is connected to the timing controller. The host can be a host computer outside the display device or a processor inside the display device. The host can read and write operations on the timing controller. The host can be connected to the timing controller through the IIC (Inter-Integrated Circuit, integrated circuit bus) channel, but when the IIC communicates, the voltage of the signal is small. In a complex electromagnetic environment, or when the communication line is long, the signal during IIC communication is easily interfered, resulting in serious signal loss. Therefore, when the host reads the state of the timing controller, it may read an error due to the signal loss, thereby performing an erroneous operation on the timing controller, resulting in the inability to continue to read and write operations on the timing controller. If the timing controller cannot be read and written, the timing controller cannot be configured with parameters, the program cannot be burned into the timing controller, and the timing controller cannot be controlled to generate display data, which causes the timing controller to be unable to operate normally, and the display data cannot be generated according to the screen to be displayed, or the display data cannot be transmitted to the display driver chip, which causes the display driver chip to be unable to drive the display device to emit light, affecting the display device to display the screen, resulting in poor performance of the display device. In addition, when the timing controller obtains the command signal sent by the host, it may execute an erroneous command due to signal loss during transmission, causing the timing controller to be unable to operate normally, and the display data cannot be generated according to the screen to be displayed, or the display data cannot be transmitted to the display driver chip, which causes the display driver chip to be unable to drive the display device to emit light, affecting the display device to display the screen, resulting in poor performance of the display device.

[0054] In view of the above technical problems, an embodiment of the present invention provides a data transmission method, which is applied to a host, and the host is connected to at least one timing controller. Among them, the host can be a host computer outside the display device, or a central processing unit (CPU) inside the display device. The timing controller is a controller inside the display device, and the timing controller can generate display data according to the picture to be displayed, and transmit the display data to the display driver chip, so that the display driver chip can generate a driving voltage according to the display data. The display device also includes a pixel circuit and a light-emitting element, and the pixel circuit is connected to the light-emitting element. The display driver chip transmits the driving voltage to the pixel circuit of the display device, and the pixel circuit generates a driving current according to the driving voltage. The light-emitting element emits light in response to the driving current, so that the display device displays the picture to be displayed. Among them, the pixel circuit can be a 2T1C pixel circuit and its deformation, or it can be a 7T1C pixel circuit and its deformation. The 2T1C pixel circuit may include a data write transistor, a drive transistor and a storage capacitor. The 7T1C pixel circuit may include a data write transistor, a drive transistor, a first reset transistor, a second reset transistor, a first light-emitting control transistor, a second light-emitting control transistor and a storage capacitor. The light-emitting element may be an organic light-emitting diode.

[0055] In some implementations, a display device is provided with a timing controller; in some other implementations, a display device is provided with a plurality of timing controllers. This embodiment does not limit the number of timing controllers.

[0056] Figure 1 is a flowchart of a data transmission method provided by an embodiment of the present invention, with reference to Figure 1 , data transmission methods include:

[0057] S110, obtaining first verification data by calculating at least one data other than the first verification data in the instruction signal.

[0058] Among them, the command signal is a signal sent by the host to the timing controller. The command signal can be a signal for configuring parameters of the timing controller, a signal for controlling the operating status of the timing controller, a signal for reading the status of the timing controller, or other signals, which are not limited in this embodiment.

[0059] Specifically, the instruction signal may include multiple data, and each data may have multiple bits. For example, the instruction signal may include a device address, so as to facilitate sending the instruction signal to the timing controller corresponding to the device address. The instruction signal may also include other data, such as instruction data and read-write flags. At least one data other than the first verification data may be operated, for example, one data other than the first verification data may be operated, such as shifting the data, or adding each bit of the data, or using other operation methods for operation, which is not limited in this embodiment. Two types of data other than the first verification data may also be operated, such as adding, subtracting, multiplying or XORing the two types of data, which is not limited in this embodiment. Multiple types of data other than the first verification data may also be operated, such as performing operations such as addition or subtraction. In this way, the first verification data may be obtained, which facilitates the timing controller to verify the instruction signal according to the first verification data.

[0060] S120, sending a command signal to all timing controllers; wherein the command signal includes a device address and first verification data.

[0061] Specifically, the host and the timing controller can be connected via the IIC bus, then all timing controllers are connected to the IIC bus, and the host can send command signals to all timing controllers via the IIC bus. All timing controllers can receive command signals, and each timing controller compares the device address in the received command signal with its own address. When the device address is consistent with its own address, the command signal can be verified according to the first verification data. When the verification passes, the timing controller acts according to the command signal. In this way, when signal loss or loss occurs during the communication process, the timing controller can be informed in time, thereby ensuring the reliability of signal transmission, avoiding the timing controller from executing according to the wrong instruction and affecting the drive of the display device, which is beneficial to improving the performance of the display device. In addition, it can avoid the problem that the timing controller cannot continue to communicate with the host due to the wrong instruction, resulting in the timing controller being unable to operate normally and affecting the drive of the display device, which is beneficial to improving the performance of the display device.

[0062] The technical solution of the embodiment of the present invention is to set the first verification data in the command signal, and the first verification data is obtained by calculating at least one data other than the first verification data in the command signal, so that the timing controller can verify other data in the command signal according to the first verification data, and ensure that the timing controller performs corresponding actions according to the correct command signal. In addition, after the command signal obtained by the timing controller contains the first verification data, the timing controller will also send a feedback signal to the host in a corresponding format, that is, send a feedback signal with the second verification data to the host, so that the host can verify the feedback signal, thereby ensuring the reliability of communication between the host and the timing controller, and then improving the performance of the display device.

[0063] On the basis of the above technical solution, optionally, the instruction signal is a read instruction or a write instruction; the instruction signal also includes a read-write flag.

[0064] Optionally, sending a command signal to all timing controllers includes:

[0065] Send a read command or a write command to all sequencers.

[0066] Specifically, the host can send a write instruction to the timing controller, so that the timing controller acts according to the write instruction. The host can send a read instruction to the timing controller, so that the timing controller sends a feedback signal according to the read instruction, so that the host can obtain the status of the timing controller. By setting the read-write flag, the timing controller knows whether the instruction signal is a read instruction or a write instruction, so as to act accurately.

[0067] In some embodiments, the host may first send a write instruction to the timing controller, and then send a read instruction; or send multiple write instructions before sending a read instruction; or send a read instruction first, then send a write instruction, and then send a read instruction. After sending multiple write instructions, a read instruction may be sent once, or multiple read instructions may be sent. The read instruction may be sent after sending the write instruction for a period of time. The host may also send read instructions and write instructions in other ways, which are not limited in this embodiment.

[0068] Figure 2 is a flowchart of another data transmission method provided by an embodiment of the present invention. Figure 2 , data transmission methods include:

[0069] S210, sending a read instruction to all timing controllers; wherein the read instruction includes a device address and first verification data, and the first verification data is obtained by calculating at least one data other than the first verification data in the read instruction.

[0070] S220 , when receiving a feedback signal sent by a timing controller corresponding to a device address, verify the feedback signal according to second verification data of the feedback signal.

[0071] Specifically, after receiving the read instruction, the timing controller will send a feedback signal to the host according to the read instruction. The feedback signal includes feedback data and second verification data, and the feedback data can be data corresponding to the state of the timing controller. The host can verify the feedback signal according to the second verification data, and determine the state of the timing controller when the verification passes. In this way, the host can accurately read the state of the timing controller, and then accurately send instructions to the timing controller according to the state of the timing controller, avoiding the problem of performing erroneous operations on the timing controller, resulting in the inability to continue to read and write operations on the timing controller, thereby ensuring that the operation of the timing controller can be controlled, so that the timing controller accurately generates display data, and then accurately drives the display device, thereby improving the performance of the display device.

[0072] The technical solution of this embodiment sets the first verification data in the command signal so that the timing controller also carries the second verification data when sending the feedback signal, which makes it easier for the host to verify the feedback signal according to the second verification data, thereby improving the reliability of signal transmission.

[0073] Optionally, the instruction signal also includes instruction data and register addresses. The instruction data is data for controlling the action of the timing controller. The timing controller includes a plurality of registers, and by setting the register addresses, it is convenient to write instruction data into the corresponding registers.

[0074] In one embodiment, Figure 3 is a flowchart of another data transmission method provided by an embodiment of the present invention. Figure 3 , data transmission methods include:

[0075] S310, operate the instruction data and the register address according to a preset operation method to obtain first verification data; wherein the preset operation method includes at least one of addition, subtraction, multiplication, shift and XOR.

[0076] Specifically, the instruction data in the instruction signal and the register address are operated according to a preset operation mode, which can be operated according to one operation mode or multiple operations can be performed multiple times according to multiple operation modes. For example, the instruction data and the data in the register address are added, subtracted, multiplied or XORed, or the instruction data or the register address are shifted and then added, subtracted, multiplied or XORed. Alternatively, the instruction data and the register address are added first and then shifted, which is not limited in this embodiment. In this way, the first verification data can be obtained, which is convenient for the timing controller to verify the instruction signal according to the first verification data.

[0077] The instruction data and register address in each transmitted instruction signal may be variable. The first verification data is obtained by performing calculations based on the instruction data and the register address to verify whether the instruction data and register address transmitted each time are correct, thereby improving the reliability of signal transmission.

[0078] S320, sending a command signal to all timing controllers; wherein the command signal includes a device address, command data, a register address and first verification data.

[0079] Exemplarily, Table 1 is a schematic table of a read instruction. As shown in Table 1, the read instruction includes a device address and a read / write flag DevAddr. The device address is, for example, 0x77, the read / write flag is read R, and the register address is D0-D3, that is, it includes four bytes. D0, D1, D2, and D3 all include 8-bit data. D0, D1, D2, and D3 form a complete register address, that is, the register address can include 32-bit data, but it is not limited. As shown in Table 1, D0 is the 0th to 7th bits of the register address, D1 is the 8th to 15th bits of the register address, D2 is the 16th to 23rd bits of the register address, and D3 is the 24th to 31st bits of the register address.

[0080] Table 1 Schematic diagram of a read instruction

[0081] byte Bit describe value DevAddr [7:0] Device address and read / write flags 0x77+R D0 [7:0] Value[7:0] - D1 [7:0] Value[15:8] - D2 [7:0] Value[23:16] - D3 [7:0] Value[31:24] - D4 [7:0] First verification data D0+D1+D2+D3

[0082] There are many possibilities for the data of the register address. The data of the register address is not limited in Table 1, and the register address can be determined according to the actual situation. The first verification data D4 is the sum of the data of all bits of the register address, that is, D4 = D0 + D1 + D2 + D3, so as to obtain the first verification data. In some other implementations, the first verification data can also be the sum of the data of the device address and the register address, and the first verification data can also be the sum of the data of the device address, the read-write flag and the register address, which is not limited in this embodiment.

[0083] In some other implementations, the read instruction may also include instruction data, which is not shown in Table 1, but is not limited thereto. The instruction data in the read instruction may determine the content to be read, so that the timing controller can send a feedback signal to the host according to the read instruction.

[0084] Table 2 is a schematic table of a write instruction. As shown in Table 2, the write instruction includes a device address and a read-write flag DevAddr. The device address is, for example, 0x77, and the read-write flag is write W. The instruction signal also includes instruction data D0. The instruction data D0 is, for example, 0x06, but it is not limited. The register address is D1-D4, that is, it includes four bytes. D1, D2, D3 and D4 all include 8-bit data. D1, D2, D3 and D4 form a complete register address, that is, the register address can include 32-bit data, but it is not limited. As shown in Table 2, D1 is the 0th to 7th bit of the register address, D2 is the 8th to 15th bit of the register address, D3 is the 16th to 23rd bit of the register address, and D4 is the 24th to 31st bit of the register address.

[0085] Table 2 Schematic diagram of a write instruction

[0086] byte Bit describe value DevAddr [7:0] Device address and read / write flags 0x77+W D0 [7:0] Instruction data 0x06 D1 [7:0] Value[7:0] - D2 [7:0] Value[15:8] - D3 [7:0] Value[23:16] - D4 [7:0] Value[31:24] - D5 [7:0] First verification data D0+D1+D2+D3+D4

[0087] There are many possibilities for the data of the register address. The data of the register address is not limited in Table 2, and the register address can be determined according to the actual situation. The first verification data D5 is the sum of the data of all bits of the instruction data D0 and the register address, that is, D5 = D0 + D1 + D2 + D3 + D4, so as to obtain the first verification data. In some other implementations, the first verification data can also be the sum of the data of the device address, instruction data and register address, and the first verification data can also be the sum of the data of the device address, instruction data, read-write flag and register address, which is not limited in this embodiment.

[0088] In another embodiment, Figure 4 is a flowchart of another data transmission method provided by an embodiment of the present invention. Figure 4 , data transmission methods include:

[0089] S410, calculating the device address, instruction data and register address according to a preset calculation method to obtain first verification data; wherein the preset calculation method includes at least one of addition, subtraction, multiplication, shift and XOR.

[0090] Specifically, when the host is connected to at least two timing controllers, the device address in the command signal sent by the host will change. Therefore, the device address, command data and register address are calculated according to a preset calculation method to obtain the first verification data, so that the timing controller can verify the device address, command data and register address according to the first verification data, thereby improving the reliability of signal transmission.

[0091] S420, sending a command signal to all timing controllers; wherein the command signal includes a device address, command data, a register address and first verification data.

[0092] The technical solution of this embodiment obtains the first verification data by calculating the instruction data and the register address, so that the timing controller can verify the instruction data and the register address according to the first verification data. Alternatively, the first verification data is obtained by calculating the device address, instruction data and register address, so that the timing controller can verify the device address instruction data and the register address according to the first verification data. In this way, the timing controller can determine whether the received instruction data and register address are correct, which is convenient for improving the reliability of signal transmission.

[0093] Based on the above technical solution, in one implementation, optionally, sending the instruction signal to all timing controllers includes:

[0094] The instruction signal is sent to all timing controllers in the order of device address, instruction data, register address and first verification data.

[0095] Specifically, for example, the host and the timing controller transmit signals in a serial communication manner. By setting the order of device address, instruction data, register address and first verification data, the instruction signal is sent to all timing controllers, so that the timing controller can compare the device address with its own address. If the device address is consistent with its own address, the instruction data and register address can be verified according to the first verification data, thereby ensuring the reliability of signal transmission. In addition, by setting the register address, the timing controller can write the instruction data to the target register corresponding to the register address, thereby ensuring the accuracy of signal transmission.

[0096] In another embodiment, sending the instruction signal to all timing controllers includes: sending the instruction signal to all timing controllers in the order of device address, register address, instruction data and first verification data. In this way, the timing controller can compare the device address with its own address. If the device address is consistent with its own address, the register address and instruction data can be verified according to the first verification data, thereby ensuring the reliability of signal transmission.

[0097] The technical solution of this embodiment places the first verification data at the end of the instruction signal, so that the timing controller can verify other data (such as instruction data and register address) in the received instruction signal according to the first verification data.

[0098] Based on the above technical solutions, Figure 5 is a flowchart of another data transmission method provided by an embodiment of the present invention. Figure 5 , data transmission methods include:

[0099] S510, adding the instruction data to the data of the register address to obtain first verification data.

[0100] Specifically, by using the addition method to perform calculations, the calculation time can be reduced, the calculation efficiency can be improved, and thus the communication efficiency between the host and the timing controller can be improved. The instruction data is added to the data of the register address, for example, each bit of the instruction data is added to each bit of the register address. The calculation can also be performed in other addition methods, which are not limited in this embodiment. In addition, it is convenient for the timing controller to perform verification, and the time used for verification is shortened.

[0101] S520, sending a command signal to all timing controllers through the IIC channel; wherein the command signal includes a device address, command data, a register address and first verification data.

[0102] Specifically, the host and the timing controller communicate via the IIC channel, so that the host can send command signals to all timing controllers via the IIC bus, and the reliability of the IIC communication is improved by setting the first verification data, so that the host and the timing controller can communicate stably.

[0103] The technical solution of this embodiment, by adding the instruction data and the data of the register address to obtain the first verification data, can simplify the operation, reduce the operation time, and improve the operation efficiency, thereby improving the communication efficiency between the host and the timing controller.

[0104] An embodiment of the present invention further provides a data transmission method, which is applied to a timing controller connected to a host.

[0105] Figure 6 is a flowchart of another data transmission method provided by an embodiment of the present invention, referring to Figure 6 , data transmission methods include:

[0106] S610, when receiving the command signal from the host, determine whether the device address in the command signal is consistent with the address of the timing controller, if so, execute step S620; if not, end.

[0107] Specifically, when the timing controller receives a command signal from the host, it compares the device address contained in the command signal with its own address. If they are consistent, it will perform subsequent operations, so that the host can communicate with the target timing controller corresponding to the device address, and then the timing controller corresponding to the device address will act according to the command signal to ensure the accuracy of communication.

[0108] S620. Verify the command signal according to first verification data in the command signal; wherein the first verification data is obtained by calculating at least one data other than the first verification data in the command signal.

[0109] Specifically, the host calculates at least one data other than the first verification data in the command signal to obtain the first verification data, and the timing controller calculates the data involved in the calculation in the same calculation method, and then compares the calculation result with the first verification data, that is, the command signal is verified according to the first verification data. In this way, when signal loss or loss occurs during the communication process, the timing controller can be notified in time, thereby ensuring the reliability of signal transmission, avoiding the timing controller from executing according to erroneous instructions and affecting the driving of the display device, which is beneficial to improving the performance of the display device. In addition, it can avoid the problem that the timing controller cannot continue to communicate with the host due to erroneous instructions, resulting in the timing controller being unable to operate normally and affecting the driving of the display device, which is beneficial to improving the performance of the display device.

[0110] The technical solution of the embodiment of the present invention sets the first verification data in the command signal, and the first verification data is obtained by calculating at least one data other than the first verification data in the command signal, so that the timing controller can verify other data in the command signal according to the first verification data, thereby ensuring that the timing controller executes corresponding actions according to the correct command signal, ensuring the reliability of communication between the host and the timing controller, and thus improving the performance of the display device.

[0111] On the basis of the above technical solution, optionally, the instruction signal is a read instruction or a write instruction; the instruction signal also includes a read-write flag.

[0112] Figure 7 is a flowchart of another data transmission method provided by an embodiment of the present invention. Figure 7 , data transmission methods include:

[0113] S710, when receiving a read command from the host, determine whether the device address in the command signal is consistent with the address of the timing controller, if so, execute step S720; if not, end.

[0114] S720, verify the command signal according to the first verification data in the command signal, and determine whether the verification is passed, if so, execute step S730; if not, end. The first verification data is obtained by calculating at least one data other than the first verification data in the command signal.

[0115] Specifically, the timing controller verifies the instruction signal according to the first verification data, and only executes the subsequent action when the verification passes, and does not take action when the verification fails, which is not limited in this embodiment. In some other implementations, when the verification fails, the timing controller may also feedback prompt information to the host, which is not specifically limited in this embodiment.

[0116] S730, sending a feedback signal to the host; wherein the feedback signal includes feedback data and second verification data.

[0117] Specifically, after receiving the read instruction, the timing controller will send a feedback signal to the host according to the read instruction. The feedback signal includes feedback data and second verification data, and the feedback data can be data corresponding to the state of the timing controller. The host can verify the feedback signal according to the second verification data, and determine the state of the timing controller when the verification passes. In this way, the host can accurately read the state of the timing controller, and then accurately send instructions to the timing controller according to the state of the timing controller, avoiding the problem of performing erroneous operations on the timing controller, resulting in the inability to continue to read and write operations on the timing controller, thereby ensuring that the operation of the timing controller can be controlled, so that the timing controller accurately generates display data, and then accurately drives the display device, thereby improving the performance of the display device.

[0118] The technical solution of this embodiment, by setting the first verification data in the command signal and setting the second verification data in the feedback signal, facilitates the host and the timing controller to verify the received signal and improves the reliability of signal transmission.

[0119] Based on the above technical solutions, Figure 8 is a flowchart of another data transmission method provided by an embodiment of the present invention. Figure 8 , data transmission methods include:

[0120] S810, when receiving a read command from the host, determine whether the device address in the command signal is consistent with the address of the timing controller, if so, execute step S820; if not, end.

[0121] S820, verify the command signal according to the first verification data in the command signal, if the verification passes, execute step S830; if not, end.

[0122] S830, operate the feedback data according to a preset operation method to obtain second verification data, and send the feedback data and the second verification data to the host; wherein the preset operation method includes at least one of addition, subtraction, multiplication, shift and XOR.

[0123] Specifically, the feedback data is operated according to a preset operation mode, which may be operated according to one operation mode or multiple operations may be performed in multiple operation modes. For example, each bit of the feedback data is added, subtracted, multiplied or shifted, or each bit of the feedback data is XORed with a preset value. Alternatively, the addition operation may be performed first, and then the shift operation may be performed, which is not limited in this embodiment. For example, the preset operation mode corresponding to the second verification data is the same as the preset operation mode corresponding to the first verification data, which is convenient for the host and the timing controller to perform verification.

[0124] On the basis of the above technical solution, optionally, the feedback data is operated according to a preset operation mode to obtain second verification data, including:

[0125] Add each bit of the feedback data to obtain the second verification data.

[0126] Specifically, by using the addition method to perform calculations, the calculation time can be reduced, the calculation efficiency can be improved, and the communication efficiency between the host and the timing controller can be improved. In addition, it is convenient for the host to perform verification and the time used for verification can be shortened.

[0127] Optionally, the data in the feedback signal is arranged in the order of the feedback data and the second verification data. This arrangement facilitates the host to first receive the feedback data, then receive the second verification data, and then verify the feedback data according to the second verification data, thereby determining whether the received feedback data is correct, thereby ensuring the reliability of communication between the host and the timing controller.

[0128] Optionally, sending a feedback signal to a host includes:

[0129] Send feedback signal to the host through the IIC channel.

[0130] Specifically, the host and the timing controller communicate via the IIC channel, so that the host can send command signals to all timing controllers through the IIC bus, and the reliability of the IIC communication is improved by setting the first verification data and the second verification data, so that the host and the timing controller can communicate reliably and stably.

[0131] The technical solution of this embodiment obtains the second verification data by calculating according to the feedback data, so that the host can verify the feedback data according to the second verification data, thereby improving the reliability of signal transmission.

[0132] An embodiment of the present invention further provides a display device, Fig. 9 is a schematic diagram of a display device provided by an embodiment of the present invention, with reference to Fig. 9, the display device comprises: a host 11 and at least one timing controller 12; the host 11 is connected to the at least one timing controller 12;

[0133] The host 11 is used to send a command signal to all timing controllers 12; wherein the command signal includes a device address and a first verification data, and the first verification data is obtained by calculating at least one data other than the first verification data in the command signal;

[0134] The timing controller 12 is used for verifying the instruction signal according to the first verification data if the device address in the instruction signal is consistent with the address of the timing controller.

[0135] The host 11 may be a central processing unit (CPU) inside the display device. The timing controller 12 may generate a driving voltage according to the image to be displayed. Fig. 9 As shown, the display device also includes at least one display driver chip 13, a plurality of pixel circuits 14 and a plurality of light-emitting elements 15, the timing controller 12 is connected to at least one display driver chip 13, and the display driver chip 13 is connected to a plurality of pixel circuits 14. The pixel circuit 14 is connected to the light-emitting element 15. The timing controller 12 can be connected to at least one display driver chip 13 through a data channel and an instruction channel, and both the data channel and the instruction channel can be bidirectional channels. Through the instruction channel, the timing controller 12 can send instructions to the display driver chip 13 to control the operation of the display driver chip 13. The instruction channel is, for example, an IIC channel.

[0136] Through the data channel, the display driver chip 13 transmits the driving voltage output by the timing controller 12 to the pixel circuit of the display device, the pixel circuit 14 generates a driving current according to the driving voltage, and the light-emitting element 15 emits light in response to the driving current, so that the display device displays the image to be displayed. Among them, the pixel circuit 14 and the light-emitting element 15 are located in the display area AA of the display device.

[0137] Specifically, the host 11 can be connected to at least one timing controller 12 through the IIC bus, then all timing controllers 12 are connected to the IIC bus, and the host 11 can send command signals to all timing controllers 12 through the IIC bus. All timing controllers 12 can receive the command signal, and each timing controller 12 compares the device address in the received command signal with its own address. When the device address is consistent with its own address, the command signal can be verified according to the first verification data. When the verification passes, the timing controller 12 acts according to the command signal. In this way, when signal loss or loss occurs during the communication process, the timing controller 12 can be informed in time, thereby ensuring the reliability of signal transmission, avoiding the timing controller 12 from executing according to the wrong instruction and affecting the driving of the display device, which is conducive to improving the performance of the display device. In addition, it can avoid the problem that the timing controller 12 cannot continue to communicate with the host 11 due to the wrong instruction, resulting in the timing controller 12 being unable to operate normally and affecting the driving of the display device, which is conducive to improving the performance of the display device.

[0138] It should be noted that Fig. 9 FIG. 1 shows a case where the host 11 is connected to one timing controller 12 , but this is not limiting.

[0139] The technical solution of the embodiment of the present invention is to set the first verification data in the command signal, and the first verification data is obtained by calculating at least one data other than the first verification data in the command signal, so that the timing controller can verify other data in the command signal according to the first verification data, and ensure that the timing controller performs corresponding actions according to the correct command signal. In addition, after the command signal obtained by the timing controller contains the first verification data, the timing controller will also send a feedback signal to the host in a corresponding format, that is, send a feedback signal with the second verification data to the host, so that the host can verify the feedback signal, thereby ensuring the reliability of communication between the host and the timing controller, and then improving the performance of the display device.

[0140] The embodiment of the present invention further provides a display module. Fig.10 is a schematic diagram of the structure of a display module provided by an embodiment of the present invention, with reference to Fig.10 The display module 20 includes the display device 21 provided in any embodiment of the present invention, so the display module 20 has the same beneficial effects as the display device 21 provided in any embodiment of the present invention, which will not be described in detail here. The display module 20 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, etc.

[0141] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0142] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A data transmission method, characterized in that: Applied to a host; the host is connected to at least one timing controller; the method comprises: A command signal is sent to all the timing controllers; wherein the command signal includes a device address and first verification data, and the first verification data is obtained by calculating at least one data other than the first verification data in the command signal.

2. The method according to claim 1, characterized in that The command signal is a read command or a write command; the command signal also includes a read-write flag; Sending a command signal to all the timing controllers includes: Sending the read instruction or the write instruction to all the timing controllers; After sending the read instruction to all the timing controllers, the method further includes: When a feedback signal sent by a timing controller corresponding to a device address is received, the feedback signal is verified according to second verification data of the feedback signal.

3. The method according to claim 1, characterized in that The command signal also includes command data and register address; Sending a command signal to all the timing controllers includes: The instruction data and the register address are operated according to a preset operation mode to obtain the first verification data, and the instruction signal is sent to all timing controllers; wherein the preset operation mode includes at least one of addition, subtraction, multiplication, shift and XOR; Alternatively, the device address, the instruction data and the register address are operated according to a preset operation method to obtain the first verification data, and the instruction signal is sent to all timing controllers.

4. The method according to claim 3, characterized in that The command signal is sent to all timing controllers, including: Sending the instruction signal to all the timing controllers in the order of the device address, the instruction data, the register address and the first verification data; Alternatively, the instruction signal is sent to all the timing controllers in the order of the device address, the register address, the instruction data and the first verification data.

5. The method according to claim 3, characterized in that: The instruction data and the register address are operated according to a preset operation mode to obtain the first verification data, including: Add the instruction data to the data of the register address to obtain the first verification data; Preferably, sending a command signal to all the timing controllers includes: The command signal is sent to all the timing controllers through the IIC channel.

6. A data transmission method, characterized in that: Applied to a timing controller, the timing controller is connected to a host; the method comprises: When receiving a command signal from the host, if the device address in the command signal is consistent with the address of the timing controller, the command signal is verified according to the first verification data in the command signal; wherein the first verification data is obtained by calculating at least one data other than the first verification data in the command signal.

7. The method according to claim 6, characterized in that The instruction signal is a read instruction or a write instruction; the instruction signal also includes a read-write flag; the method also includes: When receiving a read instruction from the host, if the device address in the instruction signal is consistent with the address of the timing controller, and the instruction signal is verified according to the first verification data in the instruction signal, a feedback signal is sent to the host; wherein the feedback signal includes feedback data and second verification data.

8. The method according to claim 7, characterized in that Sending a feedback signal to the host includes: Calculate the feedback data according to a preset calculation method to obtain the second verification data, and send the feedback data and the second verification data to the host; wherein the preset calculation method includes at least one of addition, subtraction, multiplication, shift and XOR; Preferably, the feedback data is operated according to a preset operation mode to obtain the second verification data, including: Adding each bit of the feedback data to obtain the second verification data; Preferably, the data in the feedback signal is arranged in the order of the feedback data and the second verification data; Preferably, sending a feedback signal to the host comprises: The feedback signal is sent to the host through the IIC channel.

9. A display device, characterized in that: include: A host and at least one timing controller; the host is connected to at least one of the timing controllers; The host is used to send a command signal to all the timing controllers; wherein the command signal includes a device address and a first verification data, and the first verification data is obtained by calculating at least one data other than the first verification data in the command signal; The timing controller is used for verifying the instruction signal according to the first verification data if the device address in the instruction signal is consistent with the address of the timing controller.

10. A display module, characterized in that: A display device comprising the display device according to claim 9.

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