NAND chip high voltage test system
By sharing the enable signal and clock signal in the BIST test machine, the problem of time consumption and hardware increase when testing multiple NAND chips in the prior art is solved, and simultaneous testing of multiple chips is realized, reducing costs and improving efficiency.
Patent Information
- Application Number
- CN202411534908.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-02-14
AI Technical Summary
When testing multiple NAND chips, existing BIST test machines need to be tested one by one, resulting in time consumption and hardware increase, which increases costs and troubles.
By sharing the enable signal and clock signal of a unit in the test machine, and connecting to the enable pins and clock pins of multiple chips to be tested, simultaneous testing of multiple chips is achieved.
Multiple NAND chips can be tested simultaneously without adding hardware, reducing test time and cost, and improving testing efficiency and convenience.
Smart Images
Figure CN119446247A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chips, and in particular to a system for high voltage testing of NAND chips. Background Art
[0002] The BIST machine (tester) is designed specifically for testing memory chips (e.g., NAND chips) with BIST modules, so its resource configuration has been simplified to the minimum (including 2 drivers, 1 input / output, and 1 DPS). The chip to be tested requires 5 test resources: WE, CK, DQ, VMON, and DPS. Therefore, when multiple test chips need to be tested, it is either more time-consuming to test each chip one by one, or to increase hardware. This method not only increases costs, but is also more troublesome. Summary of the invention
[0003] In view of the above problems, the present invention provides a system for high voltage testing of NAND chips that overcomes the above problems or at least partially solves the above problems.
[0004] A system for high voltage testing of a NAND chip, comprising: a first chip to be tested NAND1, a second chip to be tested NAND2 and a testing machine;
[0005] The enable pins of the first chip to be tested NAND1 and the second chip to be tested NAND2 are both connected to the M signal terminal of the first unit of the tester;
[0006] The clock pins of the first chip to be tested NAND1 and the second chip to be tested NAND2 are both connected to the SK signal terminal of the first unit of the tester;
[0007] The M signal terminal of the first unit of the tester sends an enable signal to activate the first chip to be tested NAND1 and the second chip to be tested NAND2;
[0008] The SK signal terminal of the first unit of the tester sends a clock signal to start the first chip to be tested NAND1 and the second chip to be tested NAND2, so as to test the first chip to be tested NAND1 and the second chip to be tested NAND2.
[0009] Optionally, in some optional implementations, the voltage monitoring pin of the first chip to be tested NAND1 is connected to the M signal terminal of the second unit of the tester;
[0010] The M signal terminal of the second unit of the tester sends a high voltage signal to perform a high voltage test on the first chip to be tested NAND1 and monitor the voltage of the voltage monitoring pin of the first chip to be tested NAND1.
[0011] Optionally, in some optional implementations, the voltage monitoring pin of the second chip to be tested NAND2 is connected to the SK signal terminal of the second unit of the tester;
[0012] The SK signal terminal of the second unit of the tester sends a high voltage signal to perform a high voltage test on the second chip to be tested NAND2, and monitors the voltage of the voltage monitoring pin of the second chip to be tested NAND2.
[0013] Optionally, in some optional implementations, the digital pin of the first chip to be tested NAND1 is connected to the input and output end of the first unit of the tester;
[0014] The digital pins of the second chip to be tested NAND2 are connected to the input and output terminals of the second unit of the tester.
[0015] Optionally, in some optional implementations, the system further includes: a third chip to be tested NAND3 and a fourth chip to be tested NAND4;
[0016] The enable pins of the third chip to be tested NAND3 and the fourth chip to be tested NAND4 are both connected to the M signal terminal of the third unit of the tester;
[0017] The clock pins of the third chip to be tested NAND3 and the fourth chip to be tested NAND4 are both connected to the third unit SK signal terminal of the tester;
[0018] The M signal terminal of the third unit of the tester sends an enable signal to activate the third chip to be tested NAND3 and the fourth chip to be tested NAND4;
[0019] The SK signal terminal of the third unit of the tester sends a clock signal to start the third chip to be tested NAND3 and the fourth chip to be tested NAND4, so as to test the third chip to be tested NAND3 and the fourth chip to be tested NAND4.
[0020] Optionally, in some optional implementations, the voltage monitoring pin of the third chip to be tested NAND3 is connected to the M signal terminal of the fourth unit of the tester;
[0021] The M signal terminal of the fourth unit of the tester sends a high voltage signal to perform a high voltage test on the third chip to be tested NAND3, and monitors the voltage of the voltage monitoring pin of the third chip to be tested NAND3.
[0022] Optionally, in some optional implementations, the voltage monitoring pin of the fourth chip to be tested NAND4 is connected to the SK signal terminal of the fourth unit of the tester;
[0023] The SK signal terminal of the fourth unit of the tester sends a high-voltage signal to perform a high-voltage test on the fourth chip to be tested NAND4, and monitors the voltage of the voltage monitoring pin of the fourth chip to be tested NAND4.
[0024] Optionally, in some optional implementations, the digital pin of the third chip to be tested NAND3 is connected to the input and output end of the third unit of the tester;
[0025] The digital pin of the fourth chip to be tested NAND4 is connected to the input and output end of the fourth unit of the tester.
[0026] By means of the above technical scheme, the present invention provides a system for high voltage testing of NAND chips, which can connect the enable pins of the first chip to be tested NAND1 and the second chip to be tested NAND2 to the M signal end of the first unit of the tester; the clock pins of the first chip to be tested NAND1 and the second chip to be tested NAND2 are connected to the SK signal end of the first unit of the tester; the M signal end of the first unit of the tester sends an enable signal to activate the first chip to be tested NAND1 and the second chip to be tested NAND2; the SK signal end of the first unit of the tester sends a clock signal to start the first chip to be tested NAND1 and the second chip to be tested NAND2, so as to facilitate testing of the first chip to be tested NAND1 and the second chip to be tested NAND2. It can be seen from this that the present invention can share the enable signal and clock signal of a unit (first unit) to the first chip to be tested and the second chip to be tested at the same time, and drive the two chips to be tested at the same time through one unit, without adding hardware and can drive and test the two chips to be tested at the same time, which is more convenient and fast without increasing costs.
[0027] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:
[0029] Figure 1 A schematic diagram showing the structure of a first NAND chip high voltage test system provided by the present invention;
[0030] Figure 2 A schematic diagram showing the structure of a second NAND chip high voltage test system provided by the present invention;
[0031] Figure 3 A schematic diagram showing the structure of a third NAND chip high voltage test system provided by the present invention;
[0032] Figure 4 A schematic diagram showing the structure of a fourth NAND chip high voltage test system provided by the present invention;
[0033] Figure 5 A schematic structural diagram of a fifth NAND chip high voltage test system provided by the present invention is shown. DETAILED DESCRIPTION
[0034] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to enable the scope of the present invention to be fully communicated to those skilled in the art.
[0035] like Figure 1 As shown, the present invention provides a system for high voltage testing of NAND chips, comprising: a first chip to be tested NAND1, a second chip to be tested NAND2 and a tester BIST;
[0036] The enable pins of the first chip to be tested NAND1 and the second chip to be tested NAND2 are both connected to the M signal terminal of the first unit SITE1 of the tester BIST;
[0037] Optionally, the chip under test mentioned in the present invention can be understood as testing on a device under test (DUT). A device under test is a manufactured product that is tested when it is first manufactured or later in its life cycle as part of ongoing functional testing and calibration. This can include post-repair testing to determine whether the product performs according to the original product specifications.
[0038] Optionally, NAND (NotAND) chips are well-known technical concepts in the art, and the present invention does not make too many descriptions on this. For details, please refer to the relevant explanations in the art. It should be noted that the high-voltage test of the NAND chip in the present invention can timely detect whether the high voltage is too high or too low, greatly reducing the risk of the chip being broken down by the high voltage, and enhancing the safety and reliability of the chip test. The present invention does not limit this.
[0039] Optional, optional, the M signal terminal sends an enable signal (also called M signal), which is a drive output signal. The M signal is a unidirectional signal that only outputs but does not input, and can output high-level and low-level signals. The M signal is generated by a dedicated digital logic chip inside the tester BIST. Due to the enable pin defined by the NAND chip ( Figure 1 When starting to write to the NAND chip, the WE signal must be pulled high to indicate that the write enable is complete before the NAND chip can be written. Otherwise, the unit in the tester BIST (for example, Figure 1 SITE1 in the NAND chip cannot perform any operations.
[0040] The clock pins of the first chip to be tested NAND1 and the second chip to be tested NAND2 are both connected to the SK signal terminal of the first unit SITE1 of the tester BIST;
[0041] Optionally, the SK signal terminal can generate the clock signal (also called SK signal) required by the NAND chip, which is also a driving signal. It is a unidirectional signal that only outputs but does not input, and generates high and low clock pulse signals. The SK signal is also generated by a dedicated digital logic chip inside the tester BIST. Figure 1 The NAND chip needs a unit of the test machine BIST (such as Figure 1 SITE1 in the figure provides a specific clock signal to start normal operation, otherwise the normal function test cannot be started.
[0042] The M signal terminal of the first unit SITE1 of the tester BIST sends an enable signal to activate the first chip to be tested NAND1 and the second chip to be tested NAND2;
[0043] Optionally, in SITE1, the M signal is responsible for driving the write enable (WE) pins of NAND1 and NAND2 to ensure that the two chips to be tested can accurately perform data write operations. It can be seen from this that the present invention can enable and drive two chips to be tested at the same time based on one hardware device (i.e., SITE1), which reduces the hardware cost to a certain extent, and the present invention is not limited to this.
[0044] The SK signal terminal of the first unit SITE1 of the tester BIST sends a clock signal to start the first chip to be tested NAND1 and the second chip to be tested NAND2, so as to test the first chip to be tested NAND1 and the second chip to be tested NAND2.
[0045] Optionally, in SITE1, the SK signal is specifically responsible for driving the clock pins of NAND1 and NAND2 to provide the required timing control. This design enables efficient and accurate multi-device operations in the test environment of SITE1, ensuring synchronization and stability.
[0046] Synchronicity: The biggest feature of this case is the signal sharing solution, because the WE pins of NAND1 and NAND2 are connected to the M signal terminal at the same time, and the CK pins of NAND1 and NAND2 are connected to the SK signal terminal at the same time. Therefore, when the SITE1 of the tester BIST sends out the M signal, it can drive the WE pins of NAND1 and NAND2 synchronously; when SITE1 sends out the SK signal, it can also drive the CK pins of NAND1 and NAND2 simultaneously, and the two signals can always remain synchronized.
[0047] Stability: Compared with the two SITE1 and SITE2 sending M signal and SK signal to NAND1 and NAND2 respectively, this sharing method can reduce the probability of misoperation during the test, and also greatly reduce the possibility of poor signal contact, ensuring that the signal can be given to NAND1 and NAND2 in a timely and accurate manner.
[0048] Efficiency: The shared method can reduce the time delay between testing each NAND chip, because the signals arrive at NAND1 and NAND2 at the same time. If this method is not used, there will be switching delays when the signals of NAND1 and NAND2 arrive, which reduces the test efficiency.
[0049] Optional, such as Figure 2 As shown, in some optional implementations, the voltage monitoring pin of the first chip to be tested NAND1 is connected to the M signal terminal of the second unit SITE2 of the tester BIST;
[0050] The M signal terminal of the second unit SITE2 of the tester BIST sends a high voltage signal to perform a high voltage test on the first chip to be tested NAND1 and monitor the voltage of the voltage monitoring pin of the first chip to be tested NAND1.
[0051] Optionally, the voltage monitoring pin is also called the high voltage channel (i.e., Figure 2 In the second unit SITE2 of the tester BIST (i.e., Figure 2 In SITE2 in FIG. 1 , the M signal terminal is connected to the voltage monitoring pin (VM pin) of NAND1 to monitor the voltage of NAND1 in real time to ensure that it operates within a safe working range.
[0052] Optional, such as Figure 3 As shown, in some optional implementations, the voltage monitoring pin VM of the second chip to be tested NAND2 is connected to the SK signal terminal of the second unit SITE2 of the tester BIST;
[0053] The SK signal terminal of the second unit SITE2 of the tester BIST sends a high voltage signal to perform a high voltage test on the second chip to be tested NAND2 and monitor the voltage of the voltage monitoring pin VM of the second chip to be tested NAND2.
[0054] Optionally, in the second unit SITE2 of the tester BIST (i.e., Figure 3 In SITE2 in FIG, the SK signal end is connected to the voltage monitoring pin VM (VM pin) of NAND2 to monitor the voltage of NAND2 in real time to ensure that it operates within a safe working range.
[0055] Combination Figure 3 It can be seen that at the same time, the M signal end of SITE2 is connected to the VM pin of NAND1, and the SK signal end of SITE2 is connected to the VM pin of NAND2. In this way, the voltages of NAND1 and NAND2 can be independently monitored. That is, this strategy not only allows the high voltage status of each DUT to be tracked in real time, but also helps to quickly troubleshoot problems and improve the reliability and safety of the overall test.
[0056] Optionally, since the M signal and the SK signal are the same input for all the devices under test, the two NAND chips can provide one of the NAND chip resources to the VM pin through a shared driver. That is, the present invention realizes power monitoring by connecting the VM pin Pin of the device under test to the Driver signal of the tester BIST (the M signal and the SK signal, one signal can be given to NAND1 and the other signal can be given to NAND2), and using the power management unit (PMU) module on the tester BIST board.
[0057] Optionally, the signal required by the VM pin can be directly generated through the PMU module inside the tester BIST. That is to say, at this time, the M signal end and the SK signal end in SITE2 are switched to the PMU module through the internal switch of the tester BIST, and the PMU module generates the signal required by the VM pin.
[0058] Optionally, the PMU module of the tester BIST has the function of providing and measuring high voltage. By turning on this function module and switching it to the M signal terminal and SK signal terminal of SITE2, the VM pin of the NAND chip can be tracked and checked in real time, and the high or low voltage can be detected in time, which greatly reduces the risk of the chip being broken down by high voltage and enhances the safety and reliability of chip testing.
[0059] Optional, such as Figure 4 As shown, in some optional implementations, the digital pin DQ of the first chip to be tested NAND1 is connected to the input and output terminal IO of the first unit SITE1 of the tester BIST;
[0060] The digital pin of the second chip to be tested NAND2 is connected to the input / output terminal IO of the second unit SITE2 of the tester BIST.
[0061] Optional, the input and output terminals IO are Figure 4 The tester BIST can exchange data with the NAND chip through the input and output terminals IO to facilitate functional testing of the NAND chip, which is not limited in the present invention.
[0062] Optional, such as Figure 5 As shown, in some optional embodiments, the system further includes: a third chip to be tested NAND3 and a fourth chip to be tested NAND4;
[0063] The enable pins of the third chip to be tested NAND3 and the fourth chip to be tested NAND4 are both connected to the M signal terminal of the third unit SITE3 of the tester BIST;
[0064] The clock pins of the third chip to be tested NAND3 and the fourth chip to be tested NAND4 are both connected to the signal end of the third unit SITE3SK of the tester BIST;
[0065] The M signal terminal of the third unit SITE3 of the tester BIST sends an enable signal to activate the third chip to be tested NAND3 and the fourth chip to be tested NAND4;
[0066] The SK signal terminal of the third unit SITE3 of the tester BIST sends a clock signal to start the third chip to be tested NAND3 and the fourth chip to be tested NAND4, so as to test the third chip to be tested NAND3 and the fourth chip to be tested NAND4.
[0067] Optional, such as Figure 5As shown, in some optional implementations, the voltage monitoring pin VM of the third chip to be tested NAND3 is connected to the M signal terminal of the fourth unit SITE4 of the tester BIST;
[0068] The M signal terminal of the fourth unit SITE4 of the tester BIST sends a high voltage signal to perform a high voltage test on the third chip to be tested NAND3 and monitor the voltage of the voltage monitoring pin VM of the third chip to be tested NAND3.
[0069] Optional, such as Figure 5 As shown, in some optional implementations, the voltage monitoring pin VM of the fourth chip to be tested NAND4 is connected to the SK signal terminal of the fourth unit SITE4 of the tester BIST;
[0070] The SK signal terminal of the fourth unit SITE4 of the tester BIST sends a high voltage signal to perform a high voltage test on the fourth chip to be tested NAND4 and monitor the voltage of the voltage monitoring pin VM of the fourth chip to be tested NAND4.
[0071] Optional, such as Figure 5 As shown, in some optional implementations, the digital pin of the third chip to be tested NAND3 is connected to the input and output terminal IO of the third unit SITE3 of the tester BIST;
[0072] The digital pin of the fourth chip to be tested NAND4 is connected to the input / output terminal IO of the fourth unit SITE4 of the tester BIST.
[0073] It should be noted that: for the above-mentioned third chip to be tested NAND3, fourth chip to be tested NAND4, third unit SITE3 and fourth unit SITE4, please refer to the above-mentioned first chip to be tested NAND1, second chip to be tested NAND2, first unit SITE1 and second unit SITE2 for a one-to-one correspondence, and the present invention will not elaborate on this.
[0074] Optionally, high voltage testing of NAND chips can be achieved by sharing drive resources without hardware modification. This strategy is the best solution at present because it effectively utilizes existing resource configuration and avoids additional cost and time investment. The shared drive resource approach can flexibly meet different test requirements while maintaining high test accuracy and reliability. Such a design not only improves the operating efficiency of the test system, but also leaves more room for subsequent expansion and upgrades, further enhancing the competitiveness of the BIST machine in memory chip testing.
[0075] The shared drive test method can directly provide high voltage without modifying any hardware. This solution not only simplifies the test process, but also avoids compatibility issues that may be caused by hardware changes, and improves the convenience and efficiency of testing.
[0076] By adopting a shared drive solution, test costs can be significantly reduced. Signal sharing reduces the need for more drivers and I / Os, thereby reducing system complexity and maintenance costs. At the same time, the simplified design also means less troubleshooting and upgrade work, further optimizing resource efficiency and ensuring cost-effective operation during the high-voltage test phase.
[0077] In the present invention, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0078] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0079] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined in the present invention may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown in the present invention, but will conform to the widest scope consistent with the principles and novel features disclosed in the present invention.
[0080] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims
1. A system for high voltage testing of NAND chips, characterized in that: include: A first chip to be tested NAND1, a second chip to be tested NAND2 and a tester; The enable pins of the first chip to be tested NAND1 and the second chip to be tested NAND2 are both connected to the M signal terminal of the first unit of the tester; The clock pins of the first chip to be tested NAND1 and the second chip to be tested NAND2 are both connected to the SK signal terminal of the first unit of the tester; The M signal terminal of the first unit of the tester sends an enable signal to activate the first chip to be tested NAND1 and the second chip to be tested NAND2; The SK signal terminal of the first unit of the tester sends a clock signal to start the first chip to be tested NAND1 and the second chip to be tested NAND2, so as to test the first chip to be tested NAND1 and the second chip to be tested NAND2.
2. The system according to claim 1, characterized in that The voltage monitoring pin of the first chip to be tested NAND1 is connected to the M signal terminal of the second unit of the tester; The M signal terminal of the second unit of the tester sends a high voltage signal to perform a high voltage test on the first chip to be tested NAND1 and monitor the voltage of the voltage monitoring pin of the first chip to be tested NAND1.
3. The system according to claim 1, characterized in that The voltage monitoring pin of the second chip to be tested NAND2 is connected to the SK signal terminal of the second unit of the tester; The SK signal terminal of the second unit of the tester sends a high-voltage signal to perform a high-voltage test on the second chip to be tested NAND2, and monitors the voltage of the voltage monitoring pin of the second chip to be tested NAND2.
4. The system according to claim 1, characterized in that The digital pin of the first chip to be tested NAND1 is connected to the input and output end of the first unit of the tester; The digital pins of the second chip to be tested NAND2 are connected to the input and output terminals of the second unit of the tester.
5. The system according to claim 1, characterized in that The system further includes: a third chip to be tested NAND3 and a fourth chip to be tested NAND4; The enable pins of the third chip to be tested NAND3 and the fourth chip to be tested NAND4 are both connected to the M signal terminal of the third unit of the tester; The clock pins of the third chip to be tested NAND3 and the fourth chip to be tested NAND4 are both connected to the third unit SK signal terminal of the tester; The M signal terminal of the third unit of the tester sends an enable signal to activate the third chip to be tested NAND3 and the fourth chip to be tested NAND4; The SK signal terminal of the third unit of the tester sends a clock signal to start the third chip to be tested NAND3 and the fourth chip to be tested NAND4, so as to test the third chip to be tested NAND3 and the fourth chip to be tested NAND4.
6. The system according to claim 5, characterized in that The voltage monitoring pin of the third chip to be tested NAND3 is connected to the M signal terminal of the fourth unit of the tester; The M signal terminal of the fourth unit of the tester sends a high voltage signal to perform a high voltage test on the third chip to be tested NAND3, and monitors the voltage of the voltage monitoring pin of the third chip to be tested NAND3.
7. The system according to claim 5, characterized in that The voltage monitoring pin of the fourth chip to be tested NAND4 is connected to the SK signal terminal of the fourth unit of the tester; The SK signal terminal of the fourth unit of the tester sends a high-voltage signal to perform a high-voltage test on the fourth chip to be tested NAND4, and monitors the voltage of the voltage monitoring pin of the fourth chip to be tested NAND4.
8. The system according to claim 5, characterized in that The digital pin of the third chip to be tested NAND3 is connected to the input and output end of the third unit of the tester; The digital pin of the fourth chip to be tested NAND4 is connected to the input and output end of the fourth unit of the tester.