Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a semiconductor structure and a preparation method thereof, and the preparation method comprises the steps: providing a substrate; a plurality of first grooves positioned in the first region and a plurality of second grooves positioned in the second region are formed in the substrate; forming a rewiring layer which covers the first groove, naturally extends to the surface of the substrate and forms a first opening, and covers the second groove, naturally extends to the surface of the substrate and forms a second opening; wherein the area proportion of the first opening in the first region is greater than the area proportion of the second opening in the second region; a first dielectric layer is formed, the first dielectric layer covers the rewiring layer, and the first dielectric layer fills the first opening and the second opening; nitriding the first dielectric layer so that the first dielectric layer with a partial thickness is converted into a nitride layer; forming a second dielectric layer on the surface of the nitride layer; and photoetching the second dielectric layer and the first dielectric layer to expose part of the surface of the rewiring layer in the first region.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the semiconductor field, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the rapid development of various electronic devices (e.g., transistors, diodes, resistors, capacitors, etc.), the semiconductor industry that constitutes electronic devices has also developed rapidly. The production process of semiconductors generally includes processes such as wafer manufacturing, wafer acceptance testing, chip packaging, and post-packaging testing.

[0003] In the chip packaging process, the chip's solder joint (I / O pad) position can be changed through a metal wiring process or a bump process. Generally, the chip's solder joint position can be changed by forming a redistribution layer (RDL) so that the chip can be electrically connected to different packaging substrates or other chips.

[0004] However, when the wafer is subjected to wafer acceptance testing through a test probe, in the process of etching the film layer located in the redistribution layer to expose part of the redistribution layer for testing, due to the different morphologies of the film layers in different areas of the wafer, the equipment cannot be aligned properly, thus causing problems. Summary of the invention

[0005] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least helpful in avoiding the problem of equipment stopping due to height differences between a process area and a storage area.

[0006] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising: providing a substrate, the substrate having a first region and a second region; the substrate having a plurality of first grooves and a plurality of second grooves, the plurality of first grooves being located in the first region, and the plurality of second grooves being located in the second region; forming a redistribution layer, the redistribution layer covering the first grooves and naturally extending to the surface of the substrate and forming a first opening, the redistribution layer covering the second grooves and naturally extending to the surface of the substrate and forming a second opening; wherein the area ratio of the first opening in the first region is greater than the area ratio of the second opening in the second region; forming a first dielectric layer, the first dielectric layer covering the redistribution layer, and the first dielectric layer filling the first opening and the second opening; performing a nitridation treatment on the first dielectric layer to convert a portion of the thickness of the first dielectric layer into a nitride layer; forming a second dielectric layer, the second dielectric layer being located on the surface of the nitride layer; performing photolithography on the second dielectric layer and the first dielectric layer to expose a portion of the surface of the redistribution layer located in the first region.

[0007] In some embodiments, forming the first dielectric layer includes: forming a dielectric film, the dielectric film covering the redistribution layer and filling the first opening and the second opening, wherein a top surface of the dielectric film located in the first region is lower than a top surface of the dielectric film located in the second region; performing a first planarization process on the dielectric film to make the dielectric film flush with a top surface away from the substrate, and the remaining dielectric film serves as the first dielectric layer.

[0008] In some embodiments, after the nitridation treatment and before forming the second dielectric layer, the method further includes: performing a second planarization treatment on the nitride layer.

[0009] In some embodiments, the thickness of the second dielectric layer is less than the thickness of the nitride layer after the second planarization process.

[0010] In some embodiments, the nitridation process includes a gas nitridation process, a liquid nitridation process, and a plasma nitridation process.

[0011] In some embodiments, a material of the second dielectric layer includes titanium nitride or tantalum nitride.

[0012] In some embodiments, nitriding the first dielectric layer includes: performing nitridation on the first dielectric layer at least once to convert a portion of the thickness of the first dielectric layer into at least one nitride layer, wherein the nitrogen content in the at least one nitride layer increases gradually in a direction away from the substrate.

[0013] The second dielectric layer and the first dielectric layer are subjected to photolithography, including: forming a photoresist layer, the photoresist layer being located on the surface of the second dielectric layer; exposing and developing the photoresist layer to form a pattern on the first area; and etching the second dielectric layer and the first dielectric layer along the pattern to expose a portion of the redistribution layer as a test pad or a connection pad.

[0014] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a semiconductor structure, including: a substrate, the substrate having a first region and a second region; the substrate having a plurality of first grooves and a plurality of second grooves, the plurality of first grooves being located in the first region, and the plurality of second grooves being located in the second region; a redistribution layer, the redistribution layer covering the first grooves and naturally extending to the surface of the substrate and forming a first opening, the redistribution layer covering the second grooves and naturally extending to the surface of the substrate and forming a second opening; wherein the area ratio of the first opening in the first region is greater than the area ratio of the second opening in the second region; a first dielectric layer, the first dielectric layer being located on the surface of the substrate, the first dielectric layer being located on a portion of the top surface and side surfaces of the redistribution layer, and the first dielectric layer being flush with the top surface away from the substrate; a nitride layer being provided on a side of the first dielectric layer away from the substrate; a second dielectric layer, the second dielectric layer being located on the surface of the nitride layer; a polymer layer, the polymer layer being located on the surface of the second dielectric layer and on the surface of the redistribution layer not covered by the first dielectric layer.

[0015] In some embodiments, the material of the second dielectric layer includes titanium nitride or tantalum nitride; and the thickness of the second dielectric layer ranges from 20 nm to 50 nm.

[0016] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0017] In the technical solution provided by the embodiment of the present disclosure, the embodiment of the present disclosure performs nitridation treatment on the first dielectric layer so that part of the first dielectric layer is converted into a nitride layer. The nitride layer itself can have a certain isolation effect on the laser, thereby blocking the detection light, and then the detection light cannot pass through the nitride layer to detect the redistribution layer, the first opening and the second opening located below the nitride layer, thereby ensuring that there will be no problems with the entire process, and then the production line can continue. In addition, a second dielectric layer is formed, and the second dielectric layer is used to prevent reflection detection back lines, and it can also ensure that the detection light cannot pass through the nitride layer to detect the redistribution layer, the first opening and the second opening located below the nitride layer, thereby allowing the device to operate normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 is a schematic structural diagram of a semiconductor structure;

[0020] Figure 2 A flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0021] Figure 3 to Figure 11 A schematic diagram of the structure of a semiconductor structure corresponding to each step in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] As known from the background art, in the current method for manufacturing a semiconductor structure, there is a problem that the equipment stops due to the height difference between the process area and the storage area.

[0023] Analysis found that one of the reasons for the equipment stopping due to the height difference between the process area and the storage area was that: Figure 1 A schematic diagram of a semiconductor structure. Figure 1 The semiconductor structure has a first region 11 and a second region 12, wherein the first opening 111 located in the first region 11 accounts for a larger area of ​​the first region 11 than the second opening 112 located in the second region 12, the overall total size of the first opening 111 is larger, and the overall total size of the second opening 112 is smaller, and then in the process of forming the photoresist layer 104, the second opening 112 can be filled with the photoresist layer 104, and the surface of the photoresist layer 104 located on the second opening 112 is basically flush with the surface of the photoresist layer 104 located in the redistribution layer 110, but after the first opening 111 is filled with the photoresist layer 104, the photoresist layer 104 located in the first opening 111 is not flush with the photoresist layer 104 located in the redistribution layer 110, thereby forming an uneven surface and the overall thickness of the photoresist layer 104 located in the first region 11 is lower than the thickness of the photoresist layer 104 located in the second region 12. In the subsequent photolithography process, the process proceeds to the step of automatically aligning the semiconductor structure with the notch or flat through the laser. Since the overall thickness of the photoresist layer 104 in the first area 11 is lower than the thickness of the photoresist layer 104 in the second area 12 and the laser hits the redistribution layer 110 and the first opening 111 respectively, the surface of the semiconductor structure sensed by the laser has a height difference and unevenness. The machine automatically identifies that there is a problem in the process of the semiconductor structure, thereby stopping the process and the production line, resulting in an increase in preparation costs and a series of problems.

[0024] The disclosed embodiment provides a semiconductor structure and a method for preparing the same, wherein in the preparation method, a first dielectric layer is first formed, the first dielectric layer fills the first opening and the second opening, and then the first dielectric layer is nitrided to convert part of the first dielectric layer into a nitride layer. The nitride layer itself can have a certain isolation effect on the laser, thereby blocking the detection light, and the detection light cannot pass through the nitride layer to detect the redistribution layer, the first opening, and the second opening below the nitride layer, thereby ensuring that there will be no problems with the entire process, and the production line can continue. In addition, a second dielectric layer is formed, and the second dielectric layer is used to prevent reflection detection of the reverse line, and can also ensure that the detection light cannot pass through the nitride layer to detect the redistribution layer, the first opening, and the second opening below the nitride layer, thereby allowing the device to operate normally.

[0025] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0026] Figure 2 A flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure; Figure 3 to Figure 11 A schematic diagram of the structure of a semiconductor structure corresponding to each step in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure.

[0027] refer to Figure 2 According to some embodiments of the present disclosure, the present disclosure provides a method for preparing a semiconductor structure, including:

[0028] refer to Figure 3 , S10, providing a substrate 10, the substrate 10 having a first area 11 and a second area 12; the substrate 10 has a plurality of first grooves 105 and a plurality of second grooves 106, the plurality of first grooves 105 are located in the first area 11, and the plurality of second grooves 106 are located in the second area 12.

[0029] The semiconductor structure includes a storage area and a cutting area. The storage area and the cutting area have specific circuits composed of various semiconductor devices, such as transistors, resistors, and triodes. The cutting area is used for subsequent cutting to be divided into individual chips. The semiconductor devices in the storage area have the same structure as the semiconductor devices in the cutting area. The semiconductor devices in the cutting area can be subjected to WAT testing to simulate and characterize the performance of the semiconductor devices in the storage area, which is beneficial to improving the yield of the wafer. Exemplarily, the semiconductor structure provided in the embodiment of the present disclosure can be a semiconductor structure formed in the cutting area and the storage area. Among them, the cutting area includes a process area and a test area. The first area 11 is a storage area, and the second area 12 is a process area. Therefore, various types of semiconductor devices are formed in the substrate 10.

[0030] It can be understood that, in order to describe the positional relationship between the pads 102 and the redistribution layer 110 , one of the pads 101 is partially enlarged, and the pads 102 are actually distributed at intervals, and each pad 102 has the same structure.

[0031] In some embodiments, the substrate 10 may be a laminated structure, and the substrate 10 may have electrical devices such as transistors, resistors, or capacitors, and the pads 102 may be electrically connected to the ports of the electrical devices through a variety of conductive structures (not shown in the figure) to apply a working voltage / current and derive a test voltage / current. The material of the pads 102 may be aluminum, tungsten, and copper. Aluminum, tungsten, and copper have relatively low resistance, which is beneficial to improving the conductive properties of the pads 102, thereby improving the conductive properties of the pads 102 and the subsequent redistribution layer.

[0032] In some embodiments, the base 10 includes a stacked substrate 100 and a first passivation layer 101, the pad 102 is located on the substrate 100, the first passivation layer 101 covers the surface of the pad 102, and the top surface of the first passivation layer 101 is higher than the top surface of the pad 102. The first passivation layer 101 serves as an interlayer dielectric layer (ILD) of the redistribution layer. The first passivation layer 101 is used to isolate some components located on the substrate 100 from the redistribution layer and as a support layer for the redistribution layer to prevent interference between circuits and short circuits of current. At the same time, it is also used to improve the mechanical strength and stability of the semiconductor structure and ensure the long-term reliability of the semiconductor structure.

[0033] In some embodiments, the material of the first passivation layer 101 is an insulating material, such as silicon oxide, silicon nitride or silicon carbide.

[0034] In some embodiments, a plurality of first grooves 105 and a plurality of second grooves 106 are located in the first passivation layer. The bottom of each first groove 105 located in the first region 11 exposes the pad 102 located in the first region 11, and the bottom of each second groove 106 located in the second region 12 exposes the pad 102 located in the second region 12, thereby ensuring that the redistribution layer 110 can be in electrical contact with the pad 102.

[0035] refer to Figure 4 , S20, forming a redistribution layer 110, the redistribution layer 110 covers the first groove 105 and naturally extends to the surface of the substrate 10 and forms a first opening 111, the redistribution layer 110 covers the second groove 106 and naturally extends to the surface of the substrate 10 and forms a second opening 112; wherein the area proportion of the first opening 111 in the first zone 11 is greater than the area proportion of the second opening 112 in the second zone 12.

[0036] In some embodiments, the material of the redistribution layer 110 includes any one or more of aluminum, titanium, or titanium nitride.

[0037] In some embodiments, the thickness of the redistribution layer 110 formed at the bottom of the first groove 105 is greater than 1 um. The thickness range of the redistribution layer 110 can ensure that the cross-sectional area of ​​the redistribution layer 110 is large, reduce the square resistance of the redistribution layer 110, and help reduce the total output loss of the semiconductor structure. The thickness range of the redistribution layer 110 can also ensure that the redistribution layer 110 is sufficient to withstand the stress generated by the test equipment detecting the redistribution layer 110 in the post-packaging test process, or the stress generated in the bonding process between the pad and the packaging substrate or between the pads in the chip packaging process, which helps to avoid stress damage to the semiconductor structure.

[0038] The fact that the area ratio of the first openings 111 in the first region 11 is greater than the area ratio of the second openings 112 in the second region 12 means that, in the same area, the number of the first openings 111 is greater than the number of the second openings 112, and the shape and depth of the first openings 111 are the same as the shape and depth of the second openings 112. In other words, the fact that the area ratio of the first openings 111 in the first region 11 is greater than the area ratio of the second openings 112 in the second region 12 means that the total area ratio of the first openings 111 in the first region 11 is greater than the total area ratio of the second openings 112 in the second region 12.

[0039] refer to Figure 4First, a continuous conductive film is formed on the surface of the first passivation layer 101, in the first grooves 105 and the second grooves 106, and the conductive film fills the first grooves 105 and the second grooves 106. The conductive film is patterned to form a third groove, a fourth groove, a first opening 111 and a second opening 112. The first opening 111 and the third groove are located in the first area 11, and the bottom of the third groove exposes the first passivation layer 101. The second opening 112 and the fourth groove are located in the second area 12, and the bottom of the fourth groove exposes the first passivation layer 101. The remaining conductive films serve as redistribution layers 110.

[0040] It is worth noting that the position of the first opening 111 overlaps with the position of the first groove 105, the position of the third groove does not overlap with the position of the first groove 105, the position of the second opening 112 overlaps with the position of the second groove 106, and the position of the fourth groove does not overlap with the position of the second groove 106.

[0041] In some embodiments, the process of forming the conductive film may be any one of a chemical deposition process, a physical deposition process or an electroplating process. The method of patterning the conductive film may be one of a dry etching process and a wet etching process.

[0042] Continue to refer Figure 4 , forming a second passivation layer 103, the second passivation layer 103 covers the surface of the redistribution layer 110, the surface of the first passivation layer 101 not covered by the redistribution layer 110, the inner wall surface and bottom of the first opening 111, the inner wall surface and bottom of the first opening 111, and the inner wall surface and bottom of the second opening 112.

[0043] In some embodiments, the second passivation layer 103 is used to protect the redistribution layer 110 to prevent the redistribution layer 110 from being damaged by etching and corrosion caused by water vapor in subsequent processes.

[0044] In some embodiments, the material of the second passivation layer 103 is silicon nitride, silicon carbide or silicon oxynitride.

[0045] In some embodiments, the second passivation layer 103 may be formed by a spin coating process or a thin film deposition process. The spin coating process or the thin film deposition process has good step coverage capability, so that the second passivation layer 103 can be evenly covered on the surface of the redistribution layer 110 with a height difference.

[0046] refer to Figure 4 as well as Figure 5 , S30 , forming a first dielectric layer 121 , wherein the first dielectric layer 121 covers the redistribution layer 110 , and the first dielectric layer 121 fills the first opening 111 and the second opening 112 .

[0047] In some embodiments, the material of the first dielectric layer 121 includes silicon oxide.

[0048] refer to Figure 4 , forming a dielectric film 107 , the dielectric film 107 covers the redistribution layer 110 and fills the first opening 111 and the second opening 112 , wherein a top surface of the dielectric film 107 located in the first area 11 is lower than a top surface of the dielectric film 107 located in the second area 12 .

[0049] refer to Figure 5 , the dielectric film is subjected to a first planarization treatment so that the dielectric film is flush with the top surface away from the substrate, and the remaining dielectric film is used as the first dielectric layer 121. The dielectric film is subjected to a first planarization treatment so that the first dielectric layer 121 is flush with the surface away from the substrate, thereby ensuring that the nitride layer 113 and the second dielectric layer 122 subsequently formed on the first dielectric layer 121 are also flush, thereby reducing the influence of the different area proportions of the first opening 111 in the first area 11 and the second opening 112 in the second area 12 on the detection light, so that the detection light can ignore the different concave and convex and height differences.

[0050] In some embodiments, the first planarization process includes chemical mechanical polishing (CMP).

[0051] refer to Figure 5 S40, nitriding the first dielectric layer 121 so that a portion of the first dielectric layer 121 is converted into a nitride layer 113. The nitride layer 113 itself can have a certain isolation effect on the laser, thereby blocking the detection light, and the detection light cannot pass through the nitride layer 113 to detect the redistribution layer 110, the first opening 111 and the second opening 112 located below the nitride layer 113, thereby ensuring that there will be no problems in the entire process, and the production line can continue.

[0052] In some embodiments, the nitridation process includes a gas nitridation process, a liquid nitridation process, and a plasma nitridation process (Remote Plasma Nitridation, RPN for short).

[0053] In some embodiments, plasma nitridation treatment is used to form the nitride layer 113, and the process parameters of the plasma nitridation treatment include: microwave power 1500~2500W, pressure 20~40Pa, N2 flow rate 150~400sccm, Ar (as carrier gas) flow rate 500~1500sccm, temperature 300~600℃.

[0054] The use of RPN to form the nitride layer 113 can reduce the reaction temperature of the entire reaction, thereby avoiding thermal damage to the semiconductor structure during high heat treatment. In addition, since plasma nitridation is carried out in a vacuum, an oxidation-free processing surface can be obtained without damaging the surface finish of the processed first dielectric layer 121. Moreover, since the treatment is carried out at a low temperature, the deformation of the processed workpiece is extremely small, ensuring the flatness of the first dielectric layer 121 itself.

[0055] In some embodiments, performing nitridation on the first dielectric layer 121 includes: performing at least one nitridation on the first dielectric layer 121 to convert a portion of the first dielectric layer 121 into at least one nitride layer 113, wherein the nitrogen content of the at least one nitride layer 113 increases in a direction away from the substrate. Thus, after at least one nitridation, the nitrogen content of the nitride layer 113 away from the substrate in the at least one nitride layer 113 is the largest, the adhesion between the second dielectric layer formed subsequently and the nitride layer 113 is good, the dielectric constant of the first dielectric layer 121 is less than the dielectric constant of the nitride layer 113, and the parasitic capacitance between adjacent redistribution layers 110 and another redistribution layer 110 is small.

[0056] In some embodiments, after the nitridation treatment, the process further includes: performing a second planarization treatment on the nitride layer 113. The second planarization treatment is used to remove damage on the surface of the nitride layer 113 and improve the contact performance between the nitride layer 113 and the second dielectric layer formed subsequently.

[0057] In some embodiments, the second planarization process includes chemical mechanical polishing.

[0058] refer to Figure 7 , S50, forming a second dielectric layer 122, wherein the second dielectric layer 122 is located on the surface of the nitride layer 113.

[0059] In some embodiments, the second dielectric layer 122 includes a metal nitride layer. The metal nitride layer generally has a high refractive index, so that the laser can be reflected back. That is to say, the detection light will not penetrate the second dielectric layer 122 and detect the film layer structure below the second dielectric layer 122. Therefore, the detection light of the subsequent photolithography process cannot detect the film layer structure and the depression below the second dielectric layer 122, thereby avoiding the possibility that the detection light thinks that there is a problem with the process and then stops automatically.

[0060] In addition, reference Figure 8, the material of the second dielectric layer 122 includes a metal nitride layer, and the second dielectric layer 122 is located on the surface of the nitride layer 113. At the interface between the second dielectric layer 122 and the nitride layer 113, the metal element and the nitrogen element are bonded due to the interaction force, thereby improving the adhesion between the second dielectric layer 122 and the nitride layer 113, and improving the contact performance between the nitride layer 113 and the second dielectric layer 122. The embodiment of the present disclosure is described by taking the second dielectric layer 122 as titanium nitride and the metal element as titanium as an example.

[0061] In some embodiments, the material of the second dielectric layer 122 includes titanium nitride or tantalum nitride.

[0062] In some embodiments, the thickness of the second dielectric layer 122 is less than the thickness of the nitride layer 113 after the second planarization process. A thicker second dielectric layer 122 has a higher preparation cost and increases the thickness of the entire semiconductor structure.

[0063] In some embodiments, the thickness of the second dielectric layer 122 ranges from 20 nm to 50 nm. The thickness of the second dielectric layer 122 ranges from 20 nm to 26 nm, 26 nm to 31 nm, 31 nm to 35 nm, 35 nm to 39 nm, 39 nm to 42 nm, 42 nm to 46 nm, or 46 nm to 50 nm. The thickness of the second dielectric layer 122 is within any of the above ranges, which can ensure that the thickness of the second dielectric layer 122 is sufficient to refract the detection light, thereby preventing the aligned detection light from penetrating the second dielectric layer 122. The thickness of the second dielectric layer 122 should not be too large, so as to be incompatible with existing semiconductor devices, resulting in an increase in manufacturing costs.

[0064] It can be understood that since the second dielectric layer 122 itself is conductive, the second dielectric layer 122 will be patterned subsequently to form a fifth groove, exposing a portion of the top surface of the redistribution layer 110 as a test pad. Therefore, there is at least one film layer (second passivation layer, first dielectric layer 121 or nitride layer 113) between the second dielectric layer 122 and the redistribution layer 110 to ensure that there is no short circuit between adjacent redistribution layers 110.

[0065] refer to Fig. 9 , S60 , performing photolithography on the second dielectric layer 122 and the first dielectric layer 121 to expose a portion of the surface of the redistribution layer 110 located in the first region 11 .

[0066] refer to Fig. 9 , performing photolithography on the second dielectric layer 122 and the first dielectric layer 121 , including: forming a photoresist layer 104 , wherein the photoresist layer 104 is located on the surface of the second dielectric layer 122 .

[0067] In some embodiments, a coating process is used to form the photoresist layer 104. The main components of the photoresist layer 104 are a polymer (resin), a sensitizer and a solvent. The polymer changes its structure when irradiated, the solvent enables it to be spun and form a film on the sample surface, and the sensitizer controls the chemical reaction of the polymer phase.

[0068] Continue to refer Fig. 9 , perform photolithography alignment technology to ensure the alignment between the mask and the existing pattern on the silicon wafer, and prevent pattern errors between the mask and the semiconductor structure, which may cause problems such as pattern deformation and inaccurate feature size.

[0069] refer to Fig.10 , the photoresist layer is exposed and developed to form a pattern on the first area 11; the second dielectric layer 122 and the first dielectric layer 121 are etched along the pattern to expose a portion of the redistribution layer 110 as a test pad or a connection pad, and a fifth groove 108 is formed, and a portion of the redistribution layer 110 is exposed at the bottom of the fifth groove 108 as a test pad or a connection pad.

[0070] refer to Fig.11 , a polymer layer 109 is formed. The polymer layer 109 fills the fifth groove and is located on the second dielectric layer 122 .

[0071] The polymer layer 109 is used to form a re-layout pad to meet the requirements of the new pad for the solder ball spacing; the polymer layer 109 can be used as a stress buffer medium in the packaging process. The material of the polymer layer 109 can be biphenyl cycloethylene (BCB) or polyimide (PI), resin. The polymer layer 109 can be a single layer or a stacked structure. For example, the polymer layer 109 can include a stacked first polymer layer and a second polymer layer. The first polymer layer strengthens the passivation layer of the semiconductor structure (which can be the first passivation layer 101, the first dielectric layer 121 and the second dielectric layer 122 in the substrate) and plays a role in stress buffering; the second polymer layer is used to flatten the surface of the semiconductor structure and protect the redistribution layer 110.

[0072] In the method for preparing the semiconductor structure provided by the embodiment of the present disclosure, the first dielectric layer 121 is subjected to nitridation treatment so that part of the first dielectric layer 121 is converted into a nitride layer 113. The nitride layer 113 itself can have a certain isolation effect on the laser, thereby blocking the detection light, and the detection light cannot pass through the nitride layer 113 to detect the redistribution layer 110, the first opening 111 and the second opening 112 located below the nitride layer 113, thereby ensuring that there will be no problems in the entire process, and the production line can continue. In addition, the second dielectric layer 122 is formed, and the second dielectric layer 122 is used to prevent reflection detection back lines, and can also ensure that the detection light cannot pass through the nitride layer 113 to detect the redistribution layer 110, the first opening 111 and the second opening 112 located below the nitride layer, thereby allowing the device to operate normally.

[0073] Accordingly, according to some embodiments of the present disclosure, the embodiments of the present disclosure also provide a semiconductor structure, which can be prepared using the preparation method provided by the above embodiments. The technical features that are the same as or corresponding to the above embodiments will not be elaborated here.

[0074] refer to Fig.11 The semiconductor structure includes: a substrate 10, the substrate 10 has a first area 11 and a second area 12; the substrate 10 has a plurality of first grooves 105 and a plurality of second grooves 106, the plurality of first grooves 105 are located in the first area 11, and the plurality of second grooves 106 are located in the second area 12; a redistribution layer 110, the redistribution layer 110 covers the first grooves 105 and naturally extends to the surface of the substrate 10 and forms a first opening 111, the redistribution layer 110 covers the second grooves 106 and naturally extends to the surface of the substrate 10 and forms a second opening 112; wherein the first opening 111 accounts for a large area of ​​the first area 11 The area ratio of the second opening 112 in the second zone 12; the first dielectric layer 121, the first dielectric layer 121 is located on the surface of the substrate 10, the first dielectric layer 121 is located on a portion of the top surface and the side surface of the redistribution layer 110, and the first dielectric layer 121 is flush with the top surface away from the substrate 10; the first dielectric layer 121 has a nitride layer 113 on the side away from the substrate 10; the second dielectric layer 122, the second dielectric layer 122 is located on the surface of the nitride layer 113; the polymer layer 109, the polymer layer 109 is located on the surface of the second dielectric layer 122 and the surface of the redistribution layer 110 not covered by the first dielectric layer 121.

[0075] In some embodiments, the first area 11 is a storage area, and the second area 12 is a process area. The base 10 includes a stacked substrate 100 and a first passivation layer 101. The base 10 has a pad 102, and the pad 102 is located on the substrate 100. The first passivation layer 101 covers the surface of the pad 102, and the top surface of the first passivation layer 101 is higher than the top surface of the pad 102.

[0076] In some embodiments, a plurality of first grooves 105 and a plurality of second grooves 106 are located in the first passivation layer. The bottom of each first groove 105 located in the first region 11 exposes the pad 102 located in the first region 11, and the bottom of each second groove 106 located in the second region 12 exposes the pad 102 located in the second region 12, and the redistribution layer 110 is in electrical contact with the pad 102.

[0077] In some embodiments, the material of the redistribution layer 110 includes any one or more of aluminum, titanium, or titanium nitride.

[0078] In some embodiments, the thickness of the redistribution layer 110 formed at the bottom of the first groove 105 is greater than 1 um, and the thickness of the redistribution layer 110 at the bottom of the second groove 106 is greater than 1 um.

[0079] In some embodiments, the material of the redistribution layer 110 includes any one or more of aluminum, titanium, or titanium nitride.

[0080] In some embodiments, the material of the first dielectric layer 121 includes silicon oxide.

[0081] In some embodiments, the semiconductor structure includes at least one nitride layer 113 , wherein the nitrogen content in the at least one nitride layer 113 increases gradually in a direction away from the substrate.

[0082] In some embodiments, the second dielectric layer 122 includes a metal nitride layer. The material of the second dielectric layer 122 includes titanium nitride or tantalum nitride. The thickness of the second dielectric layer 122 ranges from 20 nm to 50 nm. The thickness of the second dielectric layer 122 ranges from 20 nm to 26 nm, 26 nm to 31 nm, 31 nm to 35 nm, 35 nm to 39 nm, 39 nm to 42 nm, 42 nm to 46 nm, or 46 nm to 50 nm.

[0083] The material of the polymer layer 109 may be biphenyl cycloethylene (BCB) or polyimide (PI), resin. The polymer layer 109 may be a single layer or a stacked structure, for example, the polymer layer 109 may include a stacked first polymer layer and a second polymer layer, the first polymer layer strengthens the passivation layer of the semiconductor structure (which may be the first passivation layer 101, the first dielectric layer 121 and the second dielectric layer 122 in the substrate), and plays a role in stress buffering; the second polymer layer is used to flatten the surface of the semiconductor structure and protect the redistribution layer 110.

[0084] In some embodiments, the semiconductor structure further includes a second passivation layer 103 , and the second passivation layer 103 is located between the redistribution layer 110 and the first dielectric layer 121 .

[0085] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate having a first region and a second region; The substrate has a plurality of first grooves and a plurality of second grooves, wherein the plurality of first grooves are located in the first area, and the plurality of second grooves are located in the second area; Forming a redistribution layer, the redistribution layer covers the first groove and naturally extends to the substrate surface to form a first opening, the redistribution layer covers the second groove and naturally extends to the substrate surface to form a second opening; wherein the area ratio of the first opening in the first region is greater than the area ratio of the second opening in the second region; forming a first dielectric layer, the first dielectric layer covers the redistribution layer, and the first dielectric layer fills the first opening and the second opening; Performing a nitridation treatment on the first dielectric layer so that a portion of the thickness of the first dielectric layer is converted into a nitride layer; forming a second dielectric layer, wherein the second dielectric layer is located on a surface of the nitride layer; Photolithography is performed on the second dielectric layer and the first dielectric layer to expose a portion of the surface of the redistribution layer located in the first region.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: Forming the first dielectric layer includes: forming a dielectric film, the dielectric film covers the redistribution layer and fills the first opening and the second opening, wherein: A top surface of the dielectric film located in the first region is lower than a top surface of the dielectric film located in the second region; The dielectric film is subjected to a first planarization process to make the dielectric film flush with a top surface away from the substrate, and the remaining dielectric film serves as a first dielectric layer.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: After the nitridation treatment and before forming the second dielectric layer, the method further includes: performing a second planarization treatment on the nitride layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The thickness of the second dielectric layer is smaller than the thickness of the nitride layer after the second planarization process.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: The nitridation treatment includes gas nitridation treatment, liquid nitridation treatment and plasma nitridation treatment.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The material of the second dielectric layer includes titanium nitride or tantalum nitride.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that: Performing nitridation treatment on the first dielectric layer includes: The first dielectric layer is subjected to at least one nitridation treatment so that a portion of the first dielectric layer is converted into at least one nitride layer, wherein the nitrogen content in the at least one nitride layer increases gradually in a direction away from the substrate.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: Performing photolithography on the second dielectric layer and the first dielectric layer, comprising: forming a photoresist layer, wherein the photoresist layer is located on the surface of the second dielectric layer; exposing and developing the photoresist layer to form a pattern on the first region; The second dielectric layer and the first dielectric layer are etched along the pattern to expose a portion of the redistribution layer as a test pad or a connection pad.

9. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate has a first area and a second area; the substrate has a plurality of first grooves and a plurality of second grooves, wherein the plurality of first grooves are located in the first area, and the plurality of second grooves are located in the second area; A redistribution layer, the redistribution layer covers the first groove and naturally extends to the surface of the substrate to form a first opening, the redistribution layer covers the second groove and naturally extends to the surface of the substrate to form a second opening; wherein the area proportion of the first opening in the first region is greater than the area proportion of the second opening in the second region; A first dielectric layer, the first dielectric layer is located on the surface of the substrate, the first dielectric layer is located on a portion of the top surface and the side surface of the redistribution layer, the first dielectric layer is flush with the top surface away from the substrate; the first dielectric layer has a nitride layer on a side away from the substrate; a second dielectric layer, wherein the second dielectric layer is located on a surface of the nitride layer; A polymer layer is located on a surface of the second dielectric layer and a surface of the redistribution layer not covered by the first dielectric layer.

10. The semiconductor structure according to claim 9, characterized in that: The material of the second dielectric layer includes titanium nitride or tantalum nitride; the thickness of the second dielectric layer ranges from 20 nm to 50 nm.

Images