Method and structure for stacking and interconnecting multiple layers of substrates in ceramic SIP (Session Initiation Protocol) package

Abstract

The invention discloses a method and a structure for stacking and interconnecting multiple layers of substrates in a ceramic SIP (Session Initiation Protocol) package. The method comprises the following steps of: connecting a first layer of substrate with an integrated ceramic tube shell in a welding mode or a bonding mode; carrying out bare chip pasting and bonding on the ceramic tube shell welded with the first layer of substrate; ball mounting is carried out on the second-layer substrate through BGA solder balls, then the top of the first-layer substrate is coated with soldering paste, a passive device bonding pad of the second-layer substrate is coated with the soldering paste, a passive device is placed on the second-layer substrate, and then integrated welding is carried out; carrying out bare chip pasting and bonding on the ceramic tube shell welded with the second layer of substrate; and sealing the integrated ceramic tube shell and the airtight packaging cover plate through a parallel seam welding process, and carrying out BGA ball mounting at the bottom of the sealed ceramic tube shell to obtain the SIP module. According to the invention, the requirements of high integration level and high reliability based on the integrated ceramic tube shell can be met, the process implementation difficulty of SIP packaging based on the ceramic tube shell is remarkably reduced, and the reliability and success rate of SIP packaging are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of microelectronic packaging, and in particular relates to a method and structure for stacking and interconnecting multiple layers of substrates in a ceramic SIP package. Background Art

[0002] Three-dimensional vertical interconnection technology is a key technology for realizing lightweight miniaturization and high-density integration of electronic information systems. Microsystems based on ceramic packaging have high reliability, high flexibility and good electrical and thermal performance. For the package shell with integrated design of ceramic substrate and frame, it has the advantages of more integrated chips, high reliability, high assembly density and good sealing performance. At present, researchers at home and abroad have studied the integrated architecture and method based on ceramic substrate. Among them, CN108428672B discloses a ceramic double-sided three-dimensional integrated architecture of an ultra-wideband radio frequency microsystem, including a ceramic substrate, a metal microframe, a front cover plate, a back cover plate and a BGA solder ball: both sides of the ceramic substrate are provided with cavities for installing chips, the metal microframe is welded on the front of the ceramic substrate, the front cover plate is welded on the metal microframe, the back cover plate is welded on the back cavity of the ceramic substrate, and the back of the ceramic substrate is provided with a BGA solder pad in the area other than the back cover plate, and the BGA solder ball is welded on the back of the ceramic substrate through the BGA solder pad. This patent adopts a multi-layer step bonding design and a bare chip embedded cavity structure. Its design and process are difficult to implement, with a long production cycle, low yield and high cost. Summary of the invention

[0003] The purpose of the present invention is to provide a method and structure for interconnecting a multi-layer substrate stack in a ceramic SIP package, which can achieve high integration and high reliability requirements based on an integrated ceramic shell, significantly reduce the difficulty of implementing the process of SIP packaging based on the ceramic shell, and improve the reliability and success rate of SIP packaging.

[0004] One aspect of the present invention provides a method for stacking and interconnecting multiple layers of substrates in a ceramic SIP package, comprising:

[0005] Step S1, connecting the first substrate and the integrated ceramic shell by welding or bonding;

[0006] Step S2, performing a vapor phase cleaning treatment on the ceramic tube shell after welding the first layer of substrate, performing a pre-chip mounting treatment on the ceramic tube shell using plasma cleaning, and performing bare chip pasting and bonding on the ceramic tube shell after plasma cleaning;

[0007] Step S3, planting balls on the second layer substrate using BGA solder balls, then coating solder paste on the top of the first layer substrate, and coating solder paste on the passive device pads of the second layer substrate and placing passive devices, and then performing integrated soldering;

[0008] Step S4, performing a vapor phase cleaning treatment on the ceramic tube shell after welding the second layer substrate, performing a pre-chip mounting treatment on the ceramic tube shell using plasma cleaning, and performing bare chip pasting and bonding on the ceramic tube shell after plasma cleaning;

[0009] Step S5, sealing the integrated ceramic tube shell and the airtight packaging cover plate by a parallel seam welding process, performing BGA ball planting on the bottom of the sealed ceramic tube shell to obtain a SIP module, and cleaning the SIP module after the BGA ball planting.

[0010] Preferably, in step S1, the welding methods include soldering and BGA solder ball welding, and the bonding methods include conductive adhesive bonding and nano silver bonding.

[0011] Preferably, in the case of BGA solder ball welding, the first layer of the substrate is firstly implanted with BGA solder balls, and then solder paste is coated on the bottom of the integrated ceramic tube shell for welding.

[0012] Preferably, the material of the ceramic tube shell is Al2O3, AlN, BeO or Si3N4; the material of the first substrate and the second substrate is a ceramic substrate, an ABF substrate, a BT substrate, an HDI substrate or a multi-layer PCB board.

[0013] Preferably, in step S5, BGA ball planting is performed by using a ball planting method of printed solder paste or a laser ball planting method.

[0014] Another aspect of the present invention provides a multi-layer substrate stacking interconnection structure in a ceramic SIP package, which is manufactured using the above method.

[0015] Preferably, the structure includes BGA solder balls at the bottom of the shell, an integrated ceramic shell, a first-layer substrate and a ceramic shell connection layer, a first-layer substrate, BGA solder balls interconnected between substrates, a second-layer substrate, passive devices, bare chips, bonding wires and an airtight packaging cover.

[0016] Preferably, the structure includes BGA solder balls at the bottom of the shell, an integrated ceramic shell, BGA solder balls interconnecting the substrate and the ceramic shell, a first-layer substrate, BGA solder balls interconnecting between substrates, a second-layer substrate, passive devices, bare chips, bonding wires and an airtight packaging cover.

[0017] Preferably, the first-layer substrate includes, from bottom to top, a bottom wiring layer, a longitudinal transmission wiring structure, and a top wiring layer, the bottom wiring layer is provided with a pad connected to the ceramic tube shell, the top wiring layer is provided with a pad connected to the second-layer substrate and a bare chip, and the bare chip is connected to the top wiring layer through bonding wires.

[0018] Preferably, the second-layer substrate includes, from bottom to top, a bottom wiring layer, a longitudinal transmission wiring structure, and a top wiring layer, wherein the bottom wiring layer is provided with pads connected to the first-layer substrate; the top wiring layer is provided with passive devices and bare chips, wherein the passive devices are connected to the top wiring layer by soldering, and the bare chip is connected to the top wiring layer by bonding wires.

[0019] The multi-layer substrate stacking interconnection method and structure within the ceramic SIP package according to the above aspects of the present invention can achieve high integration and high reliability requirements based on an integrated ceramic shell, significantly reduce the difficulty of implementing the process of SIP packaging based on the ceramic shell, and improve the reliability and success rate of SIP packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings used in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work:

[0021] Figure 1 A flowchart of a method for stacking and interconnecting multiple substrates in a ceramic SIP package according to an embodiment of the present invention;

[0022] Figure 2 A cross-sectional view of a multi-layer substrate stacking interconnection structure in a ceramic SIP package according to a first embodiment of the present invention;

[0023] Figure 3 A cross-sectional view of a multi-layer substrate stacking interconnection structure in a ceramic SIP package according to a second embodiment of the present invention;

[0024] Among them, 1-BGA solder balls at the bottom of the shell; 2-integrated ceramic shell; 3-connecting layer between the first substrate and the ceramic shell; 4-first substrate; 5-BGA solder balls interconnecting the substrate; 6-second substrate; 7-passive devices; 8-bare chips; 9-bonding wires; 10-airtight packaging cover; 11-BGA solder balls interconnecting the substrate and the ceramic shell. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] The embodiment of the present invention provides a method for interconnecting a multi-layer substrate stack in a ceramic SIP package, such as Figure 1 As shown, the method includes steps S1 to S5.

[0027] In step S1, the first substrate is connected to the integrated ceramic shell by welding or bonding, and the connection methods include brazing solder welding, BGA solder ball welding, conductive adhesive bonding, and nanosilver bonding. In one embodiment, the first substrate is welded to the integrated ceramic shell using brazing solder; or the first substrate is first implanted with BGA solder balls, and then solder paste is applied to the bottom of the integrated ceramic shell for welding; welding can be completed by manual welding or reflow oven welding. In this step, an integrated ceramic shell is selected according to the design requirements of the microsystem SIP structure, signal transmission, system function and heat dissipation, wherein the material of the ceramic shell is Al2O3, AlN, BeO or Si3N4; the materials of the first substrate and the second substrate are ceramic substrates, ABF substrates, BT substrates, HDI substrates or multi-layer PCB boards.

[0028] In step S2, the ceramic shell after welding the first layer of substrate is subjected to vapor phase cleaning. At this time, the ceramic shell does not contain a bare chip and can also be cleaned with bromopropane. Plasma cleaning is used to perform pre-chip treatment on the ceramic shell, and bare chips are pasted and bonded to the ceramic shell after plasma cleaning. In one embodiment, argon gas is used for plasma cleaning, the cleaning power is set to 200W, the cleaning time is 60s, and pasting and bonding can be performed by an automatic placement machine and an automatic bonding machine, or by manual placement and bonding.

[0029] In step S3, the second substrate is balled with BGA solder balls, and then solder paste is applied on the top of the first substrate, and solder paste is applied on the passive device pads of the second substrate and passive devices are placed, and then integrated soldering is performed, and the soldering can be completed by manual soldering or reflow oven soldering. In one embodiment, a flip-chip device is used for alignment, and the second substrate with balled balls is placed on the first substrate.

[0030] In step S4, the ceramic shell after welding the second substrate is subjected to gas phase cleaning, plasma cleaning is used to perform chip pretreatment on the ceramic shell, and bare chip pasting and bonding are performed on the shell after plasma cleaning. In one embodiment, the ceramic shell after welding the second substrate is subjected to gas phase cleaning. If it is found that the cleaning is incomplete after gas phase cleaning, multiple gas phase cleanings can be performed. Then plasma cleaning is used to perform chip pretreatment on the ceramic shell, and argon gas is used for plasma cleaning. The cleaning power is set to 200W and the cleaning time is set to 60s. Then, bare chip pasting and bonding are performed on the ceramic shell after plasma cleaning. Pasting and bonding can be performed by automatic placement machine and automatic bonding machine, or manual placement and bonding can be performed.

[0031] In step S5, the ceramic integrated tube shell and the airtight packaging cover are sealed by a parallel seam welding process, and the bottom of the sealed ceramic tube shell is BGA ball-planted to obtain a SIP module. The ball planting method can be a printed solder paste planting method, and the laser ball planting method can also be used. The SIP module after ball planting is cleaned with anhydrous ethanol.

[0032] An embodiment of the present invention further provides a multi-layer substrate stacking interconnection structure in a ceramic SIP package, which is manufactured using the above method.

[0033] like Figure 2 As shown, the multi-layer substrate stacking interconnection structure in the ceramic SIP package of the first embodiment of the present invention includes a BGA solder ball 1 at the bottom of the shell, an integrated ceramic shell 2, a first-layer substrate and ceramic shell connection layer 3, a first-layer substrate 4, BGA solder balls 5 for interconnection between substrates, a second-layer substrate 6, passive devices 7, bare chips 8, bonding leads 9, and an airtight packaging cover 10.

[0034] like Figure 3 As shown, the difference between the multi-layer substrate stacking interconnection structure in the ceramic SIP package of the second embodiment of the present invention and the first embodiment is that the first substrate and ceramic shell connection layer 3 of the first embodiment is replaced by the substrate and ceramic shell interconnection BGA solder ball 11. In the first embodiment, the first substrate and the ceramic shell connection layer 3 are obtained by soldering the first substrate and the integrated ceramic shell with a brazing solder. In the second embodiment, the substrate and the ceramic shell interconnection BGA solder ball 11 is obtained by implanting the first substrate with a BGA solder ball, and then applying solder paste on the bottom of the integrated ceramic shell for soldering.

[0035] The first layer of substrate 4 includes a bottom wiring layer, a longitudinal transmission wiring structure, and a top wiring layer from bottom to top. The bottom wiring layer is provided with a pad connected to the ceramic tube shell; the top wiring layer is provided with a pad connected to the second layer of substrate and a bare chip; the bare chip is connected to the top wiring layer through wire bonding.

[0036] The second layer of substrate 6 includes a bottom wiring layer, a longitudinal transmission wiring structure, and a top wiring layer from bottom to top. The bottom wiring layer is provided with pads connected to the first layer of substrate; the top wiring layer is provided with passive devices and bare chips. The passive devices are connected to the top wiring layer by soldering; the bare chips are connected to the top wiring layer by wire bonding.

[0037] The beneficial effects of the method and structure for interconnecting the multi-layer substrate stacking in a ceramic SIP package according to the embodiment of the present invention include:

[0038] 1. The SIP module designed with an integrated ceramic shell as the basic framework of the present invention can flexibly use the MCM (Multi-Chip Module) process, adopt automated assembly, integrate multi-layer substrates, multiple chips, and multiple passive devices, and realize system-level hermetic packaging;

[0039] 2. The present invention realizes the miniaturization and multi-function of the radio frequency microsystem while performing multi-layer integration and interconnection in the vertical direction to improve the module integration;

[0040] 3. The present invention realizes the application requirements of high integration, high reliability and high heat dissipation based on an integrated ceramic shell and tube through process methods such as substrate welding, substrate ball planting, substrate stacking, integrated welding of passive devices, chip pasting and bonding of multiple assembly planes, etc., significantly reduces the difficulty of implementing the process based on ceramic shell and tube SIP packaging, improves the reliability and success rate of system-level packaging based on ceramic shell and tube, can be flexibly applied in various microsystem designs, and has broad application prospects.

[0041] The above description is only by way of illustration of certain exemplary embodiments of the present invention. It is undoubted that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A method for interconnecting multiple layers of substrates in a ceramic SIP package, characterized in that: include: Step S1, connecting the first substrate and the integrated ceramic shell by welding or bonding; Step S2, performing a vapor phase cleaning treatment on the ceramic tube shell after welding the first layer of substrate, performing a pre-chip mounting treatment on the ceramic tube shell using plasma cleaning, and performing bare chip pasting and bonding on the ceramic tube shell after plasma cleaning; Step S3, planting balls on the second layer substrate using BGA solder balls, then coating solder paste on the top of the first layer substrate, and coating solder paste on the passive device pads of the second layer substrate and placing passive devices, and then performing integrated soldering; Step S4, performing a vapor phase cleaning treatment on the ceramic tube shell after welding the second layer substrate, performing a pre-chip mounting treatment on the ceramic tube shell using plasma cleaning, and performing bare chip pasting and bonding on the ceramic tube shell after plasma cleaning; Step S5, sealing the integrated ceramic tube shell and the airtight packaging cover plate by a parallel seam welding process, performing BGA ball planting on the bottom of the sealed ceramic tube shell to obtain a SIP module, and cleaning the SIP module after the BGA ball planting.

2. The method according to claim 1, characterized in that In step S1 , the welding methods include soldering and BGA solder ball welding, and the bonding methods include conductive adhesive bonding and nano silver bonding.

3. The method according to claim 2, characterized in that In the case of BGA solder ball welding, the first layer of the substrate is firstly implanted with BGA solder balls, and then solder paste is applied to the bottom of the integrated ceramic tube shell for welding.

4. The method according to any one of claims 1 to 3, characterized in that The material of the ceramic tube shell is Al2O3, AlN, BeO or Si3N4; the material of the first substrate and the second substrate is a ceramic substrate, an ABF substrate, a BT substrate, an HDI substrate or a multi-layer PCB board.

5. The method according to any one of claims 1 to 3, characterized in that: In step S5, BGA ball planting is performed by using a ball planting method of printed solder paste or a laser ball planting method.

6. A multi-layer substrate stacking interconnection structure in a ceramic SIP package, characterized in that: The method is prepared by any one of claims 1 to 5.

7. The structure according to claim 6, characterized in that It includes BGA solder balls at the bottom of the tube shell, an integrated ceramic tube shell, a connecting layer between the first substrate and the ceramic tube shell, a first substrate, interconnected BGA solder balls between substrates, a second substrate, passive components, bare chips, bonding wires and a hermetic sealing cover.

8. The structure according to claim 6, characterized in that It includes BGA solder balls at the bottom of the tube shell, an integrated ceramic tube shell, BGA solder balls interconnecting the substrate and the ceramic tube shell, a first-layer substrate, BGA solder balls interconnecting between substrates, a second-layer substrate, passive components, bare chips, bonding leads and a hermetic sealing cover.

9. The structure according to claim 7 or 8, characterized in that: The first-layer substrate includes, from bottom to top, a bottom wiring layer, a longitudinal transmission wiring structure, and a top wiring layer. The bottom wiring layer is provided with a pad connected to the ceramic tube shell. The top wiring layer is provided with a pad connected to the second-layer substrate and a bare chip. The bare chip is connected to the top wiring layer through bonding wires.

10. The structure according to claim 7 or 8, characterized in that: The second-layer substrate includes, from bottom to top, a bottom wiring layer, a longitudinal transmission wiring structure, and a top wiring layer. The bottom wiring layer is provided with a pad connected to the first-layer substrate; the top wiring layer is provided with passive devices and a bare chip. The passive devices are connected to the top wiring layer by soldering solder, and the bare chip is connected to the top wiring layer by bonding wires.

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