Sidewall structure of storage cell and its manufacturing method
By employing a two-stage deposition and etching process to form silicon nitride sidewalls during the manufacturing of memory cells, the problem of silicon oxide erosion on the sidewalls caused by wet etching is solved, thereby improving the reliability and data retention capability of the device.
Patent Information
- Application Number
- CN202411497169.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2025-10-31
- Estimated Expiration
- 2044-10-25
AI Technical Summary
After reducing the doping concentration, the hydrofluoric acid in the wet etching process will erode the silicon oxide on the sidewall of the memory cell, forming voids. This causes the silicon nitride in the interlayer dielectric layer to back-drill into the voids, resulting in bridging of adjacent tungsten contact holes and affecting device reliability.
Silicon nitride sidewalls are formed by two deposition and etching processes, creating a step at the junction of the first oxide layer and the second oxide layer. This reduces the thickness of the first oxide layer near the ion implantation region, lowering the risk of side-penetration caused by wet cleaning, while keeping the thickness of the second oxide layer near the memory cell unchanged.
It effectively prevents side penetration of the sidewall silicon oxide, improves the reliability and data retention capability of the storage cell, and avoids bridging problems between adjacent tungsten contact holes.
Smart Images
Figure CN119447023B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor integrated circuit manufacturing technology, specifically to a sidewall structure of a memory cell and its manufacturing method. Background Technology
[0002] Ion implantation is usually required to form a doped region in the substrate between two adjacent memory cells. By reducing the concentration of the doped region, the problem of the memory cell substrate lifting due to excessive doping concentration can be avoided.
[0003] However, reducing the doping concentration in the doped region allows the hydrofluoric acid used in the subsequent wet etching process to erode the silicon oxide on the sidewalls of the memory cells, creating voids. Silicon nitride from the interlayer dielectric layer then drills back into these voids, causing defects. These defects can easily lead to bridging issues between adjacent tungsten contact holes during the filling process, negatively impacting device reliability. Summary of the Invention
[0004] This application provides a sidewall structure for a storage cell and a method for manufacturing the same, which can solve the problem that the silicon oxide on the sidewall is easily eroded and hollowed out in related technologies.
[0005] To address the technical problems in the background art, the first aspect of this application provides a method for manufacturing a sidewall structure of a storage cell, the method comprising the following steps:
[0006] A semiconductor structure having multiple memory cells is provided, with adjacent memory cells spaced apart.
[0007] A first oxide layer is formed by blanket deposition, which covers the surface of the memory cell and the spacer surface between adjacent memory cells;
[0008] A first silicon nitride layer is formed by blanket deposition, and the first silicon nitride layer covers the surface of the oxide layer;
[0009] Self-aligned etching of the first silicon nitride layer, etching to remove the first silicon nitride layer covering the front side, etching to thin the first oxide layer covering the spacer surface between adjacent memory cells to form a second oxide layer, and retaining the first silicon nitride layer covering the side of the memory cell to form a first silicon nitride sidewall.
[0010] A second silicon nitride layer is formed by blanket deposition, which covers the surface of the first silicon nitride sidewall and the surface of the second oxide layer;
[0011] The second silicon nitride layer is self-aligned and etched to remove the second silicon nitride layer covering the front side, leaving the second silicon nitride layer covering the side of the memory cell to form a second silicon nitride sidewall; a step is formed at the junction between the second oxide layer located under the second silicon nitride sidewall and the first oxide layer located under the first silicon nitride sidewall.
[0012] Optionally, the step of forming a first silicon nitride layer by blanket deposition, wherein the first silicon nitride layer covers the surface of the oxide layer, includes:
[0013] A first silicon nitride layer with a thickness of 200 Å to 300 Å is formed by blanket deposition, and the first silicon nitride layer covers the surface of the oxide layer.
[0014] Optionally, the step of forming a second silicon nitride layer by blanket deposition, wherein the second silicon nitride layer covers the surface of the first silicon nitride sidewall and the surface of the second oxide layer, includes:
[0015] A second silicon nitride layer with a thickness of 200 Å to 300 Å is formed by blanket deposition, the second silicon nitride layer covering the surface of the first silicon nitride sidewall and the surface of the second oxide layer.
[0016] Optionally, the step of forming a first oxide layer by blanket deposition, wherein the first oxide layer covers the surface of the memory cell and the spacer surface between adjacent memory cells, includes:
[0017] A first oxide layer with a thickness of 70 Å to 130 Å is formed by blanket deposition, which covers the surface of the memory cell and the spacer surface between adjacent memory cells.
[0018] Optionally, the steps of self-aligned etching of the first silicon nitride layer, etching away the first silicon nitride layer covering the front side, etching to thin the first oxide layer covering the surface of the spacer between adjacent memory cells to form a second oxide layer, and retaining the first silicon nitride layer covering the side of the memory cell to form a first silicon nitride sidewall include:
[0019] Self-aligned etching of the first silicon nitride layer, etching to remove the first silicon nitride layer covering the front side, etching to thin the first oxide layer covering the spacer surface between adjacent memory cells to form a second oxide layer with a thickness of 35 Å to 65 Å, and retaining the first silicon nitride layer covering the side of the memory cell to form a first silicon nitride sidewall.
[0020] To address the technical problems in the background art, a second aspect of this application provides a sidewall structure for a storage cell, the sidewall structure of which includes:
[0021] A semiconductor structure with multiple memory cells is formed, with adjacent memory cells spaced apart.
[0022] A first oxide layer is deposited on the outer periphery of the memory cell;
[0023] A first silicon nitride sidewall covers a first oxide layer on the side of the storage cell, and the first oxide layer under the first silicon nitride sidewall extends to both sides to form a first oxide layer extension portion.
[0024] A second oxide layer extends from the extension portion of the first oxide layer to both sides; the thickness of the second oxide layer is less than the thickness of the first oxide layer.
[0025] The second silicon nitride sidewall covers the outside of the first silicon nitride sidewall on the side of the storage cell, and the second oxide layer is located under the second silicon nitride sidewall.
[0026] Optionally, a step is formed at the junction of the second oxide layer and the first oxide layer.
[0027] The technical solution of this application has at least the following advantages: This application forms silicon nitride sidewalls by two depositions and etchings, so that a step is formed at the junction of the first oxide layer and the second oxide layer, thereby reducing the thickness of the first oxide layer near the ion implantation region and reducing the risk of side-cutting caused by wet cleaning. At the same time, the thickness of the second oxide layer near the storage cell remains unchanged, so it has no impact on the reliability of data retention in the storage cell. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0029] Figure 1 A flowchart illustrating a method for manufacturing the sidewall structure of a storage cell according to an embodiment of this application is shown.
[0030] Figure 2 A schematic diagram of the cross-sectional structure of the device after step S2 is shown;
[0031] Figure 3 A schematic diagram of the cross-sectional structure of the device after step S3 is shown;
[0032] Figure 4 A schematic diagram of the cross-sectional structure of the device after step S4 is shown;
[0033] Figure 5 A schematic diagram of the cross-sectional structure of the device after step S5 is shown;
[0034] Figure 6 A schematic diagram of the cross-sectional structure of the device after step S6 is shown. Detailed Implementation
[0035] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0036] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0037] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0038] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0039] Figure 1 A flowchart illustrating a method for manufacturing the sidewall structure of a storage cell according to an embodiment of this application is shown. Figure 1 As can be seen from this, the manufacturing method of the sidewall structure of this storage cell includes the following steps:
[0040] Step S1: Provide a semiconductor structure having multiple memory cells, with adjacent memory cells spaced apart.
[0041] Step S2: A first oxide layer is formed by blanket deposition, which covers the surface of the memory cell and the spacer surface between adjacent memory cells.
[0042] The first oxide layer covers the surface of the semiconductor structure according to the morphology of the semiconductor structure.
[0043] Figure 2 This diagram shows a cross-sectional view of the device after step S2 is completed. Figure 2 As can be seen, the first oxide layer 110 covers the surface of the memory cell 100 and the spacer surfaces between adjacent memory cells 100, according to the morphology of the semiconductor structure. That is, the first oxide layer 110 covers the upper surface, left side and right side of the memory cell 100, as well as the spacer surfaces between adjacent memory cells 100.
[0044] For example, the thickness of the first oxide layer 110 can be from 70 Å to 130 Å, and preferably, the thickness of the first oxide layer 110 is 100 Å.
[0045] Step S3: A first silicon nitride layer is formed by blanket deposition, which covers the surface of the oxide layer.
[0046] Figure 3 A schematic cross-sectional view of the device after step S3 is shown. Figure 3 As can be seen, the first silicon nitride layer 210 is in accordance with Figure 2 The surface morphology covers the first oxide layer 110.
[0047] For example, when forming the first silicon nitride layer by blanket deposition, the first silicon nitride layer with a thickness of 200 Å to 300 Å is formed by blanket deposition, and the first silicon nitride layer covers the surface of the oxide layer.
[0048] Step S4: Self-aligned etching of the first silicon nitride layer, etching to remove the first silicon nitride layer covering the front side, and etching to thin the first oxide layer covering the spacer surface between adjacent memory cells to form a second oxide layer, while retaining the first silicon nitride layer covering the side of the memory cell to form a first silicon nitride sidewall.
[0049] Figure 4 This diagram shows a cross-sectional view of the device after step S4 is completed. Figure 4 As can be seen, the first oxide layer 110 located on the spacer surface between adjacent storage cells 100 is thinned to form a second oxide layer 120, and a step is formed at the junction of the second oxide layer 120 and the first oxide layer 110.
[0050] For example, the thickness of the second oxide layer 120 can be 35 Å to 65 Å, and preferably, the thickness of the second oxide layer 120 can be 50 Å.
[0051] During the self-aligned etching of the first silicon nitride layer 210 in step S4, the etching rate of the first silicon nitride layer 210 covering the front side is greater than the etching rate of the first silicon nitride layer 210 covering the side side. As a result, after step S4, the first silicon nitride layer 210 covering the front side is completely etched away, and the remaining first silicon nitride layer 210 covering the side of the memory cell 210 forms the first silicon nitride sidewall 211. Below the first silicon nitride sidewall 211 is an extension of the first oxide layer 110, which extends from the lower end of the first oxide layer 110 to both sides.
[0052] Step S5: A second silicon nitride layer is formed by blanket deposition, which covers the surface of the first silicon nitride sidewall and the surface of the second oxide layer.
[0053] Figure 5 This diagram shows a cross-sectional view of the device after step S5. Figure 5 As can be seen, the deposited second silicon nitride layer 220 covers the... Figure 4 The device structure surface shown is the surface of the second silicon nitride layer 220 covering the surface of the first silicon nitride sidewall 221 and the exposed surface of the first oxide layer 110 and the exposed surface of the second oxide layer 120.
[0054] Step S6: Self-aligned etching of the second silicon nitride layer, etching away the second silicon nitride layer covering the front side, retaining the second silicon nitride layer covering the side of the memory cell to form a second silicon nitride sidewall; a thickness step is formed between the second oxide layer located under the second silicon nitride sidewall and the first oxide layer located under the first silicon nitride sidewall.
[0055] In this embodiment, silicon nitride sidewalls are formed by two depositions and etchings, creating a step at the junction of the first oxide layer and the second oxide layer. This reduces the thickness of the first oxide layer near the ion implantation region, lowering the risk of side-penetration caused by wet cleaning. Meanwhile, the thickness of the second oxide layer near the storage cell remains unchanged, so it has no impact on the reliability of data retention in the storage cell.
[0056] Figure 6 This diagram shows a cross-sectional view of the device after step S6. Figure 6As can be seen, during step S6, the etching rate of the second oxide layer 220 covering the front side is greater than the etching rate of the second silicon nitride layer 220 covering the side of the first silicon nitride sidewall 221. As a result, after step S6, the second silicon nitride layer 220 covering the front side is completely etched away, and the remaining second silicon nitride layer 220 covering the side of the first silicon nitride sidewall 221 forms the second silicon nitride sidewall 221. The second oxide layer 120 is located below the second silicon nitride sidewall 221.
[0057] A step is formed at the junction between the second oxide layer 120 and the first oxide layer 110.
[0058] Figure 6 The sidewall structure of a storage cell provided in an embodiment of this application is shown, with reference to... Figure 6 The sidewall structure includes:
[0059] A semiconductor structure having multiple memory cells 100 is formed, with adjacent memory cells 100 spaced apart.
[0060] A first oxide layer 110 is deposited on the outer periphery of the storage cell 100.
[0061] A first silicon nitride sidewall 211 covers a first oxide layer 110 on the side of the storage cell 100, and the first oxide layer 110 under the first silicon nitride sidewall 211 extends to both sides to form a first oxide layer extension.
[0062] The second oxide layer 120 extends to both sides from the extension portion of the first oxide layer 110; the thickness of the second oxide layer 120 is lower than the thickness of the first oxide layer 110.
[0063] The second silicon nitride sidewall 220 covers the outside of the first silicon nitride sidewall 211 on the side of the storage cell 110, and the second oxide layer 120 is located under the second silicon nitride sidewall 221.
[0064] A step is formed at the junction between the second oxide layer 120 and the first oxide layer 110.
[0065] In this embodiment, silicon nitride sidewalls are formed by two depositions and etchings, creating a step at the junction of the first oxide layer and the second oxide layer. This reduces the thickness of the first oxide layer near the ion implantation region, lowering the risk of side-penetration caused by wet cleaning. Meanwhile, the thickness of the second oxide layer near the storage cell remains unchanged, so it has no impact on the reliability of data retention in the storage cell.
[0066] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for manufacturing a sidewall structure of a storage cell, characterized in that, The method for manufacturing the sidewall structure of the storage cell includes the following steps: A semiconductor structure having multiple memory cells is provided, with adjacent memory cells spaced apart. A first oxide layer is formed by blanket deposition, which covers the surface of the memory cell and the spacer surface between adjacent memory cells; A first silicon nitride layer is formed by blanket deposition, and the first silicon nitride layer covers the surface of the oxide layer; Self-aligned etching of the first silicon nitride layer, etching to remove the first silicon nitride layer covering the front side, etching to thin the first oxide layer covering the spacer surface between adjacent memory cells to form a second oxide layer, and retaining the first silicon nitride layer covering the side of the memory cell to form a first silicon nitride sidewall. A second silicon nitride layer is formed by blanket deposition, which covers the surface of the first silicon nitride sidewall and the surface of the second oxide layer; The second silicon nitride layer is self-aligned and etched to remove the second silicon nitride layer covering the front side, leaving the second silicon nitride layer covering the side of the memory cell to form a second silicon nitride sidewall; a step is formed at the junction between the second oxide layer located under the second silicon nitride sidewall and the first oxide layer located under the first silicon nitride sidewall.
2. The method for manufacturing the sidewall structure of the storage cell as described in claim 1, characterized in that, The step of forming a first silicon nitride layer by blanket deposition, wherein the first silicon nitride layer covers the surface of the oxide layer, includes: A first silicon nitride layer with a thickness of 70 Å to 300 Å is formed by blanket deposition, and the first silicon nitride layer covers the surface of the oxide layer.
3. The method for manufacturing the sidewall structure of the storage cell as described in claim 1, characterized in that, The step of forming a second silicon nitride layer by blanket deposition, wherein the second silicon nitride layer covers the surface of the first silicon nitride sidewall and the surface of the second oxide layer, includes: A second silicon nitride layer with a thickness of 200 Å to 300 Å is formed by blanket deposition, the second silicon nitride layer covering the surface of the first silicon nitride sidewall and the surface of the second oxide layer.
4. The method for manufacturing the sidewall structure of the storage cell as described in claim 1, characterized in that, The step of forming a first oxide layer by blanket deposition, wherein the first oxide layer covers the surface of the memory cell and the spacer surface between adjacent memory cells, includes: A first oxide layer with a thickness of 70 Å to 130 Å is formed by blanket deposition, which covers the surface of the memory cell and the spacer surface between adjacent memory cells.
5. The method for manufacturing the sidewall structure of the storage cell as described in claim 1, characterized in that, The steps of self-aligned etching of the first silicon nitride layer, etching away the first silicon nitride layer covering the front side, etching and thinning the first oxide layer covering the spacer surface between adjacent memory cells to form a second oxide layer, and retaining the first silicon nitride layer covering the side of the memory cell to form a first silicon nitride sidewall include: Self-aligned etching of the first silicon nitride layer, etching to remove the first silicon nitride layer covering the front side, etching to thin the first oxide layer covering the spacer surface between adjacent memory cells to form a second oxide layer with a thickness of 35 Å to 65 Å, and retaining the first silicon nitride layer covering the side of the memory cell to form a first silicon nitride sidewall.
6. A sidewall structure for a storage cell, characterized in that, The sidewall structure of the storage unit includes: A semiconductor structure with multiple memory cells is formed, with adjacent memory cells spaced apart. A first oxide layer is deposited on the outer periphery of the memory cell; A first silicon nitride sidewall covers a first oxide layer on the side of the storage cell, and the first oxide layer under the first silicon nitride sidewall extends to both sides to form a first oxide layer extension portion. A second oxide layer extends from the extension portion of the first oxide layer to both sides; the thickness of the second oxide layer is less than the thickness of the first oxide layer. The second silicon nitride sidewall covers the outside of the first silicon nitride sidewall on the side of the storage cell, and the second oxide layer is located under the second silicon nitride sidewall.
7. The sidewall structure of the storage cell as described in claim 6, characterized in that, A step is formed at the junction of the second oxide layer and the first oxide layer.
Citation Information
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