Chip stacking structure with back power supply and preparation method thereof

Abstract

The invention provides a back power supply chip stacking structure and a preparation method thereof, the chip stacking structure comprises two chips which are bonded up and down, the two chips realize signal transmission through signal connection layers which are bonded with each other, and the two chips are connected with each other through a power rail and an embedded power layer. Only by forming the metal interconnection layer on the back of the first chip as the back power supply layer, the transistors of the upper chip and the lower chip can be powered, and transmission of electric signals is achieved. By means of the stacking design, the chip stacking structure can achieve the double transistor number under the same area, for example, only a 14 nm manufacturing process can be used, and the transistor number under a 7 nm manufacturing process can be achieved. And meanwhile, the second chip bonded with the first chip also serves as a temporary slide glass, so that the temporary slide glass does not need to be additionally provided, and the manufacturing cost is further reduced. In addition, the procedure of manufacturing the back power supply channel is moved forward, so that the preparation process is sequentially carried out from bottom to top, and the process reasonability is better.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a chip stacking structure and a preparation method thereof. Background Art

[0002] In traditional 2.5D or 3D advanced packaging, wiring is mostly done on the front side of the wafer, and signal lines and power lines are stacked and connected vertically to form semiconductor devices with two or more layers of active electronic components of an integrated circuit. Power lines are used to supply power to the chip to form a power supply network. However, there is also a signal network formed by signal lines in the front area of ​​the chip. Making the power supply network on the front of the chip means that the power supply network and signal network in the chip must share the same component space, and the power supply network often occupies a large space, making it difficult to further reduce the volume of the entire packaging structure. In addition, the three-dimensional packaging structure with increased chip density may experience high IR voltage drop, which will lead to increased power consumption and decreased device performance.

[0003] Therefore, the industry began to explore the possibility of transferring the power supply network to the back side, making backside PDN a hot technical topic. The current backside PDN technology is commonly used in 2D packaging. Based on the backside PDN technology, how to further increase the chip density of the packaging structure and increase the number of transistors to improve device performance while optimizing the process flow as much as possible to reduce costs has become another difficult problem faced by technicians. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a chip stacking structure and a preparation method thereof, so as to improve chip density and increase the number of transistors.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a chip stacking structure with back-side power supply, the chip stacking structure comprising:

[0006] A first chip includes a silicon deposition layer, a buried power layer, a dielectric layer and a signal connection layer stacked in sequence from bottom to top, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer, and a metal line is formed in the signal connection layer to achieve signal connection with the transistors;

[0007] A second chip, bonded on the first chip, comprises a second substrate, a buried power layer, a dielectric layer and a signal connection layer stacked in sequence from top to bottom, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer, and a metal line is formed in the signal connection layer to achieve signal connection with the transistor;

[0008] The first chip and the second chip are also respectively formed with power rails, which penetrate the dielectric layer and the signal connection layer to electrically connect the buried power layer; the signal connection layers of the two chips are in contact to achieve signal connection; the power rails of the two chips are in contact to achieve electrical connection.

[0009] Preferably, the chip stacking structure further comprises an isolation layer formed by a shallow trench isolation process, and the isolation layer is used for isolation between multiple buried power layers or for electrical insulation between transistors.

[0010] Preferably, a plurality of penetrating metal pillars are formed in the silicon deposition layer, and the plurality of metal pillars are electrically connected to the power rail and the buried power layer of the first chip respectively.

[0011] Preferably, a metal interconnection layer is formed on the lower surface of the silicon deposition layer for electrically leading out the metal pillars.

[0012] Preferably, the signal connection layer and the metal interconnection layer are formed based on a copper Damascene process.

[0013] The present invention also provides a method for preparing a back-side powered chip stacking structure, the method comprising the following steps:

[0014] S1: providing a first substrate, sequentially forming a metal interconnection layer and a silicon deposition layer on the first substrate, forming a plurality of penetrating metal pillars in the silicon deposition layer, wherein the metal pillars are electrically connected to metal wires of the metal interconnection layer;

[0015] S2: forming a buried power layer and a dielectric layer in sequence on the surface of the silicon deposition layer, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer to form a first chip, and the buried power layer is used as a power supply channel for the transistors;

[0016] S3: forming a signal connection layer on a surface of the dielectric layer of the first chip away from the substrate, wherein a metal line is formed in the signal connection layer to achieve signal connection with the transistor; the first chip is also formed with a power rail, wherein the power rail penetrates the dielectric layer and the signal connection layer to electrically connect the buried power layer;

[0017] S4: providing a second substrate, forming an embedded power layer, a dielectric layer and a signal connection layer on the second substrate, wherein a plurality of transistors electrically connected to the embedded power layer are formed in the dielectric layer to form a second chip, and the second chip also has a power rail penetrating the dielectric layer and the signal connection layer;

[0018] S5: Bonding the second chip to the first chip to form a stacked body, so that the signal connection layers of the two chips are in contact with each other to achieve signal connection; and the power rails of the two chips are in contact with each other to achieve electrical connection.

[0019] Preferably, the method further comprises the following steps:

[0020] S6: removing the first substrate of the first chip to expose the metal wires in the metal interconnection layer.

[0021] Preferably, the signal connection layer and the metal interconnection layer are formed based on a copper Damascene process.

[0022] Preferably, the first substrate and the second substrate are both silicon substrates.

[0023] Preferably, steps S2 and S4 further include a process of forming an isolation layer by a shallow trench isolation process, wherein the isolation layer is used for isolation between multiple buried power layers or for electrical insulation between transistors.

[0024] As described above, the present invention provides a back-powered chip stacking structure and a preparation method thereof, wherein the chip stacking structure includes two chips bonded up and down, and the two chips realize signal transmission through a mutually bonded signal connection layer. At the same time, combined with the setting of the power rail and the embedded power layer, it is only necessary to form a metal interconnection layer as a back power supply layer on the back of the first chip, so that the transistors of the upper and lower chips can be powered and the transmission of electrical signals can be realized. Through the stacking design, the chip stacking structure can realize double the number of transistors in the same area. For example, only a 14nm process can be used, and the upper and lower transistor stacking method of the present application can be combined to achieve the number of transistors under the 7nm process, and the same performance can be achieved, thereby saving process costs. At the same time, the second chip bonded to the first chip also acts as a temporary carrier, and there is no need to provide an additional temporary carrier, further reducing the production cost. In addition, the process of making the back power supply channel is moved forward, so that the preparation process is carried out sequentially from bottom to top, and the process rationality is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1-Figure 7 It is a schematic diagram showing the process steps of the chip stacking structure of the present invention.

[0026] Figure 8 Shown is a schematic structural diagram of the chip stacking structure of the present invention.

[0027] Component number description

[0028] 101 Silicon substrate layer

[0029] 102 Metal Interconnect Layer

[0030] 103 Silicon Deposition Layer

[0031] 104 buried power layer

[0032] 105 Dielectric layer

[0033] 106 Signal Connection Layer

[0034] 201 Transistor

[0035] 202 Isolation Layer

[0036] 100 First Chip

[0037] 200 Second Chip

[0038] 16 Power Rail

[0039] 31 Metal Column DETAILED DESCRIPTION

[0040] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0041] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0042] For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. As used herein, "between..." means including the end point values.

[0043] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0044] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0045] like Figure 1-Figure 7 As shown, the present invention provides a method for preparing a back-side powered chip stacking structure, which specifically includes the following steps:

[0046] S1: Provide a first substrate, such as Figure 1-Figure 3 As shown, a metal interconnection layer 102 and a silicon deposition layer 103 are sequentially formed on the first substrate, and a plurality of penetrating metal pillars 31 are formed in the silicon deposition layer 103, and the metal pillars 31 are electrically connected to the metal wires of the metal interconnection layer 102;

[0047] S2: forming a buried power layer 104 and a dielectric layer 105 on the surface of the silicon deposition layer 103 in sequence, such as Figure 4 As shown, a plurality of transistors 201 electrically connected to the buried power layer 104 are formed in the dielectric layer 105 to form the first chip 100 , and the buried power layer 104 is used as a power supply channel for the transistors 201 .

[0048] Specifically, the first substrate can be a semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon germanium substrate, etc., preferably a silicon substrate 101. The metal interconnection layer 102 can be prepared by a copper Damascene process. As an example, an insulating layer such as silicon dioxide is first deposited on the surface of the first substrate, and then etching is performed to form a groove, and then metal copper is deposited in the groove to finally form a metal interconnection layer 102, and the metal wire in the metal interconnection layer 102 is copper. The process of preparing the metal column 31 is: first, a plurality of through silicon vias (TSVs) are formed in the silicon deposition layer 103, more specifically, nano-through silicon vias (n-TSVs), and then an oxide layer is covered on the inner wall of the through silicon via, and finally a metal filling is used to form the metal column 31.

[0049] The buried power layer 104 and the dielectric layer 105 are sequentially formed on the silicon deposition layer 103. As an example, the transistor 201 may be a Fin FET, which may be formed after the buried power layer 104 is formed. The transistor 201 is obtained by covering the silicon material and then further etching, doping and other processes. The specific manufacturing process of the transistor 201 (FinFET) can refer to the prior art and will not be described in detail here. The dielectric layer 105 is used to achieve electrical insulation between the transistors 201 and the electrical insulation between the upper and lower structures.

[0050] Furthermore, step S2 may also include a shallow trench isolation (STI) process. In some embodiments, the shallow trench isolation process is used to form the buried power layer 104: first, a layer of insulating material is deposited, and a trench is formed by etching, and then the trench is filled with a conductive material to form a patterned conduction to realize power supply to the transistor. Figure 4As shown, in some other embodiments, the shallow trench isolation process is used to make the isolation layer 202 to achieve isolation between multiple buried power layers 104: for example, the chip is provided with multiple buried power layers 104 (Buried power rail, BPR), including a first BPR for providing a first power supply voltage (such as VDD) and a second BPR for providing a second power supply voltage (such as VSS or GND); or, the transistors are divided into multiple subsets, and the multiple buried power layers include a third BPR for providing the first power supply voltage to the first subset of transistors, and a fourth BPR for providing the first power supply voltage to the second subset of transistors. In some other embodiments, the shallow trench isolation process is used to achieve electrical insulation between transistors, and an isolation layer 202 is set between transistors 201 to separate them from each other and ensure mutual insulation.

[0051] Next, step S3 is performed: forming a signal connection layer 106 on the surface of the dielectric layer 105 of the first chip away from the substrate, such as Figure 5 As shown, a metal line is formed in the signal connection layer 106 to achieve signal connection with the transistor 201; the first chip 100 also forms a power rail 16, and the power rail 16 passes through the dielectric layer 105 and the signal connection layer 106 to electrically connect the buried power layer 104.

[0052] Next, step S4 is performed: providing a second substrate, such as Figure 6 As shown, an embedded power layer 104, a dielectric layer 105 and a signal connection layer 106 are formed on the second substrate. A plurality of transistors 201 electrically connected to the embedded power layer are formed in the dielectric layer 105 to form a second chip 200. The second chip 200 also has a power rail 16 that passes through the dielectric layer 105 and the signal connection layer 106.

[0053] Specifically, as an example, the second substrate is the same as the first substrate, and may be a semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon germanium substrate, etc., and is preferably a silicon substrate 101 .

[0054] The signal connection layer 106 can be prepared by a copper Damascene process. As an example, an insulating layer such as silicon dioxide is first deposited on the surface of the dielectric layer 105, and then etched to form a groove, and then metallic copper is deposited in the groove to finally form the signal connection layer 106. The metal wires in the signal connection layer 106 are copper.

[0055] It should be noted that the second chip does not have a metal interconnection layer and a silicon deposition layer similar to those of the first chip, because the back side of the first chip will need to be used as a power supply channel later, and the power supply of the second chip is achieved through the power rail after bonding with the first chip, and there is no need to prepare an additional power supply channel.

[0056] Then, proceed to step S5: Figure 7 As shown, the second chip 200 is bonded to the first chip 100 to form a stack, so that the signal connection layers 106 of the two chips are in contact to achieve signal connection; the power rails 16 of the two chips are in contact to achieve electrical connection;

[0057] Specifically, the two chips are stacked and interconnected by bonding, and the transistors 201 of the upper and lower chips can be powered by the power rail 16 and the buried power layer 104. Double the number of transistors can be achieved in the same area. For example, only the 14nm process can be used, combined with the upper and lower transistor stacking method of the present application, to achieve the same performance as the number of transistors in the 7nm process. Advanced processes mean expensive process costs. By stacking up and down, while achieving the same performance, process costs can also be saved.

[0058] Then, proceed to step S6: Figure 8 As shown, the first substrate of the first chip is removed to expose the metal wires in the metal interconnection layer 102;

[0059] Specifically, in the process, the first substrate is firstly thinned by CMP, and then the remaining part of the first substrate is removed by dry etching.

[0060] It should be noted that, in the CMP thinning process, the second chip here acts as a temporary carrier. If there is no second chip 200, a temporary carrier needs to be provided to carry and fix the first chip 100 for subsequent thinning. The temporary carrier is a temporary material with high process cost. The bonding of the first chip 100 and the second chip 200 here increases the number of collective tubes, avoids the use of a temporary carrier, and reduces the production cost.

[0061] The above-mentioned preparation method is to first prepare the metal interconnection layer 102 and the silicon deposition layer 103 (metal pillar 31) used as the power supply channel, and then bond the two chips; while the existing process is to make the power supply channel on the back side only after the first chip is bonded to the second chip. Corresponding to the structure of the present application, specifically, after bonding, the first chip is flipped so that it faces upward, and then TSV is made on the silicon deposition layer of the first chip, and then the metal interconnection layer is covered to realize electrical extraction. The present application moves the process of making the back power supply channel forward, and the preparation process is carried out sequentially from bottom to top. There is no need to flip the TSV, and the process is more reasonable. At the same time, the previously prepared metal interconnection layer 102 can also be used as a barrier layer for the silicon deposition layer 103, eliminating the process; in contrast, the existing process often requires the preparation of an additional barrier layer on the surface of the silicon deposition layer before TSV and covering the metal interconnection layer, usually an oxide material or a nitride material, to play a moisture-proof and anti-static role and protect the internal circuit.

[0062] The present invention also provides a back-side powered chip stacking structure, such as Figure 8 As shown, the chip stacking structure can be based on the above-mentioned preparation method, but is not limited to the above-mentioned preparation method, and the chip stacking structure includes:

[0063] The first chip 100 includes a silicon deposition layer 103, a buried power layer 104, a dielectric layer 105 and a signal connection layer 106 stacked in sequence from bottom to top, wherein a plurality of transistors 201 electrically connected to the buried power layer are formed in the dielectric layer 105, and metal lines are formed in the signal connection layer 106 to achieve signal connection with the transistors 201;

[0064] The second chip 200 is bonded on the first chip 100, and includes a second substrate, a buried power layer 104, a dielectric layer 105, and a signal connection layer 106 stacked in sequence from top to bottom. A plurality of transistors 201 electrically connected to the buried power layer are formed in the dielectric layer 105, and a metal line is formed in the signal connection layer 106 to achieve signal connection with the transistors 201;

[0065] The first chip 100 and the second chip 200 are also respectively formed with power rails 16, and the power rails 16 penetrate the dielectric layer 105 and the signal connection layer 106 to electrically connect the buried power layer 104; the signal connection layers 106 of the two chips are in contact to achieve signal connection; the power rails 16 of the two chips are in contact to achieve electrical connection.

[0066] Furthermore, the chip stacking structure further includes an isolation layer 202 formed by a shallow trench isolation process, and the isolation layer 202 is used for isolation between multiple buried power layers 104 or for electrical insulation between transistors 201 .

[0067] Furthermore, a plurality of penetrating metal pillars 31 are formed in the silicon deposition layer 103, and the plurality of metal pillars 31 are respectively electrically connected to the power rail 16 of the first chip 100 and the buried power layer 104. The metal pillars electrically connected to the buried power layer 104 of the first chip 100 here not only transmit power, but also have the function of signal transmission, first transmitting the signal to the first chip, and then the first chip transmits it to the second chip through the signal connection layer.

[0068] Furthermore, a metal interconnection layer 102 is formed on the lower surface of the silicon deposition layer 103 for electrically leading out the metal pillars 31 .

[0069] For specific details of the chip stacking structure, please refer to the relevant description in the above-mentioned preparation method, which will not be repeated here.

[0070] In summary, the present invention provides a back-powered chip stacking structure and a preparation method thereof, wherein the chip stacking structure comprises two chips bonded up and down, and the two chips realize signal transmission through a mutually bonded signal connection layer, and at the same time, combined with the setting of the power rail and the embedded power layer, it is only necessary to form a metal interconnection layer on the back of the first chip as a back power supply layer, so that the transistors of the upper and lower chips can be powered and the transmission of electrical signals can be realized. Through the stacking design, the chip stacking structure can realize double the number of transistors in the same area, for example, only a 14nm process can be used, combined with the upper and lower transistor stacking method of the present application, to achieve the number of transistors under the 7nm process, to achieve the same performance, thereby saving process costs. At the same time, the second chip bonded to the first chip also acts as a temporary carrier, and there is no need to provide an additional temporary carrier, further reducing the production cost. In addition, the process of making the back power supply channel is moved forward, so that the preparation process is carried out sequentially from bottom to top, and the process rationality is better.

[0071] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A chip stacking structure with back-side power supply, characterized in that: The chip stacking structure comprises: A first chip includes a silicon deposition layer, a buried power layer, a dielectric layer and a signal connection layer stacked in sequence from bottom to top, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer, and a metal line is formed in the signal connection layer to achieve signal connection with the transistors; A second chip, bonded on the first chip, comprises a second substrate, a buried power layer, a dielectric layer and a signal connection layer stacked in sequence from top to bottom, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer, and a metal line is formed in the signal connection layer to achieve signal connection with the transistor; The first chip and the second chip are also respectively formed with power rails, which penetrate the dielectric layer and the signal connection layer to electrically connect the buried power layer; the signal connection layers of the two chips are in contact to achieve signal connection; the power rails of the two chips are in contact to achieve electrical connection.

2. The chip stacking structure according to claim 1, characterized in that: The chip stacking structure further includes an isolation layer formed by a shallow trench isolation process, and the isolation layer is used for isolation between multiple buried power layers or for electrical insulation between transistors.

3. The chip stacking structure according to claim 1, characterized in that: A plurality of penetrating metal pillars are formed in the silicon deposition layer, and the plurality of metal pillars are electrically connected to the power rail of the first chip and the buried power layer respectively.

4. The chip stacking structure according to claim 3, characterized in that: A metal interconnection layer is formed on the lower surface of the silicon deposition layer for electrically leading out the metal pillars.

5. The chip stacking structure according to claim 4, characterized in that: The signal connection layer and the metal interconnection layer are formed based on a copper Damascene process.

6. A method for preparing a back-side powered chip stacking structure, characterized in that: The preparation method comprises the following steps: S1: providing a first substrate, sequentially forming a metal interconnection layer and a silicon deposition layer on the first substrate, forming a plurality of penetrating metal pillars in the silicon deposition layer, wherein the metal pillars are electrically connected to metal wires of the metal interconnection layer; S2: forming a buried power layer and a dielectric layer in sequence on the surface of the silicon deposition layer, wherein a plurality of transistors electrically connected to the buried power layer are formed in the dielectric layer to form a first chip, and the buried power layer is used as a power supply channel for the transistors; S3: forming a signal connection layer on a surface of the dielectric layer of the first chip away from the substrate, wherein a metal line is formed in the signal connection layer to achieve signal connection with the transistor; the first chip is also formed with a power rail, wherein the power rail penetrates the dielectric layer and the signal connection layer to electrically connect the buried power layer; S4: providing a second substrate, forming an embedded power layer, a dielectric layer and a signal connection layer on the second substrate, wherein a plurality of transistors electrically connected to the embedded power layer are formed in the dielectric layer to form a second chip, and the second chip also has a power rail penetrating the dielectric layer and the signal connection layer; S5: Bonding the second chip to the first chip to form a stacked body, so that the signal connection layers of the two chips are in contact with each other to achieve signal connection; and the power rails of the two chips are in contact with each other to achieve electrical connection.

7. The preparation method according to claim 6, characterized in that: The following steps are also included: S6: removing the first substrate of the first chip to expose the metal wires in the metal interconnection layer.

8. The preparation method according to claim 6, characterized in that: The signal connection layer and the metal interconnection layer are formed based on a copper Damascene process.

9. The preparation method according to claim 6, characterized in that: The first substrate and the second substrate are both silicon substrates.

10. The preparation method according to claim 6, characterized in that: Steps S2 and S4 also include a process of forming an isolation layer by a shallow trench isolation process. The isolation layer is used for isolation between multiple buried power layers or for electrical insulation between transistors.

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