Half-bridge circuit and power module

Abstract

The invention discloses a half-bridge circuit and a power module, the half-bridge circuit is integrated in the power module, the half-bridge circuit comprises a first bridge arm and a second bridge arm, the first bridge arm is electrically connected between a positive voltage direct current end and an alternating current end, and the second bridge arm is electrically connected between a negative voltage direct current end and the alternating current end; the first bridge arm comprises a first switch unit, the first end of the first switch unit is electrically connected with the positive voltage direct current end, and the second end is electrically connected with the alternating current end; the first end of the first inductor is electrically connected with the second end of the first switch unit; the first end of the first suppression unit is electrically connected with the second end of the first inductor, the second end of the first suppression unit is electrically connected with the control end of the first switch unit, and the first suppression unit is used for suppressing the negative voltage between the control end of the first switch unit and the second end of the first switch unit. According to the embodiment of the invention, the negative voltage Miller peak generated between the gate and the source can be suppressed.

Description

Technical Field

[0001] The present application belongs to the field of power semiconductor packaging, and in particular, relates to a half-bridge circuit and a power module. Background Art

[0002] When power modules are used in power electronic systems, they are generally accompanied by a switching process of power semiconductor chips, which changes the flow path of the current in the power system, namely "commutation".

[0003] However, during the "commutation" process, the current path (such as the component pins and copper layer in the PCB circuit, the terminals and bonding wires in the power module) will also have rapidly changing voltages and currents. The rapidly changing voltages and currents are coupled with the parasitic capacitance / inductance of the current path and the device itself, causing current / voltage overshoot and oscillation. Voltage oscillations can easily introduce negative source voltage noise to the semiconductor chip, causing a negative voltage Miller spike in the voltage between the gate and the source. Summary of the invention

[0004] The embodiments of the present application provide a half-bridge circuit and a power module capable of suppressing the negative voltage Miller spike generated between the gate and the source.

[0005] In a first aspect, an embodiment of the present application provides a half-bridge circuit, which is integrated in a power module. The half-bridge circuit includes a first bridge arm and a second bridge arm, wherein the first bridge arm is electrically connected between a positive voltage DC end and an AC end, and the second bridge arm is electrically connected between a negative voltage DC end and an AC end; the first bridge arm includes: a first switch unit, wherein a first end of the first switch unit is electrically connected to the positive voltage DC end, and a second end of the first switch unit is electrically connected to the AC end; a first inductor, wherein a first end of the first inductor is electrically connected to a second end of the first switch unit; a first suppression unit, wherein a first end of the first suppression unit is electrically connected to a second end of the first inductor, and a second end of the first suppression unit is electrically connected to a control end of the first switch unit, and the first suppression unit is used to suppress a negative voltage between the control end of the first switch unit and the second end of the first switch unit.

[0006] According to an implementation of the first aspect of the present application, the first switch unit includes a first transistor, and the first suppression unit includes: a first withstand voltage diode, a cathode of the first withstand voltage diode is electrically connected to the control end of the first switch unit; a first transient voltage suppression diode, an anode of the first transient voltage suppression diode is electrically connected to the anode of the first withstand voltage diode, and a cathode of the first transient voltage diode is electrically connected to the second end of the first inductor.

[0007] According to any of the aforementioned embodiments of the first aspect of the present application, the second bridge arm includes: a second switch unit, a first end of the second switch unit is electrically connected to the AC end, and a second end of the second switch unit is electrically connected to the negative voltage DC end; a second inductor, a first end of the second inductor is electrically connected to the second end of the second switch unit and the negative voltage DC end; a second suppression unit, a first end of the second suppression unit is electrically connected to the second end of the second inductor, and a second end of the second suppression unit is electrically connected to the control end of the second switch unit, and the second suppression unit is used to suppress the negative pressure between the control end of the second switch unit and the second end of the second switch unit.

[0008] According to any of the aforementioned embodiments of the first aspect of the present application, the second switch unit includes a second transistor, and the second suppression unit includes: a second withstand voltage diode, the cathode of the second withstand voltage diode is electrically connected to the control end of the second switch unit; a second transient voltage suppression diode, the anode of the second transient voltage suppression diode is electrically connected to the anode of the second withstand voltage diode, and the cathode of the second transient voltage suppression diode is electrically connected to the second end of the second inductor.

[0009] According to any of the aforementioned embodiments of the first aspect of the present application, the first switch unit includes a first transistor, the second switch unit includes a second transistor, and the power module includes a stacked substrate and a first metal layer; the first metal layer includes a first metal area, a second metal area, a third metal area, a fourth metal area, a fifth metal area, a sixth metal area and a seventh metal area; along the first direction of the power module, the first metal area, the second metal area, the third metal area, the fourth metal area, the fifth metal area, the sixth metal area and the seventh metal area are arranged at intervals; a first bare die is provided on the first metal area, the first bare die includes a first transient voltage suppression diode, and the cathode of the first transient voltage suppression diode is electrically connected to the first metal area; a second bare die is provided on the second metal area, the second bare die includes a first withstand voltage diode, and the cathode of the first withstand voltage diode is electrically connected to the second metal area; the anode of the first transient voltage suppression diode is electrically connected to the anode of the first withstand voltage diode; at least one third A bare chip, a third bare chip includes a first transistor, a drain of the first transistor is electrically connected to the third metal area, a gate of the first transistor is electrically connected to the second metal area, a source of the first transistor is electrically connected to the first metal area, and the third metal area is electrically connected to the positive voltage DC end; at least one fourth bare chip is arranged on the fourth metal area, the fourth bare chip includes a second transistor, the drain of the second transistor is electrically connected to the fourth metal area, and the fourth metal area is electrically connected to the AC end; the fifth metal area is electrically connected to the negative voltage DC end, and the fifth metal area is electrically connected to the source of the second transistor; a fifth bare chip is arranged on the sixth metal area, the fifth bare chip includes a second withstand voltage diode, the cathode of the second withstand voltage diode is electrically connected to the sixth metal area, and the sixth metal area is electrically connected to the gate of the second transistor; a sixth bare chip is arranged on the seventh metal area, the sixth bare chip includes a second transient voltage suppression diode, the cathode of the second transient voltage suppression diode is electrically connected to the seventh metal area, and the seventh metal area is electrically connected to the source of the second transistor.

[0010] According to any of the aforementioned embodiments of the first aspect of the present application, the minimum distance between the first metal zone and the second metal zone along the first direction is smaller than the minimum distance between the second metal zone and the third metal zone along the first direction, and / or the minimum distance between the sixth metal zone and the seventh metal zone along the first direction is smaller than the minimum distance between the fifth metal zone and the sixth metal zone along the first direction.

[0011] According to any of the aforementioned embodiments of the first aspect of the present application, the area of ​​the third metal zone is larger than the area of ​​at least one of the first metal zone, the second metal zone, the sixth metal zone and the seventh metal zone; the area of ​​the fifth metal zone is larger than the area of ​​at least one of the first metal zone, the second metal zone, the sixth metal zone and the seventh metal zone.

[0012] According to any of the aforementioned embodiments of the first aspect of the present application, the second metal region includes a first sub-metal region and at least one second sub-metal region, and the second bare chip is arranged in the second sub-metal region; along the first direction, the first sub-metal region and the second sub-metal region are arranged between the first metal region and the third metal region, a first gate resistor is provided on the second sub-metal region, a first end of the first gate resistor is electrically connected to the second sub-metal region, a second end of the first gate resistor is electrically connected to the first sub-metal region, a cathode of the first withstand voltage diode is electrically connected to the second sub-metal region, an anode of the first withstand voltage diode is electrically connected to an anode of the first transient voltage suppression diode, and the second sub-metal region is electrically connected to the first The gate of the transistor is electrically connected; the sixth metal region includes at least a third sub-metal region and a fourth sub-metal region, and the fifth bare chip is arranged in the third sub-metal region; along the first direction, the third sub-metal region and the fourth sub-metal region are arranged between the fifth metal region and the seventh metal region, a second gate resistor is provided on the third sub-metal region, a first end of the second gate resistor is electrically connected to the third sub-metal region, and a second end of the second gate resistor is electrically connected to the seventh metal region; a cathode of the second withstand voltage diode is electrically connected to the third sub-metal region, an anode of the second withstand voltage diode is electrically connected to an anode of the second transient voltage suppression diode, and the third sub-metal region is electrically connected to the gate of the second transistor.

[0013] According to any of the aforementioned embodiments of the first aspect of the present application, the first switch unit includes a first transistor, the second switch unit includes a second transistor, and the power module includes a stacked substrate and a first metal layer; the first metal layer includes an eighth metal area, a ninth metal area, a tenth metal area, an eleventh metal area, and a twelfth metal area; along the first direction of the power module, the eighth metal area, the ninth metal area, the tenth metal area, the eleventh metal area, and the twelfth metal area are arranged at intervals; a seventh bare chip is provided on the eighth metal area, the seventh bare chip includes a first transient voltage suppression diode, and the cathode of the first transient voltage suppression diode is electrically connected to the eighth metal area; at least one eighth bare chip is provided in the ninth metal area, the eighth bare chip includes a first transistor, the drain of the first transistor is electrically connected to the ninth metal area, and the gate of the first transistor is electrically connected to the eighth metal area. The first metal region is electrically connected to the first metal region, and the ninth metal region is electrically connected to the positive voltage DC terminal; the tenth metal region is provided with a ninth bare chip and at least one tenth bare chip, the ninth bare chip includes a first transient voltage suppression diode, the cathode of the first transient voltage suppression diode is electrically connected to the tenth metal region, the tenth bare chip includes a second transistor, and the tenth metal region is electrically connected to the AC terminal; the eleventh metal region is provided with an eleventh bare chip, the eleventh bare chip includes a second transient voltage suppression diode, the cathode of the second transient voltage suppression diode is electrically connected to the eleventh metal region, and the eleventh metal region is electrically connected to the negative voltage DC terminal; the twelfth metal region is provided with a twelfth bare chip, the twelfth bare chip includes a second withstand voltage diode, the cathode of the second withstand voltage diode is electrically connected to the twelfth metal region, and the anode of the second withstand voltage diode is electrically connected to the anode of the second transient voltage suppression diode.

[0014] According to an implementation manner of the first aspect of the present application, the first switch unit includes a first transistor, the second switch unit includes a second transistor, and the power module includes a stacked substrate and a first metal layer; the first metal layer includes a thirteenth metal area, a fourteenth metal area, a fifteenth metal area, a sixteenth metal area, a seventeenth metal area, an eighteenth metal area, a nineteenth metal area and a twenty-first metal area; the thirteenth metal area is electrically connected to the AC end; at least one thirteenth bare chip is provided on the fourteenth metal area, the thirteenth bare chip includes a first transistor, the source of the first transistor is electrically connected to the thirteenth metal area, the drain of the first transistor is electrically connected to the fourteenth metal area, and the fourteenth metal area is electrically connected to the positive voltage DC end; a fourteenth bare chip is provided on the fifteenth metal area, the fourteenth bare chip includes a first withstand voltage diode, and the cathode of the first withstand voltage diode is electrically connected to the fifteenth metal area; the fifteenth bare chip is provided on the sixteenth metal area, and the fifteenth bare chip includes a first withstand voltage diode. The bare chip includes a first transient voltage suppression diode, a cathode of the first transient voltage suppression diode is electrically connected to the sixteenth metal region, and an anode of the first transient voltage suppression diode is electrically connected to an anode of the fourteenth bare chip; the seventeenth metal region is electrically connected to the negative voltage DC terminal; at least one sixteenth bare chip is provided on the eighteenth metal region, the sixteenth bare chip includes a second transistor, a source of the second transistor is electrically connected to the seventeenth metal region, and a drain of the second transistor is electrically connected to the eighteenth metal region; a seventeenth bare chip is provided on the nineteenth metal region, the seventeenth bare chip includes a second withstand voltage diode, and a cathode of the second withstand voltage diode is electrically connected to the nineteenth metal region; an eighteenth bare chip is provided on the twentieth metal region, the eighteenth bare chip includes a second transient voltage suppression diode, a cathode of the second transient voltage suppression diode is electrically connected to the twentieth metal region, and an anode of the second transient voltage suppression diode is electrically connected to an anode of the second withstand voltage diode.

[0015] In a second aspect, an embodiment of the present application provides a power module, and the power module includes a half-bridge circuit as in the first aspect.

[0016] The half-bridge circuit and power module of the embodiment of the present application, the half-bridge circuit is integrated in the power module, the half-bridge circuit includes a first bridge arm and a second bridge arm, the first bridge arm is electrically connected between the positive voltage DC end and the AC end, and the second bridge arm is electrically connected between the negative voltage DC end and the AC end; the first bridge arm includes: a first switch unit, the first end of the first switch unit is electrically connected to the positive voltage DC end, and the second end of the first switch unit is electrically connected to the AC end; a first inductor, the first end of the first inductor is electrically connected to the second end of the first switch unit; a first suppression unit, the first end of the first suppression unit is electrically connected to the second end of the first inductor, the second end of the first suppression unit is electrically connected to the control end of the first switch unit, and the first suppression unit is used to suppress the negative voltage between the control end of the first switch unit and the second end of the first switch unit. The half-bridge circuit is integrated in the power module, and with the switching process of the first switch unit, the current flow path in the power module changes, that is, commutation. In this process, with the rapid shutdown of the second switch unit, the changing current causes the first inductor to generate an induced negative voltage drop, combined with the closed first switch unit, so that the two ends of the first switch unit and the first inductor in parallel are subjected to excessive negative pressure. The present application introduces a first suppression unit at the control end and the second end of the first switch unit, and uses the first suppression unit to slow down the change of current, thereby suppressing the negative voltage between the control end and the second end of the first switch unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 This is a circuit connection diagram of a half-bridge circuit provided in an embodiment of the present application;

[0019] Figure 2 is another circuit connection diagram of the half-bridge circuit provided in an embodiment of the present application;

[0020] Figure 3 This is another circuit connection diagram of the half-bridge circuit provided in the embodiment of the present application;

[0021] Figure 4 This is another circuit connection diagram of the half-bridge circuit provided in the embodiment of the present application;

[0022] Figure 5 This is another circuit connection diagram of the half-bridge circuit provided in the embodiment of the present application;

[0023] Figure 6 This is another circuit connection diagram of the half-bridge circuit provided in the embodiment of the present application;

[0024] Figure 7 It is a partially enlarged schematic diagram of the current flow direction when the suppression effect is formed in the half-bridge circuit provided in the embodiment of the present application;

[0025] Figure 8 is a structural schematic diagram of a bare chip provided in an embodiment of the present application;

[0026] Fig. 9 The embodiment of the present application provides Figure 6 A schematic longitudinal cross-sectional view of the buffer circuit portion obtained by taking a cross section along the dotted line path;

[0027] Fig.10 This is another circuit connection diagram of the half-bridge circuit provided in the embodiment of the present application;

[0028] Fig.11 This is another circuit connection diagram of the half-bridge circuit provided in the embodiment of the present application;

[0029] Fig.12 This is another circuit connection diagram of the half-bridge circuit provided in the embodiment of the present application;

[0030] Fig.13 The embodiment of this application provides Fig.11 A partial enlarged schematic diagram of the current flow direction when the half-bridge circuit in the circuit forms an inhibitory effect;

[0031] Fig.14 It is a schematic diagram of circuit connection inside a module that integrates gate resistance and a half-bridge circuit through a PCB provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0033] The acquisition, storage, use, and processing of data in the technical solution of this application comply with the relevant provisions of national laws and regulations.

[0034] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0035] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0036] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0037] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0038] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0039] Power semiconductor chips have been widely used in automotive motor drive and battery management, industrial inverters, photovoltaic inverters and other related fields due to their control and energy conversion functions. The power module encapsulates multiple power semiconductor chipsets in the same module to form the required circuit topology. In addition to better heat dissipation and high reliability, the higher integration of power modules reduces the space occupied by power electronic systems, and the fewer connecting wires reduces the system complexity. Therefore, power modules are often used in high-power power conversion and motor control. The power module packaging process generally includes chip matching, chip mounting, wire bonding, sub-unit welding, shell assembly, terminal interconnection, and potting. After completing the circuit topology on the insulating substrate, wire bonding and connecting terminals are performed to achieve the functions required by the circuit.

[0040] When power modules are used in power electronic systems, they are usually accompanied by the switching process of power semiconductor chips, which changes the current flow path in the power system, i.e., "current commutation". During this process, the current path (such as component pins and copper layers in PCB circuits, terminals and bonding wires in power modules) will also have rapidly changing voltages and currents. The rapidly changing voltages and currents are coupled with the parasitic capacitance and inductance of the current path and the device itself, causing current and voltage overshoots and oscillations.

[0041] In order to solve the above problems, the embodiments of the present application provide a half-bridge circuit and a power module. The negative voltage Miller suppression circuit is first introduced below.

[0042] Figure 1 is a circuit connection diagram of a half-bridge circuit provided in an embodiment of the present application, such as Figure 1 As shown, the half-bridge circuit 100 is integrated into a power module, and the half-bridge circuit 100 may include a first bridge arm 110 and a second bridge arm 120 .

[0043] The first bridge arm 110 is electrically connected between the positive voltage DC terminal DC+ and the AC terminal AC, and the second bridge arm 120 is electrically connected between the negative voltage DC terminal DC- and the AC terminal AC; the first bridge arm 110 may include: a first switch unit S1, a first inductor L2 and a first suppression unit 111.

[0044] The first end of the first switch unit S1 is electrically connected to the positive voltage DC terminal DC+, and the second end of the first switch unit S1 is electrically connected to the AC terminal AC; the first end of the first inductor L2 is electrically connected to the second end of the first switch unit S1; the first end of the first suppression unit 111 is electrically connected to the second end of the first inductor L2, and the second end of the first suppression unit 111 is electrically connected to the control end of the first switch unit S1, and the first suppression unit 111 is used to suppress the negative pressure between the control end of the first switch unit S1 and the second end of the first switch unit S1.

[0045] It should be noted that the first inductor L2 is not a specific electrical component, but is specifically a parasitic inductor generated by a magnetic effect when current flows in the metal area.

[0046] Figure 2 is another circuit connection diagram of the half-bridge circuit provided in the embodiment of the present application, such as Figure 2 As shown, in order to explain the function of the half-bridge circuit in the present application, a load inductor L1 is introduced, and the load inductor L1 is connected in parallel with the first bridge arm 110 or in parallel with the second bridge arm 120. Figure 2 Take L1 and 110 in parallel as an example.

[0047] exist Figure 2 In the embodiment, if the first suppression unit 111 does not exist, when the first switch unit S1 remains off and S2 changes from on to off, due to the existence of the load inductor L1 and the inductor current will not suddenly change, the second end of L1, that is, the first end of the first inductor L2, maintains the original current flowing to the first switch unit S1, thereby causing a negative voltage drop between the control end of S1 and the second end of S1, causing the control end of S1 to be subjected to excessive negative pressure, thereby reducing reliability.

[0048] In some embodiments, the first switch unit S1 can be a field effect transistor, the control end of the field effect transistor is the gate end electrically connected to the second end of the first suppression unit 111, the drain end of the field effect transistor is electrically connected to the positive voltage DC end DC+, and the source end of the field effect transistor is electrically connected to the first end of the first inductor L2. This embodiment is also applicable to other power semiconductor chips.

[0049] The half-bridge circuit 100 is integrated in the power module, and the first switch unit S1 remains turned off. As the second switch unit S1 switches on and off, the current flow path in the power module changes, i.e., commutation. During this process, the first switch unit S1 remains turned off. As the second switch unit S2 switches off, the changing current causes the first inductor L2 to generate an induced negative voltage drop. Combined with the turned-off first switch unit S1, the two ends of the first switch unit S1 and the first inductor L2 in parallel are subjected to excessive negative pressure. The present application introduces a first suppression unit 111 at the control end and the second end of the first switch unit S1, and the first suppression unit 111 slows down the change of the current, thereby suppressing the negative pressure between the control end and the second end of the first switch unit S1.

[0050] Figure 3 is another circuit connection diagram of the half-bridge circuit provided in the embodiment of the present application, such as Figure 3 As shown, the first switch unit S1 may include a first transistor, and the first suppression unit 111 may include: a first withstand voltage diode D1 and a first transient voltage suppression diode D2.

[0051] The cathode of the first withstand voltage diode D1 is electrically connected to the control end of the first switch unit S1; the anode of the first transient voltage suppression diode D2 is electrically connected to the anode of the first withstand voltage diode D1, and the cathode of the first transient voltage diode is electrically connected to the second end of the first inductor L2.

[0052] The second bridge arm 120 may include: a second switch unit S2, a second inductor L3, and a second suppression unit 121. The first end of the second switch unit S2 is electrically connected to the AC end AC, and the second end of the second switch unit S2 is electrically connected to the negative voltage DC end DC-; the first end of the second inductor L3 is electrically connected to the second end of the second switch unit S2 and the negative voltage DC end DC-; the first end of the second suppression unit 121 is electrically connected to the second end of the second inductor L3, and the second end of the second suppression unit 121 is electrically connected to the control end of the second switch unit S2, and the second suppression unit 121 is used to suppress the negative voltage between the control end of the second switch unit S2 and the second end of the second switch unit S2.

[0053] It should be noted that the second inductor L3 is not a specific electrical component, but is specifically a parasitic inductor generated by a magnetic effect when current flows in a metal region, and is generated in the same principle as the first inductor L2.

[0054] The second switch unit S2 includes a second transistor, and the second suppression unit 121 may include: a second withstand voltage diode D3 and a second transient voltage suppression diode D4.

[0055] The cathode of the second withstand voltage diode D3 is electrically connected to the control end of the second switch unit S2; the anode of the second transient voltage suppression diode D4 is electrically connected to the anode of the second withstand voltage diode D3, and the cathode of the second transient voltage suppression diode D4 is electrically connected to the second end of the second inductor L3.

[0056] In some embodiments, the half-bridge circuit 100 further includes a bus capacitor C, a first end of the bus capacitor C being electrically connected to the positive voltage DC terminal DC+, and a second end of the bus capacitor C being electrically connected to the negative voltage DC terminal DC-. The bus capacitor C is used for energy storage in the half-bridge circuit 100 of the present application.

[0057] In some embodiments, the first transient voltage suppressor diode D2 and the second transient voltage suppressor diode D4 may be transient voltage suppressor diodes (TVS).

[0058] When the first switch unit S1 is a field effect transistor, the first withstand voltage diode D1 and the first transient voltage suppression diode D2 are electrically connected between the gate and source terminals of the field effect transistor, and the voltage between the gate and source terminals of the bipolar transistor is clamped at the required negative voltage position through the TVS, thereby improving the reliability of the system.

[0059] The above is the connection method of the half-bridge circuit.

[0060] The working principle of the negative voltage Miller spike suppression circuit is: under normal working conditions of the half bridge, that is, Figure 2 In the absence of the first suppression unit, the negative voltage drop V is generally generated by the driving circuit on both sides of the gate source of the first switch unit that is not turned on. off (characteristic value 0~-5V) turns off the chip completely. The change of current path causes parasitic inductance to generate an induced negative voltage drop V L , where V L Calculation method:

[0061]

[0062] Among them I DS is the current of the half bridge. When V L With V off If the sum is too high, the reliability of the power semiconductor chip will be reduced. The TVS tube in the half-bridge circuit has an avalanche breakdown voltage drop V Z With the forward conduction voltage drop of the withstand diode V F (Characteristic value 0.2~0.6V). When the negative voltage drop is higher than the sum of the avalanche breakdown voltage drop of the TVS tube and the forward conduction voltage drop of the withstand diode, that is,

[0063] |V off |+|V L |>V Z +V F (2)

[0064] The TVS tube is in avalanche breakdown state, and the withstand voltage diode is forward-conducting, ensuring that the gate voltage of the power semiconductor chip and the corresponding source voltage meet the corresponding relationship, that is,

[0065] V GS_OFF =-(V Z +V F ) (3)

[0066] Among them, the turn-off voltage between the gate and the source is V GS_OFF The function of the withstand voltage diode is that when the power semiconductor chip is turned on, the withstand voltage diode is in a reverse blocking state to ensure that the power semiconductor chip is effectively turned on. Therefore, the voltage values ​​of the two diodes should be selected to meet the following requirements:

[0067] V GS_R >V Z +V F >|V off | (4)

[0068] V R >V GS_ON (5)

[0069] Among them, V R V is the maximum peak reverse voltage that the withstand diode can withstand continuously, obtained from the datasheet. GS_R The maximum negative voltage that the gate of the power semiconductor chip can withstand is obtained from the datasheet. GS_ON It is the gate-source voltage when the first switch unit is turned on. The withstand voltage diode and TVS tube are both inside the module, very close to the gate-source ends of the power semiconductor chip, and the introduced parasitic inductance is smaller, which can better suppress the negative voltage Miller spike.

[0070] For example, when the second switch unit S2 is turned off, the first switch unit S1 generates an induced electromotive force due to the first inductor L2 (a parasitic inductor), so that the gate-source voltage is -10V, and the negative voltage between the gate and the source is too large; the second transient voltage suppression diode D2 is introduced, and the breakdown voltage is selected to be 4.7V. The first withstand voltage diode D1 is introduced, and appropriate parameters are selected to make the forward conduction voltage of D1 0.6V. Then the -10V gate-source voltage is clamped at -5.3V due to the reverse breakdown of D2 and the forward conduction of D1.

[0071] Since the half-bridge circuit is used in the power module, the withstand voltage diode and TVS tube are generally set on the PCB board outside the module. Since the two diodes are connected to the gate and source of the switch unit respectively, the flexibility of the PCB layout is affected; the DC+, DC-, and AC ports of most power modules have large spacing, which further increases the space occupied by the half-bridge circuit. For the half-bridge circuit itself, the withstand voltage diode and TVS tube flow through longer wires, which increases the delay; the half-bridge circuit is connected in parallel with the gate and source of the power semiconductor chip, and the long-distance wires or the metallization layer paths of the module will generate parasitic inductance, which weakens the suppression effect.

[0072] Half-bridge circuits used in power modules generally have problems such as occupying a large space and being unable to be close to power semiconductor chips. The present application provides a layout structure of a half-bridge circuit on a power module.

[0073] Figure 4 is another circuit connection diagram of the half-bridge circuit provided in the embodiment of the present application, such as Figure 4 As shown, the half-bridge circuit is integrated in the power module, and the power module includes a stacked substrate and a first metal layer; the first metal layer includes a first metal area J1, a second metal area J2, a third metal area J3, a fourth metal area J4, a fifth metal area J5, a sixth metal area J6 and a seventh metal area J7; along the first direction of the power module, the first metal area J1, the second metal area J2, the third metal area J3, the fourth metal area J4, the fifth metal area J5, the sixth metal area J6 and the seventh metal area J7 are arranged alternately. It should be noted that Figure 4The invention relates to a design of a metal pattern of a half-bridge circuit.

[0074] Figure 5 This is another circuit connection diagram of the half-bridge circuit provided in the embodiment of the present application, which is a layout structure of the half-bridge circuit in application.

[0075] The disadvantage of setting a Miller clamp in the driving circuit is that the suppression effect is weakened due to the increase of circuit parasitic inductance. The present application integrates a half-bridge circuit into the module, which can better suppress the negative voltage Miller spike.

[0076] Combination Figure 4 , Figure 5 and Figure 6 From the perspective of FIG. 1 , a first bare die is provided on the first metal region J1, the first bare die includes a first transient voltage suppression diode D2, and the cathode of the first transient voltage suppression diode D2 is electrically connected to the first metal region J1; a second bare die is provided on the second metal region J2, the second bare die includes a first withstand voltage diode D1, the cathode of the first withstand voltage diode D1 is electrically connected to the second metal region J2; the anode of the first transient voltage suppression diode D2 is electrically connected to the anode of the first withstand voltage diode D1; at least one third bare die is provided on the third metal region J3, the third bare die includes a first transistor S1, the drain of the first transistor S1 is electrically connected to the third metal region J3, the gate of the first transistor S1 is electrically connected to the second metal region J2, the source of the first transistor S1 is electrically connected to the first metal region J1, and the third metal region J3 is electrically connected to the positive voltage DC terminal DC+; the third bare die includes a first transistor S1, the drain of the first transistor S1 is electrically connected to the third metal region J3, the gate of the first transistor S1 is electrically connected to the second metal region J2, the source of the first transistor S1 is electrically connected to the first metal region J1, and the third metal region J3 is electrically connected to the positive voltage DC terminal DC+; At least one fourth bare chip is provided on the fourth metal region J4, and the fourth bare chip includes a second transistor S2, the drain of the second transistor S2 is electrically connected to the fourth metal region J4, and the fourth metal region J4 is electrically connected to the AC end AC; the fifth metal region J5 is electrically connected to the negative voltage DC end DC-, and the fifth metal region J5 is electrically connected to the source of the second transistor S2; the sixth metal region J6 is provided with a fifth bare chip, and the fifth bare chip includes a second withstand voltage diode D3, the cathode of the second withstand voltage diode D3 is electrically connected to the sixth metal region J6, and the sixth metal region J6 is electrically connected to the gate of the second transistor S2; the seventh metal region J7 is provided with a sixth bare chip, and the sixth bare chip includes a second transient voltage suppression diode D4, the cathode of the second transient voltage suppression diode D4 is electrically connected to the seventh metal region J7, and the seventh metal region J7 is electrically connected to the source of the second transistor S2.

[0077] It should be noted that Figure 6 The connection diagram of the half-bridge circuit provided is designed for the metal area of ​​the power module with Kelvin source.

[0078] It should be noted that the electrical connection methods described above are all electrical connections through bonding wires, and the connecting devices are all bare chips. Figure 8FIG. 1 is a schematic diagram of a bare chip structure provided in an embodiment of the present application. A diode bare chip is used to replace a packaged diode device. The power semiconductor chip, the withstand voltage diode and the TVS tube bare chip structure are as follows: Figure 8 As shown in the figure, the overall process includes the bonding and potting of the die, etc., this application will not introduce additional packaging processes.

[0079] In addition, the electrical connection between the bare chip and the metal area includes reflow soldering, conductive silver glue and (silver, copper) sintering and other methods.

[0080] exist Figure 6 The black line in the middle is the bonding wire. In practical applications, the bonding processes include thick aluminum wire, aluminum ribbon bonding, copper wire and copper ribbon bonding, etc. The dotted line is the current direction when a negative pressure Miller spike is generated. The enlarged effect diagram is shown in Figure 7 . Figure 7 It is a partially enlarged schematic diagram of the current flow direction when the suppression effect is formed in the half-bridge circuit provided in the embodiment of the present application.

[0081] In some embodiments, the minimum distance between the first metal region J1 and the second metal region J2 along the first direction is smaller than the minimum distance between the second metal region J2 and the third metal region J3 along the first direction, and / or the minimum distance between the sixth metal region J6 and the seventh metal region J7 along the first direction is smaller than the minimum distance between the fifth metal region J5 and the sixth metal region J6 along the first direction.

[0082] In some embodiments, the area of ​​the third metal region J3 is greater than the area of ​​at least one of the first metal region J1, the second metal region J2, the sixth metal region J6 and the seventh metal region J7; the area of ​​the fifth metal region J5 is greater than the area of ​​at least one of the first metal region J1, the second metal region J2, the sixth metal region J6 and the seventh metal region J7.

[0083] The third metal region J3 and the fifth metal region J5 are designed to be large in area for convenient electrical connection with the external positive voltage DC terminal DC+ and the negative voltage DC terminal DC-.

[0084] Fig. 9 The embodiment of the present application provides Figure 7 A schematic longitudinal cross-sectional view of the buffer circuit portion obtained by taking a cross section along the dotted line path is shown in FIG. Fig. 9 As shown, the power module may include a stacked metallization layer on an insulating substrate, an insulating substrate, and a metallization layer under an insulating substrate.

[0085] Fig.10 is another circuit connection diagram of the half-bridge circuit provided in the embodiment of the present application, such as Fig.10 As shown, combined Figure 3From the perspective of FIG. 1 , the second metal region J2 includes a first sub-metal region J2' and at least one second sub-metal region J2", and the second bare chip is arranged in the second sub-metal region J2"; along the first direction, the first sub-metal region J2' and the second sub-metal region J2" are arranged between the first metal region and the third metal region, a first gate resistor R1 is arranged on the second sub-metal region J2", a first end of the first gate resistor R1 is electrically connected to the second sub-metal region J2", a second end of the first gate resistor R1 is electrically connected to the first sub-metal region J2', a cathode of the first withstand voltage diode is electrically connected to the second sub-metal region J2", an anode of the first withstand voltage diode is electrically connected to an anode of the first transient voltage suppression diode, and the second sub-metal region J2" is electrically connected to the cathode of the first withstand voltage diode. The metal region J2" is electrically connected to the gate of the first transistor; the sixth metal region includes at least a third sub-metal region and a fourth sub-metal region, and the fifth bare chip is arranged in the third sub-metal region; along the first direction, the third sub-metal region and the fourth sub-metal region are arranged between the fifth metal region and the seventh metal region, a second gate resistor R2 is arranged on the third sub-metal region, a first end of the second gate resistor R2 is electrically connected to the third sub-metal region, and a second end of the second gate resistor R2 is electrically connected to the seventh metal region; a cathode of the second withstand voltage diode is electrically connected to the third sub-metal region, an anode of the second withstand voltage diode is electrically connected to an anode of the second transient voltage suppression diode, and the third sub-metal region is electrically connected to the gate of the second transistor.

[0086] It should be noted that Fig.10 The connection diagram of the half-bridge circuit provided is designed for the metal area of ​​the power module with Kelvin source and the gate resistor is integrated inside the power module.

[0087] As far as the power module trend is concerned, the gate resistor is integrated inside the power module. Since the gate resistor is very close to the gate of the power semiconductor chip, the parasitic inductance is reduced.

[0088] For this type of power module, adding a Miller clamp circuit to the driver PCB cannot provide a low-impedance path, and the Miller clamp is difficult to work effectively. In the present application, the lower surface of the first voltage-resistant diode bare chip of the first bridge arm is mounted on the integrated second sub-metal area J2", and the upper surface of the first voltage-resistant diode is connected to the upper surface of the TVS tube through a bonding wire. The half-bridge circuit of the present application effectively reduces the parasitic inductance of the circuit before the gate resistor, and the suppression of negative voltage is more obvious. The number of first transistors in the first bridge arm determines the number of graphics in the second sub-metal area J2", and each second sub-metal area J2" has a voltage-resistant diode. For power modules with a high parallel number, multiple TVS tubes can be connected in parallel.

[0089] Fig.11 is another circuit connection diagram of the half-bridge circuit provided in the embodiment of the present application, such as Fig.11As shown, the first switch unit includes a first transistor, the second switch unit includes a second transistor, and the power module includes a stacked substrate and a first metal layer.

[0090] The first metal layer includes an eighth metal region J8, a ninth metal region J9, a tenth metal region J10, an eleventh metal region J11, and a twelfth metal region J12; along the first direction of the power module, the eighth metal region J8, the ninth metal region J9, the tenth metal region J10, the eleventh metal region J11, and the twelfth metal region J12 are arranged at intervals; a seventh bare chip is provided on the eighth metal region J8, the seventh bare chip includes a first transient voltage suppression diode D2, and the cathode of the first transient voltage suppression diode D2 is electrically connected to the eighth metal region J8; the ninth metal region J9 is provided with at least one eighth bare chip, the eighth bare chip includes a first transistor S1, the drain of the first transistor S1 is electrically connected to the ninth metal region J9, the gate of the first transistor S1 is electrically connected to the eighth metal region J8, and the ninth metal region J9 is electrically connected to the positive voltage DC terminal DC+; a There are a ninth bare chip and at least one tenth bare chip, the ninth bare chip includes a first transient voltage suppression diode D2, the cathode of the first transient voltage suppression diode D2 is electrically connected to the tenth metal area J10, the tenth bare chip includes a second transistor S2, and the tenth metal area J10 is electrically connected to the AC end AC; an eleventh bare chip is provided on the eleventh metal area J11, the eleventh bare chip includes a second transient voltage suppression diode D4, the cathode of the second transient voltage suppression diode D4 is electrically connected to the eleventh metal area J11, and the eleventh metal area J11 is electrically connected to the negative voltage DC end DC-; a ​​twelfth bare chip is provided on the twelfth metal area J12, the twelfth bare chip includes a second withstand voltage diode D3, the cathode of the second withstand voltage diode D3 is electrically connected to the twelfth metal area J12, and the anode of the second withstand voltage diode D3 is electrically connected to the anode of the second transient voltage suppression diode D4.

[0091] It should be noted that Fig.11 The connection diagram of the half-bridge circuit provided is designed for the metal area of ​​the power module without Kelvin source. The design of the metal area of ​​the power module without Kelvin source is not limited to Fig.11 One, not listed here one by one.

[0092] Fig.12 is another circuit connection diagram of the half-bridge circuit provided in the embodiment of the present application, such as Fig.12 As shown, the first switch unit includes a first transistor S1, the second switch unit includes a second transistor S2, and the power module includes a stacked substrate and a first metal layer;

[0093] The first metal layer includes a thirteenth metal region J13, a fourteenth metal region J14, a fifteenth metal region J15, a sixteenth metal region J16, a seventeenth metal region J17, an eighteenth metal region J18, a nineteenth metal region J19 and a twentieth metal region J20; the thirteenth metal region J13 is electrically connected to the AC end AC; at least one thirteenth bare chip is provided on the fourteenth metal region J14, the thirteenth bare chip includes a first transistor S1, the source of the first transistor S1 is electrically connected to the thirteenth metal region J13, the drain of the first transistor S1 is electrically connected to the fourteenth metal region J14, and the fourteenth metal region J14 is electrically connected to the positive voltage DC end DC+; the fifteenth bare chip is provided on the fifteenth metal region J15, the fourteenth bare chip includes a first withstand voltage diode D1, the cathode of the first withstand voltage diode D1 is electrically connected to the fifteenth metal region J15; the fifteenth bare chip is provided on the sixteenth metal region J16, the fifteenth bare chip includes a first transient voltage suppression diode D2, the first transient voltage suppression The cathode of the diode D2 is electrically connected to the sixteenth metal region J16, and the anode of the first transient voltage suppression diode D2 is electrically connected to the anode of the fourteenth bare chip; the seventeenth metal region J17 is electrically connected to the negative voltage DC terminal DC-; at least one sixteenth bare chip is provided on the eighteenth metal region J18, and the sixteenth bare chip includes a second transistor S2, the source of the second transistor S2 is electrically connected to the seventeenth metal region J17, and the drain of the second transistor S2 is electrically connected to the eighteenth metal region J18; the seventeenth bare chip is provided on the nineteenth metal region J19, and the seventeenth bare chip includes a second withstand voltage diode D3, and the cathode of the second withstand voltage diode D3 is electrically connected to the nineteenth metal region J19; the eighteenth bare chip is provided on the twentieth metal region J20, and the eighteenth bare chip includes a second transient voltage suppression diode D4, the cathode of the second transient voltage suppression diode D4 is electrically connected to the twentieth metal region J20, and the anode of the second transient voltage suppression diode D4 is electrically connected to the anode of the second withstand voltage diode D3.

[0094] It should be noted that Fig.12 What is provided is the metal area design of the power module with Kelvin source. The metal area design of the power module with Kelvin source is not limited to Figure 6 , Fig.10 and Fig.12 , which are not listed here one by one.

[0095] Fig.13 The embodiment of this application provides Fig.12 A partial enlarged schematic diagram of the current flow direction when the half-bridge circuit in FIG. 4 forms an inhibitory effect.

[0096] The structural design layout in this application is as follows Figure 6 , Fig.10 , Fig.11 and Fig.12 As shown, Fig.11For power modules without Kelvin sources, the half-bridge circuit can still achieve the negative voltage Miller spike suppression function by changing the position of the TVS tube at the Kelvin source from the Kelvin source line copper to the source copper of the power semiconductor chip. At this time, the current loop distance from the TVS tube to the corresponding power semiconductor chip should be as short as possible to achieve the purpose of reducing the parasitic inductance of this section.

[0097] In the present application, the first transistor, the second transistor, the withstand voltage diode, and the transient voltage suppression diode can be connected in the same manner, and the connection with the metallized pattern can be selected by mounting processes such as silver glue bonding, solder paste reflow soldering, and silver sintering. The connection between the upper surface of the first transistor, the second transistor, and the diode (including the withstand voltage diode and transient voltage diode in the present application) and the metallized pattern can be selected by wire bonding (aluminum wire, copper wire), copper sheet welding, conductive film welding, and other processes. The connection between the terminal and the metallized layer of the insulating substrate can be selected by wire bonding (aluminum wire, copper wire), reflow soldering, laser welding, etc. to directly connect the terminal to the metallized layer.

[0098] Fig.14 It is a schematic diagram of the internal structure and electrical connection of the module with integrated gate resistors and half-bridge circuits through PCB. The PCB inside the power module is usually bonded to an insulating substrate, on which a metallization pattern is drawn through a pad. 25. First bridge arm PCB pattern, 26. First bridge arm gate pad pattern, 27. First bridge arm integrated resistor pad pattern, 28. First bridge arm PCB Kelvin source pad pattern, 29. Second bridge arm PCB pattern, 30. Second bridge arm gate pad pattern, 31. Second bridge arm integrated resistor pad pattern, 32. Second bridge arm PCB Kelvin source pad pattern.

[0099] For power modules with internally bonded PCBs, the internal structure and electrical connection diagram are as follows: Fig.14 As shown. The gate of the first transistor of the first bridge arm of the internally bonded PCB is connected to the metallized pattern 27 on the PCB board through a bonding wire, and the metallized pattern 27 is a pad on the PCB board. It should be noted that the metallized pattern 27 is respectively connected to the bonding wire of the gate, the lower surface of the first withstand diode, and one end of the first gate resistor. On the basis of ensuring the electrical connection, the metallized pattern can be replaced to suit the metallized pattern in the power module, or PCB ink can be added to the surface. The structure of the present application can also achieve good negative voltage Miller clamping suppression in the module bonded to the PCB board. At the same time, since the circuit is located before the gate circuit, the parasitic inductance in the module is reduced. Since the PCB is bonded inside the module, the packaged TVS tube and the withstand diode can be welded to the PCB, but the chip pins will introduce parasitic inductance. In comparison, reflow soldering of the diode bare chip is more suitable.

[0100] In addition, an embodiment of the present application further provides a power module, comprising the half-bridge circuit as described above.

[0101] It should be noted that the bare chips of the components of the half-bridge circuit in the present application are connected to the metal area in the power module instead of soldering the traditional circuit components on the PCB, thereby enhancing the performance of the circuit.

[0102] In addition, the half-bridge circuit mentioned in the present application is adaptable to different power modules and different situations (with or without Kelvin source metal area, with or without gate resistor metal area, etc.), rather than just the exemplified metallization patterns.

[0103] In general, the present application proposes a layout design scheme for integrating a half-bridge circuit on the metallized surface of the upper layer of the insulating substrate inside the power module. By using bare chips of withstand voltage diodes and TVS tubes instead of packaged devices, the Miller spike suppression function is realized on the insulating substrate. This internal structure has the characteristics of small volume, high integration and strong reliability; at the same time, the Miller spike suppression circuit itself has a short line and is very close to the power semiconductor chip, and will not introduce more circuit parasitic inductance to produce a larger negative voltage Miller spike; it is applicable to the metallized graphics of different power modules. Since the diode chip installation process in the half-bridge circuit adopts chip mounting, wire bonding, potting and other processes that are consistent with the packaging power module process, adding this Miller spike suppression circuit will not add additional processes in production, and has good production adaptability.

[0104] The advantages of the present application are: (1) the present application directly integrates a half-bridge circuit inside the power module to reduce the impact of voltage overshoot caused by commutation on device reliability. (2) The half-bridge circuit is very close to the gate and source of the power semiconductor chip, reducing the impact of parasitic inductance on the Miller clamping effect. (3) The bare die of a withstand voltage diode and a TVS tube is used instead of a packaged diode to achieve the negative voltage Miller spike suppression function on an insulating substrate with only a single layer of metallization pattern. (4) The packaging process used in the half-bridge circuit is the same as the packaging process of the power semiconductor chip, and no additional process steps are introduced in the module production. (5) The position of the withstand voltage diode and the TVS tube can be replaced, but the mounting direction of the cathode and anode of the withstand voltage diode and the TVS tube is changed accordingly. (6) For power module products with integrated internal gate resistors, an excellent negative voltage Miller clamping effect can still be achieved.

[0105] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0106] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electrical module, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), appropriate firmware, plug-in, function card, etc. When implemented in software, the elements of the present application are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or communication link by a data signal carried in a carrier. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electrical modules, semiconductor memory devices, read-only memories (Read-Only Memory, ROM), flash memory, erasable read-only memories (Erasable ReadOnly Memory, EROM), floppy disks, compact discs (Compact Disc Read-Only Memory, CD-ROM), optical discs, hard disks, optical fiber media, radio frequency (Radio Frequency, RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0107] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0108] Aspects of the present disclosure are described above with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0109] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A half-bridge circuit, characterized in that: Integrated in the power module, the half-bridge circuit includes a first bridge arm and a second bridge arm, the first bridge arm is electrically connected between the positive voltage DC terminal and the AC terminal, and the second bridge arm is electrically connected between the negative voltage DC terminal and the AC terminal; The first bridge arm comprises: A first switch unit, wherein a first end of the first switch unit is electrically connected to the positive voltage DC end, and a second end of the first switch unit is electrically connected to the AC end; a first inductor, wherein a first end of the first inductor is electrically connected to a second end of the first switch unit; A first suppression unit, wherein the first end of the first suppression unit is electrically connected to the second end of the first inductor, the second end of the first suppression unit is electrically connected to the control end of the first switch unit, and the first suppression unit is used to suppress the negative pressure between the control end of the first switch unit and the second end of the first switch unit.

2. The half-bridge circuit according to claim 1, characterized in that: The first switch unit includes a first transistor, and the first suppression unit includes: a first withstand voltage diode, wherein a cathode of the first withstand voltage diode is electrically connected to a control end of the first switch unit; A first transient voltage suppressor diode, wherein an anode of the first transient voltage suppressor diode is electrically connected to an anode of the first withstand voltage diode, and a cathode of the first transient voltage suppressor diode is electrically connected to a second end of the first inductor.

3. The half-bridge circuit according to claim 2, characterized in that: The second bridge arm comprises: a second switch unit, wherein a first end of the second switch unit is electrically connected to the AC end, and a second end of the second switch unit is electrically connected to the negative voltage DC end; a second inductor, wherein a first end of the second inductor is electrically connected to a second end of the second switch unit and the negative voltage DC end; A second suppression unit, wherein the first end of the second suppression unit is electrically connected to the second end of the second inductor, the second end of the second suppression unit is electrically connected to the control end of the second switch unit, and the second suppression unit is used to suppress the negative pressure between the control end of the second switch unit and the second end of the second switch unit.

4. The half-bridge circuit according to claim 3, characterized in that: The second switch unit includes a second transistor, and the second suppression unit includes: a second withstand voltage diode, wherein a cathode of the second withstand voltage diode is electrically connected to a control end of the second switch unit; A second transient voltage suppression diode, wherein an anode of the second transient voltage suppression diode is electrically connected to an anode of the second withstand voltage diode, and a cathode of the second transient voltage suppression diode is electrically connected to a second end of the second inductor.

5. The half-bridge circuit according to claim 4, characterized in that: The first switch unit includes a first transistor, the second switch unit includes a second transistor, and the power module includes a stacked substrate and a first metal layer; The first metal layer includes a first metal region, a second metal region, a third metal region, a fourth metal region, a fifth metal region, a sixth metal region and a seventh metal region; Along a first direction of the power module, the first metal region, the second metal region, the third metal region, the fourth metal region, the fifth metal region, the sixth metal region and the seventh metal region are arranged at intervals; A first bare die is disposed on the first metal region, the first bare die includes a first transient voltage suppression diode, and a cathode of the first transient voltage suppression diode is electrically connected to the first metal region; A second bare chip is disposed on the second metal region, the second bare chip includes a first withstand voltage diode, a cathode of the first withstand voltage diode is electrically connected to the second metal region; an anode of the first transient voltage suppression diode is electrically connected to an anode of the first withstand voltage diode; At least one third bare chip is disposed on the third metal area, the third bare chip includes the first transistor, the drain of the first transistor is electrically connected to the third metal area, the gate of the first transistor is electrically connected to the second metal area, the source of the first transistor is electrically connected to the first metal area, and the third metal area is electrically connected to the positive voltage DC terminal; At least one fourth bare chip is disposed on the fourth metal area, the fourth bare chip includes the second transistor, the drain of the second transistor is electrically connected to the fourth metal area, and the fourth metal area is electrically connected to the AC end; The fifth metal region is electrically connected to the negative voltage DC terminal, and the fifth metal region is electrically connected to the source of the second transistor; A fifth bare chip is disposed on the sixth metal region, the fifth bare chip includes a second withstand voltage diode, a cathode of the second withstand voltage diode is electrically connected to the sixth metal region, and the sixth metal region is electrically connected to a gate of the second transistor; A sixth bare chip is disposed on the seventh metal region. The sixth bare chip includes a second transient voltage suppression diode. A cathode of the second transient voltage suppression diode is electrically connected to the seventh metal region. The seventh metal region is electrically connected to a source of the second transistor.

6. The half-bridge circuit according to claim 5, characterized in that: The minimum distance between the first metal region and the second metal region along the first direction is smaller than the minimum distance between the second metal region and the third metal region along the first direction, and / or the minimum distance between the sixth metal region and the seventh metal region along the first direction is smaller than the minimum distance between the fifth metal region and the sixth metal region along the first direction.

7. The half-bridge circuit according to claim 5, characterized in that: The area of ​​the third metal region is greater than the area of ​​at least one of the first metal region, the second metal region, the sixth metal region, and the seventh metal region; An area of ​​the fifth metal region is greater than an area of ​​at least one of the first metal region, the second metal region, the sixth metal region, and the seventh metal region.

8. The half-bridge circuit according to claim 5, characterized in that: The second metal region includes a first sub-metal region and at least one second sub-metal region, and the second bare chip is arranged in the second sub-metal region; along the first direction, the first sub-metal region and the second sub-metal region are arranged between the first metal region and the third metal region, a first gate resistor is arranged on the second sub-metal region, a first end of the first gate resistor is electrically connected to the second sub-metal region, a second end of the first gate resistor is electrically connected to the first sub-metal region, a cathode of the first withstand voltage diode is electrically connected to the second sub-metal region, an anode of the first withstand voltage diode is electrically connected to an anode of the first transient voltage suppression diode, and the second sub-metal region is electrically connected to the gate of the first transistor; The sixth metal region includes at least a third sub-metal region and a fourth sub-metal region, and the fifth die is disposed in the third sub-metal region; Along the first direction, the third sub-metal region and the fourth sub-metal region are arranged between the fifth metal region and the seventh metal region, a second gate resistor is arranged on the third sub-metal region, a first end of the second gate resistor is electrically connected to the third sub-metal region, and a second end of the second gate resistor is electrically connected to the seventh metal region; A cathode of the second withstand voltage diode is electrically connected to the third sub-metal region, an anode of the second withstand voltage diode is electrically connected to an anode of the second transient voltage suppression diode, and the third sub-metal region is electrically connected to a gate of the second transistor.

9. The half-bridge circuit according to claim 4, characterized in that: The first switch unit includes a first transistor, the second switch unit includes a second transistor, and the power module includes a stacked substrate and a first metal layer; The first metal layer includes an eighth metal region, a ninth metal region, a tenth metal region, an eleventh metal region, and a twelfth metal region; Along the first direction of the power module, the eighth metal region, the ninth metal region, the tenth metal region, the eleventh metal region and the twelfth metal region are arranged at intervals; A seventh bare chip is disposed on the eighth metal region, the seventh bare chip includes a first transient voltage suppression diode, and a cathode of the first transient voltage suppression diode is electrically connected to the eighth metal region; The ninth metal region is provided with at least one eighth bare chip, the eighth bare chip includes the first transistor, the drain of the first transistor is electrically connected to the ninth metal region, the gate of the first transistor is electrically connected to the eighth metal region, and the ninth metal region is electrically connected to the positive voltage DC terminal; A ninth die and at least one tenth die are disposed on the tenth metal region, the ninth die includes a first transient voltage suppression diode, a cathode of the first transient voltage suppression diode is electrically connected to the tenth metal region, the tenth die includes the second transistor, and the tenth metal region is electrically connected to the AC terminal; An eleventh bare chip is disposed on the eleventh metal region, the eleventh bare chip includes a second transient voltage suppression diode, a cathode of the second transient voltage suppression diode is electrically connected to the eleventh metal region, and the eleventh metal region is electrically connected to the negative voltage DC terminal; A twelfth bare chip is disposed on the twelfth metal region. The twelfth bare chip includes a second withstand voltage diode. A cathode of the second withstand voltage diode is electrically connected to the twelfth metal region. An anode of the second withstand voltage diode is electrically connected to an anode of the second transient voltage suppression diode.

10. The half-bridge circuit according to claim 4, characterized in that: The first switch unit includes a first transistor, the second switch unit includes a second transistor, and the power module includes a stacked substrate and a first metal layer; The first metal layer includes a thirteenth metal region, a fourteenth metal region, a fifteenth metal region, a sixteenth metal region, a seventeenth metal region, an eighteenth metal region, a nineteenth metal region and a twentieth metal region; The thirteenth metal region is electrically connected to the AC end; At least one thirteenth bare chip is disposed on the fourteenth metal region, the thirteenth bare chip includes the first transistor, the source of the first transistor is electrically connected to the thirteenth metal region, the drain of the first transistor is electrically connected to the fourteenth metal region, and the fourteenth metal region is electrically connected to the positive voltage DC terminal; A fourteenth bare chip is disposed on the fifteenth metal region, the fourteenth bare chip includes a first withstand voltage diode, and a cathode of the first withstand voltage diode is electrically connected to the fifteenth metal region; A fifteenth bare chip is disposed on the sixteenth metal region, the fifteenth bare chip comprises a first transient voltage suppression diode, a cathode of the first transient voltage suppression diode is electrically connected to the sixteenth metal region, and an anode of the first transient voltage suppression diode is electrically connected to an anode of the fourteenth bare chip; The seventeenth metal area is electrically connected to the negative voltage DC terminal; At least one sixteenth die is disposed on the eighteenth metal region, the sixteenth die includes the second transistor, a source of the second transistor is electrically connected to the seventeenth metal region, and a drain of the second transistor is electrically connected to the eighteenth metal region; A seventeenth bare chip is disposed on the nineteenth metal region, the seventeenth bare chip includes a second withstand voltage diode, and a cathode of the second withstand voltage diode is electrically connected to the nineteenth metal region; An eighteenth bare chip is disposed on the twentieth metal region, and the eighteenth bare chip includes a second transient voltage suppressor diode, a cathode of the second transient voltage suppressor diode is electrically connected to the twentieth metal region, and an anode of the second transient voltage suppressor diode is electrically connected to an anode of the second withstand voltage diode.

11. A power module, characterized in that: The method comprises the half-bridge circuit as claimed in any one of claims 1 to 10.

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