Power synthesis circuit based on multi-channel radio frequency phase-locked loop and self-correction method

Abstract

The invention discloses a power synthesis circuit based on a multi-channel radio frequency phase-locked loop. The power synthesis circuit comprises a signal control and signal processor, a synchronous reference clock, a multi-channel emission signal generation circuit, a self-correction circuit and a multi-channel emission antenna, the transmitting signal generating circuit comprises a radio frequency phase-locked loop, a driving amplifier, a DSA digital control attenuator and a power amplifier, and a delay control unit is arranged in the radio frequency phase-locked loop and used for delay phase tuning; and the self-correction circuit performs self-correction by using the frequency mixing and ADC sampling circuit. In addition, the invention further discloses a self-correction method based on the multi-channel radio frequency phase-locked loop, and the multi-channel radio frequency phase-locked loop is automatically calibrated by adopting the power synthesis circuit. According to the invention, power synthesis is carried out by using the irrelevance of the output signals of the multi-channel radio frequency phase-locked loop, so that the signal-to-noise ratio is improved and the quality of the transmitted signal is improved on the premise of improving the channel synthesis transmitting power.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a power synthesis circuit and a self-correction method based on a multi-channel radio frequency phase-locked loop. Background Art

[0002] Frequency synthesizers are widely used in wireless communications, radar systems, and electronic countermeasures. The quality of the RF transmission signal in the frequency synthesizer is the core of the radar communication system and directly affects the communication and detection distance of the system. Its main function is to generate the required RF signal through the frequency synthesizer, and then transmit the signal through the antenna through filtering, phase shifting, attenuation, and amplification. Power synthesis can increase the power of the transmitted signal and greatly increase the signal transmission distance. Therefore, the efficiency of power synthesis and signal quality have a great impact on the overall indicators of the transmission system.

[0003] When there are ultra-low-altitude flying objects, the radar will face strong ground clutter. If you want to extract the target's reflected signal from the clutter, you need to increase the radar's improvement factor. Because when the clutter signal enters the receiving unit, after mixing, it is difficult to separate the useful signal from the strong clutter reflection signal. Especially for low-speed targets and when the target is close to the ground, it is more difficult to detect the target. Therefore, it can only be achieved by increasing the radar's improvement factor. In order to improve the radar's detection capability for low-altitude targets, the low phase noise of the signal becomes very important. In general, the phase noise of the transmitted signal, clutter suppression, and the background noise of the signal directly affect the detection capability of the radar system. Figure 4 The figure shows a schematic diagram of the structure of a traditional multi-channel transmission link. The RF phase-locked loop is controlled by a signal controller to generate a set frequency. After passing through a power amplifier, a power divider is used to generate an output signal. The transmission signal of each channel is then driven by an amplifier, a phase shifter, and a power amplifier. Finally, the RF signal is transmitted through an antenna to achieve spatial synthesis of the transmission signal. In this implementation method, since there is only one transmission signal source, when each signal is synthesized, due to the influence of the signal self-phase modulation, the signal power is weighted when it is synthesized and amplified, and the noise floor is correspondingly increased. Combined with the saturated output of the amplifier, the phase shift and the synthesis phase accuracy, the signal-to-noise ratio of the transmission signal is conservatively estimated to be 2 to 3 dB deteriorated, and the power synthesis circuit based on discrete devices has great disadvantages in terms of system volume, synthesis efficiency, calibration difficulty, system cost and signal quality.

[0004] Currently, routine Figure 4 The multi-channel power synthesis method shown has the following main problems: 1) The transmission signal is completely determined by a single transmission frequency source. Due to the single transmission frequency source, its signal-to-noise ratio and phase noise will not be improved during power amplification and synthesis. On the contrary, due to factors such as amplifier noise, nonlinear Kerr effect and amplifier saturation output, its signal-to-noise ratio and phase noise will deteriorate by 2 to 3 dB. Therefore, it is not conducive to long-distance detection of radar.

[0005] 2) The power synthesis efficiency of the transmitted signal is low, the calibration accuracy is not high, and the calibration workload is large. In the traditional power synthesis method, since the power synthesis is performed through the phase shifter, the phase shifter will first introduce new noise interference. At the same time, the phase shifter has low phase shifting accuracy in the broadband working mode, and the insertion loss of the phase shifter is large. The amplifier gain at the back end of the phase shifter must be increased by more than 5dB to compensate for the loss of the phase shifter. Therefore, the system synthesis power efficiency will be reduced. Since each system is calibrated in the field or antenna darkroom and corrected according to the test data, the technical level of the calibration personnel is high, and the calibration work is cumbersome and time-consuming.

[0006] 3) The system cost and volume are high. The traditional transmission system has a link composed of many discrete devices, and each unit circuit is composed of multiple chips. This method not only causes the system volume and power consumption to be large, but also the system cost is extremely high, which is extremely unfavorable for the mass production of the system. Summary of the invention

[0007] In view of the above-mentioned problems, the present invention aims to propose a power synthesis circuit and self-correction method based on a multi-channel radio frequency phase-locked loop, which utilizes the non-correlation of the multi-channel phase-locked loop to effectively reduce the noise of the synthesized signal and improve the signal-to-noise ratio of the signal; at the same time, a delay control unit is used in the radio frequency phase-locked loop to replace the phase shifter in the prior art, and through multi-channel phase synchronization, the channel loss caused by the phase shifter is avoided, the synthesis accuracy is improved, and the power synthesis efficiency is effectively improved; moreover, the amplitude and phase of the signal are monitored and automatically adjusted for each phase-locked loop, which improves the correction speed and efficiency while ensuring the calibration accuracy; in addition, the main part of the circuit is integrated on a 4mm×4mm chip, which greatly improves the system integration and reduces the system power consumption and cost.

[0008] This is achieved through the following technical solutions: In the first aspect, a power synthesis circuit based on a multi-channel radio frequency phase-locked loop is proposed, and the power synthesis circuit includes a signal control and signal processor, a synchronous reference clock, multiple groups of transmission signal generating circuits, a self-correction circuit and multiple transmission antennas; the synchronous reference clock provides the same reference clock for each group of transmission signal generating circuits; each group of transmission signal generating circuits is controlled by the signal control and signal processor, and each group of transmission signal generating circuits includes a radio frequency phase-locked loop, a driving amplifier, a DSA digitally controlled attenuator and a power amplifier connected in sequence, and the structure of each group of transmission signal generating circuits is the same; in each group of transmission signal generating circuits, the radio frequency phase-locked loop is connected to the synchronous reference clock and the signal control and signal processor respectively, the radio frequency phase-locked loop is used to generate a radio frequency signal, the driving amplifier is used to increase the power amplitude of the radio frequency signal to improve the driving capability, the DSA digitally controlled attenuator is used to control the radio frequency signal to adjust the amplitude, and the power amplifier is used to amplify the radio frequency signal power to the required transmission power; the self-correction circuit is used to sample and correct each group of transmission signal generating circuits, and the self-correction circuit includes a mixing and ADC sampling circuit, a switch selector and multiple couplers; each coupler is connected to the switch selector and is connected to the corresponding Each power amplifier; the switch selector is used to control the connection between the mixing and ADC sampling circuit and each coupler; wherein the mixing and ADC sampling circuit includes a calibration DSA, a mixer, a low-pass filter, an intermediate frequency amplifier and an ADC sampling circuit connected in sequence, and the mixer is also connected to a calibration RF phase-locked loop; the calibration DSA is used to adjust each power-amplified RF signal, and the mixer is used to down-convert each RF signal that has passed the calibration DSA and the local oscillator signal emitted by the calibration RF phase-locked loop to obtain each intermediate frequency signal; the low-pass filter is used to down-convert each intermediate frequency signal The IF amplifier is used to amplify each IF signal after low-pass filtering; the ADC sampling circuit is used to perform ADC sampling on each amplified IF signal to obtain each digital signal and transmit it to the signal control and signal processor; the signal control and signal processor automatically tunes the initial phase and amplitude of each RF signal based on each digital signal, controls the phase consistency of each RF signal, and transmits each RF signal with the same phase as each transmission signal to each corresponding transmission antenna after passing through each corresponding coupler, and then spatially synthesizes the signal transmitted by each transmission antenna.

[0009] By utilizing the non-correlation of multiple phase-locked loops, noise can be effectively reduced when transmitting multiple RF signals, and the signal-to-noise ratio of the final output signal can be improved. At the same time, a self-correction circuit is set to adjust and calibrate each RF signal, further improving the signal quality.

[0010] Preferably, the radio frequency phase-locked loop includes a reference input divider, a delay control unit 1, a phase detector, a loop filter, a voltage-controlled oscillator, a pre-divider, a 0 / 180° inverter, a programmable divider and a delay control unit 2. After the reference input divider receives the reference clock, it is sequentially connected to the delay control unit 1, the phase detector, the loop filter and the voltage-controlled oscillator; wherein the voltage-controlled oscillator has two outputs, the first of which is connected to the corresponding drive amplifier, and the second is used to form a negative feedback circuit structure of the phase-locked loop, and the negative feedback circuit structure is that the voltage-controlled oscillator then sequentially enters the pre-divider, 0 / 180° inverter, and the voltage-controlled oscillator enters the pre-divider, 0 / 180° inverter, and the voltage-controlled oscillator enters the programmable divider and the delay control unit 2. 180° inverter, programmable frequency divider and delay control unit 2 to phase detector; voltage controlled oscillator is used to generate RF signal, delay control unit 1 is used to adjust the phase of reference clock signal, phase detector is used to detect the reference clock and RF signal, loop filter is used to filter, pre-divider is used to adjust the frequency of RF signal passing through loop filter; delay control unit 2 cooperates with delay control unit 1, and controls the phase error of each RF signal transmitted through corresponding power amplifier and coupler within ±5.0° through signal control and signal processor. By using delay control, the RF signal can be effectively adjusted in phase with the reference clock and the RF signal of each channel can be synchronized. At the same time, the use of delay control unit saves the phase shifter, reduces channel power loss, reduces system power consumption, and this circuit optimization also improves the channel band flatness.

[0011] Preferably, the calibration radio frequency phase-locked loop is an independent phase-locked circuit, which is used to input the local oscillator signal to the mixer to drive the mixer to work. The intermediate frequency signal obtained by the mixer = local oscillator signal - radio frequency signal. The intermediate frequency signal meets the sampling frequency requirements of the ADC sampling circuit, and the local oscillator signal and the radio frequency signal form a fixed difference frequency. The ADC used by the ADC sampling circuit is a 14-bit high-speed digital-to-analog converter, which is used to collect the amplitude information of the intermediate frequency signal and convert it into a digital signal to send to the signal control and signal processor. The mixer can be used to convert the radio frequency signal into a low intermediate frequency signal, which is convenient for signal processing. The 14-bit high-speed digital-to-analog converter processing improves processing efficiency and speeds up system response.

[0012] Preferably, the signal control and signal processor include an analog-to-digital conversion unit, a digital down-conversion DDC unit, a CIC and FIR filter, a detector, a CPU and a signal controller connected in sequence; wherein the analog-to-digital conversion unit is used to convert each analog signal into each digital signal; the digital down-conversion DDC unit is used to perform down-conversion processing on each analog signal and obtain each down-conversion baseband signal; the CIC and FIR filter are used to perform CIC filtering and FIR filtering on each down-conversion baseband signal to obtain each filtered signal; the detector is used to extract each amplitude and phase information from the sub-process data contained in each filtered signal and transmit it to the CPU; the CPU selects one from multiple amplitude and phase information as the reference information, and compares the other amplitude and phase information with the reference information respectively to obtain each corresponding amplitude control signal and each delay control signal; the signal controller controls the corresponding RF signal of each channel to adjust the amplitude and delay according to each amplitude control signal and each delay control signal. The signal control and signal processor can effectively control and process the signal of each channel to realize the self-correction function.

[0013] Preferably, the parts of the self-correction circuit except each coupler and switch selector, the signal control and signal processor, and the parts of each group of transmission signal generation circuit except each power amplifier are integrated using CMOS technology and integrated on a 4mm×4mm chip. After integration using CMOS technology, it is convenient for large-scale production to reduce costs, and also saves the area required for the overall circuit to reduce overall power consumption.

[0014] In the second aspect, the present invention also proposes a self-correction method based on a multi-channel RF phase-locked loop, using any of the above-mentioned power synthesis circuits based on a multi-channel RF phase-locked loop, and the self-correction method includes the following steps: S1, the self-correction circuit uses a switch selector and multiple couplers to sequentially receive each RF signal in each group of transmission signal generating circuits, and uses a calibration DSA to dynamically adjust the power of each RF signal, and then enters the mixer and down-converts the local oscillator signal generated by the calibration RF phase-locked loop to an intermediate frequency to obtain an intermediate frequency signal; then the intermediate frequency signal is sequentially sent to an ADC sampling circuit through a low-pass filter and an intermediate frequency amplifier; S2, the intermediate frequency signal in step S1 is ADC sampled by the ADC sampling circuit, and the ADC sampled data is then transmitted through the LV The DS interface is sent to the signal control and signal processor; the signal control and signal processor first performs digital down-conversion and signal detection analysis based on the data sampled by the ADC, obtains multiple amplitude and phase data, and selects one of them as the reference data according to the multiple amplitude and phase data, compares the other amplitude and phase data with the reference data, generates corresponding multiple amplitude control instructions and multiple delay control instructions, and then transmits the multiple amplitude control instructions and multiple delay control instructions to the corresponding RF phase-locked loop for amplitude and phase consistency adjustment; S3, after completing the consistency adjustment in step S2, each RF signal is transmitted to each corresponding transmitting antenna in turn through each corresponding power amplifier and each corresponding coupler for transmission, and then the signal transmitted by each transmitting antenna is spatially synthesized. Self-correction is performed on each RF signal, which can effectively improve the power synthesis efficiency and signal-to-noise ratio of the final transmitted signal.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The technical solution of the present invention utilizes the non-correlation of multiple phase-locked loops to effectively reduce the noise of the synthesized signal and improve the signal-to-noise ratio of the signal; at the same time, a delay control unit is used in the radio frequency phase-locked loop to replace the phase shifter in the prior art, and through multi-channel phase synchronization, the channel loss caused by the phase shifter is avoided, the synthesis accuracy is improved, and the power synthesis efficiency is effectively improved; moreover, the amplitude and phase of the signal are monitored and automatically adjusted for each phase-locked loop, while ensuring the calibration accuracy, the correction speed and efficiency are also improved; in addition, the main part of the circuit is integrated on a 4mm×4mm chip, which greatly improves the system integration and reduces the system power consumption and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the structure of a power synthesis circuit based on a multi-channel radio frequency phase-locked loop; Figure 2 It is a structural schematic diagram of a radio frequency phase-locked loop; Figure 3 It is a structural schematic diagram of a mixing and ADC sampling circuit; Figure 4 is a schematic diagram of the structure of a traditional multi-channel transmission link; Figure 5 It is a schematic diagram of the structure inside a signal control and signal processor. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0018] like Figure 1 As shown, it is a structural schematic diagram of a power synthesis circuit based on a multi-channel RF phase-locked loop, which mainly includes a signal control and signal processor, a synchronous reference clock, multiple groups of transmission signal generation circuits, a self-correction circuit and multiple transmission antennas. The synchronous reference clock provides the same reference clock for each group of transmission signal generation circuits, which is convenient for synchronous control. Each group of transmission signal generation circuits is controlled by the signal control and signal processor. Each group of transmission signal generation circuits includes a RF phase-locked loop, a driving amplifier, a DSA digitally controlled attenuator and a power amplifier connected in sequence, and the structure of each group of transmission signal generation circuits is the same. In each group of transmission signal generation circuits, the RF phase-locked loop is connected to the synchronous reference clock and the signal control and signal processor respectively, the RF phase-locked loop is used to generate a RF signal, the driving amplifier is used to increase the power amplitude of the RF signal to improve the driving capability, the DSA digitally controlled attenuator is used to control the RF signal for amplitude adjustment, and the power amplifier is used to amplify the RF signal power to the required transmission power.

[0019] It should be noted that since the RF phase-locked loops of different paths are independent, that is, each RF signal and each corresponding noise are independent and uncorrelated, when the RF signals of multiple channels are finally synthesized, the noise will also be synthesized accordingly. Due to the non-correlation of the signals generated by the independent phase-locked loops, the multi-channel phase-locked loops will have the beneficial effect of improving the signal-to-noise ratio when performing power synthesis. Taking two-channel phase-locked loops as an example, the combined power of two ideal independent phase-locked circuits with the same power and phase will increase by 3dB when performing power synthesis, and the noise floor will not deteriorate, that is, the signal-to-noise ratio will be improved by 3dB; taking a four-channel phase-locked loop as an example, under ideal conditions, the signal-to-noise ratio of the four-channel phase-locked loop will be improved by 6dB, and the value of the signal-to-noise ratio improvement m and the number of channels n satisfy the following relationship: .

[0020] like Figure 2As shown, it is a schematic diagram of the structure of a radio frequency phase-locked loop, which includes a reference input divider, a delay control unit 1, a phase detector, a loop filter, a voltage-controlled oscillator, a pre-divider, a 0 / 180° inverter, a programmable divider and a delay control unit 2. After the reference input divider receives the reference clock, it is sequentially connected to the delay control unit 1, the phase detector, the loop filter and the voltage-controlled oscillator. Among them, the voltage-controlled oscillator has two outputs, the first one is connected to the corresponding drive amplifier, and the second one is used to form a negative feedback circuit structure of the phase-locked loop. The negative feedback circuit structure is that the voltage-controlled oscillator then enters the pre-divider, the 0 / 180° inverter, the programmable divider and the delay control unit 2 to the phase detector in sequence. The voltage-controlled oscillator is used to generate the initial radio frequency signal, the delay control unit 1 is used to adjust the phase of the reference clock signal, the phase detector is used to perform phase detection on the reference clock and the radio frequency signal, the loop filter is used to filter, and the pre-divider is used to adjust the frequency of the radio frequency signal passing through the loop filter. The delay control unit 2 cooperates with the delay control unit 1, and controls the phase error of each RF signal transmitted through the corresponding power amplifier and coupler to be within ±5.0° through signal control and signal processor. As long as the phase error of the transmitted RF signal is controlled within ±5.0°, it is considered to be synchronized.

[0021] like Figure 5 As shown, it is a schematic diagram of the structure inside a signal control and signal processor, which includes an analog-to-digital conversion unit, a digital down-conversion DDC unit, a CIC and FIR filter, a detector, a CPU and a signal controller connected in sequence. Among them, the analog-to-digital conversion unit is used to convert each analog signal into each digital signal. The digital down-conversion DDC unit is used to down-convert each digital signal and obtain each down-converted baseband signal. The CIC and FIR filters actually include two filters connected in series, namely a CIC filter and a FIR filter. The CIC filter first performs CIC filtering on each down-converted baseband signal, and then filters it with a FIR filter to obtain each filtered signal. The detector has a detection function and can be used to extract each amplitude and phase information from the sub-process data contained in each filtered signal, and then transmit it to the CPU. The CPU selects one from multiple amplitude and phase information as the reference information, and compares the other amplitude and phase information with the reference information respectively to obtain each corresponding amplitude control signal and each delay control signal. The signal controller controls the RF signal of each corresponding RF phase-locked loop to perform amplitude adjustment and delay adjustment according to each amplitude control signal and each delay control signal, so that the phase and amplitude of each RF signal are consistent, thereby achieving synchronization. After these RF signals are synchronized, when the signal is transmitted and spatially synthesized, the noise and phase shift errors can be effectively reduced, thereby greatly improving the signal quality.

[0022] In this embodiment, the self-correction circuit is used to perform sampling correction on each group of transmission signal generating circuits, and the self-correction circuit includes a mixing and ADC sampling circuit, a plurality of couplers and a switch selector. Among them, each power amplifier is respectively connected to each corresponding DSA digitally controlled attenuator and each corresponding coupler; each coupler is connected to the switch selector and is connected to each corresponding antenna in the multi-channel transmitting antenna; the switch selector is used to control whether the mixing and ADC sampling circuit is connected to each coupler. The self-correction circuit combines signal control and signal processor, mainly completes the sampling, data processing and system-level function control of the amplitude and phase signals of each channel of the entire system circuit, and can automatically adjust and control the amplitude and phase of the system according to the information of data processing, so as to realize the software self-correction function of the system, so that the final transmission signal is effectively synchronized and the quality of signal synthesis is improved.

[0023] Specifically, Figure 3 As shown, it is a structural schematic diagram of a mixing and ADC sampling circuit, which includes a calibration DSA, a mixer, a low-pass filter, an intermediate frequency amplifier and an ADC sampling circuit connected in sequence, and the mixer is also connected to a calibration RF phase-locked loop; the calibration DSA is used to adjust each RF signal after power amplification, and the mixer is used to down-convert each RF signal and the local oscillator signal emitted by the calibration RF phase-locked loop to obtain each intermediate frequency signal; the low-pass filter is used to perform low-pass filtering on each intermediate frequency signal; the intermediate frequency amplifier is used to amplify each intermediate frequency signal after low-pass filtering; the ADC sampling circuit is used to perform ADC sampling on each amplified intermediate frequency signal, obtain each digital signal and transmit it to the signal control and signal processor; the signal control and signal processor automatically tunes the initial phase and amplitude of each RF signal based on each digital signal, controls the phase of each RF signal to be consistent, and transmits each phase-consistent RF signal as each transmission signal at each corresponding coupler to each corresponding transmitting antenna for transmission, and then performs spatial synthesis on the signal transmitted by each transmitting antenna.

[0024] In this embodiment, the coupling degree of each coupler is 30dB, and the delay control step of each delay control unit 1 and each delay control unit 2 is 1pS. The 1pS delay control step provides a high-precision time delay adjustment capability, which can respond quickly and perform fine regulation. The coupling degree of 30dB is suitable for implementing scenarios such as specific signal allocation or power allocation, and is also suitable for the coupling connection between the self-correction circuit and multiple groups of transmission signal generation circuits in this embodiment.

[0025] After the signal enters the pre-divider for pre-division, the actual frequency of the pre-divided output signal may still be much higher than the reference signal. Therefore, the signal passes through the programmable 0 / 180° inverting circuit and the programmable divider to divide the frequency of the voltage-controlled oscillator and output it to the phase detector, thereby reducing the frequency and making it consistent with the frequency of the reference clock. The output frequency of the voltage-controlled oscillator is always locked to the set output frequency through the phase detector.

[0026] In the RF phase-locked loop circuit, the 0 / 180° inverter and the delay control unit 2 can adjust the output signal delay of the phase-locked loop through the tuning interval of the delay step 1pS. Therefore, in the multi-channel RF phase-locked loop under the same reference clock, the output signal phase of the voltage-controlled oscillator can be finely tuned by controlling the delay control unit 2 and the 0 / 180° inverter through the signal control and signal processor. The 0 / 180° inverter circuit can adjust the delay control line from 0~360° to 0~±180°, shortening the delay control line by half, greatly optimizing the circuit and speeding up the response speed.

[0027] In this embodiment, in the multi-channel transmitting antenna part of the final output, multiple transmitting signals will be spatially synthesized and finally output externally. The spatial synthesis here is a technology that uses multiple antennas to work simultaneously and synthesizes their output signals to improve system performance. By reasonably combining and processing the signals received by multiple antennas, a series of functions such as beamforming, multiple access transmission and interference suppression can be achieved. This technology utilizes spatial diversity and can improve the performance and various indicators in communication transmission by performing signal processing in space.

[0028] In this embodiment, the parts of the self-correction circuit except each coupler and switch selector, the signal control and signal processor, and the parts of each group of transmission signal generating circuits except each power amplifier are integrated using CMOS technology and integrated on a 4mm×4mm chip. CMOS technology is a commonly used circuit integration technology. After integration, it is convenient for large-scale production to reduce costs, and it also saves the area required for the overall circuit to reduce overall power consumption. In addition, since the coupler and switch selector are actually used to couple and select different parts of the circuit, there are many alternative devices to choose from in actual use, and for the actual multi-scenario application and transformation needs, these two parts are not integrated.

[0029] In addition, the present invention also proposes a self-calibration method, which adopts the above-mentioned power synthesis circuit based on a multi-channel radio frequency phase-locked loop, and the self-calibration method includes the following steps: S1, the self-correction circuit uses a switch selector and multiple couplers to sequentially receive each RF signal in each group of transmission signal generation circuits, dynamically adjust the power of each RF signal using a calibration DSA, and then enter the mixer and down-convert the local oscillator signal generated by the calibration RF phase-locked loop to an intermediate frequency to obtain an intermediate frequency signal; then the intermediate frequency signal is sequentially sent to the ADC sampling circuit through a low-pass filter and an intermediate frequency amplifier; S2, using the ADC sampling circuit to perform ADC sampling on the intermediate frequency signal in step S1, and then sending the ADC sampled data to the signal control and signal processor through the LVDS interface; the signal control and signal processor first performs digital down-conversion and signal detection analysis based on the ADC sampled data to obtain multiple amplitude and phase data, and selects one of the multiple amplitude and phase data as the reference data, compares the other amplitude and phase data with the reference data, generates corresponding multiple amplitude control instructions and multiple delay control instructions, and then transmits the multiple amplitude control instructions and multiple delay control instructions to the corresponding radio frequency phase-locked loop to adjust the amplitude and phase consistency; S3. After completing the consistency adjustment in step S2, each RF signal is transmitted to each corresponding transmitting antenna in turn through each corresponding power amplifier and each corresponding coupler for transmission, and then the signal transmitted by each transmitting antenna is spatially synthesized.

[0030] The self-correction method uses the above-mentioned power synthesis circuit based on a multi-channel radio frequency phase-locked loop. The beneficial effects of the self-correction method can be referred to the relevant description above, and will not be repeated here.

[0031] Specific application examples:

[0032] A signal control and signal processor is connected in parallel with 4 groups of transmission signal generating circuits, and the structure of each group of transmission signal generating circuits is the same. The first group of transmission signal generating circuits includes a radio frequency phase-locked loop 1, a P1 driving amplifier, a DSA1 digitally controlled attenuator and a power amplifier connected in sequence, and sends out a radio frequency signal 1; the second group of transmission signal generating circuits includes a radio frequency phase-locked loop 2, a P2 driving amplifier, a DSA2 digitally controlled attenuator and a power amplifier connected in sequence, and sends out a radio frequency signal 2; the third group of transmission signal generating circuits includes a radio frequency phase-locked loop 3, a P3 driving amplifier, a DSA3 digitally controlled attenuator and a power amplifier connected in sequence, and sends out a radio frequency signal 3; the fourth group of transmission signal generating circuits includes a radio frequency phase-locked loop 4, a P4 driving amplifier, a DSA4 digitally controlled attenuator and a power amplifier connected in sequence, and sends out a radio frequency signal 4. The initial signal of each radio frequency phase-locked loop is between 8 and 12 GHz, and the synchronous reference clock sends the same reference clock to the four radio frequency phase-locked loops. At this time, the four initial radio frequency signals have slight differences in amplitude and phase.

[0033] The radio frequency signal 1 is mixed and sampled by the ADC in turn through the coupler 1 and the switch selector for down-conversion and ADC sampling to obtain the digital signal 1, and then the digital signal 1 is transmitted to the signal control and signal processor.

[0034] The second, third and fourth groups of transmission signal generating circuits also adopt the same operation method as the first group of transmission signal generating circuits to obtain and transmit digital signals 2, 3 and 4 to the signal control and signal processor respectively.

[0035] Next, the signal control and signal processor extracts the corresponding data information 1, 2, 3 and 4 from the four digital signals, and then uses data information 1 as the reference information, compares the other three data information with data information 1, and determines the delay adjustment and amplitude adjustment required for the three transmitting signal generating circuits.

[0036] Then, the first group of transmission signal generating circuits is kept unchanged, and the delay and amplitude of the RF signals in the second, third and fourth groups of transmission signal generating circuits are adjusted so that these three are synchronized with the RF signal 1 of the first group of transmission signal generating circuits, that is, the amplitude and phase are consistent.

[0037] After the four RF signals are synchronized, the amplitude and phase consistency errors of the four transmission signals are ensured to be extremely small when they are transmitted to the corresponding transmission antennas through the power amplifiers and couplers, which improves the efficiency of spatial synthesis of the output signal power. At the same time, the non-correlation of the four phase-locked loops further improves the signal-to-noise ratio of the output signal. Therefore, the four RF signals are transmitted to the corresponding antennas through the corresponding power amplifiers and corresponding couplers for spatial synthesis, and the high signal-to-noise ratio signal is finally output.

[0038] In summary, the present invention utilizes the non-correlation of multiple phase-locked loops to effectively reduce the noise of the synthesized signal and improve the signal-to-noise ratio of the signal; at the same time, a delay control unit is used in the radio frequency phase-locked loop to replace the phase shifter in the prior art, and through multi-channel phase synchronization, the channel loss caused by the phase shifter is avoided, the synthesis accuracy is improved, and the power synthesis efficiency is effectively improved; moreover, the amplitude and phase of the signal are monitored and automatically adjusted for each phase-locked loop, while ensuring the calibration accuracy, the correction speed and efficiency are also improved; in addition, the main part of the circuit is integrated on a 4mm×4mm chip, which greatly improves the system integration, reduces the system power consumption and cost, and has significant progress.

[0039] The above embodiments are only for illustrating the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A power synthesis circuit based on a multi-channel radio frequency phase-locked loop, characterized in that: The power synthesis circuit includes a signal control and signal processor, a synchronous reference clock, multiple groups of transmission signal generation circuits, a self-correction circuit and a multi-channel transmission antenna; The synchronous reference clock provides the same reference clock for each group of transmission signal generating circuits; each group of transmission signal generating circuits is controlled by a signal control and signal processor, and each group of transmission signal generating circuits includes a radio frequency phase-locked loop, a driving amplifier, a DSA digitally controlled attenuator and a power amplifier connected in sequence, and the structure of each group of transmission signal generating circuits is the same; in each group of transmission signal generating circuits, the radio frequency phase-locked loop is connected to the synchronous reference clock and the signal control and signal processor respectively, the radio frequency phase-locked loop is used to generate a radio frequency signal, the driving amplifier is used to increase the power amplitude of the radio frequency signal to improve the driving capability, the DSA digitally controlled attenuator is used to control the radio frequency signal for amplitude tuning, and the power amplifier is used to amplify the radio frequency signal power to the required transmission power; The self-correction circuit is used to perform sampling correction on each group of transmission signal generating circuits, and the self-correction circuit includes a mixing and ADC sampling circuit, a switch selector and a plurality of couplers; each coupler is connected to the switch selector and is connected to each corresponding power amplifier in the multi-channel transmission antenna; the switch selector is used to control the connection between the mixing and ADC sampling circuit and each coupler; Among them, the mixing and ADC sampling circuit includes a calibration DSA digitally controlled attenuator, a mixer, a low-pass filter, an intermediate frequency amplifier and an ADC sampling circuit connected in sequence, and the mixer is also connected to a calibration RF phase-locked loop; the calibration DSA is used to adjust each RF signal that has been power-amplified, and the mixer is used to down-convert each RF signal that has passed the calibration DSA and the local oscillator signal emitted by the calibration RF phase-locked loop to obtain each intermediate frequency signal; the low-pass filter is used to perform low-pass filtering on each intermediate frequency signal; the intermediate frequency amplifier is used to amplify each intermediate frequency signal that has passed the low-pass filtering; the ADC sampling circuit is used to perform ADC sampling on each amplified intermediate frequency signal, obtain each digital signal and transmit it to the signal control and signal processor; the signal control and signal processor automatically tunes the initial phase and amplitude of each RF signal based on each digital signal, controls the phase consistency of each RF signal, and transmits each phase-consistent RF signal as each transmission signal after passing through each corresponding coupler to each corresponding transmitting antenna for transmission, and then performs spatial synthesis on the signal transmitted by each transmitting antenna.

2. A power synthesis circuit based on a multi-channel radio frequency phase-locked loop according to claim 1, characterized in that: The radio frequency phase-locked loop includes a reference input divider, a delay control unit 1, a phase detector, a loop filter, a voltage-controlled oscillator, a pre-divider, a 0 / 180° inverter, a programmable divider and a delay control unit 2. After the reference input divider receives the reference clock, it is sequentially connected to the delay control unit 1, the phase detector, the loop filter and the voltage-controlled oscillator. Among them, the voltage-controlled oscillator has two outputs, the first one is connected to the corresponding driving amplifier, and the second one is used to form a negative feedback circuit structure of a phase-locked loop. The negative feedback circuit structure is that the voltage-controlled oscillator then enters the pre-divider, 0 / 180° inverter, programmable divider and delay control unit 2 to the phase detector in sequence; the voltage-controlled oscillator is used to generate a radio frequency signal, the delay control unit 1 is used to adjust the phase of the reference clock signal, the phase detector is used to perform phase detection on the reference clock and the radio frequency signal, the loop filter is used for filtering, and the pre-divider is used to adjust the frequency of the radio frequency signal passing through the loop filter; the delay control unit 2 cooperates with the delay control unit 1, and controls the phase error of each radio frequency signal transmitted by the corresponding power amplifier and coupler to be controlled within ±5.0° through signal control and signal processor.

3. A power synthesis circuit based on a multi-channel radio frequency phase-locked loop according to claim 1, characterized in that: The calibration RF phase-locked loop is an independent phase-locked circuit, which is used to input the local oscillator signal to the mixer to drive the mixer to work. The intermediate frequency signal obtained by the mixer = local oscillator signal - RF signal. The intermediate frequency signal meets the sampling frequency requirements of the ADC sampling circuit, and the local oscillator signal and the RF signal form a fixed difference frequency. The ADC used in the ADC sampling circuit is a 14-bit high-speed digital-to-analog converter, which is used to collect the amplitude information of the intermediate frequency signal and convert it into a digital signal to send to the signal control and signal processor.

4. A power synthesis circuit based on a multi-channel radio frequency phase-locked loop according to claim 1, characterized in that: The signal control and signal processor includes an analog-to-digital conversion unit, a digital down-conversion DDC unit, a CIC and FIR filter, a detector, a CPU and a signal controller which are connected in sequence; Among them, the analog-to-digital conversion unit is used to convert each analog signal into each digital signal; the digital down-conversion DDC unit is used to perform down-conversion processing on each analog signal and obtain each down-converted baseband signal; the CIC and FIR filters are used to perform CIC filtering and FIR filtering on each down-converted baseband signal to obtain each filtered signal; the detector is used to extract each amplitude and phase information from the sub-process data contained in each filtered signal and transmit it to the CPU; the CPU selects one from multiple amplitude and phase information as the reference information, and compares the other amplitude and phase information with the reference information respectively to obtain each corresponding amplitude control signal and each delay control signal; the signal controller controls the corresponding RF signal of each channel to perform amplitude adjustment and delay adjustment according to each amplitude control signal and each delay control signal.

5. A power synthesis circuit based on a multi-channel radio frequency phase-locked loop according to claim 1, characterized in that: The parts of the self-correction circuit except each coupler and switch selector, the signal control and signal processor, and the parts of each transmission signal generation circuit except each power amplifier are all integrated using CMOS technology and integrated on a 4mm×4mm chip.

6. A self-calibration method based on a multi-channel radio frequency phase-locked loop, using a power synthesis circuit based on a multi-channel radio frequency phase-locked loop as described in any one of claims 1 to 5, characterized in that: The self-correction method comprises the following steps: S1, the self-correction circuit uses a switch selector and multiple couplers to sequentially receive each RF signal in each group of transmission signal generation circuits, dynamically adjust the power of each RF signal using a calibration DSA, and then enter the mixer and down-convert the local oscillator signal generated by the calibration RF phase-locked loop to an intermediate frequency to obtain an intermediate frequency signal; then the intermediate frequency signal is sequentially sent to the ADC sampling circuit through a low-pass filter and an intermediate frequency amplifier; S2, using the ADC sampling circuit to perform ADC sampling on the intermediate frequency signal in step S1, and then sending the ADC sampled data to the signal control and signal processor through the LVDS interface; the signal control and signal processor first performs digital down-conversion and signal detection analysis based on the ADC sampled data to obtain multiple amplitude and phase data, and selects one of the multiple amplitude and phase data as the reference data, compares the other amplitude and phase data with the reference data, generates corresponding multiple amplitude control instructions and multiple delay control instructions, and then transmits the multiple amplitude control instructions and multiple delay control instructions to the corresponding radio frequency phase-locked loop to adjust the amplitude and phase consistency; S3. After completing the consistency adjustment in step S2, each RF signal is transmitted to each corresponding transmitting antenna in turn through each corresponding power amplifier and each corresponding coupler for transmission, and then the signal transmitted by each transmitting antenna is spatially synthesized.

Images