High-reliability RS485 bus interface control system, computing chip and industrial computer

Abstract

The invention discloses a high-reliability RS485 bus interface control system, a computing chip and an industrial computer, and relates to the technical field of computers.The system comprises the steps that when data sending is started, a receiving enable signal is set to be at a low level, RS485 receiving is closed, then an RS485 sending enable signal is set to be at a high level, and next-level equipment is set to wait for data sending; then the sending enable signal is set to be at a high level and sent to the UART sending module, and at the moment, the UART sending module can start to send data; after data transmission is completed, a transmission enable signal is placed at a low level, a transmission state is closed, an RS485 transmission enable signal is placed at a low level, a receiving enable signal is placed at a high level, RS485 receiving is started, and at the moment, a UART receiving module can start to receive data. According to the system, the enable signal is automatically set, so that the interference signal is prevented from being mistakenly received or packet loss at the sending end caused by the fluctuation of a magnetic field or a power supply in a transceiver chip can be avoided, and the reliability of an RS485 bus interface is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a high-reliability RS485 bus interface control system, a computing chip and an industrial computer. Background Art

[0002] The RS485 bus interface is a commonly used communication interface in industrial systems. The functions of the RS485 bus interface are realized by three signals: RS485 send signal, RS485 receive signal and RS485 send enable signal. When the RS485 send enable signal is high, data is sent, and when the RS485 send enable signal is low, data is received.

[0003] RS485 transmission enable signal generally requires strict timing control by the host computer, and the enable signal needs to be manually set according to the timing. When receiving data switches to sending data, the rising edge jump of the RS485 transmission enable signal will generate magnetic field or internal power supply fluctuation of the transceiver chip, which can easily introduce external interference and cause misreception; when sending data switches to receiving data, the falling edge jump of the RS485 transmission enable signal will also generate magnetic field or internal power supply fluctuation of the transceiver chip, resulting in packet loss or misreception at the end of transmission. This has caused trouble for the staff and affected the reliability of the data. Summary of the invention

[0004] The present application provides a high-reliability RS485 bus interface control system, a computing chip and an industrial computer, which avoid packet loss and erroneous reception during the transmission and reception switching process by automatically setting an enable signal, thereby improving the reliability of the RS485 bus interface.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions: In a first aspect, the present application provides a highly reliable RS485 bus interface control system, the system comprising: a transmit FIFO module, a UART transmit module, a transceiver control module, a UART receive module and a receive FIFO module; The transmitting FIFO module is used to cache UART transmission data, send a low-level empty flag signal to the transceiver control module, receive a read enable signal sent by the transceiver control module, and send the UART transmission data to the UART transmitting module when the read enable signal is at a high level. The high level of the empty flag signal indicates that there is no data in the transmitting FIFO module, and the low level indicates that there is data in the transmitting FIFO module. The initial state of the empty flag signal is a high level; The UART sending module is used to receive the UART sending data sent by the sending FIFO module, send a data sending completion signal to the transceiver control module after receiving the data, and send the UART sending data through the RS485 sending channel after receiving the high-level sending enable signal sent by the transceiver control module; The UART receiving module is used to receive the high-level receiving enable signal sent by the transceiver control module, receive the UART receiving data through the RS485 receiving channel, and then send the UART receiving data to the receiving FIFO module. When the data reception is valid, the data reception valid signal is set to a high level, and the data reception valid signal is sent to the receiving FIFO module, wherein the data reception valid signal serves as a write enable signal of the receiving FIFO module; The receiving FIFO module is used to cache UART receiving data. When the write enable signal is set to a high level, the UART receiving data received by the UART receiving module is written into the receiving FIFO module at the rising edge of the clock. The receiving FIFO module sends the UART receiving data to the host through the receiving FIFO module output interface; The transceiver control module is used to set the receiving enable signal to a low level when starting data transmission, turn off RS485 reception, then set the RS485 sending enable signal to a high level, and then set the sending enable signal to a high level; after data transmission is completed, first set the sending enable signal to a low level, then set the RS485 sending enable signal to a low level, and then set the receiving enable signal to a high level to turn on RS485 reception, wherein when the RS485 sending enable signal is at a high level, it is used to set the next level device to send data, and when the RS485 sending enable signal is at a low level, it is used to set the next level device to receive data.

[0006] In some possible implementations, the transceiver control module is specifically configured to start sending data when the sending status identification signal is converted from a low level to a high level, and complete data sending when the sending status identification signal is converted from a high level to a low level.

[0007] In some possible implementations, the transceiver control module includes a transmission control state machine; The initial state of the sending control state machine is an idle state, and it is judged whether the first preset condition is met, and the first preset condition is that the empty flag signal is set to a low level. If the first preset condition is met, it is switched to the RS485 sending preparation state, the first counter is reset, the sending state identification signal is set to a high level, the first set number of clocks are delayed, and then the sending enable signal is set to a high level to judge whether the second preset condition is met. The second preset condition is that the first set number of clocks have been delayed. If the second preset condition is met, it is switched to the RS485 sending state, and the UART sending module sends the UART sending data, and then it is judged whether the third preset condition is met. The third preset condition is that there is no UART sending data cached in the sending FIFO module. If the third preset condition is met, the sending enable signal is set to a low level and jumps to the idle state.

[0008] In some possible implementations, the transceiver control module further includes a transceiver switching state machine; The initial state of the transceiver switching state machine is an idle state, and it is judged whether the fourth preset condition is met, and the fourth preset condition is to start sending data. If the fourth preset condition is met, it is switched to the RS485 receiving closed state, the receiving enable signal is set to a low level, and switched to the strobing enabled state. In the strobing enabled state, the RS485 sending enable signal is set to a high level, and it is judged whether the fifth preset condition is met. The fifth preset condition is that the data sending is completed. If the fifth preset condition is met, it is switched to the timing closed state, the second counter is reset, the RS485 sending enable signal is set to a low level, and the second set number of clocks is delayed to judge whether the sixth preset condition is met. The sixth preset condition is that the second set number of clocks has been delayed. If the sixth preset condition is met, it is switched to the RS485 receiving open state.

[0009] In some possible implementations, the transceiver switching state machine is further specifically configured to switch from the gating enable state to the idle state if a fifth preset condition is not satisfied.

[0010] In some possible implementations, the transceiver switching state machine is further specifically configured to switch from the timing off state to the RS485 reception off state if a fourth preset condition is satisfied during the delay of a second set number of clocks.

[0011] In some possible implementations, the transceiver switching state machine is further specifically configured to set the receive enable signal to a high level in the RS485 receive on state, and switch to the RS485 receive off state if a fourth preset condition is met.

[0012] In some possible implementations, the transceiver switching state machine is further specifically configured to switch from the idle state to the timing off state if a fifth preset condition is met in the idle state.

[0013] In a second aspect, the present application provides a computing chip, the computing chip comprising the system described in any one of the first aspects.

[0014] In a third aspect, the present application provides an industrial computer, which may include the system described in any one of the first aspects.

[0015] It can be seen from the above technical solution that the present application has at least the following beneficial effects: In the present application, a transceiver control module is added to set the receive enable signal to a low level when starting data transmission, turn off RS485 reception, and stop the next-level device from sending data to the UART receiving module. The RS485 send enable signal is then set to a high level for transmission to the next-level device to determine that the next-level device is waiting for data to be sent, and then the send enable signal is set to a high level for sending to the UART sending module. At this time, the UART sending module can start sending data. After the data is sent, the send enable signal is first set to a low level to turn off the sending state, and then the RS485 send enable signal is set to a low level, and then the receive enable signal is set to a high level to turn on RS485 reception. At this time, the UART receiving module can start receiving data. In the traditional scheme, when receiving data is switched to sending data, due to the rising edge jump of the RS485 sending enable signal, the magnetic field or the fluctuation of the power supply inside the transceiver chip will be generated, which can easily introduce external interference and cause erroneous reception; when sending data is switched to receiving data, due to the falling edge jump of the RS485 sending enable signal, the magnetic field or the fluctuation of the power supply inside the transceiver chip will also be generated, resulting in packet loss or erroneous reception at the end of the transmission. It can be seen that the present application provides a transceiver control module to control the high and low levels of the signal, and ensures that the RS485 reception is turned off before the rising edge jump of the RS485 sending enable signal, and ensures that the interference signal is not mistakenly received due to the fluctuation of the magnetic field or the power supply inside the transceiver chip, and also ensures that the RS485 reception is turned on after the RS485 sending enable signal falls. By automatically setting the enable signal, it is ensured that the interference signal is not mistakenly received or the packet loss at the end of the transmission is not caused by the fluctuation of the magnetic field or the power supply inside the transceiver chip, thereby improving the reliability of the RS485 bus interface.

[0016] It should be understood that the description of technical features, technical solutions, beneficial effects or similar language in this application does not imply that all features and advantages can be realized in any single embodiment. On the contrary, it is understood that the description of features or beneficial effects means that specific technical features, technical solutions or beneficial effects are included in at least one embodiment. Therefore, the description of technical features, technical solutions or beneficial effects in this specification does not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions and beneficial effects described in the present embodiment can also be combined in any appropriate manner. Those skilled in the art will understand that the embodiment can be realized without one or more specific technical features, technical solutions or beneficial effects of a specific embodiment. In other embodiments, additional technical features and beneficial effects can also be identified in a specific embodiment that does not embody all embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of an RS485 bus interface control system provided in an embodiment of the present application; Figure 2 A schematic diagram of a signal sending sequence provided in an embodiment of the present application; Figure 3 A schematic diagram of a transmission state control state machine provided in an embodiment of the present application; Figure 4 A schematic diagram of a transceiver switching state machine provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] The terms "first", "second", "third", etc. in the specification of this application and the accompanying drawings are used to distinguish different objects rather than to limit a specific order.

[0019] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0020] In order to make the description of the following embodiments clear and concise, a brief introduction to the related technology is first given: FIFO means that the first data to enter is processed or removed first. In the field of computer technology, FIFO is often used to describe the working mode of a queue. A queue is a linear data structure in which data items are arranged in the order of insertion, and data is accessed and processed according to the principle of first-in-first-out. This structure can be used in a variety of scenarios, such as task scheduling, data buffering, etc. In the processing of network data packets, FIFO queues can ensure that data packets are processed in the order they are received, thereby ensuring normal and orderly network communication.

[0021] FIFO memory is usually a first-in, first-out dual-port buffer, that is, the first data to enter it is the first to be removed. It has an input port and an output port. The data is stored in the memory in the order in which it is written and sent out from the output port in the same order. The FIFO memory is actually a ring data structure, with the write pointer (WP) and the read pointer (RP) indicating the corresponding units for data writing and reading respectively. FIFO is increasingly widely used in high-speed data acquisition, high-speed data processing, high-speed data transmission and multi-machine processing systems due to its flexible, convenient and efficient characteristics. FIFO can improve system performance, increase data transmission rate, and process large data streams.

[0022] At present, when receiving data switches to sending data, the rising edge transition of the RS485 send enable signal will generate fluctuations in the magnetic field or the power supply inside the transceiver chip, which can easily introduce external interference and cause erroneous reception; when sending data switches to receiving data, the falling edge transition of the RS485 send enable signal will also generate fluctuations in the magnetic field or the power supply inside the transceiver chip, resulting in packet loss or erroneous reception at the end of transmission.

[0023] In view of this, an embodiment of the present application provides a highly reliable RS485 bus interface control system, in which a transceiver control module is added to set the receive enable signal to a low level when starting data transmission, turn off the RS485 reception, and enable the next-level device to no longer send data to the UART receiving module, and then set the RS485 send enable signal to a high level for transmission to the next-level device to determine that the next-level device is waiting for data transmission, and then set the send enable signal to a high level for sending to the UART sending module, at which time the UART sending module can start sending data; after the data transmission is completed, first set the send enable signal to a low level to turn off the sending state, then set the RS485 send enable signal to a low level, and then set the receive enable signal to a high level to turn on the RS485 reception, at which time the UART receiving module can start receiving data. It can be seen that the present application provides a transceiver control module to control the high and low levels of the signal, thereby ensuring that the RS485 reception is turned off before the RS485 send enable signal jumps on the rising edge, thereby ensuring that the interference signal is not mistakenly received due to the magnetic field or the fluctuation of the power supply inside the transceiver chip. It also ensures that the RS485 reception is turned on after the RS485 send enable signal jumps on the falling edge. By automatically setting the enable signal, it is ensured that the interference signal is not mistakenly received or the packet is lost at the end of the transmission due to the magnetic field or the fluctuation of the power supply inside the transceiver chip, thereby improving the reliability of the RS485 bus interface.

[0024] In order to make the technical solution of the present application clearer and easier to understand, the following describes an RS485 bus interface control system provided by the present application in conjunction with the accompanying drawings. Figure 1 As shown, this figure is a schematic diagram of an RS485 bus interface control system provided in an embodiment of the present application.

[0025] In an embodiment of the present application, the RS485 bus interface control system is always in a receiving state. When the host needs to send data, it switches to a data sending state. The control system includes: a sending FIFO module 101, a UART sending module 102, a transceiver control module 103, a UART receiving module 104 and a receiving FIFO module 105.

[0026] The sending FIFO module 101 is used to cache UART sending data. The capacity of the sending FIFO module 101 is 1024 bytes, and the data width is 8 bits. The host sends UART sending data to the sending FIFO module. The sending FIFO module 101 receives the data one by one and sends a low-level empty flag signal to the transceiver control module 103. The sending FIFO module 101 receives the read enable signal sent by the transceiver control module 103. When the read enable signal is high, the UART sending data is sent to the UART sending module 102 in each clock cycle, wherein a high level of the empty flag signal indicates that there is no data in the sending FIFO module, and a low level indicates that there is data in the sending FIFO module. In the present application, the initial state of the empty flag signal is high.

[0027] The UART sending module 102 is used to receive the UART sending data sent by the sending FIFO module 101 according to the standard UART protocol, and after receiving a byte of data, sends a data sending completion signal to the transceiver control module 103. After receiving the high-level sending enable signal sent by the transceiver control module 103, the RS485 sending is turned on to send the UART sending data through the RS485 sending channel. When the low-level sending enable signal sent by the transceiver control module 103 is received again, the RS485 sending is turned off.

[0028] The UART receiving module 104 is used to receive the high-level receiving enable signal sent by the transceiver control module 103, receive the UART receiving data through the RS485 receiving channel according to the standard UART protocol, and then send the UART receiving data to the receiving FIFO module 105. When the data reception is valid, that is, a data is completely sent to the receiving FIFO module 105, the data reception valid signal is set to a high level, and the data reception valid signal is sent to the receiving FIFO module 105 as a write enable signal of the receiving FIFO module 105; The receiving FIFO module 105 is used to cache the UART receiving data, and when the write enable signal is set to a high level, receives the UART receiving data from the UART receiving module 104, and then transmits the UART receiving data to the host; Data is received and cached through the sending FIFO module 101 and the receiving FIFO module 105, which can play a buffering role in the process of data transmission and ensure that the data can be sent one by one in sequence.

[0029] The transceiver control module 103 is used to place the receiving enable signal at a low level when starting data transmission, close the RS485 reception, and transmit to the next level device, then place the RS485 transmission enable signal at a high level, and then place the transmission enable signal at a high level, and send to the UART transmission module, and the UART transmission module can start to send data; after the data transmission is completed, first place the transmission enable signal at a low level, close the transmission state, then place the RS485 transmission enable signal at a low level, and then place the receiving enable signal at a high level, open the RS485 reception, and the UART receiving module can start to receive data. Wherein, when the RS485 transmission enable signal is at a high level, it is used to set the next level device to send data, and when the RS485 transmission enable signal is at a low level, it is used to set the next level device to receive data.

[0030] In the transceiver control module 103, there is a transmission status identification signal. When the transmission status identification signal changes from a low level to a high level, data transmission starts. When the transmission status identification signal changes from a high level to a low level, data transmission is completed.

[0031] Among them, a certain delay time must be ensured between each step. The embodiment of the present application provides a schematic diagram of the signal sending sequence, such as Figure 2 As shown, the figure is a schematic diagram of a signal sending sequence provided by an embodiment of the present application. In the figure, it can be seen that the sending status identification signal first changes from a low level to a high level, delays for a certain period of time, and the receiving enable signal changes from a high level to a low level. At this time, the RS485 reception is turned off, and a certain period of time is delayed. The RS485 sending enable signal changes from a low level to a high level and is sent to the next-level device, prompting the next-level device that the host wants to send data. After a certain period of delay, the sending enable signal changes from a low level to a high level and is sent to the UART sending module 102. Then the UART sending module 102 can send the UART send data to the next-level device through the RS485 sending channel.

[0032] The transceiver control module 103 also includes a transmission state control state machine and a transceiver switching control state machine, which are used to implement timing control, ensure the transmission and reception of data, and improve the reliability of the RS485 bus interface. The transmission state control state machine and the transceiver switching control state machine are respectively introduced in detail below.

[0033] The present application embodiment provides a schematic diagram of a sending state control state machine, such as Figure 3As shown, the figure is a schematic diagram of a sending state control state machine provided in an embodiment of the present application. It can be seen in the figure that the sending state control state machine includes an idle state, an RS485 sending preparation state and an RS485 sending state. The first preset condition is that the empty flag signal is set to a low level, the second preset condition is that the clock has been delayed by a first set number, and the third preset condition is that there is no cached UART sending data in the sending FIFO module 101.

[0034] The initial state of the sending state control state machine is the idle state. At this time, the sending state identification signal is at a low level. It is judged whether the first preset condition is met. If the first preset condition is met, it means that there is data to be sent in the sending FIFO module 101 at this time, then it is switched to the RS485 sending preparation state, the first counter is reset, the sending state identification signal is set to a high level, the clock of the first set number is delayed, and then the sending enable signal is set to a high level, RS485 sending is turned on, and then it is judged whether the second preset condition is met. If the second preset condition is met, it is switched to the RS485 sending state, and the UART sending module 102 sends the UART sending data to the next level device, and then it is judged whether the third preset condition is met. If the third preset condition is met, the sending enable signal is set to a low level, RS485 sending is turned off, and it jumps to the idle state.

[0035] In the embodiment of the present application, the first set number is 10, which is used to ensure that the receiving enable signal and the RS485 sending enable signal complete the high and low level conversion.

[0036] The embodiment of the present application also provides a schematic diagram of a transceiver switching state machine, such as Figure 4 As shown, the figure is a schematic diagram of a transceiver switching state machine provided in an embodiment of the present application. It can be seen in the figure that the transceiver switching state machine includes an idle state, an RS485 reception closed state, a selection enable state, a timing closed state and an RS485 reception open state. The fourth preset condition is to start sending data, the fifth preset condition is that data sending is completed, and the sixth preset condition is that the second set number of clocks has been delayed.

[0037] The initial state of the transceiver switching state machine is an idle state, and it is determined whether the fourth preset condition is met. If the fourth preset condition is met, it is switched to the RS485 receiving closed state, the receiving enable signal is set to a low level, and the low-level receiving enable signal is sent to the UART receiving module 104. The UART receiving module 104 closes the RS485 receiving channel, and the transceiver switching state machine is switched to the selection enable state. In the selection enable state, the RS485 sending enable signal is set to a high level, and it is determined whether the fifth preset condition is met. If the fifth preset condition is met, it is switched to the timing closed state, the second counter is reset, the RS485 sending enable signal is set to a low level, and the second set number of clocks is delayed to determine whether the sixth preset condition is met. If the sixth preset condition is met, all UART sending data has been sent out at this time, and the transceiver switching state machine is switched to the RS485 receiving open state.

[0038] The transceiver switching state machine is further specifically configured to switch from the timing off state to the RS485 receiving off state if a fourth preset condition is met during the delay of the second set number of clocks.

[0039] In an embodiment of the present application, if the host sends UART data to the transmit FIFO module 101 in the timing off state, the transmit FIFO module 101 will send a low-level empty flag signal to the transceiver control module 103, so the transceiver switching state machine will switch the timing off state to the RS485 receive off state.

[0040] The transceiver switching state machine is also specifically used to set the receive enable signal to a high level when the RS485 receive is on. If the fourth preset condition is met, indicating that there is new UART transmit data waiting to be sent, the RS485 receive is switched to the off state.

[0041] The transceiver switching state machine is also specifically used to switch from the strobe enabled state to the idle state if the fifth preset condition is not met, and in the idle state, if the fifth preset condition is met, switch from the idle state to the timing closed state. During the transmission process, the transceiver switching state machine will not remain in the strobe enabled state, but automatically switch to the idle state. When the transmission is completed, it will switch from the idle state to the timing closed state, count, and wait for new transmission data to be sent. If no new transmission data is received within the second set number of clocks, the transceiver switching state machine switches to the RS485 receiving open state.

[0042] In the embodiment of the present application, the second set number is 100, which is used to ensure that all UART transmission data is sent to the next level device.

[0043] Therefore, in the present application, a transceiver control module is added to set the receive enable signal to a low level when starting data transmission, turn off the RS485 reception, and prevent the next-level device from sending data to the UART receiving module. The RS485 transmit enable signal is then set to a high level for transmission to the next-level device to determine that the next-level device is waiting for data transmission, and then the transmit enable signal is set to a high level for sending to the UART transmitting module. At this time, the UART transmitting module can start sending data. After the data transmission is completed, the transmit enable signal is first set to a low level to turn off the sending state, and then the RS485 transmit enable signal is set to a low level, and then the receive enable signal is set to a high level to turn on the RS485 reception. At this time, the UART receiving module can start receiving data. It can be seen that the present application provides a transceiver control module to control the high and low levels of the signal, thereby ensuring that the RS485 reception is turned off before the RS485 send enable signal jumps on the rising edge, thereby ensuring that the interference signal is not mistakenly received due to the magnetic field or the fluctuation of the power supply inside the transceiver chip. It also ensures that the RS485 reception is turned on after the RS485 send enable signal jumps on the falling edge. By automatically setting the enable signal, it is ensured that the interference signal is not mistakenly received or the packet is lost at the end of the transmission due to the magnetic field or the fluctuation of the power supply inside the transceiver chip, thereby improving the reliability of the RS485 bus interface.

[0044] The embodiment of the present application further provides a computing chip, which includes any one of the modules described in the above-mentioned high-reliability RS485 bus interface control system.

[0045] The embodiment of the present application also provides an industrial computer program product including instructions. When the industrial computer program product is run on an electronic device, the electronic device executes any one of the modules described in the above-mentioned high-reliability RS485 bus interface control system.

[0046] Through the description of the above implementation methods, those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the system is divided into different functional modules to complete all or part of the functions described above. The specific working process of the system described above can refer to the corresponding process in the aforementioned embodiment, which will not be repeated here.

[0047] In the several embodiments provided in this embodiment, it should be understood that the disclosed system, chip and industrial computer can be implemented in other ways. For example, the embodiments of the system described above are only schematic, for example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0048] In addition, each functional module in each embodiment of the present embodiment may be integrated into one processing unit, or each unit may exist physically separately, or two or more modules may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional unit.

[0049] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the method described in each embodiment. The aforementioned storage medium includes: flash memory, mobile hard disk, read-only memory, random access memory, disk or optical disk and other media that can store program codes.

[0050] The embodiment of the present application further provides an industrial computer, which includes any one of the modules described in the above-mentioned high-reliability RS485 bus interface control system.

[0051] The descriptions of the processes or structures corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0052] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application.

Claims

1. A highly reliable RS485 bus interface control system, characterized in that: The system comprises: a sending FIFO module, a UART sending module, a sending and receiving control module, a UART receiving module and a receiving FIFO module; The transmitting FIFO module is used to cache UART transmission data, send a low-level empty flag signal to the transceiver control module, receive a read enable signal sent by the transceiver control module, and send the UART transmission data to the UART transmitting module when the read enable signal is at a high level. The high level of the empty flag signal indicates that there is no data in the transmitting FIFO module, and the low level indicates that there is data in the transmitting FIFO module. The initial state of the empty flag signal is a high level; The UART sending module is used to receive the UART sending data sent by the sending FIFO module, send a data sending completion signal to the transceiver control module after receiving the data, and send the UART sending data through the RS485 sending channel after receiving the high-level sending enable signal sent by the transceiver control module; The UART receiving module is used to receive the high-level receiving enable signal sent by the transceiver control module, receive the UART receiving data through the RS485 receiving channel, and then send the UART receiving data to the receiving FIFO module. When the data reception is valid, the data reception valid signal is set to a high level, and the data reception valid signal is sent to the receiving FIFO module, wherein the data reception valid signal serves as a write enable signal of the receiving FIFO module; The receiving FIFO module is used to cache UART receiving data. When the write enable signal is set to a high level, the UART receiving data received by the UART receiving module is written into the receiving FIFO module at the rising edge of the clock. The receiving FIFO module sends the UART receiving data to the host through the receiving FIFO module output interface; The transceiver control module is used to set the receiving enable signal to a low level when starting data transmission, turn off RS485 reception, then set the RS485 sending enable signal to a high level, and then set the sending enable signal to a high level; after data transmission is completed, first set the sending enable signal to a low level, then set the RS485 sending enable signal to a low level, and then set the receiving enable signal to a high level to turn on RS485 reception, wherein when the RS485 sending enable signal is at a high level, it is used to set the next level device to send data, and when the RS485 sending enable signal is at a low level, it is used to set the next level device to receive data.

2. The system according to claim 1, characterized in that The transceiver control module is specifically used to start sending data when the sending state identification signal is converted from a low level to a high level, and complete data sending when the sending state identification signal is converted from a high level to a low level.

3. The system according to claim 1, characterized in that The transceiver control module includes a transmission control state machine; The initial state of the sending control state machine is an idle state, and it is judged whether the first preset condition is met, and the first preset condition is that the empty flag signal is set to a low level. If the first preset condition is met, it is switched to the RS485 sending preparation state, the first counter is reset, the sending state identification signal is set to a high level, the first set number of clocks are delayed, and then the sending enable signal is set to a high level to judge whether the second preset condition is met. The second preset condition is that the first set number of clocks have been delayed. If the second preset condition is met, it is switched to the RS485 sending state, and the UART sending module sends the UART sending data, and then it is judged whether the third preset condition is met. The third preset condition is that there is no UART sending data cached in the sending FIFO module. If the third preset condition is met, the sending enable signal is set to a low level and jumps to the idle state.

4. The system according to claim 1, characterized in that The transceiver control module also includes a transceiver switching state machine; The initial state of the transceiver switching state machine is an idle state, and it is judged whether the fourth preset condition is met, and the fourth preset condition is to start sending data. If the fourth preset condition is met, it is switched to the RS485 receiving closed state, the receiving enable signal is set to a low level, and switched to the strobing enabled state. In the strobing enabled state, the RS485 sending enable signal is set to a high level, and it is judged whether the fifth preset condition is met. The fifth preset condition is that the data sending is completed. If the fifth preset condition is met, it is switched to the timing closed state, the second counter is reset, the RS485 sending enable signal is set to a low level, and the second set number of clocks is delayed to judge whether the sixth preset condition is met. The sixth preset condition is that the second set number of clocks has been delayed. If the sixth preset condition is met, it is switched to the RS485 receiving open state.

5. The system according to claim 4, characterized in that The transceiver switching state machine is further specifically configured to switch from the enable state to the idle state if a fifth preset condition is not satisfied.

6. The system according to claim 4, characterized in that The transceiver switching state machine is also specifically configured to switch from the timing off state to the RS485 receiving off state if a fourth preset condition is satisfied during the delay of the second set number of clocks.

7. The system according to claim 4, characterized in that The transceiver switching state machine is also specifically used to set the receiving enable signal to a high level when the RS485 receiving is in the on state, and switch to the RS485 receiving off state if the fourth preset condition is met.

8. The system according to claim 4, characterized in that The transceiver switching state machine is also specifically configured to switch from the idle state to the timing off state if a fifth preset condition is met in the idle state.

9. A computing chip, characterized in that: A system comprising any one of claims 1 to 8.

10. An industrial computer, characterized in that: A system comprising any one of claims 1 to 8.

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