Heterogeneous hybrid programmable switch structure system and method

Abstract

The invention provides a heterogeneous hybrid programmable switch fabric system and method. The system comprises three stages of target units, namely an ASIC (Application Specific Integrated Circuit) unit, an FPGA (Field Programmable Gate Array) unit and a CPU (Central Processing Unit) unit, which are sequentially arranged according to the processing rate from high to low; the ASIC unit is used for carrying out basic processing on the received data message to generate a data message in a preset format; the FPGA unit is used for receiving the data message from the ASIC unit, processing the received data message according to a rule and generating a data message in a preset format; and the CPU unit is used for receiving the data message from the ASIC unit and / or the FPGA unit, processing the received data message according to a rule and generating a data message in a preset format. According to the invention, diversified data processing requirements can be met.

Description

Technical Field

[0001] The present invention relates to the field of programmable network technology, and in particular to a heterogeneous hybrid programmable switch structure system and method. Background Art

[0002] The development of the Internet has entered a new era of the Internet of Everything. With the emergence of new business applications such as driverless cars, the metaverse, and large models, the deep integration of industrial production, social life, and the Internet has been accelerated. These new business systems not only require the network to provide high-speed and stable data transmission capabilities, but also need to provide flexible computing and efficient storage capabilities, thereby meeting the multi-dimensional differences in the storage and conversion capabilities of the network in the diversified vertical industry applications. Under the current technical process level, a device cannot support flexibility and high-performance processing at the same time, and relying on the performance of a single chip is not enough to cope with the rapidly growing storage and computing needs in the development of network services. Summary of the invention

[0003] In order to meet the current network requirements for switch flexibility and throughput, the present invention adopts a software and hardware heterogeneous collaboration approach to provide a heterogeneous hybrid programmable switch structure system and method that can meet diverse data processing requirements.

[0004] In one aspect, the present invention provides a heterogeneous hybrid programmable switch fabric system, comprising: three levels of target units, namely, an ASIC unit, an FPGA unit, and a CPU unit, arranged in descending order of processing rate; The ASIC unit is used to perform basic processing on the received data message to generate a data message in a preset format; The FPGA unit is used to receive the data message from the ASIC unit, and process the received data message according to the rules and generate a data message in a preset format; The CPU unit is used to receive data messages from the ASIC unit and / or the FPGA unit, process the received data messages according to the rules, and generate data messages in a preset format.

[0005] Furthermore, each level of target unit is obtained by combining three or more modules among the parser, matching action module, inverse parser and traffic management module; The parser is used to perform protocol analysis and key information extraction on the arriving data packets; the matching action module is used to perform matching table lookup based on the key information extracted by the parser, and execute corresponding actions according to the table lookup results; the inverse parser is used to encapsulate the data into a data packet in a preset format; the traffic management module is used to perform exchange scheduling and traffic shaping on the data packets.

[0006] Furthermore, the ASIC unit includes a primary parser, a primary matching action module, a primary inverse parser, a traffic management module, a secondary parser, a secondary matching action module and a secondary inverse parser connected in sequence.

[0007] Furthermore, the FPGA unit includes an input queue module, a parser, a matching action module, an inverse parser and an output queue module which are connected in sequence.

[0008] Furthermore, the CPU unit includes a parser, a primary matching action module, a traffic management module, a secondary matching action module and a reverse parser which are connected in sequence.

[0009] Furthermore, an external function module is also provided in the FPGA unit and / or the CPU unit, and the external function module is used to support user-defined operations; correspondingly, the FPGA unit and / or the CPU unit processes the received data message according to the rules and / or the output of the external function module and generates a data message in a preset format.

[0010] Furthermore, the data message in the preset format includes a data message formed by encapsulating a custom Ethernet header outside the original data message to encapsulate the original data message and the metadata together.

[0011] Furthermore, the customized Ethernet header includes a reserved field, a CAT field, a source and destination device physical interface number field, an ETHTYPE field, and a VALUE field; The CAT field is used to indicate whether the table lookup of the previous target unit is hit, whether there is a custom calculation, and to indicate the valid location of the custom calculation result; The source-destination device physical interface number field is a multiplexed field. When a data message is sent to each target unit for table lookup matching, this field is used to indicate the source device physical interface number of the data message; when the table lookup matching of the data message hits, this field is used to indicate the destination device physical interface number of the data message; The ETHTYPE field is used in conjunction with the CAT field to indicate the internal encapsulation format; The VALUE field is used to store the corresponding five-tuple information and custom calculation results when the table is hit and / or there is a custom calculation.

[0012] On the other hand, the present invention provides a data processing method of a heterogeneous hybrid programmable switch structure system as described in the first aspect, comprising: The ASIC unit receives data packets arriving from the external network, performs protocol analysis on the received data packets and extracts key information, performs a match table lookup based on the extracted key information, and if the table lookup matches, executes the corresponding action according to the rule, and encapsulates the preset metadata with the original data packet, and then forwards the encapsulated data packet to the FPGA unit, CPU unit or system output port according to the table lookup result; if the table lookup does not match, the preset metadata is directly encapsulated with the original data packet, and the encapsulated data packet is forwarded to the CPU unit; The FPGA unit extracts metadata from the received data message, extracts the key from the metadata, and uses the key to perform table lookup matching. If the table lookup matches, the corresponding action is executed according to the rule, and the table lookup result is filled in the metadata. The metadata is then encapsulated with the original data message, and then the encapsulated data message is forwarded to the ASIC unit according to the table lookup result. If the table lookup does not match, the metadata is directly encapsulated with the original data message, and the encapsulated data message is forwarded to the CPU unit. The CPU unit extracts metadata from the received data message, extracts the key from the metadata, uses the key to perform table lookup matching, and if the table lookup matches, performs the corresponding action according to the rule, and forwards the table lookup result to the ASIC unit; The ASIC unit receives the data message from the FPGA unit or the CPU unit, and directly forwards the data message according to the outbound interface indication in the metadata of the data message.

[0013] Beneficial effects of the present invention: The present invention adopts three programmable target units with different characteristics. By combining the characteristics of different target units, a switch structure with high-performance processing rate, large-capacity flow table and flexible and definable structure is integrated to meet diverse data processing needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A heterogeneous hybrid programmable switch structure system provided by an embodiment of the present invention; Figure 2 A data frame format of a customized Ethernet header metadata is provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0016] like Figure 1 As shown, an embodiment of the present invention provides a heterogeneous hybrid programmable switch structure system, including: three levels of target units, namely, ASIC units, FPGA units and CPU units, arranged in order from high to low processing rates; that is, in the three-level pipeline structure, in order from high to low processing rates and from low to high flexibility, the ASIC unit is the first level, and the FPGA unit and the CPU unit are the second and third levels respectively.

[0017] The ASIC unit is used to perform basic processing on the received data message to generate a data message of a preset format; the FPGA unit is used to receive the data message from the ASIC unit, and process the received data message according to the rules and generate a data message of a preset format; the CPU unit is used to receive the data message from the ASIC unit and / or the FPGA unit, and process the received data message according to the rules and generate a data message of a preset format. All three target units are programmable.

[0018] It should be noted that, in the ASIC unit, the data message may come from the message arriving from the external network, or may be the data message processed by the CPU unit or the FPGA.

[0019] In the heterogeneous hybrid programmable switch structure system provided by the embodiment of the present invention, different target units are physically decoupled from each other and interconnected using standard Ethernet. The programmable ASIC unit at the front end is mainly used for basic data processing, while the FPGA unit and CPU unit can realize the function definition of the external function unit (extern function) in P4, support more flexible data processing, and flow tables with larger capacity, which can overcome the bottleneck shortcomings of existing programmable switches in complex function calculation, security function and state processing.

[0020] On the basis of the above embodiment, in this embodiment, each level of target unit is obtained by combining three or more modules among the parser, the matching action module, the inverse parser and the traffic management module; The parser is used to perform protocol analysis and extract key information (such as quintuple information) from the arriving data packets; the matching action module is used to match and look up the table based on the key information extracted by the parser, and perform corresponding actions according to the table lookup results; the inverse parser is used to encapsulate the data into a data packet in a preset format; the traffic management module is used to perform exchange scheduling and traffic shaping on the data packets. The matching table lookup includes three matching table lookup operations: longest match, exact match, and range match, and the corresponding actions include adding, modifying, or deleting a protocol field.

[0021] like Figure 1 As shown, as an implementable embodiment, the ASIC unit includes a first-level parser, a first-level matching action module, a first-level inverse parser, a traffic management module, a second-level parser, a second-level matching action module, and a second-level inverse parser connected in sequence. The FPGA unit includes an input queue module, a parser, a matching action module, an inverse parser, and an output queue module connected in sequence. The CPU unit includes a parser, a first-level matching action module, a traffic management module, a second-level matching action module, and an inverse parser connected in sequence.

[0022] On the basis of the above embodiments, an external function module is further provided in the FPGA unit and the CPU unit, and the external function module is used to support user-defined operations for functional expansion of the entire system. Specifically, in the CPU unit, the external function module interacts with two matching action modules so as to process data messages according to the output of the external function module. The FPGA unit interacts with the parser, the matching action module and the inverse parser so as to process data messages according to the output of the external function module.

[0023] On the basis of the above embodiments, in order to better coordinate the efficiency of heterogeneous resources, this embodiment defines a data message format, and the three target units use this custom data message format to transmit data messages and metadata. Specifically, based on the data frame format of the standard Ethernet layer 2 frame structure transmission, a custom Ethernet header format is used to encapsulate a metadata before the original layer 2 frame, so as to pass the interface, key, matching structure and other information of the previous level to the programmable unit of the next level. Figure 2 As shown, the customized Ethernet header in the embodiment of the present invention includes a reserved RSV field, a CAT field, a source and destination device physical interface number field, an ETHTYPE field and a VALUE field.

[0024] The custom Ethernet header uses a total of 59 (6+6+2+45) bytes. Since the data is encapsulated and transmitted within the entire system, there is no problem of communicating with external devices, so the definition of the protocol field is optimized. The specific format is as follows: In the standard DMAC field, the first two bytes are reserved, that is, the two-byte RSV field, which is all 0 by default; the middle two-byte CAT field is used for classification description in the three-level target unit processing stage, which is used to indicate whether the table lookup of the previous level target unit is hit, whether there is a custom calculation, and indicate the valid position of the custom calculation result; the last 2 bytes of the standard DMAC field plus the 6 bytes of SMAC form an 8-byte source and destination device physical interface number field, which is a multiplexed field. When the data message is sent to each target unit for table lookup matching, this field is used to indicate the source device physical interface number of the data message; when the table lookup match of the data message is hit, this field is used to indicate the destination device physical interface number of the data message. This field is 8 bytes, using one-hot encoding to correspond to physical ports, and can support up to 64 physical ports. When multiple ports are required to forward data packets, the bit position corresponding to the interface can be set to 1. The ETHTYPE field (i.e., Ethernet type field) is used to cooperate with the CAT field to indicate the internal encapsulation format; specifically, this field inherits the usage of standard Ethernet and uses the undetermined "0xAAAA" as the identifier of the internal format encapsulation. If the ETHTYPE field is "0xAAAA" and the CAT value is all 0, it means that the original data packet is after the ETHTYPE field, that is, there is no VALUE field at this time, otherwise there is a VALUE field. The VALUE field is used to store the corresponding five-tuple information and custom calculation results when the table is hit and / or there is a custom calculation. The field is 45 bytes in total, of which the first 13 bytes are 5-tuple information and the last 32 bytes are the custom calculation results. The effective length of the custom calculation result can be obtained according to the last byte of the CAT field, and the maximum length does not exceed 256 bits.

[0025] Based on the above-mentioned heterogeneous hybrid programmable switch structure system, an embodiment of the present invention further provides a data processing method of the system, which is divided into three processing stages: ASIC processing, FPGA processing and CPU processing. The specific processing flow is as follows: The ASIC unit receives data packets arriving from the external network, performs protocol analysis on the received data packets and extracts key information (such as source IP address, destination IP address, source port, destination port, etc.), performs matching table lookup (such as longest match of destination IP, exact match of five-tuple, or range match, etc.) according to the extracted key information. If the table lookup is a hit, the corresponding action is executed according to the rule, and the preset metadata is encapsulated with the original data packet, and then the encapsulated data packet is forwarded to the FPGA unit, CPU unit or system output port according to the table lookup result; if the table lookup is not a hit, the preset metadata is directly encapsulated with the original data packet, and the encapsulated data packet is forwarded to the CPU unit; Specifically, after the data message arrives, it must first enter the first-level parser for protocol parsing, and then extract the keywords in the data message. According to the extracted keywords, a matching table lookup is performed in the first-level matching action module. After the first-level inverse parser is used to encapsulate the table lookup result and the data message, the data packet is exchanged to the second-level parser through the traffic management module. After extracting the corresponding keywords, a table lookup operation is performed again in the second-level matching action module. The data packet is then edited and modified, and sent to the inverse parser to be encapsulated into a new data message, and the new data message is forwarded to the FPGA unit, CPU unit or system output port.

[0026] The FPGA unit extracts metadata from the received data message, extracts the key from the metadata, and uses the key to perform table lookup matching (table lookup matching in the on-chip TCAM or off-chip SDRAM HASH). If the table lookup matches, the corresponding action is executed according to the rule (when an external functional module is set in the FPGA internal unit, the action here may include the action output by the external functional module), and the table lookup result is filled in the metadata, and then the metadata is encapsulated with the original data message, and then the encapsulated data message is forwarded to the ASIC unit according to the table lookup result; if the table lookup does not hit, the metadata is directly encapsulated with the original data message, and the encapsulated data message is forwarded to the CPU unit; Specifically, in the FPGA unit, the data message sent from the ASIC unit is received. After the data message arrives, it first enters the input queue module for queuing before processing, and then enters the parser to parse the internal data format, and perform a table lookup operation in the matching action module according to the definition of the internal format field. Data processing is performed based on the table lookup results. This part of the processing can be performed in a user-defined external function unit, and then the data message is encapsulated by the inverse parser and sent to the next-level target unit.

[0027] The CPU unit extracts metadata from the received data message, extracts the key from the metadata, uses the key to perform table lookup and matching, and if the table lookup matches, executes the corresponding action according to the rule (when an external function module is provided in the CPU internal unit, the action here may include the action output by the external function module), and forwards the table lookup result to the ASIC unit; Specifically, in the CPU unit, data packets sent from the ASIC unit and the FPGA unit are received. After the data packet arrives, it first enters the parser to parse the internal data format, and performs a table lookup operation in the matching action module according to the definition of the internal format field. Data processing is performed based on the table lookup results. This part of the processing can be performed in a user-defined external function unit, and then the data packet is encapsulated through the inverse parser and sent to the next-level target unit.

[0028] The ASIC unit receives data packets from the FPGA unit or the CPU unit, and directly forwards the data packets according to the outgoing interface indication in the metadata of the data packets; that is, for data packets returned from the CPU unit or the FPGA unit to the ASIC unit and requiring secondary processing in the ASIC unit, the ASIC unit directly forwards the data packets out of the ASIC unit according to the outgoing interface indication in the metadata of the data packets, without performing a secondary table lookup operation.

[0029] The heterogeneous hybrid programmable switch structure system and method provided by the present invention adopt three programmable target units with different characteristics, and by combining the characteristics of different target units, a switch structure with high-performance processing rate, large-capacity flow table and flexible and definable is integrated.

[0030] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A heterogeneous hybrid programmable switch structure system, characterized in that: include: Three levels of target units, ASIC unit, FPGA unit, and CPU unit, arranged in descending order of processing rate; The ASIC unit is used to perform basic processing on the received data message to generate a data message in a preset format; The FPGA unit is used to receive the data message from the ASIC unit, and process the received data message according to the rules and generate a data message in a preset format; The CPU unit is used to receive data messages from the ASIC unit and / or the FPGA unit, process the received data messages according to the rules, and generate data messages in a preset format.

2. A heterogeneous hybrid programmable switch structure system according to claim 1, characterized in that: Each level of target unit is obtained by combining three or more modules among the parser, matching action module, inverse parser and traffic management module; The parser is used to perform protocol parsing and key information extraction on the arriving data message; the matching action module is used to perform matching table lookup based on the key information extracted by the parser, and execute corresponding actions according to the table lookup result; The reverse parser is used to encapsulate the data into a data message in a preset format; The traffic management module is used to perform exchange scheduling and traffic shaping on data messages.

3. A heterogeneous hybrid programmable switch structure system according to claim 2, characterized in that: The ASIC unit includes a primary parser, a primary matching action module, a primary inverse parser, a traffic management module, a secondary parser, a secondary matching action module and a secondary inverse parser which are connected in sequence.

4. A heterogeneous hybrid programmable switch structure system according to claim 2, characterized in that: The FPGA unit includes an input queue module, a parser, a matching action module, an inverse parser and an output queue module which are connected in sequence.

5. A heterogeneous hybrid programmable switch structure system according to claim 2, characterized in that: The CPU unit includes a parser, a primary matching action module, a traffic management module, a secondary matching action module and a reverse parser which are connected in sequence.

6. A heterogeneous hybrid programmable switch structure system according to claim 1, characterized in that: An external function module is also provided in the FPGA unit and / or the CPU unit, and the external function module is used to support user-defined operations; correspondingly, the FPGA unit and / or the CPU unit processes the received data message according to the rules and / or the output of the external function module and generates a data message in a preset format.

7. A heterogeneous hybrid programmable switch structure system according to any one of claims 1 to 6, characterized in that: The data message in the preset format includes a data message formed by encapsulating a custom Ethernet header outside the original data message to encapsulate the original data message and metadata together.

8. A heterogeneous hybrid programmable switch structure system according to claim 7, characterized in that: The custom Ethernet header includes a reserved field, a CAT field, a source-destination device physical interface number field, an ETHTYPE field, and a VALUE field; The CAT field is used to indicate whether the table lookup of the previous target unit is hit, whether there is a custom calculation, and to indicate the valid location of the custom calculation result; The source-destination device physical interface number field is a multiplexed field. When a data message is sent to each target unit for table lookup matching, this field is used to indicate the source device physical interface number of the data message; when the table lookup matching of the data message hits, this field is used to indicate the destination device physical interface number of the data message; The ETHTYPE field is used in conjunction with the CAT field to indicate the internal encapsulation format; The VALUE field is used to store the corresponding five-tuple information and custom calculation results when the table is hit and / or there is a custom calculation.

9. A data processing method for a heterogeneous hybrid programmable switch structure system according to any one of claims 1 to 8, characterized in that: include: The ASIC unit receives data packets arriving from the external network, performs protocol analysis on the received data packets and extracts key information, performs a match table lookup based on the extracted key information, and if the table lookup matches, executes the corresponding action according to the rule, and encapsulates the preset metadata with the original data packet, and then forwards the encapsulated data packet to the FPGA unit, CPU unit or system output port according to the table lookup result; if the table lookup does not match, the preset metadata is directly encapsulated with the original data packet, and the encapsulated data packet is forwarded to the CPU unit; The FPGA unit extracts metadata from the received data message, extracts the key from the metadata, uses the key to perform table lookup matching, and if the table lookup matches, executes the corresponding action according to the rule, and fills the table lookup result into the metadata, then encapsulates the metadata and the original data message together, and then forwards the encapsulated data message to the ASIC unit according to the table lookup result; If the table query does not hit, the metadata is directly encapsulated with the original data message, and the data message generated after encapsulation is forwarded to the CPU unit; The CPU unit extracts metadata from the received data message, extracts the key from the metadata, uses the key to perform table lookup matching, and if the table lookup matches, performs the corresponding action according to the rule, and forwards the table lookup result to the ASIC unit; The ASIC unit receives the data message from the FPGA unit or the CPU unit, and directly forwards the data message according to the outbound interface indication in the metadata of the data message.

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