Semiconductor structure and forming method thereof

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a substrate comprising a memory cell region, the memory cell region comprising sub-cell regions extending in a first direction and adjacent in a second direction, the first direction being perpendicular to the second direction, each subunit region comprises a first channel structure and a second channel structure which are located on the substrate, extend in the first direction and are arranged in parallel in the second direction; the first gate structure stretches across the first channel structure and the second channel structure, the first gate structure and the first channel structure form a pull-down transistor, and the first gate structure and the second channel structure form a pull-up transistor; the second gate structures are separately arranged on the two sides of the first channel structure, the second gate structures and the first channel structure form a transmission gate transistor, and the second gate structures and the first gate structures are arranged in parallel in the first direction. The reading working range and the writing working range of the semiconductor structure can be reduced or increased, so that the performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be primarily categorized into three main types: logic, memory, and analog circuits. Memory devices account for a significant portion of integrated circuit products. With the advancement of semiconductor technology, the wider application of memory devices requires integrating these devices with other device areas on a single chip to form an embedded semiconductor memory device. For example, if a memory device is embedded within a central processing unit (CPU), it is necessary to ensure compatibility with the CPU platform and maintain the original memory device specifications and corresponding electrical performance.

[0003] Generally, the memory device needs to be compatible with the embedded standard logic device. For embedded semiconductor devices, they are usually divided into a logic area and a storage area. The logic area usually includes logic devices, and the storage area includes memory devices. With the development of storage technology, various types of semiconductor memories have emerged, such as static random access memory (SRAM), dynamic random access memory (DRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory (Flash). Due to the advantages of low power consumption and fast operating speed, static random access memory and its formation method have received more and more attention.

[0004] However, the performance of SRAM devices still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to improving the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a memory cell area, the memory cell area including a sub-cell area extending along a first direction and adjacent along a second direction, the first direction being perpendicular to the second direction, the sub-cell area including: a first channel structure and a second channel structure located on the substrate and extending along the first direction and arranged in parallel along the second direction; a first gate structure spanning the first channel structure and the second channel structure, the first gate structure and the first channel structure constituting a pull-down transistor, and the first gate structure and the second channel structure constituting a pull-up transistor; a second gate structure separated on both sides of the first channel structure, the second gate structure and the first channel structure constituting a transfer gate transistor, and the second gate structure and the first gate structure being arranged in parallel along the first direction.

[0007] Optionally, the semiconductor structure also includes: a first source-drain doped layer, located in the first channel structure on both sides of the first gate structure and on both sides of the second gate structure; a second source-drain doped layer, located in the second channel structure on both sides of the first gate structure; the first source-drain doped layer of the pull-down transistor is electrically connected to the second source-drain doped layer of the pull-up transistor.

[0008] Optionally, the semiconductor structure also includes: a shared plug, located on the top of the first source-drain doped layer between the first gate structure and the second gate structure, and extending along the second direction and also located on the top of the second source-drain doped layer on the same side of the first gate structure; a source-drain plug, located on the top of the second source-drain doped layer on the other side of the first gate structure, and on the top of the remaining first source-drain doped layer; a gate plug, located on the top of the first gate structure, and the first gate structure is electrically connected to the gate plug.

[0009] Optionally, the gate plug is further located on top of a shared plug of an adjacent sub-cell region, and the gate plug is electrically connected to the shared plug of the adjacent sub-cell region.

[0010] Optionally, the source-drain plug on top of the second source-drain doped layer on the other side of the first gate structure is used to access VDD; the source-drain plug on top of the first source-drain doped layer on the other side of the first gate structure is used to access VSS.

[0011] Optionally, the semiconductor structure also includes: a first word line, located on the top of the second gate structure on one side of the first channel structure, and the first word line is electrically connected to the second gate structure; a second word line, located on the top of the second gate structure on the other side of the first channel structure, and the second word line is electrically connected to the second gate structure.

[0012] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a memory cell area, the memory cell area including a sub-cell area extending along a first direction and adjacent along a second direction, the first direction being perpendicular to the second direction; in the sub-cell area, forming a first channel structure and a second channel structure extending along the first direction and arranged in parallel along the second direction on the substrate; forming a first gate structure spanning the first channel structure and the second channel structure, the first gate structure and the first channel structure constituting a pull-down transistor, and the first gate structure and the second channel structure constituting a pull-up transistor; forming a second gate structure separated on both sides of the first channel structure, the second gate structure and the first channel structure constituting a transfer gate transistor, and the second gate structure and the first gate structure are arranged in parallel along the first direction.

[0013] Optionally, after forming the first gate structure and the second gate structure, the formation method also includes: forming a first source-drain doping layer in the first channel structure on both sides of the first gate structure and on both sides of the second gate structure; forming a second source-drain doping layer in the second channel structure on both sides of the first gate structure; and electrically connecting the first source-drain doping layer of the pull-down transistor to the second source-drain doping layer of the pull-up transistor.

[0014] Optionally, the steps of forming the first gate structure and the second gate structure include: forming a first dielectric layer covering the first channel structure and the second channel structure on the top of the substrate of the sub-unit area; forming a first opening in the first dielectric layer to expose a portion of the top and side walls of the first channel structure and the second channel structure, and forming a second opening in the first dielectric to expose a portion of the top and side walls of the first channel structure, the first opening and the second opening extending along the second direction and arranged parallel to the first direction; forming a gate material layer in the first opening and the second opening; flattening the gate material layer located in the second opening so that the top of the remaining gate material layer in the second opening is flush with the top of the first channel structure, and using the gate material layer located in the first opening as the first gate structure and the remaining gate material layer located in the second opening as the second gate structure.

[0015] Optionally, after forming the first source-drain doped layer and the second source-drain doped layer, the method for forming the semiconductor structure further includes: forming a shared plug on the top of the first source-drain doped layer located between the first gate structure and the second gate structure, and on the top of the second source-drain doped layer extending along the second direction and also located on the same side of the first gate structure; forming a source-drain plug on the top of the second source-drain doped layer located on the other side of the first gate structure, and on the top of the remaining first source-drain doped layer; forming a gate plug on the top of the first gate structure, and the first gate structure is electrically connected to the gate plug.

[0016] Optionally, in the step of forming the gate plug, the gate plug is also located on top of the shared plug of the adjacent sub-cell region, and the gate plug is electrically connected to the shared plug of the adjacent sub-cell region.

[0017] Optionally, in the step of forming source-drain plugs, the source-drain plug formed on the top of the second source-drain doped layer on the other side of the first gate structure is used to access VDD; the source-drain plug formed on the top of the first source-drain doped layer on the other side of the first gate structure is used to access VSS.

[0018] Optionally, after forming a second gate structure separated from both sides of the first channel structure, the method for forming a semiconductor structure further includes: forming a first word line on the top of the second gate structure on one side of the first channel structure, and the first word line is electrically connected to the second gate structure; forming a second word line on the top of the second gate structure on the other side of the first channel structure, and the second word line is electrically connected to the second gate structure.

[0019] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0020] The semiconductor structure provided by an embodiment of the present invention is provided with a second gate structure separated on both sides of the first channel structure, the second gate structure and the first channel structure constitute a transmission gate transistor, and the second gate structure and the first gate structure are arranged parallel to each other along a first direction. By providing the second gate structure separated on both sides of the first channel structure, a voltage signal can be applied to the second gate structures on both sides of the first channel structure separately, or a voltage signal can be applied to the second gate structures on both sides of the first channel structure at the same time, so that the current of the transmission gate transistor can be reduced or increased, that is, the reading operating range and the writing operating range of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 2 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0022] Figures 3 to 9 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0023] The performance of current semiconductor structures needs to be improved. Specifically, the read operating range of SRAM devices is determined by the beta ratio (I pd / I pg ), the write operating range of the SRAM device is determined by the gamma ratio (Ipg / Ipu), however, when the SRAM device is in operation, the Ipg value remains fixed, resulting in the read operating range and the write operating range of the SRAM device not being expanded or reduced.

[0024] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a memory cell area, the memory cell area including a sub-cell area extending along a first direction and adjacent along a second direction, the first direction being perpendicular to the second direction, the sub-cell area including: a first channel structure and a second channel structure located on the substrate and extending along the first direction and arranged in parallel along the second direction; a first gate structure spanning the first channel structure and the second channel structure, the first gate structure and the first channel structure constituting a pull-down transistor, and the first gate structure and the second channel structure constituting a pull-up transistor; a second gate structure separated on both sides of the first channel structure, the second gate structure and the first channel structure constituting a transfer gate transistor, and the second gate structure and the first gate structure are arranged in parallel along the first direction.

[0025] In the semiconductor structure provided by an embodiment of the present invention, a second gate structure is provided separately on both sides of the first channel structure, the second gate structure and the first channel structure constitute a transmission gate transistor, and the second gate structure and the first gate structure are arranged parallel to each other along a first direction. By providing a second gate structure separately on both sides of the first channel structure, a voltage signal can be applied separately to the second gate structures on both sides of the first channel structure, or a voltage signal can be applied to the second gate structures on both sides of the first channel structure at the same time, so that the current of the transmission gate transistor can be reduced or increased, that is, the reading operating range and the writing operating range of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure.

[0026] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] Figures 1 to 2 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 1 is a top view of the semiconductor structure. Figure 2 yes Figure 1 Cross-sectional view along direction BB.

[0028] The semiconductor structure includes: a substrate 201, including a memory cell region 200A, the memory cell region 200A including a first direction (eg Figure 1 X direction) and extends along the second direction (as shown in FIG. Figure 1The first direction is perpendicular to the second direction. The sub-unit area 200B is adjacent to the substrate 201, and includes: a first channel structure 202 and a second channel structure 203 located on the substrate 201, extending along the first direction and arranged in parallel along the second direction; a first gate structure 210 spanning the first channel structure 202 and the second channel structure 203, wherein the first gate structure 210 and the first channel structure 202 constitute a pull-down transistor, and the first gate structure 210 and the second channel structure 203 constitute a pull-up transistor; and a second gate structure 212 separated on both sides of the first channel structure 202, wherein the second gate structure 212 and the first channel structure 202 constitute a transfer gate transistor, and the second gate structure 212 and the first gate structure 210 are arranged in parallel along the first direction.

[0029] It should be noted that by providing a second gate structure 212 separated from both sides of the first channel structure 202, a voltage signal can be applied to the second gate structures 212 on both sides of the first channel structure 202 separately, or a voltage signal can be applied to the second gate structures 212 on both sides of the first channel structure 202 at the same time, so that the current of the transmission gate transistor can be reduced or increased, that is, the reading operating range and the writing operating range of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure.

[0030] The substrate 201 provides a process platform for disposing semiconductor structures.

[0031] In this embodiment, the base 201 includes a substrate.

[0032] The substrate is made of silicon. In other embodiments, the substrate may be made of one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be a material suitable for process requirements or easy to integrate.

[0033] In this embodiment, the semiconductor structure is an SRAM device, and the SRAM device includes a plurality of memory cell areas 200A.

[0034] Specifically, in the SRAM device, a plurality of memory cell regions 200A are arranged in a matrix along the first direction and the second direction.

[0035] In this embodiment, the memory cell region 200A includes sub-cell regions 200B extending along a first direction and adjacent to each other along a second direction, where the first direction is perpendicular to the second direction.

[0036] Specifically, each sub-unit region 200B includes a pass gate transistor region, a pull-down transistor region, and a pull-up transistor region.

[0037] Specifically, the pass gate transistor region is used to form a pass gate transistor, the pull-down transistor region is used to form a pull-down transistor, and the pull-up transistor region is used to form a pull-up transistor. The pass gate transistor and the pull-down transistor are both N-type transistors, and the pull-up transistor is a P-type transistor.

[0038] The first channel structure 202 is used to provide a conductive channel for the pull-down transistor and the pass-gate transistor, and the second channel structure 203 is used to provide a conductive channel for the pull-up transistor.

[0039] In this embodiment, the materials of the first channel structure 202 and the second channel structure 203 are both silicon. In other embodiments, the materials of the first channel structure 202 and the second channel structure 203 may also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The material of the first channel structure 202 may also be different from that of the substrate.

[0040] It should be noted that the first gate structure 210 is used to control the on and off of the conductive channels of the pull-down transistor and the pull-up transistor, and the second gate structure 212 is used to control the on and off of the conductive channel of the transfer gate transistor.

[0041] The first gate structure 210 spans the first channel structure 202 and the second channel structure 203 . That is, the first gate structure 210 covers the top and sidewalls of the fin.

[0042] It should also be noted that by providing a second gate structure 212 separated from both sides of the first channel structure 202, a voltage signal can be applied to the second gate structures 212 on both sides of the first channel structure 202 separately, or a voltage signal can be applied to the second gate structures 212 on both sides of the first channel structure 202 at the same time, so that the current of the transmission gate transistor can be reduced or increased, that is, the reading operating range and the writing operating range of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure.

[0043] Specifically, the read operating range of the SRAM device is determined by the beta ratio (I pd / I pg ) is determined by the gamma ratio (I pg / I pu ) determines that by controlling the current of the transmission gate transistor to increase or decrease, the beta ratio and gamma ratio of the SRAM device are increased or decreased, thereby reducing or increasing the read operating range and write operating range of the SRAM device.

[0044] In this embodiment, the first gate structure 210 and the second gate structure 212 are both metal gate structures. The first gate structure 210 includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer. The second gate structure 212 also includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0045] The gate dielectric layer is used to electrically isolate the gate electrode layer from the first channel structure 202 , and to electrically isolate the gate electrode layer from the second channel structure 203 .

[0046] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0047] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0048] It should be noted that the gate dielectric layer may further include a gate oxide layer, which is located between the high-k gate dielectric layer and the first channel structure 202, and between the high-k gate dielectric layer and the second channel structure 203. Specifically, the gate oxide layer may be made of silicon oxide.

[0049] In this embodiment, the material of the gate electrode layer is one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0050] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to electrically lead out the metal gate structure.

[0051] In other embodiments, according to process requirements, the first gate structure and the second gate structure may also be polysilicon gate structures.

[0052] It should be noted that, as an example, the transfer gate transistor and the pull-down transistor share the same first channel structure 202 to meet the working requirements of the SRAM device.

[0053] As an example, the pull-down transistor and the pull-up transistor share the first gate structure 210 to meet the operating requirements of the SRAM device.

[0054] In this embodiment, the semiconductor structure further includes: a first source-drain doped layer (not labeled) located in the first channel structure 202 on both sides of the first gate structure 210 and on both sides of the second gate structure 212 .

[0055] The first source-drain doped layer is used as the source region and the drain region of the pull-down transistor, and is used as the source region and the drain region of the transfer gate transistor.

[0056] The doping type of the first source-drain doping layer is the same as the channel conductivity type of the corresponding transistor.

[0057] Since both the transfer gate transistor and the pull-down transistor are N-type transistors, the doping type of the first source-drain doping layer is N-type.

[0058] It should be noted that, as an example, in the process of forming the first channel structure 202 , the first channel structure 202 has doping ions, and the doping type is the same as that of the first source and drain doping layer.

[0059] The first channel structure 202 has doping ions, and the doping type is the same as that of the first source and drain doping layer. Therefore, both the transfer gate transistor and the pull-down transistor are junctionless field effect transistors (JLT), which is beneficial to simplifying the formation process and steps of the SRAM device.

[0060] In this embodiment, the semiconductor structure further includes a second source-drain doped layer (not labeled) located in the second channel structure 203 on both sides of the first gate structure 210 .

[0061] The second source-drain doped layer is used as the source region and the drain region of the pull-up transistor.

[0062] The doping type of the second source-drain doping layer is the same as the channel conductivity type of the corresponding transistor.

[0063] Since the pull-up transistor is a P-type transistor, the doping type of the second source-drain doping layer is P-type.

[0064] It should be noted that, as an example, in the process of forming the second channel structure 203 , the second channel structure 203 has doping ions, and the doping type is the same as that of the second source and drain doping layer.

[0065] The second channel structure 203 has doping ions, and the doping type is the same as that of the second source and drain doping layer. The pull-up transistor adopts a junctionless field effect transistor (JLT), which is beneficial to simplifying the formation process and steps of the SRAM device.

[0066] That is to say, after forming the first channel structure 202 and the second channel structure 203 with doped ions, there is no need to perform source-drain doping. Instead, the first channel structure 202 on both sides of the first gate structure 210 and the first channel structure 212 on both sides are used as the first source-drain doping layer, and the second channel structure 203 on both sides of the first gate structure 210 are used as the second source-drain doping layer, thereby forming a junction-less field effect transistor, which greatly reduces the difficulty of forming the semiconductor structure.

[0067] In this embodiment, the second source-drain doped layer of the pull-up transistor is electrically connected to the first source-drain doped layer of the pull-down transistor.

[0068] Specifically, in each sub-unit area 200B, the drain region of the pull-up transistor is connected to the drain region of the pull-down transistor, and the pull-up transistor and the pull-down transistor share the first gate structure 210. Then, in two adjacent sub-unit areas 200B, the pull-up transistor and the pull-down transistor constitute a first CMOS transistor and a second CMOS transistor, respectively. The input end of the first CMOS transistor is connected to the output end of the second CMOS transistor, and the output end of the first CMOS transistor is connected to the input end of the second CMOS transistor.

[0069] In this embodiment, the semiconductor structure further includes: a shared plug 228 located on top of the first source / drain doped layer between the first gate structure 210 and the second gate structure 212 , and extending along the second direction and located on top of the second source / drain doped layer on the same side as the first gate structure 210 .

[0070] It should be noted that the shared plug 228 electrically connects the first source-drain doped layer between the first gate structure 210 and the second gate structure 212 and the second source-drain doped layer extending along the second direction and located on the same side of the first gate structure 210, thereby achieving electrical connection between the drain region of the pull-up transistor and the drain region of the pull-down transistor in each sub-unit area 200B.

[0071] In this embodiment, the shared plug 228 is made of tungsten. In other embodiments, the shared plug may be made of cobalt or ruthenium.

[0072] In this embodiment, the semiconductor structure further includes: a source / drain plug 226 , a top portion of the second source / drain doped layer located on the other side of the first gate structure 210 , and a top portion of the remaining first source / drain doped layer.

[0073] The source-drain plug 226 is used to electrically lead out the first source-drain doped layer and the second source-drain doped layer, so that in each sub-unit area 200B, the source area of ​​the pull-up transistor is connected to the power supply voltage, the source area of ​​the pull-down transistor is connected to the power supply voltage, and the source area of ​​the transfer gate transistor is connected to the bit line BL.

[0074] In this embodiment, the source-drain plug 226 on the top of the second source-drain doped layer on the other side of the first gate structure 210 is used to access VDD.

[0075] Specifically, VDD represents an input positive working voltage.

[0076] In this embodiment, the source-drain plug 226 on the top of the first source-drain doped layer on the other side of the first gate structure 210 is used to access VSS.

[0077] Specifically, VSS represents an input negative working voltage.

[0078] In this embodiment, the source / drain plugs 226 are made of tungsten. In other embodiments, the source / drain plugs 226 may be made of cobalt or ruthenium.

[0079] In this embodiment, the semiconductor structure further includes a gate plug 230 located on top of the first gate structure 210 , and the first gate structure 210 is electrically connected to the gate plug 230 .

[0080] The gate plug 230 is used to electrically lead out the first gate structure 210 , thereby controlling the conductive channels of the first channel structure 202 and the second channel structure 203 .

[0081] In this embodiment, the gate plug 230 is also located on top of the shared plug 228 of the adjacent sub-unit region 200B, and the gate plug 230 is electrically connected to the shared plug 228 of the adjacent sub-unit region 200B.

[0082] It should be noted that, in two adjacent sub-unit areas 200B, the pull-up transistor and the pull-down transistor constitute a first CMOS transistor and a second CMOS transistor respectively, and the gate plug 230 is electrically connected to the shared plug 228 of the adjacent sub-unit area 200B, so that the input end of the first CMOS transistor is connected to the output end of the second CMOS transistor, and the output end of the first CMOS transistor is connected to the input end of the second CMOS transistor.

[0083] In this embodiment, the semiconductor structure also includes: a first word line 261, located on the top of the second gate structure 212 on one side of the first channel structure 202, and the first word line 261 is electrically connected to the second gate structure 212; a second word line 260, located on the top of the second gate structure 212 on the other side of the first channel structure 202, and the second word line 260 is electrically connected to the second gate structure 212.

[0084] It should be noted that the first word line 261 and the second word line 260 are used to control the reading operation and the writing operation of the SRAM device.

[0085] It should also be noted that by setting the first word line 261 and the second word line 260 on both sides of the first channel structure 202, voltage signals can be applied to the first word line 261 and the second word line 260 respectively, or voltage signals can be applied to the first word line 261 and the second word line 260 at the same time, so that the current of the transmission gate transistor can be reduced or increased, that is, the read operating range and the write operating range of the semiconductor structure can be reduced or increased, thereby improving the performance of the SRAM device.

[0086] In this embodiment, the materials of the first word line 261 and the second word line 260 include one or more of TiN, Cu and W.

[0087] Figures 3 to 9 It is a schematic structural diagram corresponding to each step in an embodiment of a method for manufacturing a semiconductor structure of the present invention.

[0088] refer to Figure 3 , providing a substrate 101, the substrate 101 includes a memory cell region 100A, the memory cell region 100A includes a first direction (such as Figure 3 X direction) and extends along the second direction (as shown in FIG. Figure 3 For adjacent sub-unit regions 100B (shown in the Y direction), the first direction is perpendicular to the second direction.

[0089] The substrate 101 provides a process platform for forming a semiconductor structure.

[0090] In this embodiment, the base 101 includes a substrate.

[0091] The substrate is made of silicon. In other embodiments, the substrate may be made of one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be a material suitable for process requirements or easy to integrate.

[0092] In this embodiment, the semiconductor structure is an SRAM device, and the SRAM device includes a plurality of memory cell areas 100A.

[0093] Specifically, in the SRAM device, a plurality of memory cell regions 100A are arranged in a matrix along a first direction and a second direction.

[0094] In this embodiment, the memory cell region 100A includes sub-cell regions 100B extending along a first direction and adjacent to each other along a second direction, where the first direction is perpendicular to the second direction.

[0095] Specifically, each sub-unit region 100B includes a pass gate transistor region, a pull-down transistor region, and a pull-up transistor region.

[0096] Specifically, the pass gate transistor region is used to form a pass gate transistor, the pull-down transistor region is used to form a pull-down transistor, and the pull-up transistor region is used to form a pull-up transistor. The pass gate transistor and the pull-down transistor are both N-type transistors, and the pull-up transistor is a P-type transistor.

[0097] refer to Figure 4 In the sub-unit region 100B, a first channel structure 102 and a second channel structure 103 extending along a first direction and arranged in parallel along a second direction are formed on a substrate 101 .

[0098] Specifically, the first channel structure 102 is used to provide a conductive channel for the pull-down transistor and the pass-gate transistor, and the second channel structure 103 is used to provide a conductive channel for the pull-up transistor.

[0099] In this embodiment, the materials of the first channel structure 102 and the second channel structure 103 are both silicon. In other embodiments, the materials of the first channel structure 102 and the second channel structure 103 may also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, and indium gallium. The material of the first channel structure 102 may also be different from that of the substrate.

[0100] In this embodiment, the steps of forming the first channel structure 102 and the second channel structure 103 include: forming a channel material layer (not shown) on the substrate 101; forming a first mask layer (not shown) and a second mask layer (not shown) on top of the channel material layer, the first mask layer and the second mask layer both extending along the first direction and arranged in parallel with each other along the second direction; using the first mask layer and the second mask layer as masks, patterning the channel material layer to form the first channel structure 102 and the second channel structure 103 extending along the first direction and arranged in parallel with the second direction on the substrate 101.

[0101] In this embodiment, the process of patterning the channel material layer includes a dry etching process.

[0102] refer to Figure 5 and Figure 6 ,in, Figure 5 It is a top view. Figure 6 yes Figure 5 In the cross-sectional view along the AA direction, a first gate structure 110 is formed spanning the first channel structure 102 and the second channel structure 103. The first gate structure 110 and the first channel structure 102 constitute a pull-down transistor, and the first gate structure 110 and the second channel structure 103 constitute a pull-up transistor, forming a second gate structure 112 separated on both sides of the first channel structure 102. The second gate structure 112 and the first channel structure 102 constitute a transfer gate transistor, and the second gate structure 112 and the first gate structure 110 are arranged parallel to each other along the first direction.

[0103] It should be noted that the first gate structure 110 is used to control the on and off of the conductive channels of the pull-down transistor and the pull-up transistor, and the second gate structure 112 is used to control the on and off of the conductive channel of the transfer gate transistor.

[0104] It should also be noted that by providing a second gate structure 112 separated from both sides of the first channel structure 102, a voltage signal can be applied to the second gate structures 112 on both sides of the first channel structure 102 separately, or a voltage signal can be applied to the second gate structures 112 on both sides of the first channel structure 102 at the same time, so that the current of the transmission gate transistor can be reduced or increased, that is, the reading operating range and the writing operating range of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure.

[0105] Specifically, the read operating range of the SRAM device is determined by the beta ratio (I pd / I pg ) is determined by the gamma ratio (I pg / I pu ) determines that by controlling the current of the transmission gate transistor to increase or decrease, the beta ratio and gamma ratio of the SRAM device are increased or decreased, thereby reducing or increasing the read operating range and write operating range of the SRAM device.

[0106] In this embodiment, the steps of forming the first gate structure 110 and the second gate structure 112 include: forming a first dielectric layer (not shown) covering the first channel structure 102 and the second channel structure 103 on the top of the substrate 101 of the sub-unit area 100B; forming a first opening (not shown) in the first dielectric layer to expose a portion of the top and sidewalls of the first channel structure 102 and the second channel structure 103, and forming a second opening (not shown) in the first dielectric layer to expose a portion of the top and sidewalls of the first channel structure 102, the first opening and the second opening extending along the second direction and arranged parallel to the first direction; forming a gate material layer (not shown) in the first opening and the second opening; and performing a planarization process on the gate material layer located in the second opening so that the top of the remaining gate material layer in the second opening is flush with the top of the first channel structure 102, and using the gate material layer located in the first opening as the first gate structure 110, and using the remaining gate material layer located in the second opening as the second gate structure 112.

[0107] The first opening provides a spatial location for forming the first gate structure 110 .

[0108] In this embodiment, the process of forming the first opening includes an anisotropic dry etching process.

[0109] Specifically, the anisotropic dry etching process has the characteristics of anisotropic etching, its longitudinal etching rate is greater than the lateral etching rate, and it has better pattern transfer accuracy, thereby improving the morphology quality of the side wall of the first opening. At the same time, in the anisotropic dry etching process, the etching selectivity ratio between the first dielectric layer and the first channel structure 102 can be utilized to achieve the purpose of removing the first dielectric layer and reduce the probability of damaging the first channel structure 102.

[0110] The second opening provides a spatial location for forming the first gate structure 110 .

[0111] In this embodiment, the process of forming the second opening includes an anisotropic dry etching process.

[0112] As an example, the process of forming the gate material layer in the first opening and the second opening includes an atomic layer deposition process or a chemical vapor deposition process.

[0113] It should be noted that by flattening the gate material layer located in the second opening, the top of the remaining gate material layer in the second opening can be made flush with the top of the first channel structure 102, so that there are gate material layers on both sides of the first channel structure 102, and the gate material layers on both sides of the first channel structure 102 are used as the second gate structure 112, thereby achieving the purpose of applying voltage signals to the second gate structures 112 on both sides of the first channel structure 102 respectively, or applying voltage signals to the second gate structures 112 on both sides of the first channel structure 102 at the same time.

[0114] It should also be noted that the first gate structure 110 and the second gate structure 112 are formed in the same step, which reduces the number of process steps and reduces the process cost. In other embodiments, the first gate structure 110 and the second gate structure 112 can also be formed in different steps.

[0115] In this embodiment, the first gate structure 110 and the second gate structure 112 are both metal gate structures. The first gate structure 110 includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer. The second gate structure 112 also includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer.

[0116] The gate dielectric layer is used to electrically isolate the gate electrode layer from the first channel structure 102 , and to electrically isolate the gate electrode layer from the second channel structure 103 .

[0117] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0118] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0119] It should be noted that the gate dielectric layer may further include a gate oxide layer, which is located between the high-k gate dielectric layer and the first channel structure 102, and between the high-k gate dielectric layer and the second channel structure 103. Specifically, the gate oxide layer may be made of silicon oxide.

[0120] In this embodiment, the material of the gate electrode layer is one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0121] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to electrically lead out the metal gate structure.

[0122] In other embodiments, according to process requirements, the first gate structure 110 and the second gate structure 112 may also be polysilicon gate structures.

[0123] It should be noted that, as an example, the transfer gate transistor and the pull-down transistor share the same first channel structure 102 to meet the working requirements of the SRAM device.

[0124] As an example, the pull-down transistor and the pull-up transistor share the first gate structure 110 to meet the operating requirements of the SRAM device.

[0125] refer to Figure 7 After forming the first gate structure 110 and the second gate structure 112, the formation method further includes: forming a first source-drain doped layer 120 in the first channel structure 102 on both sides of the first gate structure 110 and on both sides of the second gate structure 112, and forming a second source-drain doped layer 122 in the second channel structure 103 on both sides of the first gate structure 110, and the first source-drain doped layer 120 of the pull-down transistor is electrically connected to the second source-drain doped layer 122 of the pull-up transistor.

[0126] The first source-drain doped layer 120 is used as the source region and the drain region of the pull-down transistor, and is used as the source region and the drain region of the pass-gate transistor.

[0127] The doping type of the first source / drain doped layer 120 is the same as the channel conductivity type of the corresponding transistor.

[0128] Since both the transfer gate transistor and the pull-down transistor are N-type transistors, the doping type of the first source-drain doped layer 120 is N-type.

[0129] It should be noted that, as an example, in the step of forming the first channel structure 102 , the first channel structure 102 has doping ions, and the doping type is the same as that of the first source / drain doping layer 120 .

[0130] The first channel structure 102 has doping ions, and the doping type is the same as that of the first source-drain doping layer 120 . Therefore, both the transfer gate transistor and the pull-down transistor are junctionless field effect transistors (JLT), which is beneficial to simplifying the formation process and steps of the SRAM device.

[0131] The second source-drain doped layer 122 is used as the source region and the drain region of the pull-up transistor.

[0132] The doping type of the second source / drain doped layer 122 is the same as the channel conductivity type of the corresponding transistor.

[0133] Since the pull-up transistor is a P-type transistor, the doping type of the second source-drain doped layer 122 is P-type.

[0134] It should be noted that, as an example, in the step of forming the second channel structure 103 , the second channel structure 103 has doping ions, and the doping type is the same as that of the second source / drain doping layer 122 .

[0135] The second channel structure 103 has doping ions, and the doping type is the same as that of the second source / drain doping layer 122 . The pull-up transistor adopts a junctionless field effect transistor (JLT), which is beneficial to simplifying the formation process and steps of the SRAM device.

[0136] That is to say, after forming the first channel structure 102 and the second channel structure 103 with doped ions, there is no need to perform source and drain doping. Instead, the first channel structure 102 on both sides of the first gate structure 110 and the first channel structure 112 on both sides are used as the first source and drain doping layer 120, and the second channel structure 103 on both sides of the first gate structure 110 are used as the second source and drain doping layer 122, thereby forming a junctionless field effect transistor, which greatly reduces the difficulty of forming the semiconductor structure.

[0137] In this embodiment, the second source-drain doped layer 122 of the pull-up transistor is electrically connected to the first source-drain doped layer 120 of the pull-down transistor.

[0138] Specifically, in each sub-unit area 100B, the drain region of the pull-up transistor is connected to the drain region of the pull-down transistor, and the pull-up transistor and the pull-down transistor share the first gate structure 110. Then, in two adjacent sub-unit areas 100B, the pull-up transistor and the pull-down transistor constitute a first CMOS transistor and a second CMOS transistor, respectively. The input end of the first CMOS transistor is connected to the output end of the second CMOS transistor, and the output end of the first CMOS transistor is connected to the input end of the second CMOS transistor.

[0139] refer to Figure 8 After forming the first source-drain doped layer 120 and the second source-drain doped layer 122, and before subsequently forming the shared plug, the gate plug and the source-drain plug, the second dielectric layer (not shown) is formed on top of the first dielectric layer, the first gate structure 110 and the second gate structure 112.

[0140] The second dielectric layer provides a process basis for the subsequent formation of shared plugs, source and drain plugs, and gate plugs.

[0141] In this embodiment, the second dielectric layer is made of an insulating material, specifically, one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide.

[0142] Continue to refer Figure 8 After forming the first source-drain doped layer 120 and the second source-drain doped layer 122, the method for forming the semiconductor structure further includes: forming a shared plug 128 on the top of the first source-drain doped layer 120 located between the first gate structure 110 and the second gate structure 112, and on the top of the second source-drain doped layer 122 extending along the second direction and also located on the same side of the first gate structure 110, forming a source-drain plug 126 on the top of the second source-drain doped layer 122 located on the other side of the first gate structure 110, and on the top of the remaining first source-drain doped layer 120, and forming a gate plug 130 on the top of the first gate structure 110, and the first gate structure 110 is electrically connected to the gate plug 130.

[0143] It should be noted that the shared plug 128 electrically connects the first source-drain doped layer 120 between the first gate structure 110 and the second gate structure 112, and the second source-drain doped layer 122 extending along the second direction and also located on the same side of the first gate structure 110, thereby achieving electrical connection between the drain region of the pull-up transistor and the drain region of the pull-down transistor in each sub-unit area 100B.

[0144] In this embodiment, the shared plug 128 is made of tungsten. In other embodiments, the shared plug may be made of cobalt or ruthenium.

[0145] The source-drain plug 126 is used to electrically lead out the first source-drain doped layer 120 and the second source-drain doped layer 122, so that in each sub-unit area 100B, the source area of ​​the pull-up transistor is connected to the power supply voltage, the source area of ​​the pull-down transistor is connected to the power supply voltage, and the source area of ​​the transfer gate transistor is connected to the bit line BL.

[0146] In this embodiment, in the step of forming the source-drain plug 126 , the source-drain plug 126 formed on the top of the second source-drain doped layer 122 on the other side of the first gate structure 110 is used to access VDD.

[0147] Specifically, VDD represents an input positive working voltage.

[0148] In this embodiment, in the step of forming the source / drain plug 126 , the source / drain plug 126 formed on the top of the first source / drain doped layer 120 on the other side of the first gate structure 110 is used to access VSS.

[0149] Specifically, VSS represents an input negative working voltage.

[0150] In this embodiment, the source / drain plugs 126 are made of tungsten. In other embodiments, the source / drain plugs 126 may be made of cobalt or ruthenium.

[0151] The gate plug 130 is used to electrically lead out the first gate structure 110 , thereby controlling the conductive channels of the first channel structure 102 and the second channel structure 103 .

[0152] In this embodiment, during the step of forming the gate plug 130 , the gate plug 130 is also located on top of the shared plug 128 of the adjacent sub-unit region 100B, and the gate plug 130 is electrically connected to the shared plug 128 of the adjacent sub-unit region 100B.

[0153] It should be noted that, in two adjacent sub-unit areas 100B, the pull-up transistor and the pull-down transistor constitute a first CMOS transistor and a second CMOS transistor, respectively, and the gate plug 130 is electrically connected to the shared plug 128 of the adjacent sub-unit area 100B, so that the input end of the first CMOS transistor is connected to the output end of the second CMOS transistor, and the output end of the first CMOS transistor is connected to the input end of the second CMOS transistor.

[0154] refer to Figure 9After forming the second gate structures 112 separated on both sides of the first channel structure 102, the method for forming the semiconductor structure further includes: forming a first word line 161 on top of the second gate structure 112 on one side of the first channel structure 102, and the first word line 161 is electrically connected to the second gate structure 112; forming a second word line 160 on top of the second gate structure 112 on the other side of the first channel structure 102, and the second word line 160 is electrically connected to the second gate structure 112.

[0155] It should be noted that the first word line 161 and the second word line 160 are used to control the reading operation and the writing operation of the SRAM device.

[0156] It should also be noted that by arranging the first word line 161 and the second word line 160 on both sides of the first channel structure 102, voltage signals can be applied to the first word line 161 and the second word line 160 respectively, or voltage signals can be applied to the first word line 161 and the second word line 160 at the same time, so that the current of the transmission gate transistor can be reduced or increased, that is, the reading operating range and the writing operating range of the semiconductor structure can be reduced or increased, thereby improving the performance of the semiconductor structure.

[0157] In this embodiment, the materials of the first word line 161 and the second word line 160 include one or more of TiN, Cu and W.

[0158] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, comprising a memory cell region, wherein the memory cell region comprises sub-unit regions extending along a first direction and adjacent to each other along a second direction, wherein the first direction is perpendicular to the second direction, and the sub-unit regions comprise: A first channel structure and a second channel structure located on the substrate and extending along the first direction and arranged in parallel along the second direction; a first gate structure spanning the first channel structure and the second channel structure, the first gate structure and the first channel structure forming a pull-down transistor, and the first gate structure and the second channel structure forming a pull-up transistor; A second gate structure is separated on both sides of the first channel structure, the second gate structure and the first channel structure constitute a transmission gate transistor, and the second gate structure and the first gate structure are arranged in parallel along the first direction.

2. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a first source-drain doped layer, located in the first channel structure on both sides of the first gate structure and on both sides of the second gate structure; A second source-drain doped layer is located in the second channel structure on both sides of the first gate structure; The first source-drain doping layer of the pull-down transistor is electrically connected to the second source-drain doping layer of the pull-up transistor.

3. The semiconductor structure according to claim 2, wherein: The semiconductor structure further includes: a shared plug located on the top of the first source-drain doped layer between the first gate structure and the second gate structure and extending along the second direction and located on the top of the second source-drain doped layer on the same side of the first gate structure; A source-drain plug located on the top of the second source-drain doped layer on the other side of the first gate structure and on the top of the remaining first source-drain doped layer; A gate plug is located on the top of the first gate structure, and the first gate structure is electrically connected to the gate plug.

4. The semiconductor structure according to claim 3, characterized in that The gate plug is also located on top of a shared plug adjacent to the sub-unit region, and the gate plug is electrically connected to the shared plug adjacent to the sub-unit region.

5. The semiconductor structure according to claim 3, wherein: A source-drain plug located on the top of the second source-drain doped layer on the other side of the first gate structure is used to access VDD; The source-drain plug located on the top of the first source-drain doped layer on the other side of the first gate structure is used to access VSS.

6. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a first word line located on the top of the second gate structure on one side of the first channel structure, and the first word line is electrically connected to the second gate structure; The second word line is located on the top of the second gate structure on the other side of the first channel structure, and the second word line is electrically connected to the second gate structure.

7. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a memory cell region, the memory cell region comprising sub-unit regions extending along a first direction and adjacent to each other along a second direction, the first direction being perpendicular to the second direction; In the sub-unit region, a first channel structure and a second channel structure extending along the first direction and arranged in parallel along the second direction are formed on the substrate; forming a first gate structure spanning the first channel structure and the second channel structure, wherein the first gate structure and the first channel structure constitute a pull-down transistor, and the first gate structure and the second channel structure constitute a pull-up transistor; A second gate structure is formed separately on both sides of the first channel structure, the second gate structure and the first channel structure constitute a transmission gate transistor, and the second gate structure and the first gate structure are arranged in parallel along the first direction.

8. The method for forming a semiconductor structure according to claim 7, wherein: After forming the first gate structure and the second gate structure, the forming method further includes: forming a first source-drain doping layer in the first channel structure on both sides of the first gate structure and on both sides of the second gate structure; forming a second source-drain doped layer in the second channel structure on both sides of the first gate structure; The first source-drain doped layer of the pull-down transistor is electrically connected to the second source-drain doped layer of the pull-up transistor.

9. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming the first gate structure and the second gate structure includes: forming a first dielectric layer covering the first channel structure and the second channel structure on the top of the substrate in the sub-unit area; Forming a first opening in the first dielectric layer to expose a portion of the top and sidewalls of the first and second channel structures, and forming a second opening in the first dielectric layer to expose a portion of the top and sidewalls of the first channel structure, wherein the first opening and the second opening extend along the second direction and are arranged in parallel along the first direction; forming a gate material layer in the first opening and the second opening; The gate material layer located in the second opening is planarized so that the top of the remaining gate material layer in the second opening is flush with the top of the first channel structure, and the gate material layer located in the first opening is used as the first gate structure, and the remaining gate material layer located in the second opening is used as the second gate structure.

10. The method for forming a semiconductor structure according to claim 8, wherein: After forming the first source-drain doped layer and the second source-drain doped layer, the method for forming the semiconductor structure further includes: forming a shared plug on the top of the first source-drain doped layer located between the first gate structure and the second gate structure, and on the top of the second source-drain doped layer extending along the second direction and also located on the same side of the first gate structure; forming a source-drain plug on the top of the second source-drain doped layer located on the other side of the first gate structure and on the top of the remaining first source-drain doped layer; A gate plug is formed on a top of the first gate structure, and the first gate structure is electrically connected to the gate plug.

11. The method for forming a semiconductor structure according to claim 10, wherein: In the step of forming the gate plug, the gate plug is also located on top of a shared plug of an adjacent sub-unit region, and the gate plug is electrically connected to the shared plug of the adjacent sub-unit region.

12. The method for forming a semiconductor structure according to claim 10, wherein: In the step of forming a source-drain plug, the source-drain plug formed on the top of the second source-drain doped layer on the other side of the first gate structure is used to access VDD; The source-drain plug formed on the top of the first source-drain doped layer on the other side of the first gate structure is used to access VSS.

13. The method for forming a semiconductor structure according to claim 7, wherein: After forming the second gate structure separated on both sides of the first channel structure, the method for forming the semiconductor structure further includes: forming a first word line on the top of the second gate structure on one side of the first channel structure, and the first word line is electrically connected to the second gate structure; A second word line is formed on the top of the second gate structure at the other side of the first channel structure, and the second word line is electrically connected to the second gate structure.

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