Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a storage unit region; a stacked gate structure is formed on the substrate of the storage unit area, the stacked gate structure comprises a floating gate structure and a control gate structure located on the floating gate structure, and acute angles are formed between the top face of the floating gate structure and the side walls of the two sides; in the storage unit area, an erase gate structure is formed on the substrate on one side of the floating gate structure, the erase gate structure covers part of the side wall of the laminated gate structure, and the top of the erase gate structure is higher than the top of the floating gate structure. According to the invention, the writing and erasing efficiency of the semiconductor structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be divided into three main types: analog circuits, digital circuits, and mixed analog / digital circuits. Among them, memory devices are an important type of digital circuits. In recent years, among memory devices, flash memory has developed particularly rapidly. The main feature of flash memory is that it can retain stored information for a long time without power; it also has the advantages of high integration, fast access speed, easy erasure and rewriting, etc., so it has been widely used in many fields such as microcomputers and automation control.

[0003] Flash memory mainly includes stacked gate flash memory and split gate flash memory, among which split gate flash memory has the advantages of low programming voltage and high programming efficiency and is widely used. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are helpful to ensure the performance of the semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a storage cell region; a stacked gate structure, located on the substrate in the storage cell region, the stacked gate structure including a floating gate structure and a control gate structure located on the floating gate structure, the top surface of the floating gate structure and the side walls on both sides form an acute angle; an erase gate structure, located in the storage cell region and on the substrate on one side of the floating gate structure, the erase gate structure covers part of the side walls of the stacked gate structure, and the top of the erase gate structure is higher than the top of the floating gate structure.

[0006] Optionally, the memory cell region includes two stacked gate structures, and the acute angles of the floating gate structures of the two stacked gate structures are arranged opposite to each other; and two adjacent stacked gate structures share the same erase gate structure.

[0007] Optionally, the semiconductor structure further includes: a dielectric layer located between the floating gate structure and the erase gate structure.

[0008] Optionally, the thickness of the dielectric layer located on the side of the top surface of the floating gate structure is to The thickness of the dielectric layer located on the bottom side of the floating gate structure is to

[0009] Optionally, the material of the dielectric layer includes silicon oxide.

[0010] Optionally, a doped region located at the top of the floating gate structure is formed in the floating gate structure, and the doped region contains inhibitory ions for inhibiting oxidation, and the doping concentration of the inhibitory ions gradually decreases from the top to the bottom of the doped region; the dielectric layer is obtained by oxidizing the material of the floating gate structure.

[0011] Optionally, a ratio of the thickness of the doped region to the total thickness of the floating gate structure is greater than or equal to 1 / 3.

[0012] Optionally, the doping ions in the doping region include nitrogen ions.

[0013] Optionally, the thickness of the floating gate structure is to

[0014] Optionally, the material of the floating gate structure includes polysilicon; the material of the control gate structure includes polysilicon; and the material of the erase gate structure includes polysilicon.

[0015] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, including a storage cell area; forming a stacked gate structure on the substrate in the storage cell area, the stacked gate structure including a floating gate structure and a control gate structure located on the floating gate structure, the top surface of the floating gate structure and the side walls on both sides form an acute angle; in the storage cell area, forming an erase gate structure on the substrate on one side of the floating gate structure, the erase gate structure covering part of the side walls of the stacked gate structure, and the top of the erase gate structure is higher than the top of the floating gate structure.

[0016] Optionally, in the step of forming the stacked gate structure, two stacked gate structures are formed in the memory cell region, and the acute angles of the floating gate structures of the two stacked gate structures are arranged relative to each other; in the step of forming the erase gate structure, two adjacent stacked gate structures share the same erase gate structure.

[0017] Optionally, the step of forming a stacked gate structure includes: forming a first gate material layer covering the substrate, and a second gate material layer located on the first gate material layer; patterning the second gate material layer, retaining the remaining second gate material layer protruding from the first gate material layer in the storage cell area as a control gate structure; patterning the first gate material layer exposed by the control gate structure to form an initial floating gate structure; performing side wall tilting processing on the initial floating gate structure to obtain an initial floating gate structure in which the top surface and the side walls on both sides form an acute angle as a floating gate structure.

[0018] Optionally, the step of patterning the first gate material layer exposed by the control gate structure to form an initial floating gate structure includes: forming a sidewall on the sidewall of the control gate structure; using the sidewall as a mask, patterning the first gate material layer exposed by the sidewall to form an initial floating gate structure.

[0019] Optionally, after forming the first gate material layer and before forming the second gate material layer, the formation method also includes: performing ion implantation treatment on the first gate material layer to form a doped region located at the top of the first gate material, wherein the doped region has inhibition ions for inhibiting oxidation; the step of performing sidewall tilting treatment on the initial floating gate structure includes: performing oxidation treatment on the sidewall of the initial floating gate structure to convert part of the material on the side of the initial floating gate structure into a dielectric layer, wherein the thickness of the dielectric layer gradually increases from the top to the bottom of the initial floating gate structure along a direction perpendicular to the sidewall of the floating gate structure, and the remaining initial floating gate structure is retained as a floating gate structure.

[0020] Optionally, in the step of performing ion implantation on the first gate material layer, a ratio of a thickness of the doped region to a total thickness of the first gate material layer is greater than or equal to 1 / 3.

[0021] Optionally, in the step of performing ion implantation on the first gate material layer, the implanted ions include nitrogen ions.

[0022] Optionally, in the step of performing ion implantation on the first gate material layer, an implantation dose of the ion implantation is 1E11 atoms / cm2 to 9E15 atoms / cm2, and an implantation energy is 2KeV to 30KeV.

[0023] Optionally, in the step of performing oxidation treatment on the sidewalls of the initial floating gate structure, the gas used for the oxidation treatment includes oxygen or a mixed gas of nitrogen and oxygen.

[0024] Optionally, in the step of performing oxidation treatment on the sidewalls of the initial floating gate structure, the oxidation treatment process temperature is 600° C. to 1200° C., and the process time is 10 seconds to 120 minutes.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0026] In the semiconductor structure provided by the embodiment of the present invention, the top surface of the floating gate structure and the side walls on both sides form an acute angle, the erase gate structure is located in the storage cell area and on the substrate on one side of the floating gate structure, the erase gate structure covers part of the side walls of the stacked gate structure, and the top of the erase gate structure is higher than the top of the floating gate structure; in the embodiment of the present invention, the top surface of the floating gate structure and the side walls on both sides form an acute angle, which is conducive to flexible selection of the formation position of the erase gate structure, and the top surface of the floating gate structure and the side walls on both sides form an acute angle, that is, the corner from the floating gate structure to the erase gate structure is an acute angle, the electric field at the acute angle is large, which is conducive to reducing the distance from the floating gate structure to the erase gate structure. The energy band barrier of the structure makes it easier for electrons to reach the erase gate structure from the floating gate structure, which is beneficial to improving the writing and erasing efficiency of the semiconductor structure. In addition, the corner pointing from the floating gate structure to the erase gate structure is an acute angle, which is beneficial to reducing the degree to which the corner pointing from the floating gate structure to the erase gate structure becomes rounded due to oxidation in the subsequent process, thereby helping to reduce the impact on the erase efficiency. At the same time, reducing the degree to which the corner pointing from the floating gate structure to the erase gate structure becomes rounded due to oxidation in the subsequent process is also beneficial to improving the coupling capacitance of the floating gate structure, thereby helping to improve the writing efficiency of the semiconductor structure, and further helping to ensure the performance of the semiconductor structure.

[0027] In the formation method provided by the embodiment of the present invention, the top surface of the floating gate structure and the side walls on both sides form an acute angle. In the storage cell area, an erase gate structure is formed on the substrate on one side of the floating gate structure, the erase gate structure covers part of the side walls of the stacked gate structure, and the top of the erase gate structure is higher than the top of the floating gate structure. In the embodiment of the present invention, the top surface of the floating gate structure and the side walls on both sides form an acute angle, which is conducive to flexible selection of the formation position of the erase gate structure, and the top surface of the floating gate structure and the side walls on both sides form an acute angle, that is, the corner from the floating gate structure to the erase gate structure is an acute angle, and the electric field at the acute angle is large, which is conducive to reducing the floating gate structure to the erase gate structure. The energy band barrier of the structure makes it easier for electrons to reach the erase gate structure from the floating gate structure, which is beneficial to improving the writing and erasing efficiency of the semiconductor structure. In addition, the corner pointing from the floating gate structure to the erase gate structure is an acute angle, which is beneficial to reducing the degree to which the corner pointing from the floating gate structure to the erase gate structure becomes rounded due to oxidation in the subsequent process, thereby helping to reduce the impact on the erase efficiency. At the same time, reducing the degree to which the corner pointing from the floating gate structure to the erase gate structure becomes rounded due to oxidation in the subsequent process is also beneficial to improving the coupling capacitance of the floating gate structure, thereby helping to improve the writing efficiency of the semiconductor structure, and further helping to ensure the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;

[0029] Figure 2 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0030] Figures 3 to 11 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0031] At present, the working performance of semiconductor structures is difficult to guarantee. Now, the reasons why the working performance is difficult to guarantee are analyzed in combination with a method for forming a semiconductor structure.

[0032] Figure 1 It is a structural diagram of a semiconductor structure.

[0033] refer to Figure 1 The semiconductor structure includes: a substrate 10, including a storage cell region 10S; a floating gate structure 24, and a control gate structure 22 located on the floating gate structure 24, located on the substrate 10 in the storage cell region 10S, the floating gate structure 24 protrudes outward relative to the sidewall of the control gate structure 22, and in the protruding portion of the floating gate structure 24, the top surface of the floating gate structure 24 is perpendicular to the sidewall structure; an erase gate structure 25, located on the substrate 10 on the side of the floating gate structure 24 protruding outward in the storage cell region 10S, the erase gate structure 25 covers the top surface and sidewall of the floating gate structure 24 exposed by the control gate structure 22.

[0034] The semiconductor structure is a Flash memory, specifically, a split-gate memory. The split-gate memory completes the erase operation through the tunneling effect principle from the floating gate (FG) structure 24 to the erase gate (EG) structure 25. In order to improve the erase efficiency and increase the tunneling area, in the existing process, a right-angle floating gate (FG) tip (such as Figure 1 The dotted circle in the middle shows the shape of the FG tip, which is used to improve the electric field distribution and increase the area of ​​the EG-coupled FG, so that the electrons in the floating gate structure 24 can be easily pulled out. However, in the subsequent thermal process, the FG tip is easily oxidized and becomes rounded, especially after the bipolar-complementary-bipolar-metal oxide semi-field effect transistor (Bipolar-CMOS-DMOS, BCD) device is embedded, the gate oxidation process of the BCD device is added, and the annealing (thermal) process is added during the process, which further aggravates the rounding of the FG tip during the process, thereby reducing the electric field at the FG tip and shortening the width of the floating gate structure 24 extending into the erase gate structure 25, thereby reducing the erase efficiency of the split-gate memory and affecting the performance of the semiconductor structure.

[0035] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate, including a storage cell area; a stacked gate structure, located on the substrate in the storage cell area, the stacked gate structure including a floating gate structure and a control gate structure located on the floating gate structure, the top surface of the floating gate structure and the side walls on both sides form an acute angle; an erase gate structure, located in the storage cell area and on the substrate on one side of the floating gate structure, the erase gate structure covers part of the side walls of the stacked gate structure, and the top of the erase gate structure is higher than the top of the floating gate structure.

[0036] In the embodiment of the present invention, the top surface of the floating gate structure and the side walls on both sides form an acute angle, which is conducive to flexible selection of the formation position of the erase gate structure. Moreover, the top surface of the floating gate structure and the side walls on both sides form an acute angle, that is, the corner where the floating gate structure points to the erase gate structure is an acute angle. The electric field at the acute angle is relatively large, which is conducive to reducing the energy band barrier from the floating gate structure to the erase gate structure, and electrons can more easily reach the erase gate structure from the floating gate structure, which is conducive to improving the writing and erasing efficiency of the semiconductor structure. In addition, the corner where the floating gate structure points to the erase gate structure is an acute angle, which is conducive to reducing the degree to which the corner where the floating gate structure points to the erase gate structure becomes rounded due to oxidation in the subsequent process, thereby helping to reduce the impact on the erase efficiency. At the same time, reducing the degree to which the corner where the floating gate structure points to the erase gate structure becomes rounded due to oxidation in the subsequent process is also conducive to improving the coupling capacitance of the floating gate structure, thereby helping to improve the writing efficiency of the semiconductor structure, and further helping to ensure the performance of the semiconductor structure.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Figure 2 It is a structural schematic diagram of an embodiment of a semiconductor structure of the present invention.

[0039] The semiconductor structure includes: a substrate 100, including a memory cell region 100S; a stacked gate structure 500, located on the substrate 100 in the memory cell region 100S, the stacked gate structure 500 including a floating gate structure 240, and a control gate structure 220 located on the floating gate structure 240, the top surface of the floating gate structure 240 and the side walls on both sides form an acute angle; an erase gate structure 260, located in the memory cell region 100S and on the substrate 100 on one side of the floating gate structure 240, the erase gate structure 260 covers part of the side walls of the stacked gate structure 500, and the top of the erase gate structure 260 is higher than the top of the floating gate structure 240.

[0040] In this embodiment, the semiconductor structure is a Flash memory, specifically, a Nor Flash memory, and the Flash memory is a non-volatile storage device.

[0041] Specifically, in this embodiment, the semiconductor structure is a split-gate memory.

[0042] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0043] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide and indium gallium. The substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0044] The memory cell region 100S is used to form a split-gate memory structure composed of a floating gate structure 240 , a coupling gate (CG) structure 220 , and an erase gate (EG) structure 260 .

[0045] In this embodiment, a word line (WL) region is located between adjacent memory cell regions 100S, and a gate structure for controlling channel electrons is formed in the WL region.

[0046] In this embodiment, an isolation layer 110 is further formed between the substrate 100 and the stacked gate structure 500 , for isolating the stacked gate structure 500 from the substrate 100 , and isolating the erase gate structure 260 from the substrate 100 .

[0047] The stacked gate structure 500 is used to implement signal writing of the memory. Specifically, the floating gate structure 240 is used as a unit structure for storing data in the memory, and the control gate structure 220 is used to electrically connect to the outside to control the longitudinal electric field of the floating gate structure 240 .

[0048] Specifically, a high voltage is applied to the gate structure of the WL region to open the channel, and a high voltage is applied to the control gate structure 220 to create a strong vertical electric field between the floating gate structure 240 and the control gate structure 220. The strong vertical electric field accelerates the channel electrons in the vertical direction, and a portion of the electrons are injected into the floating gate structure 240 through the isolation layer 110, thereby realizing electron injection and signal writing.

[0049] It should be noted that, in this embodiment, the thickness of the floating gate structure 240 should not be too large or too small. If the thickness of the floating gate structure 240 is too large, it is easy to cause the height of the stacked gate structure 500 to be too large, occupy too much space, cause unnecessary waste, and also affect the integration of the semiconductor structure. In addition, in the semiconductor process, it is necessary to perform ion implantation on the floating gate structure 240 with a partial thickness to obtain a doping area that inhibits oxidation, so that when the sidewall of the floating gate structure 240 is oxidized, the oxidation effect of the floating gate structure 240 is gradually enhanced from top to bottom, and a dielectric layer with a thickness increasing from top to bottom is obtained, and a floating gate structure 240 with an inverted trapezoidal morphology is obtained accordingly. Therefore, if the thickness of the floating gate structure 240 is too large, it is easy to cause the area for ion implantation to be too large, and too much material for oxidation is too much, which increases the process cost; if the thickness of the floating gate structure 240 is too small, it is easy to cause the volume of the floating gate structure 240 to be too small, which affects the signal writing of the semiconductor structure, and it is also easy to increase the difficulty of ion implantation, which affects the formation of the semiconductor structure. Therefore, in this embodiment, the thickness of the floating gate structure 240 is to

[0050] The erase gate structure 260 is used to implement signal erasure of the memory.

[0051] Specifically, by applying a high voltage to the erase gate structure 260, a potential difference is formed on the first dielectric layer between the erase gate structure 260 and the floating gate structure 240 due to the coupling capacitance, and the electrons in the floating gate structure 240 can be pulled to the erase gate structure 260 through tunneling. As the electrons in the floating gate structure 240 are pulled out, the potential of the floating gate structure 240 increases, and the difference between its potential and the erase gate structure 260 will decrease, weakening the potential difference between the first dielectric layers, and finally the electrons in the floating gate structure 240 are completely pulled out, realizing the signal erasure of the memory.

[0052] The erase gate structure 260 covers part of the sidewall of the stacked gate structure 500 , and the top of the erase gate structure 260 is higher than the top of the floating gate structure 240 , so that the erase gate structure 260 can cover the acute angle of the floating gate structure 240 .

[0053] In this embodiment, the top surface of the floating gate structure 240 and the side walls on both sides form an acute angle, which is conducive to making the formation position of the erase gate structure 260 flexibly selected. Moreover, the top surface of the floating gate structure 240 and the side walls on both sides form an acute angle, that is, the corner where the floating gate structure 240 points to the erase gate structure 260 is an acute angle. The electric field at the acute angle is large, which is conducive to reducing the energy band barrier from the floating gate structure 240 to the erase gate structure 260. It is easier for electrons to reach the erase gate structure 260 from the floating gate structure 240, which is conducive to improving the writing and erasing efficiency of the semiconductor structure. In addition, the corner where the floating gate structure 240 points to the erase gate structure 260 is an acute angle, which is beneficial to reducing the degree to which the corner where the floating gate structure 240 points to the erase gate structure 260 becomes rounded due to oxidation in the subsequent process, thereby helping to reduce the impact on the erase efficiency. At the same time, reducing the degree to which the corner where the floating gate structure 240 points to the erase gate structure 260 becomes rounded due to oxidation in the subsequent process is also beneficial to improving the coupling capacitance of the floating gate structure 240, thereby helping to improve the write efficiency of the semiconductor structure, and further helping to ensure the performance of the semiconductor structure.

[0054] Specifically, in the present embodiment, the top surface of the floating gate structure 240 and the side walls on both sides form an acute angle, so that the cross-section is an inverted trapezoidal morphology.

[0055] In this embodiment, the memory cell region 100S includes two stacked gate structures 500 , and the acute angles of the floating gate structures 240 of the two stacked gate structures 500 are arranged opposite to each other.

[0056] The memory cell region 100S includes two stacked gate structures 500 , and the floating gate structures 240 of the two stacked gate structures 500 are arranged at acute angles relative to each other, so that in the memory cell region 100S, two floating gate structures 240 are simultaneously used for signal writing, which is beneficial to improving the efficiency of signal writing.

[0057] In this embodiment, two adjacent stacked gate structures 500 share the same erase gate structure 260 .

[0058] Two adjacent stacked gate structures 500 share the same erase gate structure 260 , and two floating gate structures 240 are used simultaneously to perform signal erasure, which is beneficial to improving the efficiency of signal erasure.

[0059] In this embodiment, the material of the floating gate structure 240 includes polysilicon; the material of the control gate structure 220 includes polysilicon; and the material of the erase gate structure 260 includes polysilicon.

[0060] In this embodiment, the semiconductor structure further includes: a dielectric layer 140 located between the floating gate structure 240 and the erase gate structure 260 .

[0061] The dielectric layer 140 is used to isolate the floating gate structure 240 from the erase gate structure 260 .

[0062] In this embodiment, the dielectric layer 140 is obtained by oxidizing the material of the floating gate structure 240 .

[0063] The dielectric layer 140 is obtained by oxidizing the material of the floating gate structure 240, so there is no need to form an additional film layer to obtain the dielectric layer 140. Moreover, the size and morphology of the converted floating gate structure 240 material can be adjusted by oxidizing part of the floating gate structure 240 material into the dielectric layer 140. Accordingly, the morphology of the floating gate structure 240 in which the top surface and the side wall form an acute angle can be obtained through adjustment.

[0064] In the present embodiment, the material of the floating gate structure 240 is polysilicon. Accordingly, in the present embodiment, the material of the dielectric layer 140 includes silicon oxide, so that the isolation effect is better.

[0065] It should be noted that, in this embodiment, the thickness d1 of the dielectric layer 140 located on the side of the top surface of the floating gate structure 240 should not be too large or too small. If the thickness d1 of the dielectric layer 140 located on the side of the top surface of the floating gate structure 240 is too large, it is easy to cause too much floating gate structure 240 to be oxidized on the top, and it is easy to cause the size of the top surface of the floating gate structure 240 to be close to the size of the bottom surface, thereby causing the acute angle formed by the top surface and the side wall of the floating gate structure 240 to be too large, making it difficult to obtain a large electric field at the acute angle, and thus it is difficult to improve the writing and erasing efficiency of the semiconductor structure. In addition, it is difficult to effectively alleviate the degree to which the corner of the floating gate structure 240 pointing to the erase gate structure 260 becomes rounded due to oxidation in the subsequent process, so it is difficult to reduce the impact on the erase efficiency, and thus the performance of the semiconductor structure is affected; if the thickness d1 of the dielectric layer 140 located on the side of the top surface of the floating gate structure 240 is too small, it is easy to affect the isolation effect of the dielectric layer 140 on the floating gate structure 240 and the erase gate structure 260 at the top of the floating gate structure 240, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the thickness d1 of the dielectric layer 140 located on the side of the top surface of the floating gate structure 240 is to

[0066] It should also be noted that, in this embodiment, the thickness d2 of the dielectric layer 140 located on the side of the bottom surface of the floating gate structure 240 should not be too large or too small. If the thickness d2 of the dielectric layer 140 located on the side of the bottom surface of the floating gate structure 240 is too large, it is easy to cause too much material of the floating gate structure 240 to be converted at the bottom of the floating gate structure 240, resulting in too little material of the floating gate structure 240 close to the substrate 100, and it is also easy to cause too little material of the floating gate structure 240 as a whole, thereby affecting the signal writing of the semiconductor structure; if the thickness d2 of the dielectric layer 140 located on the side of the bottom surface of the floating gate structure 240 is too small, it is easy to cause too much floating gate structure 240 to be oxidized at the bottom, and it is easy to cause the top surface size of the floating gate structure 240 to be close to the bottom surface size, thereby affecting the signal writing of the semiconductor structure; This causes the acute angle formed by the top surface and the sidewall of the floating gate structure 240 to be too large, making it difficult to obtain a large electric field at the acute angle, and thus it is difficult to improve the writing and erasing efficiency of the semiconductor structure. Moreover, it is difficult to effectively alleviate the degree to which the corner of the floating gate structure 240 pointing to the erase gate structure 260 becomes rounded due to oxidation during the subsequent process, and thus it is difficult to reduce the impact on the erase efficiency, which in turn affects the performance of the semiconductor structure. It is also easy to affect the isolation effect of the dielectric layer 140 between the floating gate structure 240 and the erase gate structure 260 at the bottom of the floating gate structure 240, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the thickness d2 of the dielectric layer 140 located on the side of the bottom surface of the floating gate structure 240 is to

[0067] In this embodiment, a doping region 200a is formed in the floating gate structure 240 and is located at the top of the floating gate structure 240. The doping region 200a contains inhibitory ions for inhibiting oxidation, and the doping concentration of the inhibitory ions gradually decreases from the top to the bottom of the doping region 200a.

[0068] As can be seen from the foregoing, in the semiconductor process, the floating gate structure 240 is subjected to ion implantation treatment to obtain an oxidation-inhibiting doping region 200a, and the inhibiting ions are used to inhibit the oxidation effect. Therefore, the doping concentration of the inhibiting ions gradually decreases from the top to the bottom of the doping region 200a, so that when the sidewalls of the floating gate structure 240 are subjected to oxidation treatment, the oxidation effect of the floating gate structure 240 is gradually enhanced from top to bottom, and a dielectric layer 140 whose thickness increases from top to bottom is obtained, and accordingly a floating gate structure 240 with an inverted trapezoidal morphology is obtained.

[0069] It should be noted that, in this embodiment, the ratio of the thickness of the doping region 200a to the total thickness of the floating gate structure 240 should not be too small. If the ratio of the thickness of the doping region 200a to the total thickness of the floating gate structure 240 is too small, the thickness of the floating gate structure 240 with ion suppression is too small, and the thickness without ion suppression is too large, resulting in a small difference in doping concentration between the top and bottom surfaces of the doping region 200a, while the doping concentration of the bottom surface of the doping region 200a is similar to that of the bottom surface of the floating gate structure 240, which results in similar oxidation effects on the top and bottom surfaces of the floating gate structure 240 when the sidewall of the floating gate structure 240 is oxidized, making it difficult to obtain a dielectric layer 140 with a thickness increasing from top to bottom, and accordingly, it is difficult to obtain a floating gate structure 240 with an inverted trapezoidal morphology. For this reason, in this embodiment, the ratio of the thickness of the doping region 200a to the total thickness of the floating gate structure 240 is greater than or equal to 1 / 3.

[0070] In this embodiment, the doping ions of the doping region 200 a include nitrogen ions.

[0071] Nitrogen ions can effectively inhibit oxidation. Moreover, doping nitrogen ions in the floating gate structure 240 will hardly affect the function of the floating gate structure 240, which is beneficial to ensuring the performance of the semiconductor structure.

[0072] In this embodiment, the aforementioned dielectric layer 140 is used as the first dielectric layer 140 , and the semiconductor structure further includes: a second dielectric layer 120 located between the floating gate structure 240 and the control gate structure 220 .

[0073] The second dielectric layer 120 is used to isolate the floating gate structure 240 from the control gate structure 220 .

[0074] In this embodiment, the second dielectric layer 120 is an Oxide-Nitride-Oxide (ONO) structure of a silicon oxide layer, a silicon nitride layer on the silicon oxide layer, and a silicon oxide layer on the silicon nitride layer.

[0075] In this embodiment, the semiconductor structure further includes: a spacer 300 covering the sidewall of the control gate structure 220 .

[0076] The spacer 300 is used to protect the sidewalls of the control gate structure 220 and is also used as an etching mask for obtaining the floating gate structure 240 in a semiconductor manufacturing process.

[0077] In this embodiment, the spacer 300 is a silicon oxide layer and a silicon nitride layer covering the silicon oxide layer.

[0078] In this embodiment, the semiconductor structure further includes: a hard mask layer 130 located on the top of the control gate structure 220 .

[0079] The hard mask layer 130 is used as an etching mask for forming the control gate structure 220 .

[0080] In the present embodiment, the hard mask layer 130 is a silicon nitride layer, a silicon oxide layer on the silicon nitride layer, and a silicon nitride layer on the silicon oxide layer. The structure is a nitride-oxide-nitride (NON) structure.

[0081] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure.

[0082] Figures 3 to 11 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0083] refer to Figure 3 , providing a substrate 100 including a memory cell region 100S.

[0084] In this embodiment, the semiconductor structure is a Flash memory, specifically, a Nor Flash memory, and the Flash memory is a non-volatile storage device.

[0085] Specifically, in this embodiment, the semiconductor structure is a split-gate memory.

[0086] The substrate 100 provides a process operation basis for the formation process of the semiconductor structure.

[0087] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide and indium gallium. The substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0088] The memory cell region 100S is used to form a split-gate memory structure consisting of a floating gate structure, a coupling gate (CG) structure, and an erase gate (EG) structure.

[0089] In this embodiment, a word line (WL) region is located between adjacent memory cell regions 100S, and a gate structure for controlling channel electrons is formed in the WL region.

[0090] In the present embodiment, in the step of providing the substrate 100 , the memory cell region 100S includes a preset region for subsequently forming an erase gate structure.

[0091] In this embodiment, an isolation layer 110 is further formed on the substrate 100 to isolate the subsequently formed stacked gate structure from the substrate 100 , and the subsequently formed isolated erase gate structure from the substrate 100 .

[0092] Combined with reference Figures 3 to 9 A stacked gate structure 500 is formed on the substrate 100 of the memory cell region 100S. The stacked gate structure 500 includes a floating gate structure 240 and a control gate structure 220 located on the floating gate structure 240. The top surface of the floating gate structure 240 forms an acute angle with the sidewalls on both sides.

[0093] The stacked gate structure 500 is used to implement signal writing of the memory. Specifically, the floating gate structure 240 is used as a unit structure for storing data in the memory, and the control gate structure 220 is used to electrically connect to the outside to control the longitudinal electric field of the floating gate structure 240 .

[0094] Specifically, a high voltage is applied to the gate structure of the WL region to open the channel, and a high voltage is applied to the control gate structure 220 to create a strong vertical electric field between the floating gate structure 240 and the control gate structure 220. The strong vertical electric field accelerates the channel electrons in the vertical direction, and a portion of the electrons are injected into the floating gate structure 240 through the isolation layer 110, thereby realizing electron injection and signal writing.

[0095] In the present embodiment, the top surface of the floating gate structure 240 and the side walls on both sides form an acute angle, which is conducive to the flexible selection of the formation position of the subsequent erase gate structure. Moreover, the top surface of the floating gate structure 240 and the side walls on both sides form an acute angle, that is, the corner of the floating gate structure 240 pointing to the erase gate structure is an acute angle. The electric field at the acute angle is large, which is conducive to reducing the energy band barrier from the floating gate structure 240 to the erase gate structure, and electrons are more likely to reach the erase gate structure from the floating gate structure 240, which is conducive to improving the writing and erasing efficiency of the semiconductor structure. In addition, the corner of the floating gate structure 240 pointing to the erase gate structure is an acute angle, which is conducive to reducing the degree to which the corner of the floating gate structure 240 pointing to the erase gate structure becomes rounded due to oxidation in the subsequent process, thereby helping to reduce the impact on the erase efficiency. At the same time, reducing the degree to which the corner of the floating gate structure 240 pointing to the erase gate structure 260 becomes rounded due to oxidation in the subsequent process is also conducive to improving the coupling capacitance of the floating gate structure 240, thereby helping to improve the writing efficiency of the semiconductor structure, and further helping to ensure the performance of the semiconductor structure.

[0096] Specifically, in the present embodiment, the top surface of the floating gate structure 240 and the side walls on both sides form an acute angle, so that the cross-section is an inverted trapezoidal morphology.

[0097] It should be noted that, in the step of forming the stacked gate structure 500 in this embodiment, the thickness of the floating gate structure 240 should not be too large or too small. If the thickness of the floating gate structure 240 is too large, it is easy to cause the height of the stacked gate structure 500 to be too large, occupy too much space, cause unnecessary waste, and also affect the integration of the semiconductor structure. Moreover, in the semiconductor process, it is necessary to perform ion implantation treatment on the floating gate structure 240 with a partial thickness to obtain a doped area that inhibits oxidation, so that when the sidewall of the floating gate structure 240 is oxidized, the oxidation effect of the floating gate structure 240 is gradually enhanced from top to bottom, and a dielectric layer with a thickness increasing from top to bottom is obtained, and a floating gate structure 240 with an inverted trapezoidal morphology is obtained accordingly. Therefore, if the thickness of the floating gate structure 240 is too large, it is easy to cause the area for ion implantation treatment to be too large, and too much material is required for oxidation, which increases the process cost; if the thickness of the floating gate structure 240 is too small, it is easy to cause the volume of the floating gate structure 240 to be too small, which affects the signal writing of the semiconductor structure, and it is also easy to increase the difficulty of ion implantation treatment, which affects the formation of the semiconductor structure. For this reason, in the step of forming the stacked gate structure 500 in this embodiment, the thickness of the floating gate structure 240 is to

[0098] In the present embodiment, in the step of forming the stacked gate structure 500 , two stacked gate structures 500 are formed in the memory cell region 100S, and the acute angles of the floating gate structures 240 of the two stacked gate structures 500 are arranged opposite to each other.

[0099] The memory cell region 100S includes two stacked gate structures 500 , and the floating gate structures 240 of the two stacked gate structures 500 are arranged at acute angles relative to each other, so that in the memory cell region 100S, two floating gate structures 240 are simultaneously used for signal writing, which is beneficial to improving the efficiency of signal writing.

[0100] In this embodiment, in the step of forming the stacked gate structure 500 , the material of the floating gate structure 240 includes polysilicon; and the material of the control gate structure 220 includes polysilicon.

[0101] Combined with reference Figures 3 to 5 The step of forming the stacked gate structure 500 includes: forming a first gate material layer 200 covering the substrate 100 , and a second gate material layer 210 located on the first gate material layer 200 .

[0102] The first gate material layer 200 is used to form a floating gate structure 240 , and the second gate material layer 210 is used to form a control gate structure 220 .

[0103] Specifically, in this embodiment, the first gate material layer 200 covers the isolation layer 110 .

[0104] Correspondingly, in this embodiment, the material of the first gate material layer 200 includes polysilicon; the material of the second gate material layer 210 includes polysilicon.

[0105] refer to Figure 3 After forming the first gate material layer 200 and before forming the second gate material layer 210, the formation method also includes: performing ion implantation treatment on the first gate material layer 200 to form a doped region 200a located at the top of the first gate material layer 200, wherein the doped region 200a has inhibitory ions for inhibiting oxidation.

[0106] In the semiconductor manufacturing process, the first gate material layer 200 is subjected to ion implantation treatment to obtain an oxidation inhibiting doping region 200a. The inhibiting ions are used to inhibit oxidation. The ion implantation treatment is performed from the upper surface of the first gate material layer 200, and accordingly, the doping concentration of the inhibiting ions gradually decreases from the top to the bottom of the doping region 200a. In the initial floating gate structure subsequently obtained through the first gate material layer 200, the doping concentration of the inhibiting ions gradually decreases from the top to the bottom of the doping region 200a, so that when the sidewalls of the initial floating gate structure are subjected to oxidation treatment, the oxidation effect of the initial floating gate structure is gradually enhanced from top to bottom, and a dielectric layer with a thickness increasing from top to bottom is obtained, and accordingly, a floating gate structure 240 with an inverted trapezoidal morphology is obtained.

[0107] It should be noted that, in the present embodiment, in the step of performing ion implantation on the first gate material layer 200, the ratio of the thickness of the doping region 200a to the total thickness of the first gate material layer 200 should not be too small. If, in the step of performing ion implantation on the first gate material layer 200, the ratio of the thickness of the doping region 200a to the total thickness of the first gate material layer 200 is too small, the thickness of the initial floating gate structure with ion inhibition is too small, while the thickness without ion inhibition is too large, resulting in a small difference in doping concentration between the top and bottom surfaces of the doping region 200a, while the doping concentration of the bottom surface of the doping region 200a is similar to that of the bottom surface of the initial floating gate structure, which results in similar oxidation effects on the top and bottom surfaces of the initial floating gate structure when the sidewalls of the initial floating gate structure are oxidized, making it difficult to obtain a dielectric layer whose thickness increases from top to bottom, and accordingly, it is difficult to obtain a floating gate structure 240 with an inverted trapezoidal morphology. To this end, in the present embodiment, in the step of performing ion implantation on the first gate material layer 200 , the ratio of the thickness of the doped region 200 a to the total thickness of the first gate material layer 200 is greater than or equal to 1 / 3.

[0108] It should also be noted that, in the step of performing ion implantation on the first gate material layer 200 in this embodiment, the implantation dose of the ion implantation should not be too large or too small. If the injection dose of the ion implantation treatment is too large, it is easy to cause the ion implantation range to be too large, the process technology is difficult to control, and it is easy to cause the doping concentration difference from the top surface to the bottom surface of the doping region 200a to be too small, resulting in that when the side wall of the initial floating gate structure is oxidized, the oxidation effect of the top surface and the bottom surface of the initial floating gate structure is similar, and it is difficult to obtain a dielectric layer whose thickness increases from top to bottom, and correspondingly it is difficult to obtain a floating gate structure 240 with an inverted trapezoidal morphology; if the injection dose of the ion implantation treatment is too small, the reaction time of the ion implantation is too long, the efficiency of the process technology is reduced, and it is also easy to cause the depth of the doping region 200a to be too small, resulting in a small difference in doping concentration between the top surface and the bottom surface of the doping region 200a, while the doping concentration of the bottom surface of the doping region 200a is similar to that of the bottom surface of the initial floating gate structure, correspondingly when the side wall of the initial floating gate structure is oxidized, the oxidation effect of the top surface and the bottom surface of the initial floating gate structure is similar, and it is difficult to obtain a dielectric layer whose thickness increases from top to bottom, and correspondingly it is difficult to obtain a floating gate structure 240 with an inverted trapezoidal morphology. Therefore, in this embodiment, in the step of performing ion implantation on the first gate material layer 200, the implantation dose of the ion implantation is 1E11 atoms / cm 2 To 9E15 atoms / cm 2 .

[0109] It should also be noted that, in the step of performing ion implantation on the first gate material layer 200 in this embodiment, the implantation energy should not be too large or too small. If the implantation energy is too large, it is easy to cause the process to be difficult to control; if the implantation energy is too small, the reaction time of the ion implantation is too long, the efficiency of the process is reduced, and it is also easy to cause the depth of the doping region 200a to be too small, resulting in a small difference in the doping concentration between the top and bottom surfaces of the doping region 200a, while the doping concentration of the bottom surface of the doping region 200a is similar to that of the bottom surface of the initial floating gate structure, which results in that when the sidewall of the initial floating gate structure is oxidized, the oxidation effects of the top and bottom surfaces of the initial floating gate structure are similar, making it difficult to obtain a dielectric layer with a thickness increasing from top to bottom, and accordingly, it is difficult to obtain a floating gate structure 240 with an inverted trapezoidal morphology. For this reason, in the step of performing ion implantation on the first gate material layer 200 in this embodiment, the implantation energy is 2KeV to 30KeV.

[0110] In the present embodiment, in the step of performing ion implantation on the first gate material layer 200 , the implanted ions in the ion implantation include nitrogen ions.

[0111] Nitrogen ions can effectively inhibit oxidation. Moreover, doping nitrogen ions in the floating gate structure 240 will hardly affect the function of the floating gate structure 240, which is beneficial to ensuring the performance of the semiconductor structure.

[0112] refer to Figure 5 , taking the aforementioned dielectric layer as the first dielectric layer, after performing ion implantation on the first gate material layer 200 and before forming the second gate material layer 210 , further comprising: forming a second dielectric layer 120 covering the first gate material layer 200 .

[0113] The second dielectric layer 120 is used to isolate the first gate material layer 200 from the second gate material layer 210 , and correspondingly isolate the floating gate structure 240 from the control gate structure 220 .

[0114] In this embodiment, the second dielectric layer 120 is an Oxide-Nitride-Oxide (ONO) structure of a silicon oxide layer, a silicon nitride layer on the silicon oxide layer, and a silicon oxide layer on the silicon nitride layer.

[0115] In this embodiment, after forming the second gate material layer 210 , the method further includes: forming a hard mask layer 130 covering the second gate material layer 210 .

[0116] The hard mask layer 130 is used as an etching mask for forming the control gate structure 220 .

[0117] In the present embodiment, the hard mask layer 130 is a silicon nitride layer, a silicon oxide layer on the silicon nitride layer, and a silicon nitride layer on the silicon oxide layer. The structure is a nitride-oxide-nitride (NON) structure.

[0118] refer to Figure 6 , patterning the second gate material layer 210 , retaining the remaining second gate material layer 210 protruding from the first gate material layer 200 in the memory cell region 100S as a control gate structure 220 .

[0119] Specifically, in this embodiment, the step of patterning the second gate material layer 210 includes: patterning the hard mask layer 130 so that the remaining hard mask layer 130 is separated on the second gate material layer 210; patterning the second gate material layer 210 using the remaining hard mask layer 130 as a mask to form a control gate structure 220.

[0120] Accordingly, in this embodiment, in the step of patterning the second gate material layer 210 , the second dielectric layer 120 is also patterned, and the second dielectric layer 120 located at the bottom of the control gate structure 220 is retained.

[0121] Combined with reference Figure 7 and Figure 8 , the first gate material layer 200 exposed by the control gate structure 220 is patterned to form an initial floating gate structure 230 .

[0122] The initial floating gate structure 230 is used to form a floating gate structure 240 .

[0123] Accordingly, in this embodiment, a doped region 200 a is formed at the top of the initial floating gate structure 230 .

[0124] In this embodiment, an anisotropic dry etching process is used to pattern the first gate material layer 200 to form an initial floating gate structure 230 .

[0125] The anisotropic dry etching process is more directional, and the etching rate in the longitudinal direction is much greater than the etching rate in the lateral direction, which is conducive to obtaining an initial floating gate structure 230 with higher surface quality and higher dimensional accuracy, so that the sidewall verticality of the initial floating gate structure 230 is better.

[0126] refer to Figure 7 The step of patterning the first gate material layer 200 exposed by the control gate structure 220 to form the initial floating gate structure 230 includes: forming a spacer 300 on the sidewall of the control gate structure 220 .

[0127] The spacer 300 is used to protect the sidewalls of the control gate structure 220 and is also used as an etching mask for obtaining the floating gate structure 240 in a semiconductor manufacturing process.

[0128] In this embodiment, the spacer 300 is a silicon oxide layer and a silicon nitride layer covering the silicon oxide layer.

[0129] refer to Figure 8 , using the sidewall spacer 300 as a mask, the first gate material layer 200 exposed by the sidewall spacer 300 is patterned to form an initial floating gate structure 230 .

[0130] refer to Fig. 9 The initial floating gate structure 230 is subjected to a sidewall tilting process to obtain an initial floating gate structure 230 whose top surface and sidewalls on both sides form an acute angle as a floating gate structure 240 .

[0131] Specifically, in this embodiment, the step of performing sidewall tilting treatment on the initial floating gate structure 230 includes: performing oxidation treatment on the sidewall of the initial floating gate structure 230, converting part of the material on the side of the initial floating gate structure 230 into a dielectric layer 140, and gradually increasing the thickness of the dielectric layer 140 from the top to the bottom of the initial floating gate structure 230 along a direction perpendicular to the sidewall of the floating gate structure 230, and retaining the remaining initial floating gate structure 230 as a floating gate structure 240.

[0132] The dielectric layer 140 is used to isolate the floating gate structure 240 from the erase gate structure 260 .

[0133] The sidewalls of the initial floating gate structure 230 are oxidized to convert part of the material on the side of the initial floating gate structure 230 into the dielectric layer 140. The dielectric layer 140 can be obtained without forming an additional film layer. Moreover, the size and morphology of the converted material of the initial floating gate structure 230 can be adjusted by oxidizing part of the material of the initial floating gate structure 230 into the dielectric layer 140. Accordingly, the morphology of the floating gate structure 240 in which the top surface and the sidewall form an acute angle can be obtained through adjustment.

[0134] Specifically, in this embodiment, the doping concentration of the suppression ions gradually decreases from the top to the bottom of the doping region 200a, so that when the side wall of the initial floating gate structure 230 is oxidized, the oxidation effect of the initial floating gate structure 230 is gradually enhanced from top to bottom, and the dielectric layer 140 with increasing thickness from top to bottom is obtained, and accordingly a floating gate structure 240 with an inverted trapezoidal morphology is obtained.

[0135] In this embodiment, the material of the initial floating gate structure 230 is polysilicon. Accordingly, in this embodiment, the material of the dielectric layer 140 includes silicon oxide, so that the isolation effect is better.

[0136] It should be noted that, in this embodiment, the thickness d1 of the dielectric layer 140 located on the side of the top surface of the floating gate structure 240 should not be too large or too small. If the thickness d1 of the dielectric layer 140 located on the side of the top surface of the floating gate structure 240 is too large, it is easy to cause too many floating gate structures 240 to be oxidized on the top, and it is easy to cause the size of the top surface of the floating gate structure 240 to be close to the size of the bottom surface, thereby causing the acute angle formed by the top surface and the sidewall of the floating gate structure 240 to be too large, making it difficult to obtain a large electric field at the acute angle, thereby making it difficult to improve the writing and erasing efficiency of the semiconductor structure, and it is difficult to effectively alleviate the degree to which the corner of the floating gate structure 240 pointing to the erase gate structure becomes rounded due to oxidation in the subsequent process, thereby making it difficult to reduce the impact on the erase efficiency, thereby affecting the performance of the semiconductor structure; if the thickness d1 of the dielectric layer 140 located on the side of the top surface of the floating gate structure 240 is too small, it is easy to affect the isolation effect of the dielectric layer 140 on the floating gate structure 240 and the erase gate structure at the top of the floating gate structure 240, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the thickness d1 of the dielectric layer 140 located on the top side of the floating gate structure 240 is to

[0137] It should also be noted that, in this embodiment, the thickness d2 of the dielectric layer 140 located on the side of the bottom surface of the floating gate structure 240 should not be too large or too small. If the thickness d2 of the dielectric layer 140 located on the side of the bottom surface of the floating gate structure 240 is too large, it is easy to cause too much material of the floating gate structure 240 to be converted at the bottom of the floating gate structure 240, resulting in too little material of the floating gate structure 240 close to the substrate 100, and it is also easy to cause too little material of the floating gate structure 240 as a whole, thereby affecting the signal writing of the semiconductor structure; if the thickness d2 of the dielectric layer 140 located on the side of the bottom surface of the floating gate structure 240 is too small, it is easy to cause too much floating gate structure 240 to be oxidized at the bottom, and it is easy to cause the top surface size of the floating gate structure 240 to be close to the bottom surface size. The top surface of the floating gate structure 240 and the side wall of the floating gate structure 240 are too close, resulting in an acute angle between the top surface and the side wall of the floating gate structure 240 being too large, making it difficult to obtain a large electric field at the acute angle, and thus making it difficult to improve the writing and erasing efficiency of the semiconductor structure. Moreover, it is difficult to effectively alleviate the degree to which the corner of the floating gate structure 240 pointing to the erase gate structure becomes rounded due to oxidation in the subsequent process, and thus it is difficult to reduce the impact on the erase efficiency, and thus affecting the performance of the semiconductor structure. It is also easy to affect the isolation effect of the dielectric layer 140 between the floating gate structure 240 and the erase gate structure at the bottom of the floating gate structure 240, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the thickness d2 of the dielectric layer 140 located at the side of the bottom surface of the floating gate structure 240 is to

[0138] In the present embodiment, in the step of performing oxidation treatment on the sidewalls of the initial floating gate structure 230, the gas used for the oxidation treatment includes oxygen or a mixed gas of nitrogen and oxygen.

[0139] Oxidation treatment using oxygen or a mixture of nitrogen and oxygen can oxidize the sidewall material of the initial floating gate structure 230. Moreover, the introduced gas has little effect on the floating gate structure 240, which is beneficial to ensuring the performance of the semiconductor structure.

[0140] It should be noted that, in the step of oxidizing the sidewalls of the initial floating gate structure 230 in this embodiment, the process temperature of the oxidation treatment should not be too high or too low. If the process temperature of the oxidation treatment is too high, it is easy to cause the semiconductor structure to be damaged by high temperature; if the process temperature of the oxidation treatment is too low, it is easy to affect the oxidation effect of oxidizing the sidewall material of the initial floating gate structure 230, affect the function of the dielectric layer 140, and affect the acquisition of the sharp-angle morphology of the floating gate structure 240. For this reason, in the step of oxidizing the sidewalls of the initial floating gate structure 230 in this embodiment, the process temperature of the oxidation treatment is 600°C to 1200°C.

[0141] It should also be noted that, in the step of performing oxidation treatment on the sidewall of the initial floating gate structure 230 in this embodiment, the process time of the oxidation treatment should not be too long or too short. If the process time of the oxidation treatment is too long, the process at high temperature for a long time is likely to cause damage to the semiconductor structure; if the process time of the oxidation treatment is too short, it is easy to affect the oxidation effect of oxidizing the sidewall material of the initial floating gate structure 230, affect the function of the dielectric layer 140, and affect the acquisition of the sharp-angle morphology of the floating gate structure 240. For this reason, in the step of performing oxidation treatment on the sidewall of the initial floating gate structure 230 in this embodiment, the process time of the oxidation treatment is 10 seconds to 120 minutes.

[0142] Combined with reference Fig.10 and Fig.11 In the memory cell region 100S, an erase gate structure 260 is formed on the substrate 100 on one side of the floating gate structure 240 , the erase gate structure 260 covers a portion of the sidewall of the stacked gate structure 500 , and the top of the erase gate structure 260 is higher than the top of the floating gate structure 240 .

[0143] The erase gate structure 260 is used to implement signal erasure of the memory.

[0144] Specifically, by applying a high voltage to the erase gate structure 260, a potential difference is formed on the first dielectric layer between the erase gate structure 260 and the floating gate structure 240 due to the coupling capacitance, and the electrons in the floating gate structure 240 can be pulled to the erase gate structure 260 through tunneling. As the electrons in the floating gate structure 240 are pulled out, the potential of the floating gate structure 240 increases, and the difference between its potential and the erase gate structure 260 will decrease, weakening the potential difference between the first dielectric layers, and finally the electrons in the floating gate structure 240 are completely pulled out, realizing the signal erasure of the memory.

[0145] The erase gate structure 260 covers part of the sidewall of the stacked gate structure 500 , and the top of the erase gate structure 260 is higher than the top of the floating gate structure 240 , so that the erase gate structure 260 can cover the acute angle of the floating gate structure 240 .

[0146] In this embodiment, in the step of forming the erase gate structure 260 , two adjacent stacked gate structures 500 share the same erase gate structure 260 .

[0147] Two adjacent stacked gate structures 500 share the same erase gate structure 260 , and two floating gate structures 240 are used simultaneously to perform signal erasure, which is beneficial to improving the efficiency of signal erasure.

[0148] In this embodiment, the material of the erase gate structure 260 includes polysilicon.

[0149] In this embodiment, in the step of forming the erase gate structure 260 , a gate structure for controlling channel electrons is formed in the WL region between adjacent memory cell regions 100S.

[0150] Specifically, refer to Fig.10 In the memory cell region 100S, the step of forming the erase gate structure 260 on the substrate 100 on one side of the floating gate structure 240 includes: forming a third gate material layer 250 covering the substrate 100 and the stacked gate structure 500 .

[0151] The third gate material layer 250 is used to form an erase gate structure 260 .

[0152] refer to Fig.11 The third gate material layer 250 is planarized and etched back, and the third gate material layer 250 whose top is higher than the floating gate structure 240 and located in the memory cell area 100S is retained as the erase gate structure 260.

[0153] Accordingly, in this embodiment, during the steps of planarizing and etching back the third gate material layer 250, the third gate material layer 250 whose top is higher than the floating gate structure 240 and located between adjacent memory cell regions 100S is retained as the gate structure of the WL region.

[0154] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: a substrate including a storage unit region; A stacked gate structure, located on the substrate of the memory cell region, the stacked gate structure comprising a floating gate structure and a control gate structure located on the floating gate structure, wherein a top surface of the floating gate structure and sidewalls on both sides form an acute angle; An erase gate structure is located in the memory cell area and on the substrate on one side of the floating gate structure. The erase gate structure covers part of the sidewall of the stacked gate structure, and the top of the erase gate structure is higher than the top of the floating gate structure.

2. The semiconductor structure according to claim 1, wherein: The memory cell region includes two stacked gate structures, and the floating gate structures of the two stacked gate structures are arranged at acute angles relative to each other; Two adjacent stacked gate structures share the same erase gate structure.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The semiconductor structure further includes: a dielectric layer located between the floating gate structure and the erase gate structure.

4. The semiconductor structure according to claim 3, characterized in that The thickness of the dielectric layer located on the side of the top surface of the floating gate structure is to The thickness of the dielectric layer located on the bottom side of the floating gate structure is to 5. The semiconductor structure according to claim 3, wherein: The material of the dielectric layer includes silicon oxide.

6. The semiconductor structure according to claim 3, characterized in that A doping region located at the top of the floating gate structure is formed in the floating gate structure, wherein the doping region contains inhibitory ions for inhibiting oxidation, and the doping concentration of the inhibitory ions gradually decreases from the top to the bottom of the doping region; The dielectric layer is obtained by oxidizing the material of the floating gate structure.

7. The semiconductor structure according to claim 6, wherein: The ratio of the thickness of the doped region to the total thickness of the floating gate structure is greater than or equal to 1 / 3.

8. The semiconductor structure according to claim 6, wherein: The doping ions in the doping region include nitrogen ions.

9. The semiconductor structure according to claim 1, wherein: The thickness of the floating gate structure is to 10. The semiconductor structure according to claim 1, wherein: The material of the floating gate structure includes polysilicon; the material of the control gate structure includes polysilicon; and the material of the erase gate structure includes polysilicon.

11. A method for forming a semiconductor structure, characterized in that: include: providing a substrate including a memory cell region; forming a stacked gate structure on the substrate of the memory cell region, wherein the stacked gate structure comprises a floating gate structure and a control gate structure located on the floating gate structure, wherein a top surface of the floating gate structure and sidewalls on both sides form an acute angle; In the memory cell area, an erase gate structure is formed on the substrate at one side of the floating gate structure, the erase gate structure covers part of the sidewall of the stacked gate structure, and the top of the erase gate structure is higher than the top of the floating gate structure.

12. The method for forming a semiconductor structure according to claim 11, wherein: In the step of forming the stacked gate structure, two stacked gate structures are formed in the memory cell region, and the acute angles of the floating gate structures of the two stacked gate structures are arranged opposite to each other; In the step of forming the erase gate structure, two adjacent stacked gate structures share the same erase gate structure.

13. The method for forming a semiconductor structure according to claim 11 or 12, characterized in that: The step of forming the stacked gate structure includes: forming a first gate material layer covering the substrate, and a second gate material layer located on the first gate material layer; Patterning the second gate material layer, and retaining the remaining second gate material layer protruding from the first gate material layer in the memory cell area as the control gate structure; Patterning the first gate material layer exposed by the control gate structure to form an initial floating gate structure; The initial floating gate structure is subjected to a sidewall tilting process to obtain an initial floating gate structure in which a top surface and sidewalls on both sides form an acute angle as the floating gate structure.

14. The method for forming a semiconductor structure according to claim 13, wherein: The step of patterning the first gate material layer exposed by the control gate structure to form the initial floating gate structure includes: forming a sidewall spacer on the sidewall of the control gate structure; The sidewall spacer is used as a mask to perform a patterning process on the first gate material layer exposed by the sidewall spacer to form the initial floating gate structure.

15. The method for forming a semiconductor structure according to claim 13, wherein: After forming the first gate material layer and before forming the second gate material layer, the forming method further comprises: performing ion implantation on the first gate material layer to form a doped region located at a top position of the first gate material layer, wherein the doped region has inhibiting ions for inhibiting oxidation; The step of performing a sidewall tilting treatment on the initial floating gate structure includes: performing an oxidation treatment on the sidewall of the initial floating gate structure, converting part of the material on the side of the initial floating gate structure into a dielectric layer, and gradually increasing the thickness of the dielectric layer from the top to the bottom of the initial floating gate structure along a direction perpendicular to the sidewall of the floating gate structure, and retaining the remaining initial floating gate structure as the floating gate structure.

16. The method for forming a semiconductor structure according to claim 15, wherein: In the step of performing ion implantation on the first gate material layer, the ratio of the thickness of the doped region to the total thickness of the first gate material layer is greater than or equal to 1 / 3.

17. The method for forming a semiconductor structure according to claim 15, wherein: In the step of performing ion implantation on the first gate material layer, the implanted ions include nitrogen ions.

18. The method for forming a semiconductor structure according to claim 15, wherein: In the step of performing ion implantation on the first gate material layer, the implantation dose of the ion implantation is 1E11atoms / cm 2 To 9E15atoms / cm 2 , the implantation energy is 2KeV to 30KeV.

19. The method for forming a semiconductor structure according to claim 15, wherein: In the step of performing oxidation treatment on the sidewalls of the initial floating gate structure, the gas used for the oxidation treatment includes oxygen or a mixed gas of nitrogen and oxygen.

20. The method for forming a semiconductor structure according to claim 15, wherein: In the step of performing oxidation treatment on the sidewall of the initial floating gate structure, the process temperature of the oxidation treatment is 600° C. to 1200° C., and the process time is 10 seconds to 120 minutes.

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