Semiconductor device, memory system, and method of manufacturing semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a memory system. The semiconductor device comprises a storage column which comprises a storage function layer and an inner electrode which are sequentially arranged from outside to inside; the channel structure is located at the end of the storage column and comprises a gate dielectric layer and a channel layer which are sequentially arranged from outside to inside, and the channel layer is connected with the inner electrode; the channel structure further comprises a first electrode, and the first electrode is located at the end, away from the storage column, of the channel structure and connected with the channel layer. The material of the channel layer comprises a metal oxide semiconductor, and the material of the first electrode and the material of the part, close to the channel layer, of the inner electrode both comprise metal.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a memory system, and a method for manufacturing a semiconductor device. Background Art

[0002] The new memory is widely used in portable medical devices, wearable devices, IoT sensors, industrial and automotive applications due to its advantages such as high-speed interface, ultra-low power operation, instant non-volatile storage and unlimited read and write cycle endurance.

[0003] In the new memory, each memory cell may include a transistor and a capacitor. Currently, how to further optimize the performance of the transistor in the memory cell is one of the problems to be solved urgently. Summary of the invention

[0004] The present application provides a semiconductor device, a memory system, and a method for manufacturing a semiconductor device that can at least partially solve the above-mentioned problems existing in the related art or other problems in the art.

[0005] In a first aspect, some embodiments of the present application provide a semiconductor device. The semiconductor device includes: a storage column, including a storage function layer and an inner electrode arranged in sequence from the outside to the inside; and a channel structure, located at the end of the storage column, and including a gate dielectric layer and a channel layer arranged in sequence from the outside to the inside, and the channel layer is connected to the inner electrode; wherein the channel structure also includes a first electrode, the first electrode is located at the end of the channel structure away from the storage column, and is connected to the channel layer; the material of the channel layer includes a metal oxide semiconductor, and the material of the first electrode and the material of the part of the inner electrode close to the channel layer both include metal.

[0006] In some embodiments, the semiconductor device further includes a first transition layer located between the channel layer and the first electrode.

[0007] In some embodiments, the material of the first transition layer includes a metal oxide semiconductor or a metal oxide conductor.

[0008] In some embodiments, the semiconductor device further includes a second transition layer located between the channel layer and the internal electrode.

[0009] In some embodiments, the material of the second transition layer includes a metal oxide semiconductor or a metal oxide conductor.

[0010] In some embodiments, the inner electrode includes a metal pillar connected to the channel layer.

[0011] In some embodiments, the inner electrode further includes a metal nitride layer, and the metal nitride layer is located between the metal pillar and the storage function layer.

[0012] In some embodiments, the inner electrode includes a conductive layer and a metal plug, the conductive layer is located on the inner side wall of the storage functional layer, the metal plug is located inside the conductive layer and close to the channel layer, and is connected to the channel layer.

[0013] In some embodiments, the storage pillar further includes an insulating pillar located in a space surrounded by the conductive layer and the metal plug.

[0014] In some embodiments, the material of the conductive layer includes metal nitride.

[0015] In some embodiments, a semiconductor device has a storage area and a connection area, and the semiconductor device also includes: a first stacking structure, located in the storage area and the connection area, and including a first dielectric layer and a plate line layer alternately arranged, and the storage column passes through the first stacking structure in the storage area; a second stacking structure, located on one side of the first stacking structure in the storage area, and including a gate layer and a second dielectric layer located on opposite sides of the gate layer, and a channel structure passes through the second stacking structure; a bit line contact, located on a side of the second stacking structure away from the first stacking structure and connected to the first electrode; a gate contact, located on a side of the second stacking structure away from the first stacking structure and extending to the gate layer; and multiple contact structures, extending to different layers of plate line layers along the stacking direction of the first stacking structure in the connection area; wherein the material of at least one of the plate line layer, the gate layer, the bit line contact, the gate contact and the multiple contact structures includes a metal oxide semiconductor or a metal oxide conductor.

[0016] In some embodiments, the materials of the plate line layer, the gate layer, the bit line contact, the gate contact, and the plurality of contact structures all include indium tin oxide.

[0017] In some embodiments, the material of the channel layer includes indium gallium zinc oxide.

[0018] In some embodiments, the material of the storage function layer includes a ferroelectric material. In a second aspect, some embodiments of the present application provide a memory system. The memory system includes: a memory device, including a semiconductor device as mentioned in any embodiment above; and a controller coupled to the memory device, for controlling the memory device to store data.

[0019] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes: forming a first stacking structure, and forming a storage column passing through the first stacking structure, the storage column including a storage function layer and an inner electrode arranged sequentially from the outside to the inside; and forming a second stacking structure on one side of the first stacking structure, and forming an initial channel structure passing through the second stacking structure to the storage column, the initial channel structure including a gate dielectric layer and a channel layer arranged sequentially from the outside to the inside, and the channel layer is connected to the inner electrode; and forming a first electrode at the end of the initial channel structure away from the storage column to form a channel structure; wherein the material of the channel layer includes a metal oxide semiconductor, and the material of the first electrode and the material of the part of the inner electrode close to the channel layer both include metal.

[0020] In some embodiments, before forming a first electrode at an end of the initial channel structure away from the storage pillar to form the channel structure, the method further includes: forming a first transition layer at an end of the initial channel structure away from the storage pillar.

[0021] In some embodiments, before forming a second stack structure on one side of the first stack structure and forming an initial channel structure penetrating the second stack structure to the storage column, the method further includes: forming a second transition layer at an end of the inner electrode.

[0022] In some embodiments, forming a storage column passing through the first stack structure includes: forming a storage hole passing through the first stack structure; forming a storage function layer on an inner wall of the storage hole; and forming a metal column inside the storage function layer to form an inner electrode.

[0023] In some embodiments, forming a metal pillar inside the storage function layer to form an inner electrode includes: forming a metal nitride layer on an inner wall of the storage function layer; and forming a metal pillar inside the metal nitride layer.

[0024] In some embodiments, forming a storage column passing through the first stacking structure includes: forming a storage hole passing through the first stacking structure; forming a storage function layer on the inner wall of the storage hole; forming a conductive layer on the inner wall of the storage function layer; forming an insulating column at the bottom of the inner side of the conductive layer; and forming a metal plug at the top of the inner side of the conductive layer to form an internal electrode.

[0025] According to at least one embodiment of the present application, the semiconductor device, memory system and method for manufacturing a semiconductor device provided by the present application can reduce the equivalent resistance of the transistor while reducing the thermal budget of the transistor, thereby improving the electrical performance of the transistor by forming a channel layer made of a material such as a metal oxide semiconductor, and forming a first electrode made of a material such as a metal and a portion of the inner electrode close to the channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0027] Figure 1A is a block diagram of a system having a memory system provided by an embodiment of the present application;

[0028] Figure 1B and Figure 1C is a schematic diagram of a memory system provided by an embodiment of the present application;

[0029] Figure 2 is a circuit diagram of a storage unit provided in an embodiment of the present application;

[0030] Figure 3 is a schematic diagram of a top view of a semiconductor device provided in an embodiment of the present application;

[0031] Figure 4 The embodiment of the present application provides Figure 3 A schematic cross-sectional structure diagram taken along line AA' is shown;

[0032] Figure 5 is a schematic diagram of a cross-sectional structure of a semiconductor device provided by an embodiment of the present application taken within a connection region;

[0033] Figure 6 is a schematic cross-sectional structural diagram of a semiconductor device provided in another embodiment of the present application;

[0034] Figure 7 is a schematic cross-sectional structural diagram of a semiconductor device provided in yet another embodiment of the present application;

[0035] Figure 8 is a schematic cross-sectional structural diagram of a semiconductor device provided in yet another embodiment of the present application;

[0036] Fig. 9 is a schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0037] FIG. 10A to FIG. 10E is a schematic diagram of a cross-sectional structure of a semiconductor device provided in an embodiment of the present application during a manufacturing process; and

[0038] FIG. 11A to FIG. 11C It is a schematic diagram of the cross-sectional structure of a semiconductor device during the manufacturing process provided by another embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first stacking structure discussed in this application may also be referred to as the second stacking structure, and vice versa.

[0041] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0042] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0043] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0044] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0045] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0046] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0047] 1 is a block diagram of a system having a memory system according to an embodiment of the present application. For example, the memory system 12 may be a ferroelectric random access memory (FeRAM).

[0048] like Figure 1A As shown, the system 11 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device has the memory system 12 located therein). Figure 1A As shown, the system 11 may include a host 18 and a memory system 12. The memory system 12 has one or more memory devices 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the memory device 14.

[0049] In some embodiments, the controller 16 is coupled to the memory device 14 and the host 18, and is configured to control the memory device 14. For example, the controller 16 may be configured to control the memory device 14 such as read, erase, and program operations. The controller 16 may also manage data stored in the memory device 14 and communicate with the host 18. For example, the controller 16 may communicate with an external device (e.g., the host 18) according to a specific communication protocol.

[0050] In some embodiments, the controller 16 and one or more memory devices 14 may be integrated into various types of memory systems. Figure 1B In one example shown in FIG. 1 , the controller 16 and the single memory device 14 may be integrated into a memory card 22. The memory card 22 may further include a memory card connector 24 that couples the memory card 22 to a host (e.g., the host 18 in FIG. A). Figure 1C In another example shown in FIG. 1 , the controller 16 and the plurality of memory devices 14 may be integrated into an SSD 26. The SSD 26 may further include a processor that interfaces the SSD 26 with a host (e.g., Figure 1A An SSD connector 28 coupled to the host 18).

[0051] Figure 2 is a circuit diagram of a storage unit provided in an embodiment of the present application. Figure 2 As shown, the storage unit 111 includes a transistor T. For example, the transistor T may include a metal-oxide-semiconductor field-effect transistor (MOSFET). In some embodiments, the transistor T may be an NMOS (N-channel metal-oxide-semiconductor transistor) or a PMOS (P-channel metal-oxide-semiconductor transistor). The storage unit 111 also includes at least two capacitors. For example, the capacitor C may include a ferroelectric capacitor. Figure 2 It is exemplarily shown that the storage unit 111 includes three capacitors C. Of course, it may also include two capacitors C, or more capacitors C.

[0052] In the memory cell 111, the first electrode of the transistor T is electrically connected to the bit line BL, the control terminal of the transistor T is electrically connected to the word line WL, the first terminals of the plurality of capacitors C are electrically connected to the second electrode of the transistor T, and the second terminal of each capacitor C is electrically connected to the plate line PL. In the present application, one of the drain or source of the transistor T is referred to as the first electrode, the corresponding other electrode is referred to as the second electrode, and the control terminal of the transistor T is the gate.

[0053] In this embodiment, a storage unit 111 includes a plurality of capacitors C electrically connected to a transistor T, so that a storage unit 111 can be used to store multiple bits of data to increase the storage capacity of each storage unit. From another perspective, a plurality of capacitors C share a transistor T, which can reduce the number of transistors T in each storage unit 111 to increase storage density.

[0054] for Figure 2For a storage unit 111 shown, when the capacitor C is a ferroelectric capacitor, in the writing stage, the word line WL is used to receive the word line control signal, so that the transistor T is turned on, the bit line BL is used to receive the bit line control signal, and the plate line PL electrically connected to the selected capacitor C is used to receive the plate line control signal. The voltage difference between the bit line control signal and the plate line control signal causes the ferroelectric layer of the selected capacitor C to be positively polarized or negatively polarized, so as to write different logical information in the selected capacitor C. For example, when the ferroelectric layer is positively polarized, the logical signal "0" is written. For another example, when the ferroelectric layer is negatively polarized, the logical signal "1" is written.

[0055] The reading stage includes a first reading stage, a second reading stage and a third reading stage. In the first reading stage, the word line WL is used to receive a word line control signal to turn on the transistor T, and the bit line BL is used to receive a bit line control signal to precharge the voltage of the first end of the selected capacitor C; in the second reading stage, the word line WL is used to receive another word line control signal to turn off the transistor T, and the plate line PL electrically connected to the selected capacitor C is used to receive the plate line control signal. The voltage difference between the plate line control signal and the first end may keep the polarization direction of the ferroelectric layer of the selected capacitor C unchanged, or may cause the polarization direction of the ferroelectric layer of the selected capacitor C to flip, so as to release the polarization charge and change the voltage on the bit line BL; in the third reading stage, the word line WL is used to receive a word line electrical control signal to turn on the transistor T, detect the voltage or current on the bit line BL, determine whether the polarization direction of the selected capacitor C is flipped, and then read the logic information stored therein.

[0056] Will Figure 2 The memory cells 111 shown are arranged in an array to obtain a memory cell array. The circuit structure of each memory cell 111 is the same. Those skilled in the art can design the arrangement of the memory cells 111 and the number of the memory cells 111 in the memory cell array according to the storage capacity requirements of the memory system.

[0057] Figure 3 It is a schematic diagram of the top view structure of the semiconductor device provided in an embodiment of the present application. Figure 4 The embodiment of the present application provides Figure 3 The cross-sectional structure schematic diagram taken along line AA' is shown. Figure 5 1 is a schematic diagram of a cross-sectional structure of a semiconductor device provided by an embodiment of the present application taken in a connection region. For example, the semiconductor device may be a part of a memory device in the above-mentioned memory system.

[0058] It should be noted that, in the following, the x-direction, y-direction, and z-direction in each figure illustrate the spatial relationship of the components in the semiconductor device. For example, the z-direction is the stacking direction of the first stacking structure, and the x-direction and the y-direction are two directions perpendicular to each other on a plane perpendicular to the stacking direction. The same concept will be used throughout this application to describe the spatial relationship of the components in the semiconductor device.

[0059] like Figure 4 As shown, the semiconductor device 200 includes a storage column 231. The storage column 231 may have an outer contour that is roughly cylindrical. The storage column 231 includes a storage function layer 232 and an inner electrode 233 that are arranged in sequence from the outside to the inside. The storage function layer 232 may be roughly a tubular structure with one end closed, and the inner electrode 233 may be roughly a columnar structure and embedded in the inner side of the storage function layer 232. In this embodiment, the inner electrode 233 may include a metal column 235 and a metal nitride layer 234. The metal nitride layer 234 may be roughly a tubular structure with one end closed, and embedded in the inner wall of the storage function layer 232. Among them, the closed ends of the metal nitride layer 234 and the storage function layer 232 face the same direction. The metal column 235 may be roughly a solid or hollow columnar structure and occupy the entire inner space of the metal nitride layer 234. Exemplarily, the material of the metal nitride layer 234 may include titanium nitride (TiN) and / or tantalum nitride (TaN). The material of the metal pillar 235 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti) or any other appropriate metal material. The metal pillar 235 can improve the overall conductivity of the inner electrode 233, and the metal nitride layer 234 can improve the bonding performance between the metal pillar 235 and the storage function layer 232. It should be noted that the metal nitride layer 234 can be omitted, that is, the metal pillar 235 is embedded in the inner wall of the storage function layer 232 and occupies the entire inner space of the storage function layer 232, and the present application does not limit this.

[0060] In some embodiments, the material of the storage functional layer 232 may include ferroelectric materials. When an electric field is applied to the ferroelectric layer, the central atoms stop at a low energy state along the electric field. Conversely, when the electric field is reversed and applied to the ferroelectric layer, the central atoms move in the crystal along the direction of the electric field and stop at another low energy state. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, which form polarized charges under the action of the electric field. The polarized charge formed by the reversal of the ferroelectric domain under the electric field is higher, and the polarized charge formed by the non-reversal of the ferroelectric domain under the electric field is lower. The binary stable state of this ferroelectric material allows it to be used as a storage functional layer to store logical information. Exemplarily, the ferroelectric material may include zirconium oxide (ZrO2), hafnium oxide (HfO2), aluminum (Al) doped HfO2, silicon (Si) doped HfO2, zirconium (Zr) doped HfO2, lanthanum (La) doped HfO2, yttrium (Y) doped HfO2, and one or more of other elements doped based on the ferroelectric material.

[0061] In some embodiments, the semiconductor device 200 may further include a first stacked structure 221. The first stacked structure 221 may include first dielectric layers 222 and board line layers 223 that are alternately stacked. For example, the first dielectric layer 222 may be silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. In some examples, the material of the plate line layer 223 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si) or any other suitable conductive material. In other examples, the material of the plate line layer 223 may be a metal oxide conductor or a metal oxide semiconductor, for example, indium (In), gallium (Ga), zinc (Zn) oxide and any combination thereof (for example, indium gallium zinc oxide IGZO) or indium (In) and tin (Sn) oxide with a predetermined doping ratio (for example, indium tin oxide ITO). In the first stacked structure 221, the thickness of each of the multiple first dielectric layers 222 may be the same or different, and the thickness of each of the multiple plate line layers 223 may be the same or different. The thickness of the first dielectric layer 222 and the plate line layer 223 can be selected according to actual needs. In addition, Figure 4 It is exemplarily shown that the first stacking structure 221 includes two board line layers 223. In an optional embodiment, the first stacking structure 221 may also include three board line layers 223, or more board line layers 223, and the present application does not impose any specific limitation on this.

[0062] In some embodiments, Figure 4As shown, the first stacked structure 221 is located on one side of the substrate 211. For example, the substrate 211 can be used to support the first stacked structure 221. Exemplarily, the substrate 211 can be a semiconductor substrate. For example, the material of the substrate 211 can be silicon (Si), germanium (Ge), gallium arsenide (GaAs) or indium phosphide (InP). Exemplarily, the substrate 211 can be a silicon on insulator (SOI) or germanium on insulator (GeOI) substrate, etc.

[0063] In some embodiments, the storage pillar 231 passes through the first stacked structure 221 along the z direction. For example, the storage pillar 231 may extend from the surface of the first stacked structure 221 away from the substrate 211 toward the substrate 211 and stay in the first dielectric layer 222 closest to the substrate 211.

[0064] It should be noted that, in the semiconductor device 200, the portion of the storage function layer 232 and the inner electrode 233 respectively surrounded by a plate line layer 223, and the portion of the plate line layer 223 in contact with the storage function layer 232 constitute a capacitor C. For example, a ferroelectric capacitor C. Among them, the portion of the inner electrode 233 surrounded by the plate line layer 223 serves as the first end of the capacitor C, the portion of the plate line layer 223 in contact with the storage function layer 232 serves as the second end of the capacitor, and the other portion of the plate line layer 223 serves as the plate line PL. In this way, multiple capacitors C are arranged along the z direction, and the first ends of multiple capacitors C share the inner electrode 233 to achieve electrical connection with each other.

[0065] like Figure 4 As shown, the semiconductor device 200 also includes a channel structure 241. The channel structure 241 is located at the end of the storage column 231, and includes a gate dielectric layer 242 and a channel layer 243 arranged in sequence from the outside to the inside. Among them, the channel layer 243 is connected to the inner electrode 233 (for example, directly in contact). When the power is turned on, the electrical connection between the channel layer 243 and the inner electrode 233 is achieved. The channel structure 241 may have an outer contour that is roughly cylindrical. The gate dielectric layer 242 may be roughly a tubular structure with two ends open, the channel layer 243 is located on the inner side of the gate dielectric layer 242, and the end surface of the channel layer 243 away from the storage column 231 has a recess relative to the end surface of the gate dielectric layer 242 away from the storage column 231. In other words, the gate dielectric layer 242 surrounds the outer side wall of the channel layer 243 and protrudes from the end surface of the channel layer 243 away from the storage column 231. In some examples, the channel layer 243 may be a substantially tubular structure with both ends open, and an insulating column (not shown) is located inside the channel layer 243. In other examples, the channel layer 243 may be a substantially solid or hollow columnar structure, and the present application does not limit the specific structure of the channel layer 243. For example, the material of the gate dielectric layer 242 may be silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y) or any other suitable insulating material or materials.

[0066] In the channel layer 243, its material may include a metal oxide semiconductor. For example, the metal oxide semiconductor material may be indium (In), gallium (Ga), zinc (Zn) oxide, and any combination thereof (for example, indium gallium zinc oxide IGZO). For another example, the metal oxide semiconductor material may be indium (In) and tin (Sn) oxide with a predetermined doping ratio (for example, indium tin oxide ITO).

[0067] like Figure 4 As shown, the channel structure 241 also includes a first electrode 244. The first electrode 244 is located at the end of the channel structure 241 away from the storage column 231, and is connected to (for example, directly in contact with) the channel layer 243. When powered on, the first electrode 244 is electrically connected to the channel layer 243. For example, the first electrode 244 is located in the space enclosed by the gate dielectric layer 242 and the channel layer 243, and the end surface of the first electrode 244 away from the storage column 231 is substantially flush with the end surface of the gate dielectric layer 242 away from the storage column 231. The material of the first electrode 244 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), or any other appropriate metal material.

[0068] In some embodiments, the semiconductor device 200 may further include a second stacked structure 251. The second stacked structure 251 is located on a side of the first stacked structure 221 away from the substrate 211, and includes a gate layer 253 and a second dielectric layer 252 located on opposite sides of the gate layer 253. The channel structure 241 may penetrate the second stacked structure 251 and be connected to the storage pillar 231. For example, the material of the second dielectric layer 252 may be silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. In some examples, the material of the gate layer 253 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), or any other suitable conductive material. In other examples, the material of the gate layer 253 may be a metal oxide conductor or a metal oxide semiconductor, for example, indium (In), gallium (Ga), zinc (Zn) oxide, and any combination thereof (for example, indium gallium zinc oxide IGZO) or indium (In) and tin (Sn) oxide with a predetermined doping ratio (for example, indium tin oxide ITO).

[0069] In the semiconductor device 200, the channel layer 243, the gate dielectric layer 242, the first electrode 244, and the portion of the gate layer 253 in contact with the gate dielectric layer 242 constitute a transistor T. For example, a vertical channel transistor T. Among them, the first electrode 244 can be used as the first electrode of the transistor T, the end of the inner electrode 233 close to the channel layer 243 can be used as the second electrode of the transistor T, the portion of the gate layer 253 in contact with the gate dielectric layer 242 is used as the gate of the transistor T, and the other portion of the gate layer 253 can be used as a word line WL. In this way, the transistor T and the plurality of capacitors C constitute a storage unit.

[0070] In this embodiment, the metal oxide semiconductor material can be formed by a low-temperature thin film deposition process. By selecting a metal oxide semiconductor as the material of the channel layer 243, selecting a metal as the material of the first electrode 244, and setting a metal column 235, the equivalent resistance of the transistor T can be reduced while reducing the thermal budget of the transistor T, thereby improving the electrical performance of the transistor T.

[0071] In some embodiments, Figure 3 and Figure 4 As shown, the substrate 211 and the first stacked structure 221 extend laterally along the x-direction and the y-direction, and are divided into a storage area 201 and a connection area 202 along the y-direction. In the storage area 201, a plurality of storage cells (corresponding to the channel structure 241) are arranged in an array along the x-direction and the y-direction. In the connection area 202, the semiconductor device 200 may further include a plurality of contact structures (not shown) and gate contacts (not shown), which are respectively used to lead the plate line layer 223 and the gate layer 253 out along the z-direction, which will be described in detail below.

[0072] In some embodiments, Figure 3 and Figure 4 As shown, the semiconductor device 200 may further include an isolation structure 261. For example, the isolation structure 261 penetrates the second stacked structure 251 and extends into the first dielectric layer 222 closest to the substrate 211 in the first stacked structure 221. The isolation structure 261 may also extend in the storage area 201 and the connection area 202 along the y direction to divide the storage blocks. It should be noted that the position and arrangement of the storage area 201 and the connection area 202 may be selected according to actual needs, and this application does not impose any specific restrictions on this.

[0073] In some embodiments, Figure 4As shown, the semiconductor device 200 may further include a bit line contact 262 and a gate contact 263. The bit line contact 262 is located on a side of the second stacked structure 251 away from the first stacked structure 221 and is connected to the first electrode 244. When powered on, the electrical connection between the bit line contact 262 and the first electrode 244 is achieved. For example, the bit line contact 262 may be used as a connection structure between a bit line (not shown) and the first electrode 244. The gate contact 263 is located on a side of the second stacked structure 251 away from the first stacked structure 221 and, for example, extends along the z direction into the gate layer 253 to be connected to the gate layer 253. When powered on, the electrical connection between the gate contact 263 and the gate layer 253 is achieved. In some examples, the materials of the bit line contact 262 and the gate contact 263 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si) or any other suitable conductive material. In other examples, the material of the bit line contact 262 and the gate contact 263 may be a metal oxide conductor or a metal oxide semiconductor, for example, indium (In), gallium (Ga), zinc (Zn) oxide, and any combination thereof (for example, indium gallium zinc oxide IGZO) or indium (In) and tin (Sn) oxide having a predetermined doping ratio (for example, indium tin oxide ITO).

[0074] In some embodiments, Figure 5 As shown, within the connection region 202, the semiconductor device 200 may further include a plurality of contact structures 264. For example, each contact structure 264 may have an outer profile that is substantially cylindrical. The plurality of contact structures 264 extend to the plate line layers 223 of different layers along the z direction, respectively, to connect with the plate line layers 223 of different layers, and lead the plate line layers 223 out along the z direction. For example, when power is turned on, the plurality of contact structures 264 are electrically connected to the plate line layers 223 of different layers. In some examples, the material of the contact structure 264 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), or any other suitable conductive material. In other examples, the material of contact structure 264 may be a metal oxide conductor or a metal oxide semiconductor, for example, indium (In), gallium (Ga), zinc (Zn) oxide, and any combination thereof (for example, indium gallium zinc oxide IGZO), or indium (In) and tin (Sn) oxide having a predetermined doping ratio (for example, indium tin oxide ITO).

[0075] In some embodiments, at least one of the materials of the above-mentioned plate line layer 223, gate layer 253, bit line contact 262, gate contact 263 and multiple contact structures 264 is a metal oxide semiconductor or a metal oxide conductor. This material selection method is beneficial to reducing the thermal budget of the semiconductor device and reducing the impact of thermal stress on the semiconductor device.

[0076] In some embodiments, Figure 5 As shown, the semiconductor device 200 may further include a protective layer 265. The protective layer 265 may be sleeved on the outside of the contact structure 264 and used to protect the plate line layer 223 from being damaged during the manufacturing process of the contact structure 264. Exemplarily, the material of the protective layer 265 may be different from the material of the plate line layer 223, so that the protective layer 265 and the plate line layer 223 have different etching selectivities relative to the same etching material. For example, the material of the protective layer 265 may include silicon oxide (SiO2).

[0077] Figure 6 2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present application. For the purpose of concise description, the same structure as the semiconductor device 200 described in the above embodiment will not be described in detail in the following embodiments.

[0078] like Figure 6 As shown, unlike the semiconductor device 200, the semiconductor device 300 may further include a first transition layer 346. The first transition layer 346 may be located between the channel layer 343 and the first electrode 344. For example, the first transition layer 346 is located at the sidewall and the bottom of the first electrode 344. The portion of the first transition layer 346 located at the bottom of the first electrode 344 contacts the channel layer 343, and the portion of the first transition layer 346 located at the sidewall of the first electrode 344 contacts the gate dielectric layer 342. It should be noted that the portion of the first transition layer 346 located at the sidewall of the first electrode 344 may be omitted, while the portion of the first transition layer 346 located at the bottom of the first electrode 344 is retained, so that the first transition layer 346 is located between the channel layer 343 and the first electrode 344. Exemplarily, the material of the channel layer 343 may have a first work function, the material of the first electrode 344 may have a second work function, and the work function of the material of the first transition layer 346 may be between the first work function and the second work function, so as to reduce the contact resistance between the first electrode 344 and the channel layer 343. For example, the material of the first transition layer 346 may include a metal oxide conductor or a metal oxide semiconductor, such as indium (In), gallium (Ga), zinc (Zn) oxide, and any combination thereof (e.g., indium gallium zinc oxide IGZO) or indium (In) and tin (Sn) oxide having a predetermined doping ratio (e.g., indium tin oxide ITO).

[0079] like Figure 6As shown, the semiconductor device 300 may further include a second transition layer 336. The second transition layer 336 may be located between the channel layer 343 and the internal electrode 333. For example, at the end of the internal electrode 333 close to the channel structure 341, the metal pillar 335 has a recess relative to the metal nitride layer 334, and the second transition layer 336 is located in the recess, so that the second transition layer 336 is located between the channel layer 343 and the internal electrode 333. It should be noted that the second transition layer 336 may also be located at other positions between the channel layer 343 and the internal electrode 333, for example, at the end of the channel layer 343 away from the first electrode 344, and surrounded by the gate dielectric layer 342 (not shown). The material of the internal electrode 333 (for example, the metal pillar 335) has a third work function. The work function of the material of the second transition layer 336 may be between the first work function and the third work function to reduce the contact resistance between the channel layer 343 and the metal pillar 335. For example, the material of the second transition layer 336 may include a metal oxide conductor or a metal oxide semiconductor, such as indium (In), gallium (Ga), zinc (Zn) oxide, and any combination thereof (e.g., indium gallium zinc oxide IGZO) or indium (In) and tin (Sn) oxide with a predetermined doping ratio (e.g., indium tin oxide ITO).

[0080] It should be noted that the first transition layer 346 and the second transition layer 336 can be provided at the same time, or one of them can be provided, and the present application does not impose any specific limitation on this.

[0081] Figure 7 FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor device provided by another embodiment of the present application. Figure 7As shown, unlike the semiconductor device 200, in the semiconductor device 400, the storage column 431 includes a storage function layer 432 and an inner electrode 433 arranged in sequence from the outside to the inside. In this embodiment, the inner electrode 433 may include a conductive layer 437 and a metal plug 438. The conductive layer 437 may be located on the inner wall of the storage function layer 432, and the metal plug 438 may be located on the inner side of the conductive layer 437 and close to the channel layer 443, and connected to the channel layer 443 (for example, directly contacting). When the power is turned on, the metal plug 438 is electrically connected to the channel layer 443. For example, the conductive layer 437 may be a tubular structure with one end closed, and is embedded in the inner wall of the storage function layer 432. Among them, the closed ends of the conductive layer 437 and the storage function layer 432 face the same direction. The metal plug 438 may be a columnar structure and occupy part of the inner space of the conductive layer 437. For example, the material of the conductive layer 437 may be one or more of tungsten (W), molybdenum (Mo), copper (Gu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), polysilicon (Poly-Si), or any other suitable conductive material. When the material of the conductive layer 437 is a metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)), the bonding performance between the metal plug 438 and the storage function layer 432 can be improved.

[0082] In some embodiments, the storage column 431 may further include an insulating column 439 located in the space surrounded by the conductive layer 437 and the metal plug 438. For example, the insulating column 439 occupies part of the inner space of the conductive layer 437 away from the channel layer 443, and occupies the entire inner space of the conductive layer 437 together with the metal plug 438. The insulating column 439 may play a role in supporting the metal plug 438. Exemplarily, the insulating column 439 material may be silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material or materials.

[0083] In this embodiment, by selecting a metal oxide semiconductor as the material of the channel layer 443, selecting a metal as the material of the first electrode 444, and providing a metal plug 438, the equivalent resistance of the transistor T can be reduced while reducing the thermal budget of the transistor T, thereby improving the electrical performance of the transistor T.

[0084] Figure 8 FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor device provided in yet another embodiment of the present application. Figure 8As shown, unlike the semiconductor device 400, the semiconductor device 500 may include a first transition layer 546 and a second transition layer 536. The first transition layer 546 may be located between the channel layer 543 and the first electrode 544. The second transition layer 536 may be located between the channel layer 543 and the inner electrode 533. For example, at the end of the inner electrode 533 close to the channel structure 541, the metal plug 538 has a recess relative to the conductive layer 537, and the second transition layer 536 is located in the recess, so that the second transition layer 536 is located between the channel layer 543 and the inner electrode 533. It should be noted that the second transition layer 536 may also be located at other positions between the channel layer 543 and the inner electrode 533, for example, at the end of the channel layer 543 away from the first electrode 544, and its sidewall is surrounded by the gate dielectric layer 542 (not shown). It should be noted that the first transition layer 546 and the second transition layer 536 may be provided at the same time, or one of them may be selected for provision, and the present application does not impose specific restrictions on this.

[0085] In this embodiment, the first transition layer 546 and / or the second transition layer 536 are provided to help reduce contact resistance and improve conductivity.

[0086] An embodiment of the present application also provides a method for manufacturing a semiconductor device. Fig. 9 10 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application. As shown in FIG10 , a method for manufacturing a semiconductor device 600 (hereinafter referred to as manufacturing method 600 ) may include the following steps.

[0087] S610, forming a first stacking structure, and forming a storage column passing through the first stacking structure, wherein the storage column includes a storage function layer and an inner electrode sequentially arranged from the outside to the inside.

[0088] S620, forming a second stacking structure on one side of the first stacking structure, and forming an initial channel structure that penetrates the second stacking structure to the storage column, the initial channel structure includes a gate dielectric layer and a channel layer arranged in sequence from the outside to the inside, and the channel layer is connected to the inner electrode.

[0089] S630, forming a first electrode at an end of the initial channel structure away from the storage pillar to form a channel structure, wherein the material of the channel layer includes a metal oxide semiconductor, and the material of the first electrode and the material of a portion of the inner electrode close to the channel layer both include metal.

[0090] According to the manufacturing method of the semiconductor device provided in this embodiment, by forming a channel layer made of a material such as a metal oxide semiconductor, and forming a first electrode made of a material such as a metal and a portion of an internal electrode close to the channel layer, the equivalent resistance of the transistor can be reduced while reducing the thermal budget of the transistor, thereby improving the electrical performance of the transistor.

[0091] FIG. 10A to FIG. 10Eis a schematic diagram of a cross-sectional structure of a semiconductor device provided in an embodiment of the present application during the manufacturing process. For example, the intermediate structure of the semiconductor device in the embodiment during the manufacturing process can be based on Fig. 9 The manufacturing method shown is formed and used to form Figure 6 The semiconductor device 300 is shown. FIG. 10A to FIG. 10E The above-mentioned steps S610 to S630 are described.

[0092] In step S610, Fig. 10C As shown, a first stacked structure 321 is formed, and a storage column 331 passing through the first stacked structure 321 is formed. The storage column 331 includes a storage function layer 332 and an internal electrode 333 which are sequentially arranged from the outside to the inside.

[0093] In some embodiments, the first stacked structure 321 and the storage pillar 331 may be formed by a manufacturing method described below. Fig. 10A As shown, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof may be used to alternately form a first dielectric layer 322 and a board line layer 323 on one side of the substrate 311, thereby forming a first stacked structure 321. Next, as Fig. 10B As shown, a storage hole 371 passing through the first stacked structure 321 may be formed by photolithography and etching (eg, dry etching or wet etching) processes. Then, as shown in FIG. Fig. 10B and Fig. 10C As shown, a storage function layer 332 may be formed on the inner wall of the storage hole 371 by a thin film deposition process of CVD, PVD, ALD or any combination thereof, and a metal nitride layer 334 may be formed on the inner wall of the storage function layer 332, and a metal pillar 335 may be formed on the inner side of the metal nitride layer 334. In this case, the metal nitride layer 334 and the metal pillar 335 serve as the inner electrode 333. Alternatively, the step of forming the metal nitride layer 334 may be omitted, and the metal pillar 335 may be directly formed on the inner side of the storage function layer 332. In this case, the metal pillar 335 serves as the inner electrode 333.

[0094] In some embodiments, the manufacturing method 600 may further include a step of forming a second transition layer 336. For example, an etching process may be used to remove a portion of the metal pillar 335 away from the substrate 311, and the second transition layer 336 may be formed in a recess formed after the removal of the portion of the metal pillar 335. The material of the second transition layer 336 may have a predetermined work function. For example, the channel layer 343 to be formed (see Fig. 10D) has a first work function, the material of the internal electrode 333 (for example, the metal pillar 335) has a third work function, and the work function of the material of the second transition layer 336 is between the first work function and the third work function to reduce the contact resistance between the channel layer 343 and the internal electrode 333.

[0095] In step S620, if Fig. 10D As shown, a second stacked structure 351 is formed on one side of the first stacked structure 321. For example, a second dielectric layer 352, a gate layer 353, and a second dielectric layer 352 may be sequentially formed on the surface of the first stacked structure 321 by using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. In this step, after the second stacked structure 351 is formed, an initial channel structure 341' is formed that penetrates the second stacked structure 351 to the storage column 331. The initial channel structure 341' includes a gate dielectric layer 342 and a channel layer 343 sequentially arranged from the outside to the inside, and the channel layer 343 is connected to the internal electrode 333. For example, when power is turned on, the electrical connection between the channel layer 343 and the internal electrode 333 is achieved.

[0096] In some embodiments, the initial channel structure 341' may be formed by a manufacturing method described below. First, a channel hole (corresponding to the outer contour of the initial channel structure 341') ​​that passes through the second stacked structure 351 to the storage pillar 331 may be formed by photolithography and etching (e.g., dry etching or wet etching). For example, the channel hole exposes the second transition layer 336. Then, as shown in FIG. Fig. 10D As shown, a gate dielectric layer 342 may be formed on the sidewall of the channel hole by a thin film deposition process such as CVD, PVD, ALD or any combination thereof, and a channel layer 343 may be formed on the inner side of the gate dielectric layer 342, so that the channel layer 343 is connected to the inner electrode 333 through the second transition layer 336. For example, when power is turned on, the channel layer 343 is electrically connected to the second transition layer 336 through the second transition layer 336.

[0097] In step S630, Fig. 10D and Fig.10E As shown, a first electrode 344 is formed at the end of the initial channel structure 341' away from the storage pillar 331 to form the channel structure 341. For example, an etching process can be used to remove a portion of the channel layer 343 away from the storage pillar 331, and the first electrode 344 is formed in the recess formed after removing the portion of the channel layer 343, thereby forming the channel structure 341.

[0098] In some embodiments, the manufacturing method 600 may further include the step of forming a first transition layer 346. For example, after removing a portion of the channel layer 343 away from the storage pillar 331 and before forming the first electrode 344, the first transition layer 346 may be formed on the inner wall of the recess formed after removing the portion of the channel layer 343. The material of the first transition layer 346 may have a predetermined work function. For example, the work function of the material of the first transition layer 336 is between the first work function of the material of the channel layer 343 and the second work function of the material of the first electrode 344, so as to reduce the contact resistance between the channel layer 343 and the first electrode 344.

[0099] In the channel layer 343 , the material thereof may be, for example, a metal oxide semiconductor; in the first electrode 344 and the metal pillar 335 , the material thereof may be, for example, a metal.

[0100] In this embodiment, by forming a channel layer 343 of a material such as a metal oxide semiconductor, and forming a first electrode 344 and a metal pillar 335 of a material such as a metal, the equivalent resistance of the transistor can be reduced while reducing the thermal budget of the transistor, thereby improving the electrical performance of the transistor.

[0101] FIG. 11A to FIG. 11C FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor device during the manufacturing process provided by another embodiment of the present application. For example, the intermediate structure of the semiconductor device during the manufacturing process in this embodiment can be based on Fig. 9 The manufacturing method shown is formed and used to form Figure 8 The semiconductor device 500 is shown. In this embodiment, the same contents as the steps in the above embodiments are not repeated in this application. FIG. 11A to FIG. 11C Steps S610 to S630 are described.

[0102] In step S610, Fig.11A As shown, after the first stacking structure 521 is formed, a storage column 531 passing through the first stacking structure 521 is formed, and the storage column 531 includes a storage function layer 532 and an internal electrode 533 arranged in sequence from the outside to the inside.

[0103] In some embodiments, the storage pillar 531 may be formed by a manufacturing method described below. Fig.11A As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to deposit a thin film in the storage hole 371 (refer to Fig. 10B) is formed on the inner wall of the storage function layer 532, and a conductive layer 537 is formed on the inner wall of the storage function layer 532. Next, an insulating column 539 is formed at the bottom of the inner side of the conductive layer 537, and a metal plug 538 is formed at the top of the inner side of the conductive layer 537. In this case, the conductive layer 537 and the metal plug 538 serve as the inner electrode 533. Optionally, a second transition layer 536 may be formed at the end of the inner electrode 533.

[0104] In step S620, if Fig. 11B As shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to form a second stack structure 551 on one side of the first stack structure 521, and an initial channel structure 541' is formed that penetrates the second stack structure 551 to the storage column 531. The initial channel structure 541' includes a gate dielectric layer 542 and a channel layer 543 that are sequentially arranged from the outside to the inside, and the channel layer 543 is connected to the internal electrode 533 (for example, a metal plug 538). For example, when power is turned on, the electrical connection between the channel layer 543 and the internal electrode 533 is achieved.

[0105] In step S620, if Fig. 11B and Fig. 11C As shown, a first electrode 544 is formed at the end of the initial channel structure 541' away from the storage pillar 531 to form the channel structure 541. Exemplarily, an etching process may be used to remove a portion of the channel layer 543 away from the storage pillar 531, and the first electrode 544 may be formed in a recess formed after the portion of the channel layer 543 is removed, thereby forming the channel structure 541. Optionally, after removing a portion of the channel layer 543 away from the storage pillar 531 and before forming the first electrode 544, a first transition layer 546 may be formed on the inner wall of the recess formed after the portion of the channel layer 543 is removed.

[0106] In the channel layer 543 , the material thereof may be, for example, a metal oxide semiconductor; in the first electrode 544 and the metal plug 538 , the material thereof may be, for example, a metal.

[0107] In this embodiment, by forming a channel layer 543 of a material such as a metal oxide semiconductor, and forming a first electrode 544 and a metal plug 538 of a material such as a metal, the equivalent resistance of the transistor can be reduced while reducing the thermal budget of the transistor, thereby improving the electrical performance of the transistor.

[0108] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor device, characterized in that: include: The storage column comprises a storage function layer and an inner electrode arranged in sequence from the outside to the inside; as well as A channel structure, located at the end of the storage column, and comprising a gate dielectric layer and a channel layer arranged in sequence from the outside to the inside, wherein the channel layer is connected to the inner electrode; Wherein, the channel structure further includes a first electrode, which is located at an end of the channel structure away from the storage column and connected to the channel layer; A material of the channel layer includes a metal oxide semiconductor, and a material of the first electrode and a material of a portion of the internal electrode close to the channel layer both include a metal.

2. The semiconductor device according to claim 1, wherein The invention also includes a first transition layer located between the channel layer and the first electrode.

3. The semiconductor device according to claim 2, wherein: The material of the first transition layer includes metal oxide semiconductor or metal oxide conductor.

4. The semiconductor device according to claim 1 or 2, wherein: A second transition layer is also included, which is located between the channel layer and the inner electrode.

5. The semiconductor device according to claim 4, wherein: The material of the second transition layer includes metal oxide semiconductor or metal oxide conductor.

6. The semiconductor device according to claim 1, wherein The inner electrode includes a metal column connected to the channel layer.

7. The semiconductor device according to claim 6, wherein: The inner electrode further includes a metal nitride layer, and the metal nitride layer is located between the metal pillar and the storage function layer.

8. The semiconductor device according to claim 1, wherein The inner electrode includes a conductive layer and a metal plug. The conductive layer is located on the inner side wall of the storage function layer. The metal plug is located inside the conductive layer and close to the channel layer and is connected to the channel layer.

9. The semiconductor device according to claim 8, wherein: The storage column further includes an insulating column located in a space surrounded by the conductive layer and the metal plug.

10. The semiconductor device according to claim 8, wherein The material of the conductive layer includes metal nitride.

11. The semiconductor device according to claim 1, wherein The semiconductor device has a storage area and a connection area, and the semiconductor device further comprises: A first stacking structure is located in the storage area and the connection area and includes first dielectric layers and plate line layers that are alternately arranged, and the storage column passes through the first stacking structure in the storage area; A second stacked structure, located at one side of the first stacked structure in the storage area, and comprising a gate layer and second dielectric layers located at two opposite sides of the gate layer, wherein the channel structure penetrates the second stacked structure; A bit line contact, located at a side of the second stack structure away from the first stack structure and connected to the first electrode; a gate contact, located on a side of the second stack structure away from the first stack structure and extending to the gate layer; and A plurality of contact structures extending to different board line layers in the connection region along the stacking direction of the first stacking structure; Wherein, the material of at least one of the plate line layer, the gate layer, the bit line contact, the gate contact and the plurality of contact structures comprises a metal oxide semiconductor or a metal oxide conductor.

12. The semiconductor device according to claim 11, wherein The materials of the plate line layer, the gate layer, the bit line contact, the gate contact and the plurality of contact structures all include indium tin oxide.

13. The semiconductor device according to claim 1, wherein The material of the channel layer includes indium gallium zinc oxide.

14. The semiconductor device according to claim 1, wherein The material of the storage function layer includes ferroelectric material.

15. A memory system, characterized in that: include: A memory device comprising the semiconductor device according to any one of claims 1 to 14; as well as The controller is coupled to the memory device and is used to control the memory device to store data.

16. A method for manufacturing a semiconductor device, characterized in that: include: forming a first stacking structure, and forming a storage column passing through the first stacking structure, wherein the storage column comprises a storage function layer and an inner electrode arranged sequentially from the outside to the inside; as well as forming a second stacking structure on one side of the first stacking structure, and forming an initial channel structure penetrating the second stacking structure to the storage column, the initial channel structure comprising a gate dielectric layer and a channel layer sequentially arranged from outside to inside, and the channel layer is connected to the inner electrode; and forming a first electrode at an end of the initial channel structure away from the storage pillar to form a channel structure; The material of the channel layer includes a metal oxide semiconductor, and the material of the first electrode and the material of a portion of the inner electrode close to the channel layer both include metal.

17. The manufacturing method according to claim 16, wherein: Before forming a first electrode at an end of the initial channel structure away from the storage pillar to form a channel structure, the method further includes: A first transition layer is formed at an end of the initial channel structure away from the storage pillar.

18. The manufacturing method according to claim 16 or 17, wherein: Before forming a second stack structure on one side of the first stack structure and forming an initial channel structure penetrating the second stack structure to the storage column, the method further includes: A second transition layer is formed at an end portion of the inner electrode.

19. The manufacturing method according to claim 16, wherein: Forming a storage column passing through the first stack structure includes: forming a storage hole through the first stacking structure; forming the storage function layer on the inner wall of the storage hole; and The metal pillar is formed inside the storage function layer to form the inner electrode.

20. The manufacturing method according to claim 19, wherein: Forming the metal pillar inside the storage function layer to form the inner electrode comprises: forming a metal nitride layer on the inner wall of the storage function layer; and The metal pillar is formed inside the metal nitride layer.

21. The manufacturing method according to claim 16, wherein: Forming a storage column passing through the first stack structure includes: forming a storage hole through the first stacking structure; forming the storage function layer on the inner wall of the storage hole; forming a conductive layer on the inner wall of the storage functional layer; forming an insulating column at the bottom of the inner side of the conductive layer; and A metal plug is formed on the top of the inner side of the conductive layer to form the inner electrode.

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