Laterally diffused metal oxide semiconductor device and manufacturing method thereof

Abstract

The invention provides a laterally diffused metal oxide semiconductor device and a manufacturing method thereof. The method comprises the following steps: forming a gate material layer and a silicon nitride mask layer on a substrate; etching the gate material layer by taking the silicon nitride mask layer as a mask to form a gate; forming a patterned photoresist layer with a first opening; performing high-energy ion implantation by taking the patterned photoresist layer and the silicon nitride mask layer as masks to form a first body region; trimming the patterned photoresist layer to form a second opening; performing low-energy ion implantation by taking the patterned photoresist layer and the silicon nitride mask layer as masks to form a second body region; and removing the patterned photoresist layer and the silicon nitride mask layer. According to the method, the silicon nitride mask layer is not removed after the grid electrode is formed by taking the silicon nitride mask layer as the mask, and the ion implantation is carried out by taking the patterned photoresist layer and the silicon nitride mask layer as the mask, so that ions can be prevented from directly penetrating through the patterned photoresist layer to enter the grid electrode during high-energy ion implantation, and the resistance of the grid electrode is prevented from being influenced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a laterally diffused metal oxide semiconductor device and a manufacturing method thereof. Background Art

[0002] Laterally diffused metal oxide semiconductor (LDMOS) is a high-voltage and high-power semiconductor device that is widely used in power integrated circuits. Laterally diffused metal oxide semiconductors have the characteristics of high voltage and high current of high-isolation devices, and have absorbed the advantages of high-density intelligent logic control of low-voltage integrated circuits. A single chip can achieve the functions that can only be completed by multiple chips, greatly reducing the area, reducing costs, and improving energy efficiency. It is in line with the development direction of miniaturization, intelligence, and low energy consumption of modern power electronic devices.

[0003] Laterally diffused metal oxide semiconductor devices are usually laid out as very wide strips, consisting of alternating strip source regions and strip drain regions. In the strip source regions, heavily doped N+ and P+ regions are made to contact the source region and body region respectively. There is a P-type shallow body region below the N+ and P+ regions, and the lateral diffusion of the P-type shallow body region below the polysilicon gate determines the channel of the laterally diffused metal oxide semiconductor. The ion implantation used to form the shallow body region is very shallow, so that the polysilicon gate is sufficient to form an effective ion implantation barrier, which means that the shallow body region can be self-aligned with the edge of the polysilicon gate.

[0004] In addition, a P-type deep body region is required in the strip source region to increase the curvature radius of the PN junction between the body region and the drain region and reduce the resistance value of the body region under the N+ source region, thereby preventing device damage caused by the conduction of the parasitic NPN transistor under high drain voltage.

[0005] However, the ion implantation to form the deep body region must have a projection range of up to 0.5μm, while the thickness of the polysilicon gate of the lateral diffused metal oxide semiconductor is usually 0.1μm to 0.3μm, which is not enough to block the ion implantation in the deep body region. Therefore, the deep body region must be realized through a special photolithography step using a photoresist layer at least 0.8μm thick. However, the photoresist layer cannot completely block the ion implantation into the polysilicon gate, thereby affecting the resistance of the polysilicon gate and ultimately affecting the device performance. Summary of the invention

[0006] The object of the present invention is to provide a laterally diffused metal oxide semiconductor device and a method for manufacturing the same, so as to prevent ions from directly penetrating a photoresist layer into a gate during high energy ion implantation, and to prevent ion implantation from affecting the resistance of the gate, thereby improving device performance.

[0007] In order to solve the above technical problems, the present invention provides a method for manufacturing a laterally diffused metal oxide semiconductor device, comprising the following steps:

[0008] Providing a substrate, and sequentially forming a gate material layer and a silicon nitride mask layer on the substrate;

[0009] Etching the gate material layer using the silicon nitride mask layer as a mask to form a gate;

[0010] Forming a patterned photoresist layer, wherein the patterned photoresist layer covers the substrate surface, the gate sidewalls, and the sidewalls and top of the silicon nitride mask layer, and has a first opening exposing a portion of the substrate between adjacent gates;

[0011] Using the patterned photoresist layer and the silicon nitride mask layer as masks, high-energy ion implantation is performed through the first opening to form a first body region in the substrate between adjacent gates;

[0012] trimming a portion of the patterned photoresist layer on both sides of the first opening to form a second opening that at least exposes the gate sidewall;

[0013] Using the patterned photoresist layer and the silicon nitride mask layer as masks, low-energy ion implantation is performed through the second opening to form a second body region in the substrate between adjacent gates; and

[0014] The patterned photoresist layer and the silicon nitride mask layer are removed.

[0015] Optionally, the thickness of the silicon nitride mask layer is greater than or equal to 200 nm and less than or equal to 400 nm.

[0016] Optionally, before forming the gate material layer on the substrate, the method further includes: forming a gate oxide layer on the substrate.

[0017] Optionally, the thickness of the gate oxide layer is greater than or equal to 11 nm and less than or equal to 15 nm; the thickness of the gate material layer is greater than or equal to 100 nm and less than or equal to 300 nm.

[0018] Optionally, the method for forming the silicon nitride mask layer includes:

[0019] forming a silicon nitride material layer on the gate material layer;

[0020] forming a photoresist layer on the silicon nitride material layer, and exposing and developing the photoresist layer to form a patterned photoresist layer;

[0021] Using the patterned photoresist layer as a mask, etching the silicon nitride material layer until the gate material layer is exposed; and

[0022] The patterned photoresist layer is removed.

[0023] Optionally, the ion dose of the high energy ion implantation is smaller than the ion dose of the low energy ion implantation.

[0024] Optionally, a lower surface of the first body region is lower than a lower surface of the second body region.

[0025] Optionally, after performing low-energy ion implantation, the manufacturing method further includes: performing a thermal annealing activation treatment.

[0026] Optionally, after removing the patterned photoresist layer and the silicon nitride mask layer, the method further includes: forming a sidewall spacer on the sidewall of the gate.

[0027] Correspondingly, the present invention also provides a laterally diffused metal oxide semiconductor device, which is manufactured using the manufacturing method of the laterally diffused metal oxide semiconductor device as described above.

[0028] In summary, in the laterally diffused metal oxide semiconductor device and the manufacturing method thereof provided by the present invention, a substrate is first provided, a gate material layer and a silicon nitride mask layer are sequentially formed on the substrate, and then the gate material layer is etched using the silicon nitride mask layer as a mask to form a gate, and then a patterned photoresist layer is formed, wherein the patterned photoresist layer covers the substrate surface, the gate sidewalls, and the sidewalls and top of the silicon nitride mask layer, and has a first opening exposing a portion of the substrate between adjacent gates, and then the patterned photoresist layer and the silicon nitride mask layer are used as masks to perform high-energy ion implantation through the first opening to form a first body region in the substrate between adjacent gates, and then the portions of the patterned photoresist layer on both sides of the first opening are trimmed to form a second opening exposing at least the gate sidewalls, and then the patterned photoresist layer and the silicon nitride mask layer are used as masks to perform low-energy ion implantation through the second opening to form a second body region in the substrate between adjacent gates, and then the patterned photoresist layer and the silicon nitride mask layer are removed. The present invention uses a silicon nitride mask layer as a mask to etch a gate material layer to form a gate. After the gate is formed, the silicon nitride mask layer is not removed, but ion implantation is performed using a patterned photoresist layer and the silicon nitride mask layer as masks. This can prevent ions from directly penetrating the patterned photoresist layer into the gate during high-energy ion implantation, that is, the presence of the silicon nitride mask layer can prevent ions from being implanted into the gate, thereby avoiding affecting the resistance of the gate, thereby improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1It is a flow chart of a method for manufacturing a laterally diffused metal oxide semiconductor device provided by one embodiment of the present invention.

[0030] Figure 2 It is a schematic diagram of the structure after forming a silicon nitride material layer provided by an embodiment of the present invention.

[0031] Figure 3 It is a schematic diagram of the structure after forming a silicon nitride mask layer provided by an embodiment of the present invention.

[0032] Figure 4 It is a schematic diagram of the structure after the gate is formed provided by an embodiment of the present invention.

[0033] Figure 5 It is a schematic diagram of the structure after the first body region is formed provided by an embodiment of the present invention.

[0034] Figure 6 It is a schematic diagram of the structure after the second body region is formed provided by an embodiment of the present invention.

[0035] Figure 7 It is a schematic diagram of the structure after the silicon nitride mask layer is removed provided by an embodiment of the present invention.

[0036] Description of reference numerals:

[0037] 10-substrate; 11-gate oxide layer; 12-gate material layer; 13-silicon nitride material layer; 14-silicon nitride mask layer; 15-gate; 16-patterned photoresist layer; 171-first opening; 172-second opening; 181-first body region; 182-second body region. DETAILED DESCRIPTION

[0038] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0039] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, unless the content clearly indicates otherwise. As used in the present invention, the term "or" is generally used in a sense that includes "and / or", unless the content clearly indicates otherwise. As used in the present invention, the term "several" is generally used in a sense that includes "at least one", unless the content clearly indicates otherwise. As used in the present invention, the term "at least two" is generally used in a sense that includes "two or more", unless the content clearly indicates otherwise. In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features.

[0040] Figure 1 FIG. 1 is a flow chart of a method for manufacturing a laterally diffused metal oxide semiconductor device according to an embodiment of the present invention. Figure 1 As shown, the method for manufacturing the laterally diffused metal oxide semiconductor device comprises the following steps:

[0041] S1: providing a substrate, and sequentially forming a gate material layer and a silicon nitride mask layer on the substrate;

[0042] S2: etching the gate material layer using the silicon nitride mask layer as a mask to form a gate;

[0043] S3: forming a patterned photoresist layer, wherein the patterned photoresist layer covers the substrate surface, the gate sidewalls, and the sidewalls and top of the silicon nitride mask layer, and has a first opening exposing a portion of the substrate between adjacent gates;

[0044] S4: using the patterned photoresist layer and the silicon nitride mask layer as masks, performing high-energy ion implantation through the first opening to form a first body region in the substrate between adjacent gates;

[0045] S5: trimming a portion of the patterned photoresist layer on both sides of the first opening to form a second opening that at least exposes the side wall of the gate;

[0046] S6: using the patterned photoresist layer and the silicon nitride mask layer as masks, performing low-energy ion implantation through the second opening to form a second body region in the substrate between adjacent gates; and

[0047] S7: removing the patterned photoresist layer and the silicon nitride mask layer.

[0048] Figures 2 to 7FIG. 1 is a schematic diagram of the structure of each step of a method for manufacturing a lateral diffused metal oxide semiconductor device according to an embodiment of the present invention. Figure 1 and Figures 2 to 7 The method for manufacturing a laterally diffused metal oxide semiconductor device provided by an embodiment of the present invention is described in detail.

[0049] In step S1, refer to Figure 3 As shown, a substrate 10 is provided, and a gate material layer 12 and a silicon nitride mask layer 14 are sequentially formed on the substrate 10 .

[0050] The material of the substrate 10 may be silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium gallium, etc., or may be silicon on insulator, germanium on insulator; or may be other materials, such as III-V compounds such as gallium arsenide. In this embodiment, the material of the substrate 10 is silicon.

[0051] In one embodiment of the present invention, please refer to Figure 2 As shown, before forming the gate material layer 12, a gate oxide layer 11 is formed on the substrate 10. Exemplarily, the material of the gate oxide layer 11 is silicon oxide, and the gate oxide layer 11 can be formed by a thermal oxidation process, or by a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or a combination thereof.

[0052] Next, please continue to refer to Figure 2 As shown, a gate material layer 12 is formed on the gate oxide layer 11, and the gate material layer 12 covers the gate oxide layer 11. The gate material layer 12 is, for example, polycrystalline silicon, and can be formed by methods known to those skilled in the art, such as thermal decomposition, chemical vapor deposition, and decomposed silicon compound method. Exemplarily, the thermal decomposition method uses a chemical reaction of silicon gas and hydrogen to generate polycrystalline silicon, which has the advantages of simple preparation process and low cost; the chemical vapor deposition method uses silicon source gas, doping gas and diluent gas to generate polycrystalline silicon through chemical reaction, which has the advantages of high purity, good uniformity and loose film layer; the decomposed silicon compound method uses solid phase reaction in the presence of easily decomposable silicon compounds (such as silicon trichloride, silane, etc.) to generate polycrystalline silicon, which has the advantages of simple preparation process and high purity; the specific manufacturing method can be determined according to the specific requirements for the gate material layer 12.

[0053] Next, please continue to refer to Figure 2As shown, a silicon nitride material layer 13 is formed on the gate material layer 12, and the silicon nitride material layer 13 covers the gate material layer 12. The silicon nitride material layer 13 is a silicon nitride layer, and in order to distinguish it from the subsequent silicon nitride mask layer, it is named as a silicon nitride material layer here. Exemplarily, the silicon nitride material layer 13 can be formed by a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process or a combination thereof.

[0054] Then, a photoresist layer (not shown) is formed on the silicon nitride material layer 13, and the photoresist layer is exposed and developed to form a patterned photoresist layer, and then the patterned photoresist layer is used as a mask to etch the silicon nitride material layer 13 until the gate material layer 12 is exposed to form a silicon nitride mask layer 14, and the silicon nitride mask layer 14 exposes the gate material layer 12 to be removed. Exemplarily, the silicon nitride material layer 13 can be etched by wet etching or dry etching, for example, hot phosphoric acid can be used for wet etching, and CF4 gas can be used in combination with O2 and N2 for dry etching, but it is certainly not limited thereto.

[0055] That is, the silicon nitride material layer 13 is etched to form a silicon nitride mask layer 14, and the silicon nitride mask layer 14 is used as a mask layer when etching the gate material layer 12 to form a gate. Of course, after forming the silicon nitride mask layer 14, the patterned photoresist layer is removed. Exemplarily, the patterned photoresist layer is removed by an ashing process or a wet etching process. Finally, the following is formed: Figure 3 The structure shown.

[0056] In one embodiment of the present invention, the thickness of the gate oxide layer 11 is greater than or equal to 11 nm and less than or equal to 15 nm, but it is not limited thereto. The thickness of the gate oxide layer 11 can be determined according to the actual requirements of the device. Exemplarily, the thickness of the gate oxide layer 11 is 11 nm, 13 nm or 15 nm, and preferably, the thickness of the gate oxide layer 11 is 13 nm.

[0057] The thickness of the gate material layer 12 is greater than or equal to 100 nm and less than or equal to 300 nm. The thickness of the gate material layer 12 determines the thickness of the gate formed subsequently. The thickness of the gate material layer 12 is of course not limited thereto, and the thickness of the gate material layer 12 can be determined according to the actual requirements of the device. Exemplarily, the thickness of the gate material layer 12 is 100 nm, 150 nm, 200 nm, 250 nm or 300 nm. Preferably, the thickness of the gate material layer 12 is 200 nm.

[0058] The thickness of the silicon nitride mask layer 14 is greater than or equal to 200nm and less than or equal to 400nm. For example, the thickness of the silicon nitride mask layer 14 is 200nm, 250nm, 300nm, 350nm or 400nm. Preferably, the thickness of the silicon nitride mask layer 14 is 300nm. The silicon nitride mask layer 14 is not only used as a mask layer when the gate material layer 12 is etched, but also used as a mask layer for subsequent high-energy ion implantation. Its thickness can be determined according to actual needs. Exemplarily, the thickness of the silicon nitride mask layer 14 cannot be too thin. Its thickness needs to ensure that high-energy ions will not penetrate the silicon nitride mask layer 14 and protect the gate from ion invasion. At the same time, it cannot be too thick. A too thick silicon nitride mask layer 14 not only causes a waste of material, but also increases the difficulty of removal. Therefore, a suitable thickness can be selected according to actual conditions.

[0059] In step S2, please refer to Figure 4 As shown, the gate material layer 12 is etched using the silicon nitride mask layer 14 as a mask to form a gate 15 .

[0060] Exemplarily, the gate material layer 12 may be etched by dry etching or wet etching. Dry etching mainly utilizes active particles in plasma to physically bombard and chemically react with polysilicon to achieve material removal. Wet etching utilizes chemical reactions to remove polysilicon materials, usually using an etching solution, such as HNO3-HF etching solution, the etching principle of which involves a chemical reaction of an oxidant (such as HNO3) and a complexing agent (such as HF) to form soluble SiO2, thereby achieving corrosion of polysilicon.

[0061] In this embodiment, the gate material layer 12 is etched using the silicon nitride mask layer 14 as a mask until the gate oxide layer 11 is exposed, thereby forming the gate 15. Exemplarily, the etching of the gate material layer 12 may also include endpoint detection, by directly detecting the etching layer macroscopically, the light waves emitted from the etching layer, the concentration of plasma etchant ions, etc., to compensate for the process control and process judgment in the etching, so as to compensate for the change in etching rate caused by the fluctuation of material composition and thickness or the change of working parameters.

[0062] In step S3, please refer to Figure 5 As shown, a patterned photoresist layer 16 is formed, which covers the surface of the substrate 10, the sidewalls of the gate 15, and the sidewalls and top of the silicon nitride mask layer 14, and has a first opening 171 exposing a portion of the substrate 10 between adjacent gates 15.

[0063] Exemplarily, first, a photoresist layer is formed, and the photoresist layer covers the substrate 10, the sidewalls of the gate 15, and the sidewalls and top of the silicon nitride mask layer 14, that is, the photoresist layer covers the entire surface of the substrate 10 and has a relatively thick thickness. Then, the photoresist layer is exposed and developed to form a first opening 171 that exposes a portion of the substrate 10 between adjacent gates 15. The first opening 171 only exposes a portion of the substrate 10 between adjacent gates 15, and the patterned photoresist layer 16 covers the sidewalls of the gate 15.

[0064] In one embodiment of the present invention, the distances between the first opening 171 and the gates 15 on two adjacent sides may be equal, that is, the thickness of the photoresist layer between the first opening 171 and the gates 15 on two adjacent sides is consistent. Of course, in another embodiment of the present invention, the distances between the first opening 171 and the gates 15 on two adjacent sides may also be unequal, for example, the first opening 171 may be close to the gates 15 on two adjacent sides. Figure 5 The gate 15 on the left side, or the first opening 171 is close to Figure 5 The gate 15 located on the right side of the circuit is not limited in the present invention and can be determined according to the required position of the first body region formed by the first opening 171. For example, if the first body region needs to be located in the middle area between the adjacent gates 15, that is, the distances to the gates 15 on both sides are the same, then the first opening 171 is at the same distance from the adjacent gates 15 on both sides; if the first body region needs to be close to the gate 15 on the left side, then the first opening 171 is close to the gate 15 on the left side.

[0065] In this embodiment, after the gate 15 is formed, the silicon nitride mask layer 14 is not removed, and the patterned photoresist layer 16 is directly formed on the silicon nitride mask layer 14. When high-energy ion implantation is subsequently performed, the patterned photoresist layer 16 is used as a mask for ion implantation. The silicon nitride mask layer 14 can also serve as a mask layer, which can prevent high-energy ions from penetrating the patterned photoresist layer 16 and entering the gate 15 and being injected into the gate 15, thereby avoiding the influence of high-energy ion implantation on the gate 15.

[0066] In step S4, please continue to refer to Figure 5 As shown, with the patterned photoresist layer 16 and the silicon nitride mask layer 14 as masks, high energy ion implantation is performed through the first opening 171 to form a first body region 181 in the substrate 10 between adjacent gates 15 .

[0067] In this embodiment, high-energy ion implantation is performed using the patterned photoresist layer 16 as a mask, and the high-energy ion implantation enters the substrate 10 from the first opening 171 to form a first body region 181 in the substrate 10. During the ion implantation process, due to the high energy, the ions will penetrate the patterned photoresist layer 16, but due to the presence of the silicon nitride mask layer 14, the ions will not penetrate the silicon nitride mask layer 14 and be implanted into the gate 15. Therefore, this ion implantation uses the patterned photoresist layer 16 and the silicon nitride mask layer 14 as masks. The silicon nitride mask layer 14 serves as a protective layer for the gate 15 to protect the gate 15 from the influence of ion implantation.

[0068] In one embodiment of the present invention, the ions implanted in the high energy ion implantation include boron. Exemplarily, the high energy ion implantation can be divided into two ion implantations, the energy of the first ion implantation is, for example, 300 KeV, and the dose of the ion implantation is, for example, 2×10 13 atom / cm 2 The energy of the second ion implantation is, for example, 100 KeV, and the dose of the ion implantation is, for example, 2.3×10 13 atom / cm 2 , of course, it is not limited to this. This high energy implantation is high energy and low dose (wherein low dose is relative to low energy ion implantation).

[0069] In step S5, please refer to Figure 5 and Figure 6 As shown, part of the patterned photoresist layer 16 on both sides of the first opening 171 is trimmed to form a second opening 172 that at least exposes the side wall of the gate 15 .

[0070] In this embodiment, trimming the portion of the patterned photoresist layer 16 on both sides of the first opening 171 includes removing the portion of the patterned photoresist layer 16 on both sides of the first opening 171, that is, expanding the first opening 171 to form a second opening 172, that is, the cross-sectional size of the second opening 172 is larger than the cross-sectional size of the first opening 171.

[0071] The second opening 172 at least exposes the sidewall of the gate 15. In one embodiment of the present invention, the second opening 172 just exposes the sidewall of the gate 15, that is, the sidewall of the second opening 172 coincides with the sidewall of the gate 15, or the sidewall of the patterned photoresist layer 16 is flush with the sidewall of the gate 15. In another embodiment of the present invention, the second opening 172 not only exposes the sidewall of the gate 15, but also exposes a portion of the top of the gate 15 (e.g., Figure 6 shown).

[0072] Exemplarily, the photoresist layer trimming step adopts an isotropic plasma etching process, and the photoresist layer trimming step includes etching the patterned photoresist layer 16 with oxygen-containing plasma to expose the sidewall of the gate 15 or expose the sidewall of the gate 15 and a portion of the top of the gate 15. In one embodiment, the gas used in the photoresist layer trimming step is O2, the flow rate of O2 is 50sccm to 250sccm, the RF power is 300W to 800W, the bias power is 0 to 10W, and the chamber pressure is 5mtorr to 50mtorr, so that the photoresist is trimmed with a higher accuracy to accurately expose the corresponding second opening 172.

[0073] In step S6, please continue to refer to Figure 6 As shown, using the patterned photoresist layer 16 and the silicon nitride mask layer 14 as masks, low-energy ion implantation is performed through the second opening 172 to form a second body region 182 in the substrate 10 between adjacent gates 15 .

[0074] In this embodiment, low-energy ion implantation is performed using the patterned photoresist layer 16 and the silicon nitride mask layer 14 as masks. Since the cross-sectional size of the second opening 172 is greater than or equal to the size between adjacent gates 15 , low-energy ion implantation is performed between adjacent gates 15 to form a second body region 182 .

[0075] In one embodiment of the present invention, the ion dose of the high energy ion implantation is less than the ion dose of the low energy ion implantation. The lower surface 181a of the first body region 181 is lower than the lower surface 182a of the second body region 182. That is, the first body region 181 is equivalent to a deep body region, and the second body region 182 is equivalent to a shallow body region. In a direction parallel to the substrate 10 ( Figure 6 The cross-sectional dimension W1 of the first body region 181 is smaller than the cross-sectional dimension W2 of the second body region 182, and in the direction perpendicular to the substrate 10 ( Figure 6 In the vertical direction), the cross-sectional size of the first body region 181 is greater than the cross-sectional size of the second body region 182.

[0076] Exemplarily, the low-energy ion implantation is divided into two ion implantations. The ions implanted in the first ion implantation include boron, the energy of the ion implantation is, for example, 30 KeV, and the dose of the ion implantation is, for example, 8.5×10 13 atom / cm 2 The ions implanted in the second ion implantation include arsenic, the energy of the ion implantation is, for example, 15 KeV, and the dose of the ion implantation is, for example, 5×10 14 atom / cm 2, of course, it is not limited to this. This low energy implantation is low energy and high dose (wherein high dose is relative to high energy ion implantation).

[0077] In one embodiment of the present invention, after low-energy ion implantation, the manufacturing method further includes: performing a thermal annealing activation process to activate ions in the first body region 181 and / or the second body region 182 .

[0078] In step S6, please refer to Figure 7 As shown, the patterned photoresist layer 16 and the silicon nitride mask layer 14 are removed.

[0079] In one embodiment of the present invention, the patterned photoresist layer 16 is first removed, for example, by using an ashing process or a wet etching process to remove the patterned photoresist layer 16. Then, the silicon nitride mask layer 14 is removed, and the silicon nitride mask layer 14 can be removed by using a wet etching process or a dry etching process.

[0080] In another embodiment of the present invention, the patterned photoresist layer 16 and the silicon nitride mask layer 14 may be removed in the same process step. For example, the patterned photoresist layer 16 may be removed by wet etching, and then the silicon nitride mask layer 14 may be removed.

[0081] After removing the patterned photoresist layer 16 and the silicon nitride mask layer 14, the process further includes: forming a sidewall on the sidewall of the gate 15. The subsequent process also includes heavy doping ion implantation and annealing activation to form source and drain contact areas, body contact areas, contact holes and front metal, etc., which are the same as the existing process and will not be described in detail.

[0082] In the method for manufacturing a lateral diffused metal oxide semiconductor device provided by the present invention, a substrate 10 is first provided, a gate material layer 12 and a silicon nitride mask layer 14 are sequentially formed on the substrate 10, and then the gate material layer 12 is etched using the silicon nitride mask layer 14 as a mask to form a gate 15, and then a patterned photoresist layer 16 is formed, wherein the patterned photoresist layer 16 covers the surface of the substrate 10, the sidewalls of the gate 15, and the sidewalls and top of the silicon nitride mask layer 14, and has a first opening 171 exposing a portion of the substrate 10 between adjacent gates 15, and then the patterned photoresist layer 16 and the silicon nitride mask layer 14 are used as a mask to form a gate 15. The film layer 14 is used as a mask, and high-energy ion implantation is performed through the first opening 171 to form a first body region 181 in the substrate 10 between adjacent gates 15. Then, part of the patterned photoresist layer 16 on both sides of the first opening 171 is trimmed to form a second opening 172 that at least exposes the side wall of the gate 15. Then, the patterned photoresist layer 16 and the silicon nitride mask layer 14 are used as masks to perform low-energy ion implantation through the second opening 172 to form a second body region 182 in the substrate 10 between adjacent gates 15. Then, the patterned photoresist layer 16 and the silicon nitride mask layer 14 are removed. The present invention uses a silicon nitride mask layer 14 as a mask to etch a gate material layer 12 to form a gate 15. After the gate 15 is formed, the silicon nitride mask layer 14 is not removed, but ion implantation is performed using a patterned photoresist layer 16 and the silicon nitride mask layer 14 as masks. This can prevent ions from directly penetrating the patterned photoresist layer 16 and entering the gate 15 during high-energy ion implantation. That is, the presence of the silicon nitride mask layer 14 can prevent ions from being implanted into the gate 15, thereby avoiding affecting the resistance of the gate 15, thereby improving device performance.

[0083] Accordingly, the present invention also provides a laterally diffused metal oxide semiconductor device, which is manufactured using the manufacturing method of the laterally diffused metal oxide semiconductor device as described above. Figure 7 As shown, the laterally diffused metal oxide semiconductor device comprises:

[0084] Substrate 10;

[0085] A gate 15, located on the substrate 10;

[0086] The first body region 181 and the second body region 182 are located in the substrate 10 between the adjacent gates 15, and the cross-sectional dimension W2 of the second body region 182 is larger than the cross-sectional dimension W1 of the first body region 181 (wherein the cross-sectional dimension refers to Figure 7 Horizontal cross-sectional dimensions as shown).

[0087] In one embodiment of the present invention, a gate oxide layer 11 is formed between the substrate 10 and the gate 15, and the gate oxide layer 11 covers the substrate 10. The material of the gate oxide layer 11 is, for example, silicon oxide.

[0088] In one embodiment of the present invention, the lower surface of the first body region 181 is lower than the lower surface of the second body region 182. That is, in a direction perpendicular to the substrate 10 ( Figure 7 In the vertical direction shown), the cross-sectional dimension of the first body region 181 is greater than the cross-sectional dimension of the second body region 182.

[0089] In summary, in the laterally diffused metal oxide semiconductor device and the manufacturing method thereof provided by the present invention, a substrate is first provided, a gate material layer and a silicon nitride mask layer are sequentially formed on the substrate, and then the gate material layer is etched using the silicon nitride mask layer as a mask to form a gate, and then a patterned photoresist layer is formed, wherein the patterned photoresist layer covers the substrate surface, the gate sidewalls, and the sidewalls and top of the silicon nitride mask layer, and has a first opening exposing a portion of the substrate between adjacent gates, and then the patterned photoresist layer and the silicon nitride mask layer are used as masks to perform high-energy ion implantation through the first opening to form a first body region in the substrate between adjacent gates, and then the portions of the patterned photoresist layer on both sides of the first opening are trimmed to form a second opening exposing at least the gate sidewalls, and then the patterned photoresist layer and the silicon nitride mask layer are used as masks to perform low-energy ion implantation through the second opening to form a second body region in the substrate between adjacent gates, and then the patterned photoresist layer and the silicon nitride mask layer are removed. The present invention uses a silicon nitride mask layer as a mask to etch a gate material layer to form a gate. After the gate is formed, the silicon nitride mask layer is not removed, but ion implantation is performed using a patterned photoresist layer and the silicon nitride mask layer as masks. This can prevent ions from directly penetrating the patterned photoresist layer into the gate during high-energy ion implantation, that is, the presence of the silicon nitride mask layer can prevent ions from being implanted into the gate, thereby avoiding affecting the resistance of the gate, thereby improving device performance.

[0090] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a laterally diffused metal oxide semiconductor device, characterized in that: The following steps are involved: Providing a substrate, and sequentially forming a gate material layer and a silicon nitride mask layer on the substrate; Etching the gate material layer using the silicon nitride mask layer as a mask to form a gate; Forming a patterned photoresist layer, wherein the patterned photoresist layer covers the substrate surface, the gate sidewalls, and the sidewalls and top of the silicon nitride mask layer, and has a first opening exposing a portion of the substrate between adjacent gates; Using the patterned photoresist layer and the silicon nitride mask layer as masks, high-energy ion implantation is performed through the first opening to form a first body region in the substrate between adjacent gates; trimming a portion of the patterned photoresist layer on both sides of the first opening to form a second opening that at least exposes the sidewall of the gate; Using the patterned photoresist layer and the silicon nitride mask layer as masks, low-energy ion implantation is performed through the second opening to form a second body region in the substrate between adjacent gates; as well as The patterned photoresist layer and the silicon nitride mask layer are removed.

2. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The thickness of the silicon nitride mask layer is greater than or equal to 200 nm and less than or equal to 400 nm.

3. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: Before forming the gate material layer on the substrate, the method further includes: forming a gate oxide layer on the substrate.

4. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 3, characterized in that: The thickness of the gate oxide layer is greater than or equal to 11 nm and less than or equal to 15 nm; the thickness of the gate material layer is greater than or equal to 100 nm and less than or equal to 300 nm.

5. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The method for forming the silicon nitride mask layer includes: forming a silicon nitride material layer on the gate material layer; forming a photoresist layer on the silicon nitride material layer, and exposing and developing the photoresist layer to form a patterned photoresist layer; Using the patterned photoresist layer as a mask, etching the silicon nitride material layer until the gate material layer is exposed; and The patterned photoresist layer is removed.

6. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The ion dose of the high energy ion implantation is smaller than the ion dose of the low energy ion implantation.

7. The method for manufacturing a laterally diffused metal oxide semiconductor device according to claim 6, characterized in that: A lower surface of the first body region is lower than a lower surface of the second body region.

8. The method for manufacturing a laterally diffused metal oxide semiconductor device according to any one of claims 1 to 7, characterized in that: After low-energy ion implantation, the manufacturing method further includes: performing thermal annealing activation treatment.

9. The method for manufacturing a laterally diffused metal oxide semiconductor device according to any one of claims 1 to 7, characterized in that: After removing the patterned photoresist layer and the silicon nitride mask layer, the method further includes: forming a sidewall on the sidewall of the gate.

10. A laterally diffused metal oxide semiconductor device, characterized in that: The device is manufactured by the method for manufacturing a laterally diffused metal oxide semiconductor device according to any one of claims 1 to 9.

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