Semiconductor device

Abstract

A semiconductor device includes a semiconductor layer, a gate structure, a control source electrode plate, and a drain electrode. The gate structure has a surface to contact the semiconductor layer. A control source electrode plate contacts the semiconductor layer, wherein the control source electrode plate covers the gate structure in a direction perpendicular to the surface of the gate structure. A drain electrode contacts the semiconductor layer. According to the semiconductor device, the source electrode plate and the gate structure are controlled to be overlapped in the gate electric field direction, the area and the occurrence probability of the linear tunneling effect are increased, the secondary threshold swing is reduced, and the problems that the process is complex and difficult, the occupied area is large, the generated linear tunneling area is too small, and the linear tunneling probability is low can be solved.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] The conventional tunnel field-effect transistor (TFET) is a gate-controlled reverse biased PIN diode, which has a small inherent driving current (Ion) and a dominant current mechanism of point-tunneling. It is easily affected by energy traps in semiconductor materials and interface energy traps, which generates leakage current assisted by energy traps, resulting in an increase in the subthreshold swing. It is difficult to produce a conventional TFET element with a subthreshold swing of less than 60mV / Dec, and it is impossible to perform low power supply voltage applications. In addition, the conventional TFET element is a PIN structure, which requires three different doping regions (i.e., at least two to three ion implantation technologies and subsequent annealing technologies with very high thermal budgets), and the cost is very high. In addition, the subthreshold swing of the conventional TFET element tends to gradually deteriorate with the increase of the gate bias value, resulting in a significant decay of the average subthreshold swing, which far exceeds 60mV / Dec. In addition, the am-bipolar behavior of the conventional TFET element is serious and tends to occur early, resulting in a large amount of leakage current.

[0003] In order to solve the problem of too small driving current, line tunneling between semiconductors with different doping is used, such as the L-type line tunneling crystal field effect transistor, whose source electrode and gate area are on the same surface of the PIN semiconductor, or the source electrode and drain electrode are both in the edge area. And its line tunneling only occurs between semiconductors of different types or different doping, so the probability of line tunneling is too small, and the doping concentration of the two layers of semiconductors in the source area cannot be large enough, resulting in a significantly small probability of line tunneling. The previous patent (TWM598528U) uses the inversion layer under the gate and the equally highly doped source area below to increase the probability of line tunneling. However, because the source electrode is only connected to the side edge of the semiconductor block, it is impossible to generate a uniform large electric field to assist line tunneling. The probability of line tunneling is still not high enough, and the Ion current cannot be amplified. Summary of the invention

[0004] The purpose of the present disclosure is to provide a semiconductor device that can overcome all the problems encountered by traditional PIN TFETs, and can also solve the problems faced by various previous wire tunneling structures, such as complex and difficult processes, large area, too small area that can produce wire tunneling, and low wire tunneling probability. In some embodiments of the present disclosure, by making the control source electrode plate overlap with the gate structure along the gate electric field direction, the area and occurrence probability of the linear tunneling effect are increased, thereby increasing Ion and reducing the sub-threshold swing. In some embodiments of the present disclosure, it is also possible to design a control source electrode plate and a drain electrode so that one of them is a Schottky contact and the other is an ohmic contact. The setting of the Schottky contact will form an impurity sensing area in the semiconductor layer to omit the ion implantation step, thereby simplifying the process and reducing the process cost. In some embodiments of the present disclosure, a charge enhancement oxide layer can also be designed to reduce the contact area of ​​the Schottky contact, prevent the problem of Fermi-level pinning at a specific position (Fermi-level Pinning), and improve the performance of the semiconductor device.

[0005] According to some embodiments of the present disclosure, a semiconductor device includes a semiconductor layer, a gate structure, a control source electrode plate, and a drain electrode. The semiconductor layer has a channel region. The gate structure has a surface to contact the semiconductor layer, wherein the gate structure overlaps the channel region of the semiconductor layer along a direction perpendicular to the surface of the gate structure. The control source electrode plate contacts the semiconductor layer, wherein the control source electrode plate covers the gate structure and the channel region of the semiconductor layer along the direction perpendicular to the surface of the gate structure. The drain electrode contacts the semiconductor layer.

[0006] In all embodiments, the drain electrode does not overlap the gate structure along this direction.

[0007] In some embodiments, one of the source electrode plate and the drain electrode is controlled to form a Schottky contact with the semiconductor layer, and the other of the source electrode plate and the drain electrode is controlled to form an ohmic contact with the semiconductor layer.

[0008] In some embodiments, the semiconductor layer includes: a first semiconductor region and a second semiconductor region. The first semiconductor region is adjacent to the control source electrode plate, and the second semiconductor region is adjacent to the drain electrode, wherein the first semiconductor region and the second semiconductor region are of the same conductivity type.

[0009] In some embodiments, the semiconductor layer includes: a first semiconductor region and a second semiconductor region. The first semiconductor region is adjacent to the control source electrode plate, and the second semiconductor region is adjacent to the drain electrode, wherein the first semiconductor region and the second semiconductor region are of opposite conductivity types.

[0010] In some embodiments, the semiconductor layer includes a first semiconductor region, a second semiconductor region, a semiconductor pocket layer, and a semiconductor protective pad layer. The first semiconductor region is located between the control source electrode plate and the gate structure. The second semiconductor region is adjacent to the drain electrode. The semiconductor pocket layer is at least located between the first semiconductor region and the gate structure. The semiconductor protective pad layer is at least located between the first semiconductor region and the control source electrode plate, wherein the first semiconductor region, the second semiconductor region, the semiconductor pocket layer, and the semiconductor protective pad layer include different components.

[0011] In some embodiments, the semiconductor layer has a first region and a second region. The first region is located between the gate structure and the control source electrode plate, and the second region is adjacent to the drain electrode and is not located between the gate structure and the control source electrode plate, wherein the thickness of the second region is smaller than that of the first region.

[0012] In some implementations, the source electrode plate is controlled to completely overlap the gate structure along the direction.

[0013] In some implementations, the control source electrode plate further extends beyond a side wall of the gate structure.

[0014] In some embodiments, the semiconductor device further includes a charge enhancement oxide layer. The charge enhancement oxide layer is located between the control source electrode plate and the semiconductor layer, wherein the control source electrode plate includes a first control source and a second control source, the first control source of the control source electrode plate contacts the charge enhancement oxide layer, the second control source of the control source electrode plate does not contact the charge enhancement oxide layer, and the first control source and the second control source are separated. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The various aspects of the present disclosure can be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that the various features are not drawn to scale. In fact, the size of the various features can be arbitrarily increased or reduced.

[0016] Figure 1A is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0017] Figure 1B for Figure 1A A schematic diagram of the operation of a semiconductor device;

[0018] Figure 1C for Figure 1A A three-dimensional schematic diagram of an embodiment of a semiconductor device;

[0019] Figure 1D is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0020] Figure 1E Based on Figure 1D A three-dimensional schematic diagram of an embodiment of a semiconductor device;

[0021] Figure 1F Based on Figure 1D A three-dimensional schematic diagram of an embodiment of a semiconductor device;

[0022] Figure 2 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0023] Figure 3 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0024] Figure 4 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0025] Figure 5 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0026] Figure 6 is a schematic diagram of a semiconductor device according to some embodiments of the present disclosure;

[0027] Figure 7 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0028] FIG. 8A to FIG. 8H are cross-sectional views of various stages of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0029] Fig. 9 FIG. 4 is a graph showing the relationship between gate voltage and drain current of a semiconductor device according to some embodiments of the present disclosure.

[0030]

Explanation of symbols

[0031] 100,DA1,DA2,DB:Semiconductor device

[0032] 110: Semiconductor layer

[0033] 110A, 110B, 110C, 110D: Surface

[0034] 111,112,113,114: Area

[0035] 120: Gate structure

[0036] 122: Gate dielectric layer

[0037] 124: Gate electrode

[0038] 130: Control source electrode plate

[0039] 130A: first control source

[0040] 130B: Second control source

[0041] 140: Drain electrode

[0042] 150,150A,150B: Control gate structure

[0043] 152, 152A, 152B: control gate dielectric layer

[0044] 154,154A,154B: Control gate electrode

[0045] 162,164: Charge Enhanced Oxide Layer

[0046] IVR: Area

[0047] t d ,,t body :thickness

[0048] d bp :distance

[0049] X,Y: Direction

[0050] SUB:Substrate

[0051] LT: Arrow

[0052] SP: Prominent Structure

[0053] DL1, DL1', DL2: dielectric layer

[0054] PM1,PM2,PM3: Etching mask

[0055] ET1,ET2,ET3: Etching process

[0056] CPG: Gate Contact

[0057] CPD: Contact Drain

[0058] CPS: Source Contact DETAILED DESCRIPTION

[0059] Figure 1A Schematic diagram of a semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 includes a semiconductor layer 110 , a gate structure 120 , a control source electrode plate 130 , and a drain electrode 140 .

[0060] The semiconductor layer 110 has a channel region and may include all appropriate semiconductor materials, such as silicon, germanium, silicon germanium, oxide semiconductors, III-V, II-VI, two-dimensional semiconductor materials or combinations thereof. The semiconductor layer 110 is a first-type semiconductor as a whole. The semiconductor layer 110 may be a bulk semiconductor, such as a silicon body, a silicon germanium body, etc. In some embodiments, the semiconductor layer 110 may be a p-type bulk semiconductor as a whole, which may be directly purchased from a desired doped wafer or may be formed into a p-type semiconductor through doping technology. Alternatively, the semiconductor layer 110 may be a p-type bulk semiconductor that is doped into an n-type semiconductor through n-type doping. In some embodiments, only one doping is required for the body of the semiconductor layer 110, which may reduce process steps, reduce the number of times the mask is used, avoid the problem of misalignment, and reduce process costs. In addition, the semiconductor layer 110 has a first surface (i.e., surface 110A) and a second surface (i.e., surface 110B) relative to each other, which may contact the gate structure 120 and the control source electrode plate 130, respectively.

[0061] The gate structure 120 includes a gate dielectric layer 122 and a gate electrode 124. The gate dielectric layer 122 may include any suitable dielectric material, such as silicon oxide or a high-k dielectric material (such as hafnium dioxide). The gate electrode 124 may include any suitable conductive material, such as doped polysilicon or metal.

[0062] In the present embodiment, the gate structure 120 and the control source electrode plate 130 are respectively disposed on the opposite surfaces 110A and 110B of the semiconductor layer 110 along the direction Y. The gate structure 120 has a surface to contact the semiconductor layer 110, wherein the gate structure 120 overlaps the channel region of the semiconductor layer 110 along a direction perpendicular to the surface of the gate structure 120. The control source electrode plate 130 contacts the semiconductor layer 110, wherein the control source electrode plate 130 covers the gate structure 120 and the channel region of the semiconductor layer along a direction perpendicular to the surface of the gate structure 120. For the convenience of description, the direction parallel to the contact surface of the gate structure 120 and the semiconductor layer 110 (i.e., the surface 110A) is defined as the direction X, and the direction perpendicular to the contact surface of the gate structure 120 and the semiconductor layer 110 (i.e., the surface 110A) is defined as the direction Y. The direction Y can also be regarded as the direction of the electric field provided by the gate structure 120. In another embodiment, the gate electrode 124 and the control source electrode plate 130 can have different metal materials.

[0063] In some embodiments, the control source electrode plate 130 is separated from the gate structure 120 along the direction Y, and the control source electrode plate 130 covers the gate structure 120 along the direction Y. The control source electrode plate 130 and the gate structure 120 may partially or completely overlap along the direction Y. The edge of the gate electrode 124 may be completely aligned or slightly misaligned with the edge of the control source electrode plate 130. The control source electrode plate 130 may be applied with a ground voltage or any voltage without being limited to ground.

[0064] The drain electrode 140 may be disposed on a portion of the semiconductor layer 110 away from the control source electrode plate 130, and the drain electrode 140 may not overlap the gate structure 120 along this direction. In this embodiment, the drain electrode 140 contacts the surface 110B of the semiconductor layer 110, but the present invention is not limited thereto. The drain electrode 140 may contact all or one or two of the surface 110A, the surface 110B, and the side surface 110C of the semiconductor layer 110.

[0065] In some embodiments, by designing the work function of the metal material and / or the concentration distribution of the semiconductor layer 110 , one of the source electrode plate 130 and the drain electrode 140 can be controlled to form an Ohmic contact with the semiconductor layer 110 and the other to form a Schottky contact with the semiconductor layer 110 .

[0066] In some embodiments, the control source electrode plate 130 and the drain electrode 140 include the same metal material, and the ohmic contact and Schottky contact are achieved by designing the doping concentration of the region of the semiconductor layer 110 adjacent to the control source electrode plate 130 and the region adjacent to the drain electrode 140 to be different. For example, the doping concentration of the region of the semiconductor layer 110 adjacent to the ohmic contact is greater than the doping concentration of the region of the semiconductor layer 110 adjacent to the Schottky contact. In another embodiment, the doping concentration of the region of the semiconductor layer 110 adjacent to the control source electrode plate 130 and the region of the semiconductor layer 110 adjacent to the drain electrode 140 are similar, and the ohmic contact and Schottky contact are achieved by designing the control source electrode plate 130 and the drain electrode 140 to include different metal materials. For example, when the semiconductor layer 110 is a p-type semiconductor, the metal material used to form an ohmic contact electrode may be Ni, Ir, a similar metal or a combination thereof, and the metal material used to form a Schottky contact electrode may be Zr, Mn, Ta, Ti, Sn, Sb, Ru, Os, a similar metal or a combination thereof.

[0067] Accordingly, in the present embodiment, a p-type block is used as the semiconductor layer 110. When the p-type block is used as the p-type semiconductor layer 110, the source is designed to be an ohmic contact and the drain is designed to be a Schottky contact, and an n-type iTFET can be formed. When the p-type block is used as the p-type semiconductor layer 110, the drain is designed to be an ohmic contact and the source is designed to be a Schottky contact, and a p-type iTFET can be formed. When the p-type block is n-doped as the n-type semiconductor layer 110, the source is designed to be an ohmic contact and the drain is designed to be a Schottky contact, and a p-type iTFET can be formed. Conversely, when the p-type block is n-doped as the n-type semiconductor layer 110, the drain is designed to be an ohmic contact and the source is designed to be a Schottky contact, and an n-type iTFET can be formed. Thereby, the process complexity and cost of the semiconductor device can be significantly reduced.

[0068] The Schottky contact between the drain electrode 140 (or the control source electrode plate 130) and the semiconductor layer 110 forms an impurity-sensitive region in the semiconductor layer 110, for example, an n-type impurity-sensitive region is formed in the p-type semiconductor layer 110. The impurity-sensitive region may be referred to as a drain-sensitive region. The formation of the impurity-sensitive region does not require any ion implantation process steps, which can greatly reduce the steps and thermal costs required for the process, such as a thermal annealing process.

[0069] Figure 1B for Figure 1A Schematic diagram of the operation of a semiconductor device of a semiconductor device. When a gate voltage (V G ), the region IVR below the p-type semiconductor layer 110 will be inverted to form an n-type channel. By setting the control source electrode plate 130 to cover the gate structure 120 along the Y direction, the n-type inversion conduction region IVR generated by the p-type semiconductor layer 110 of the semiconductor device 100 of the disclosed embodiment can overlap with the control source electrode plate 130 in a large range along the direction Y, thereby generating line tunneling when conducting, as indicated by the arrow LT.

[0070] like Figure 1BAs shown, the semiconductor device 100 may be provided with one or more control gate structures 150 in the drain region according to functional requirements. The control gate structure 150 may reduce the electric field of the drain electrode 140 and reduce the am-bipolar effect of the semiconductor device 100, so as to reduce the leakage current of the semiconductor device 100. In addition, the control gate structure 150 may be formed simultaneously with the gate structure 120 by the same process, or may be formed at different times by different processes. The control gate structure 150 may be provided on the same surface 110A as the gate structure 120 or on a different surface 110B. The control gate structure 150 includes a control gate electrode 154 and a control gate dielectric layer 152. The control gate electrode 154 may overlap and align with or not align with the drain electrode 140, and may be provided on both sides of the semiconductor block at the same time or at different times. The control gate dielectric layer 152 may include any appropriate dielectric material, such as silicon oxide or high-k dielectric material. The control gate electrode 154 may include any appropriate conductive material, such as doped polysilicon or metal.

[0071] The semiconductor device 100 can be of any type, including horizontal, vertical, three-dimensional (eg, fin-type), etc. This design can simplify the process, improve performance, and reduce costs. For example, in one embodiment, Figure 1A It can be a cross-sectional view of a planar induced-Tunneling Field Effect Transistor (iTFET). In another embodiment, Figure 1A It can be a top view of the fin-type iTFET. Figure 1C Can Figure 1A Schematic diagram of a semiconductor device of the present invention. In the present embodiment, the semiconductor device 100 may be manufactured by the following process. For example, a dielectric layer may be deposited on the fins of the semiconductor layer 110, and then the dielectric layer may be patterned to form a gate dielectric layer 122 and a control gate dielectric layer 152. Next, a metal layer may be deposited on the gate dielectric layer 122, the control gate dielectric layer 152 and the fins of the semiconductor layer 110, and then the metal layer may be patterned to form a gate electrode 124, a control gate electrode 154, a control source electrode plate 130 and a drain electrode 140. Therefore, in some embodiments, the gate dielectric layer 122 and the control gate dielectric layer 152 may include the same dielectric material, and one or more of the gate electrode 124, the control gate electrode 154, the control source electrode plate 130 and the drain electrode 140 may include the same metal material. In some other embodiments, the gate dielectric layer 122 and the control gate dielectric layer 152 may include different dielectric materials, and one or more of the gate electrode 124 , the control gate electrode 154 , the control source electrode plate 130 , and the drain electrode 140 may include different metal materials.

[0072] Figure 1DSchematic diagram of a semiconductor device 100 according to some embodiments of the present disclosure. In some embodiments, the semiconductor layer 110 may include regions 111, 112, 113, and 114, wherein the regions 111, 112, 113, and 114 may be a combination of multiple semiconductor materials or components. In some embodiments, the regions 111, 112, 113, and 114 are the same material or component, which may be a doped semiconductor material or an intrinsic semiconductor material. In some embodiments, any two of the regions 111, 112, 113, and 114 are the same material or component (e.g., a doped semiconductor material or an intrinsic semiconductor material), and are different from the materials or components of the other two of the regions 111, 112, 113, and 114 (e.g., a doped semiconductor material or an intrinsic semiconductor material). In some embodiments, any three of the regions 111, 112, 113, and 114 are of the same material or component (e.g., doped semiconductor material or intrinsic semiconductor material), and are different from the material or component (e.g., doped semiconductor material or intrinsic semiconductor material) of the other one of the regions 111, 112, 113, and 114. In some embodiments, the regions 111, 112, 113, and 114 include different materials or components (e.g., doped semiconductor material or intrinsic semiconductor material).

[0073] For example, in some embodiments, the semiconductor layer 110 may include a first semiconductor doping region and a second semiconductor doping region. The first semiconductor doping region (i.e., region 111) is located between the control source electrode plate 130 and the gate structure 120. The second semiconductor doping region (i.e., region 112) is adjacent to the drain electrode 140, wherein the first semiconductor doping region and the second semiconductor doping region are of the same conductivity type. In another embodiment, the first semiconductor doping region and the second semiconductor doping region are of opposite conductivity types.

[0074] For example, in some embodiments, the semiconductor layer 110 may include a first semiconductor doping region, a second semiconductor doping region, a semiconductor pocket layer, and a semiconductor cushion layer. The first semiconductor doping region (i.e., region 111) is adjacent to the control source electrode plate 130. The second semiconductor doping region (i.e., region 112) is adjacent to the drain electrode 140. The semiconductor pocket layer (i.e., region 113) is at least located between the first semiconductor doping region 111 and the gate structure 120. The semiconductor cushion layer (i.e., region 114) is at least located between the first semiconductor doping region 111 and the control source electrode plate 130.

[0075] For example, in some embodiments, the semiconductor layer 110 may have a first region (i.e., region 111) located between the gate structure 120 and the control source electrode plate 130. The semiconductor layer 110 may have a second region (i.e., region 112) adjacent to the drain electrode 140 and not located between the gate structure 120 and the control source electrode plate 130, wherein the thickness of the second region may be less than the thickness of the first region.

[0076] Furthermore, in this embodiment, region 111 and region 112 may be composed of semiconductor materials with different energy gaps. For example, region 111 may be composed of a semiconductor material with a narrow energy gap, and region 112 may be composed of a semiconductor material with a wide energy gap. Pocket layers and pad layers (i.e., region 113 and region 114) may be formed by different doping / epitaxial methods. This design may facilitate the formation of source and drain desmodiolar contacts and ohmic contacts. It may also further reduce the electric field of the drain electrode 140 and reduce the tunneling probability of point-tunneling (PT), thereby further reducing the leakage current.

[0077] In this embodiment, the control source electrode plate 130 is disposed on the side surface 110D and the surface 110B of the semiconductor layer 110, wherein the control source electrode plate 130 completely overlaps the gate electrode 124 along this direction, and the control source electrode plate 130 contacts the side surface 110D of the semiconductor layer 110. In some other embodiments, the control source electrode plate 130 may contact all or one of the side surface 110D and the surface 110B of the semiconductor layer 110. In some other embodiments, the control source electrode plate 130 further extends beyond the side wall of the gate structure 120.

[0078] In this embodiment, the drain electrode 140 is disposed on the surface 110A, the surface 110B, and the side surface 110C of the semiconductor layer 110, and the drain electrode 140 contacts the surface 110A of the semiconductor layer 110. In some other embodiments, the drain electrode 140 may contact all or one or two of the surface 110A, the surface 110B, and the side surface 110C of the semiconductor layer 110.

[0079] and Figure 1B and Figure 1C Similarly, in this embodiment, Figure 1D The semiconductor device 100 is provided with a control gate structure 150A and a control gate structure 150B. This design can reduce the electric field of the drain electrode 140 and reduce the am-bipolar effect of the semiconductor device 100, thereby reducing the leakage current of the semiconductor device 100.

[0080] In addition, the semiconductor device 100 can set a charge enhancement oxide layer 162 and / or 164 on any contact surface between the control source electrode plate 130 and / or the drain electrode 140 and the semiconductor layer 110 according to functional requirements. The charge enhancement oxide layer 162 and the charge enhancement oxide layer 164 can be a low-k and / or high-k dielectric material, such as Si3N4 or a suitable oxide. The charge enhancement oxide layers 162 and 164 can be formed by various deposition (such as evaporation or sputtering) techniques. Thereby. The charge enhancement oxide layers 162 and 164 can reduce the contact area between the control source electrode plate 130 and the drain electrode 140 and the semiconductor layer 110, and enhance the charge concentration of the source and drain. This design can improve the Ion of the semiconductor device 100, and also improve and alleviate the problem of Fermi-level pinning, thereby improving the performance of the semiconductor device 100.

[0081] and Figure 1A and Figure 1C Similarly, in this embodiment, Figure 1D The semiconductor device 100 may be of any type, including horizontal, vertical, three-dimensional (e.g., fin-type), etc. This design can simplify the process, improve performance, and reduce costs. For example, in one embodiment, Figure 1D It can be a cross-sectional view of a planar induced-Tunneling Field Effect Transistor (iTFET). In another embodiment, Figure 1D It can be a top view of the fin-type iTFET. Figure 1E Can Figure 1D A three-dimensional schematic diagram of a semiconductor device. Figure 1C The embodiment of the present invention is similar to that of the present invention, except that the semiconductor layer 110 forms regions 111 to 114 through different doping / epitaxial methods according to functional requirements. Next, a dielectric layer may be deposited on the fins of the semiconductor layer 110, and then the dielectric layer may be patterned to form a gate dielectric layer 122, a control gate dielectric layer 152A, a control gate dielectric layer 152B, a charge enhancement oxide layer 162, and a charge enhancement oxide layer 164. Then, a metal layer is deposited thereon, and then the metal layer is patterned to form a gate electrode 124, a control gate electrode 154A, a control gate electrode 154B, a control source electrode plate 130, and a drain electrode 140.

[0082] In another embodiment, Figure 1F Can Figure 1D A three-dimensional schematic diagram of a semiconductor device. Figure 1EThe embodiment of the present invention is similar to that of the present invention, except that: after forming the semiconductor layer 110, a dielectric layer may be deposited on the surfaces 110A and 110B of the semiconductor layer 110. Then, a metal layer may be deposited on the dielectric layer. The metal layer is then patterned to form the gate structure 120, the control gate structure 150A and the control gate structure 150B, the control source electrode plate 130 and the drain electrode 140. The control source electrode plate 130 includes a first control source 130A and a second control source 130B. In this embodiment, the first control source 130A and the second control source 130B may be separated. The first control source 130A is located on the surface 110B of the semiconductor layer 110 and contacts the charge enhancement oxide layer 162, wherein the charge enhancement oxide layer 162 is located between the first control source 130A and the semiconductor layer 110. The second control source 130B is located on the surface 110D of the semiconductor layer 110 and does not contact the charge enhancement oxide layer 162. The first control source 130A may be a control source electrode plate, and a ground voltage or any voltage may be applied without limitation to grounding. The second control source 130B may be a control source electrode plate, and a ground voltage or any voltage may be applied. In this embodiment, the surface 110D of the semiconductor layer 110 may not be aligned with the first control source 130A and the gate structure 120. In another embodiment, the surface 110D of the semiconductor layer 110 is aligned with the first control source 130A and the gate structure 120. In addition, in some embodiments, the first control source 130A and the second control source 130B may be connected together or not connected together and used as a source according to functional requirements.

[0083] Figure 2 Schematic diagram of a semiconductor device according to some embodiments of the present disclosure. As described above, the semiconductor device may include a charge-enhanced oxide layer 162 and / or 164, both of which may be adjusted to different positions, lengths or segments according to device requirements. In this embodiment, the charge-enhanced oxide layer 162 exposes the lower surface 110B of the semiconductor layer 110 so that the control source electrode plate 130 contacts the lower surface 110B of the semiconductor layer 110. In this embodiment, the charge-enhanced oxide layer 164 exposes the side surface 110C of the semiconductor layer 110 so that the drain electrode 140 contacts the side surface 110C of the semiconductor layer 110.

[0084] Figure 3Schematic diagram of a semiconductor device according to some embodiments of the present disclosure. As described above, the semiconductor device may include a control gate electrode 154, which may overlap with the drain electrode 140, be aligned or not aligned with the edge of the drain electrode 140, and be disposed on the same side or opposite sides of the semiconductor layer 110 as the drain electrode 140. In some embodiments, the drain electrode 140 may be exchanged with the control gate structure 150, for example, the drain electrode 140 is located on the lower surface 110B of the semiconductor layer 110, and the control gate structure 150 is located on the upper surface 110A of the semiconductor layer 110.

[0085] Figure 4 FIG. 1 is a cross-sectional view of a semiconductor device 100 according to some embodiments of the present disclosure. Figure 1B The difference is that the upper portion of the semiconductor layer 110 in this embodiment is retracted by a distance d bp , and the thickness of the semiconductor layer 110 is t body Greater than thickness t d .exist Figure 4 In the embodiment, the semiconductor layer 110 adjacent to the drain electrode 140 and not located between the control source electrode plate 130 and the drain electrode 140 can be thinned by retreating the upper portion or the lower portion of the semiconductor layer 110. d The size of the drain electrode can adjust the electric field, thereby reducing the probability of lateral point-tunneling (PT), thereby further reducing the leakage current.

[0086] Figure 5 Schematic diagram of a semiconductor device 100 according to some embodiments of the present disclosure. In this embodiment, the semiconductor layer 110 includes a region 111, a region 113, and a region 114. The region 113 can be formed in the region 111 by ion implantation, diffusion, or other methods of changing doping. The region 113 with the same energy gap or different energy gaps, different doping, or intrinsic semiconductor can also be formed outside the region 111 by growing an epitaxial layer, evaporation, sputtering, or other methods of growing a semiconductor layer outward. Furthermore, the region 114 can be formed in the region 111 by ion implantation, diffusion, or other methods of changing doping inward. The region 114 with the same energy gap or different energy gaps, different doping, or intrinsic semiconductor can also be formed outside the region 111 by growing an epitaxial layer, evaporation, sputtering, or other methods of growing a semiconductor layer outward.

[0087] The length and shape of the region 113 and the region 114 can be changed according to functional requirements. For example, in this embodiment, the region 113 and the region 114 can cover the entire conductor layer. This design can assist in the formation and improvement of the Schottky junction and suppress the generation of leakage current. In other embodiments, the region 113 and the region 114 are only aligned with the overlapping area of ​​the gate structure 120 and the control source electrode plate 130. This design can help the rapid proliferation of carriers in the inversion layer and improve the Ion current driving force.

[0088] Figure 6 Schematic diagram of a semiconductor device according to some embodiments of the present disclosure. Figure 5 The embodiment of the present invention is similar to that of the embodiment of the present invention, except that: in the present embodiment, the semiconductor layer 110 further includes a region 112, and the region 112 can form a heterojunction with the region 111. The region 111 and the region 112 forming the heterojunction can be formed by doping or epitaxy at the same time or at different times, using the same or different semiconductor materials, and using the same or different techniques.

[0089] Figure 7 1 is a cross-sectional view of a semiconductor device 100 according to some embodiments of the present disclosure. In this embodiment, the semiconductor substrate SUB can be patterned to form a protruding structure SP. On the semiconductor substrate SUB, a gate electrode 124, a gate dielectric layer 122, a semiconductor layer 110 (including as a region 111 and a region 114) and a charge enhancement oxide layer 162 are sequentially deposited. Among them, the region 114 and the charge enhancement oxide layer 162 can be patterned to expose the region 111. The control source electrode plate 130 can be formed by depositing a metal material and etching or flattening to define the shape of the metal material. Similarly, the drain electrode 140 can be formed by depositing a metal material and etching or flattening to define the shape of the metal material.

[0090] FIG. 8A to FIG. 8H The diagrams are cross-sectional views of various stages of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0091] exist Fig. 8A In the embodiment, the semiconductor substrate SUB is patterned by an etching process ET1 using an etching mask PM1 to form a protruding semiconductor region 111. In some embodiments, the semiconductor substrate SUB and the semiconductor region 111 are made of silicon.

[0092] exist Figure 8B In the embodiment, a semiconductor region 113 is deposited on one side of the semiconductor region 111. In some embodiments, the semiconductor region 113 is composed of silicon germanium. After the deposition step, a chemical polishing process may be selectively performed to make the upper surface of the semiconductor region 113 flush with the upper surface of the semiconductor region 111.

[0093] exist Figure 8C In the embodiment, the semiconductor region 113 is patterned by an etching process ET2 using an etching mask PM2.

[0094] exist Fig.8D In the process, a gate dielectric layer 122 is deposited, and the gate dielectric layer 122 and the semiconductor region 111 are patterned by an etching process ET3 using an etching mask PM3.

[0095] exist Fig. 8E In the process, a metal layer is deposited on the gate dielectric layer 122, and then a dielectric layer DL1 is deposited. Then, a chemical polishing process is performed to remove the upper portion of the metal layer, so that the lower portion of the metal layer forms the gate electrode 124 and the control source electrode plate 130 respectively.

[0096] exist Fig.8F In the embodiment, the semiconductor region 112 is selectively epitaxially grown on the semiconductor region 111 and the semiconductor region 113 .

[0097] exist Figure 8G In the process, a dielectric layer is deposited and etched to expose the semiconductor region 112. After etching, the dielectric layer and the dielectric layer DL1 (refer to Fig.8F ) are collectively referred to as dielectric layer DL1'.

[0098] exist Figure 8H In the embodiment of the present invention, a drain electrode 140 is deposited to contact the exposed semiconductor region 112. Next, a dielectric layer DL2 is deposited and a plurality of contact openings are etched therein. Then, a metal material is deposited in the contact openings and a chemical polishing process is performed to form a gate contact CPG, a drain contact CPD and a source contact CPS, which are electrically connected to the gate electrode 124, the drain electrode 140 and the control source electrode plate 130, respectively.

[0099] Fig. 9 1 is a diagram showing the relationship between gate voltage and drain current of a semiconductor device 100 (e.g., FIG. 1 ) according to some embodiments of the present disclosure. In each embodiment of the present disclosure, the semiconductor device 100 may use a homogeneous or heterogeneous structure as the semiconductor layer 110. For example, the semiconductor device DA1 uses a homogeneous structure Ge as the semiconductor layer 110, the semiconductor device DA2 uses a homogeneous structure GaAs as the semiconductor layer 110, and the semiconductor device DB uses a heterogeneous structure Ge / GaAs as the semiconductor layer 110. Fig. 9 As shown, the heterostructured semiconductor device DB can reduce Ioff to 2.63x 10 while maintaining a high on-state current, compared with the homostructured semiconductor devices DA1 and DA2. -14A / um, and suppress the bipolar effect current. The design of this heterostructure can further highlight the efficacy of the above description.

[0100] The purpose of the present disclosure is to provide a semiconductor device that can overcome all the problems encountered by traditional PIN TFETs, and can also solve the problems faced by various previous wire tunneling structures, such as complex and difficult processes, large area, too small area that can produce wire tunneling, and low wire tunneling probability. In some embodiments of the present disclosure, by making the control source electrode plate overlap with the gate structure along the gate electric field direction, the area and occurrence probability of the linear tunneling effect are increased, thereby increasing Ion and reducing the sub-threshold swing. In some embodiments of the present disclosure, it is also possible to design a control source electrode plate and a drain electrode so that one of them is a Schottky contact and the other is an ohmic contact. The setting of the Schottky contact will form an impurity sensing area in the semiconductor layer to omit the ion implantation step, thereby simplifying the process and reducing the process cost. In some embodiments of the present disclosure, a charge enhancement oxide layer can also be designed to reduce the contact area of ​​the Schottky contact, prevent the problem of Fermi-level pinning at a specific position (Fermi-level Pinning), and improve the performance of the semiconductor device.

[0101] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor layer having a channel region; a gate structure having a surface for contacting the semiconductor layer, wherein the gate structure overlaps the channel region of the semiconductor layer along a direction perpendicular to the surface of the gate structure; a control source electrode plate contacting the semiconductor layer, wherein the control source electrode plate covers the gate structure and the channel region of the semiconductor layer along the direction perpendicular to the surface of the gate structure; and A drain electrode contacts the semiconductor layer.

2. The semiconductor device according to claim 1, wherein The drain electrode does not overlap the gate structure along the direction.

3. The semiconductor device according to claim 1, wherein: One of the control source electrode plate and the drain electrode forms a Schottky contact with the semiconductor layer, and the other of the control source electrode plate and the drain electrode forms an ohmic contact with the semiconductor layer.

4. The semiconductor device according to claim 1, wherein: The semiconductor layer comprises: a first semiconductor region adjacent to the control source electrode plate; and A second semiconductor region is adjacent to the drain electrode, wherein the first semiconductor region and the second semiconductor region are of the same conductivity type.

5. The semiconductor device according to claim 1, wherein The semiconductor layer comprises: a first semiconductor region adjacent to the control source electrode plate; and A second semiconductor region is adjacent to the drain electrode, wherein the first semiconductor region and the second semiconductor region are of opposite conductivity types.

6. The semiconductor device according to claim 1, wherein: The semiconductor layer comprises: A first semiconductor region located between the control source electrode plate and the gate structure; a second semiconductor region adjacent to the drain electrode; A semiconductor pocket layer, at least located between the first semiconductor region and the gate structure; as well as A semiconductor pad layer is at least located between the first semiconductor region and the control source electrode plate, wherein the first semiconductor region, the second semiconductor region, the semiconductor pocket layer and the semiconductor pad layer contain different components.

7. The semiconductor device according to claim 1, wherein The semiconductor layer has a first region located between the gate structure and the control source electrode plate and a second region adjacent to the drain electrode and not located between the gate structure and the control source electrode plate, wherein the thickness of the second region is less than the thickness of the first region.

8. The semiconductor device according to claim 1, wherein The control source electrode plate completely overlaps the gate structure along the direction.

9. The semiconductor device according to claim 1, wherein: The control source electrode plate further extends beyond a side wall of the gate structure.

10. The semiconductor device according to claim 1, wherein Also includes: A charge enhancement oxide layer is located between the control source electrode plate and the semiconductor layer, wherein the control source electrode plate includes a first control source and a second control source, the first control source of the control source electrode plate contacts the charge enhancement oxide layer, the second control source of the control source electrode plate does not contact the charge enhancement oxide layer, and the first control source and the second control source are separated.

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