Laterally diffused metal oxide semiconductor device and preparation method thereof
By forming a decreasing thickness injection masking structure on the substrate of the LDMOS device, a gradient drift region is formed, which solves the problems of fast depletion of the drift region and electric field enhancement, and improves the reliability of the device and the open-state breakdown voltage.
Patent Information
- Application Number
- CN202310950872.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-28
- Publication Date
- 2025-02-14
AI Technical Summary
In existing LDMOS devices, the low concentration of the drift zone leads to faster depletion, the Kirk effect is enhanced, and the open-state breakdown voltage is reduced; the high concentration of the drift zone leads to slow depletion, and the electric field is enhanced, reducing device reliability.
By forming an injection masking structure with a decrease in thickness from the body region to the edge of the substrate on the substrate, a drift region with gradients of depth and concentration is formed.
Reduce the electric field near one end of the drift region to improve device reliability; reduce the Kirk effect and increase the open-state breakdown voltage.
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Figure CN119451184A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and in particular to a laterally diffused metal oxide semiconductor device and a method for preparing the same. Background Art
[0002] Lateral Double-Diffused MOSFET (LDMOS) in power devices has the advantages of fast switching speed, high output power, high linear gain, and good durability. At the same time, LDMOS devices are based on mature silicon processes, which makes their production costs low. Therefore, LDMOS devices gradually replace silicon bipolar power devices and are widely used in power management, display drive, automotive electronics and other fields. In current LDMOS devices, the low concentration of the drift region leads to fast depletion of the drift region, enhanced Kirk effect of the device, and reduced on-state breakdown voltage. The high concentration of the drift region leads to slow depletion of the end of the drift region close to the channel region, enhanced electric field, and reduced device reliability. How to balance the on-state breakdown voltage and device reliability has become an urgent problem to be solved. Summary of the invention
[0003] Based on this, it is necessary to provide a laterally diffused metal oxide semiconductor device and a method for preparing the same in order to address at least one of the above problems.
[0004] In order to achieve at least one of the above purposes, in a first aspect, an embodiment of the present application provides a method for preparing a laterally diffused metal oxide semiconductor device, the method comprising:
[0005] providing a substrate;
[0006] forming a body region in the substrate;
[0007] An injection masking structure is formed on the substrate, wherein the injection masking structure covers a portion of the surface of the substrate; wherein the body region is located within the orthographic projection of the injection masking structure on the substrate; and the thickness of the injection masking structure decreases along a first direction from the body region to the edge of the substrate; and the first direction is parallel to the thickness direction of the substrate;
[0008] A drift region is formed in the substrate; the drift region is adjacent to the body region, and the depth of the drift region increases gradually along the first direction from the body region to the edge of the substrate.
[0009] The method for preparing a laterally diffused metal oxide semiconductor device provided in an embodiment of the present application forms an injection masking structure on a substrate with a decreasing thickness from a body region to an edge of the substrate. In this way, when ion implantation is performed, a drift region with a gradual depth change and a gradual concentration change can be formed in the substrate. On the one hand, it is beneficial to reduce the electric field at one end of the drift region close to the channel region, thereby improving the reliability of the device; on the other hand, it is beneficial to reduce the Kirk effect and improve the on-state breakdown voltage.
[0010] In one embodiment, the step of forming an implantation masking structure on the substrate, wherein the implantation masking structure covers a portion of the surface of the substrate, comprises:
[0011] A barrier layer is formed on the substrate; the barrier layer comprises a first portion and a second portion connected to each other, the body region is located within an orthographic projection of the first portion on the substrate, and is located outside an orthographic projection of the second portion on the substrate;
[0012] forming a first photoresist layer on the barrier layer, wherein the first photoresist layer covers a surface of the first portion;
[0013] The barrier layer and the first photoresist layer are etched to form the implantation masking structure.
[0014] In one embodiment, the step of etching the barrier layer and the first photoresist layer to form the implantation masking structure includes:
[0015] Etching the barrier layer so that the thickness of the second portion along the first direction is smaller than the thickness of the first portion along the first direction;
[0016] The first photoresist layer is etched to form a second photoresist layer; the second photoresist layer covers a portion of the surface of the first portion; and the exposed surface of the first portion is adjacent to the second portion.
[0017] In one embodiment, the ratio of the thickness of the second portion to the thickness of the first portion is between 0.3 and 0.7;
[0018] And / or, the material of the barrier layer includes at least one of nitride and oxide.
[0019] In one embodiment, doping ions are implanted once into the substrate with the same implantation energy to form the drift region.
[0020] In one embodiment, the method for preparing the laterally diffused metal oxide semiconductor device further comprises:
[0021] A first doped region is formed in the substrate; the first doped region is located at the bottom of the drift region and is adjacent to the drift region.
[0022] In one embodiment, the method for preparing the laterally diffused metal oxide semiconductor device further comprises:
[0023] forming a gate on the substrate, wherein the gate covers surfaces of the body region and the drift region;
[0024] A source lead-out region, a drain lead-out region and a body lead-out region are formed in the substrate, the drain lead-out region is located in the drift region, and the source lead-out region and the body lead-out region are located in the body region.
[0025] In a second aspect, an embodiment of the present application provides a laterally diffused metal oxide semiconductor device, the laterally diffused metal oxide semiconductor device comprising:
[0026] substrate;
[0027] a body region disposed in the substrate;
[0028] A drift region is arranged in the substrate and is adjacent to the body region; from the body region to the edge of the substrate, the depth of the drift region increases along a first direction, and the concentration of the drift region increases; the first direction is parallel to the thickness direction of the substrate.
[0029] In one embodiment, the drift region includes a plurality of sub-drift regions connected in sequence; each of the sub-drift regions extends from the surface of the substrate to the interior of the substrate;
[0030] From the body region to the edge of the substrate, the depths of the plurality of sub-drift regions gradually increase in the first direction, so that the drift regions are arranged in steps.
[0031] In one of the embodiments, the LDMOS device further comprises a first doped region, wherein the first doped region is located at the bottom of the drift region and is adjacent to the drift region;
[0032] Among them, the first doping region includes multiple sub-doping regions, each of which is arranged at the bottom of a sub-drift region; in two adjacent sub-drift regions, the sum of the depths of the sub-drift region close to the body region and the sub-doping region corresponding to the sub-drift region along the first direction is not less than the depth of the sub-drift region away from the body region along the first direction.
[0033] The laterally diffused metal oxide semiconductor device provided in the embodiment of the present application forms a drift region in the substrate with increasing concentration and depth from the body region to the edge of the substrate. On the one hand, it is beneficial to reduce the electric field at one end of the drift region close to the channel region, thereby improving the reliability of the device; on the other hand, it is beneficial to reduce the Kirk effect and improve the on-state breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the drawings required for use in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0035] Figure 1 A schematic flow chart of a method for preparing a laterally diffused metal oxide semiconductor device provided in accordance with an embodiment of the present application.
[0036] Figure 2 for Figure 1 A schematic diagram of a process of S300 in the preparation method shown.
[0037] Figure 3 for Figure 2 A schematic diagram of a process flow of S330 in the preparation method shown.
[0038] Figure 4-Figure 8 for Figure 1 Schematic diagram of the device structure during the preparation method shown.
[0039] Fig. 9 A schematic structural diagram of a laterally diffused metal oxide semiconductor device provided in one embodiment of the present application.
[0040] Description of reference numerals:
[0041] 1. Laterally diffused metal oxide semiconductor device; 11. substrate; 111. body region; 112. drift region; 1121. sub-drift region; 113. first doped region; 1131. sub-doped region; 114. source lead-out region; 115. drain lead-out region; 116. body lead-out region; 12. gate; 121. gate oxide layer; 122. gate dielectric layer; 21. barrier layer; 211. first portion; 212. second portion; 22. first photoresist layer; 23. second photoresist layer. DETAILED DESCRIPTION
[0042] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0044] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0045] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0046] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0047] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the application.
[0048] First, refer to Figure 1 As shown, an embodiment of the present application provides a method for preparing a laterally diffused metal oxide semiconductor device 1, wherein the laterally diffused metal oxide semiconductor device 1 takes an N-type laterally diffused metal oxide semiconductor device 1 as an example, wherein the first doping type is P-type and the second doping type is N-type. In other embodiments, the laterally diffused metal oxide semiconductor device 1 may also be a P-type laterally diffused metal oxide semiconductor device 1, wherein the first doping type is N-type and the second doping type is P-type.
[0049] Specifically, the method for preparing the laterally diffused metal oxide semiconductor device 1 includes:
[0050] S100: Provide a substrate 11. The material of the substrate 11 can be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI) or low temperature polysilicon (LTPS), or other materials known to those skilled in the art.
[0051] S200: forming a body region 111 in the substrate 11. In one example, ions of a first doping type may be implanted into the substrate 11 by ion implantation to form the body region 111.
[0052] It should be noted that since ion implantation will damage the substrate 11, the mobility and life of the electron-hole pairs will be greatly reduced. In addition, most of the implanted ions are not in the lattice position in a substitutional form. In order to activate the ions and restore the original mobility, the substrate 11 must be annealed at an appropriate temperature. Annealing can repair lattice defects and move impurity atoms to lattice points to activate impurities. Generally, it takes about 450-550°C to repair lattice defects and 900-1000°C to activate impurities. The activation of impurities is related to time and temperature. The longer the time and the higher the temperature, the more fully the impurities are activated. Commonly used annealing methods for the substrate 11 include high-temperature thermal annealing and rapid thermal annealing (RTA). In one example, a high-temperature thermal annealing process can be used for annealing. Specifically, a high-temperature furnace is used to heat the silicon wafer to 800-1000°C and maintain it for 20-40 minutes. In another example, a rapid thermal annealing process may be used for annealing. Compared with a high temperature thermal annealing process, the rapid thermal annealing process has a shorter annealing time, can avoid diffusion of doped ions caused by long-term high temperature, and reduce instantaneous enhanced diffusion of doped ions.
[0053] After annealing, the following steps are followed:
[0054] S300: An injection masking structure (not shown) is formed on the substrate 11, and the injection masking structure covers a portion of the surface of the substrate 11. The body region 111 is located within the orthographic projection of the injection masking structure on the substrate 11. The thickness of the injection masking structure decreases from the body region 111 to the edge of the substrate 11. Here, the thickness of the injection masking structure refers to the size of the injection masking structure along the first direction X, and the first direction X is parallel to the thickness direction of the substrate 11.
[0055] It can be understood that the implantation masking structure can be a structure composed of a single film layer or a structure composed of a plurality of stacked film layers.
[0056] S400: forming a drift region 112 in the substrate 11. The drift region 112 is adjacent to the body region 111, and the depth of the drift region 112 increases from the body region 111 to the edge of the substrate 11. Here, the depth of the drift region 112 refers to the dimension of the drift region 112 along the first direction X. In one example, ions of the second doping type are implanted into the substrate 11 by ion implantation to form the drift region 112.
[0057] It is understandable that the thickness of the implantation masking structure is distributed in an increasing manner. Therefore, when performing ion implantation, the ion implantation concentration and ion implantation depth in the substrate 11 below the implantation masking structure of different thickness are different. In addition, the ion implantation concentration in the substrate 11 not covered by the implantation masking structure is the highest and the ion implantation depth is the deepest.
[0058] The method for preparing the lateral diffused metal oxide semiconductor device 1 provided in the embodiment of the present application forms an implantation masking structure with a decreasing thickness from the body region 111 to the edge of the substrate 11 on the substrate 11. In this way, when performing ion implantation, it is convenient to form a drift region 112 with a gradual depth and concentration change in the substrate 11. On the one hand, it is helpful to reduce the electric field at one end of the drift region 112 close to the channel region and improve the reliability of the device. On the other hand, it is helpful to reduce the Kirk effect and improve the on-state breakdown voltage.
[0059] In one embodiment, the same implantation energy is used to implant doping ions into the substrate 11 at one time to form the drift region 112. In this way, with the help of the implantation masking structure, the drift region 112 with increasing depth and concentration can be formed in one implantation process, thereby reducing the manufacturing process of the drift region 112 and further reducing the manufacturing difficulty of the drift region 112.
[0060] In one embodiment, referring to Figure 2 , and combined with Figure 4 and Figure 5 As shown, S300: forming an injection masking structure on the substrate 11, wherein the injection masking structure covers a portion of the surface of the substrate 11, specifically comprising the following steps:
[0061] S310 : forming a barrier layer 21 on the substrate 11 . The barrier layer 21 includes a first portion 211 and a second portion 212 connected to each other, and the body region 111 is located within the orthographic projection of the first portion 211 on the substrate 11 , and is located outside the orthographic projection of the second portion 212 on the substrate 11 .
[0062] In one example, the material of the barrier layer 21 includes at least one of a nitride and an oxide. In the embodiment of the present application, the material of the barrier layer 21 is an oxide. Specifically, a barrier material layer is formed on the surface of the substrate 11, and a first mask layer is formed on the surface of the barrier material layer to expose a portion of the surface of the barrier material layer. Then, the exposed barrier material layer is etched to form the barrier layer 21.
[0063] S320 : forming a first photoresist layer 22 on the blocking layer 21 , wherein the first photoresist layer 22 covers the surface of the first portion 211 .
[0064] Specifically, a photoresist material is formed on the surface of the blocking layer 21 , the photoresist material is selectively exposed, and developed, and after the development, the photoresist material in the area to be etched is removed.
[0065] S330: etching the barrier layer 21 and the first photoresist layer 22 to form an implantation masking structure.
[0066] In one embodiment, referring to Figure 3 , and combined with Figure 6 and Figure 7 As shown, S330: etching the barrier layer 21 and the first photoresist layer 22 to form an implantation masking structure, specifically comprising the following steps:
[0067] S331: etching the barrier layer 21 so that the thickness of the second portion 212 is smaller than the thickness of the first portion 211. Here, the thickness of the second portion 212 refers to the size of the second portion 212 along the first direction X, and the thickness of the first portion 211 refers to the size of the first portion 211 along the first direction X.
[0068] Specifically, the first photoresist layer 22 is selectively etched by a dry or wet process, that is, the thickness of the second portion 212 is reduced.
[0069] In one embodiment, referring to Figure 6 As shown, the ratio of the thickness H2 of the second portion 212 to the thickness H1 of the first portion 211 is between 0.3 and 0.7. For example, the ratio of the thickness H2 of the second portion 212 to the thickness H1 of the first portion 211 may be 0.3, 0.4, 0.5, 0.55, 0.65 or 0.7.
[0070] By making the ratio of the thickness H2 of the second portion 212 to the thickness H1 of the first portion 211 within the above range, it is possible to easily control the concentration and depth of the drift region 112 below the first portion 211 and the concentration and depth of the drift region 112 below the second portion 212, thereby improving the reliability of the device.
[0071] S332: Etching the first photoresist layer 22 to form a second photoresist layer 23. The second photoresist layer 23 covers a portion of the surface of the first portion 211. The exposed surface of the first portion 211 is adjacent to the second portion 212.
[0072] Specifically, the second photoresist layer 23 can be etched by a wet process to expose a portion of the surface of the first portion 211. Thus, the second photoresist layer 23 and the barrier layer 21 together form a stepped implantation masking structure, and after ion implantation, a stepped drift region 112 can be formed in the substrate 11.
[0073] In one embodiment, the method for preparing the laterally diffused metal oxide semiconductor device 1 further includes:
[0074] S340: forming a first doping region 113 in the substrate 11. The first doping region 113 is located at the bottom of the drift region 112 and is adjacent to the drift region 112. Specifically, ions of a first doping type are implanted into the substrate 11 by ion implantation to form the first doping region 113.
[0075] It should be noted that the step of manufacturing the first doping region 113 may be prior to the step of manufacturing the drift region 112 .
[0076] In one embodiment, in combination Fig. 9 As shown, the method for preparing the laterally diffused metal oxide semiconductor device 1 further includes:
[0077] S500 : forming a gate 12 on the substrate 11 , wherein the gate 12 covers surfaces of the body region 111 and the drift region 112 .
[0078] In one example, S500: forming a gate 12 on the substrate 11, wherein the gate 12 covers the surface of the body region 111 and the drift region 112, specifically includes the following steps:
[0079] S510: forming a gate oxide material layer on the surface of the substrate 11. The gate oxide material layer may be made of silicon dioxide.
[0080] S520: forming a gate dielectric material layer on the surface of the gate oxide material layer. The gate dielectric material layer may be made of polysilicon or a metal material, such as a high-K (dielectric constant) metal material.
[0081] S530: forming a photolithography blocking layer on the surface of the gate dielectric material layer, and performing photolithography on the photolithography blocking layer to form a window region.
[0082] S540 : etching the gate dielectric material layer and the gate oxide material layer to form a gate 12 .
[0083] After the gate 12 is formed, the following steps are followed:
[0084] S600: forming a source lead-out region 114, a drain lead-out region 115, and a body lead-out region 116 in the substrate 11, wherein the drain lead-out region 115 is located in the drift region 112, and the source lead-out region 114 and the body lead-out region 116 are located in the body region 111. Specifically, ions of a first doping type are implanted into the substrate 11 by ion implantation to form the body lead-out region 116, and ions of a second doping type are implanted to form the source lead-out region 114 and the drain lead-out region 115.
[0085] It should be noted that the drain lead-out region 115 is located at one end of the drift region 112 away from the body region 111. From the body region 111 to one end of the drain lead-out region 115, the concentration of the drift region 112 gradually increases, and the depth of the drift region 112 gradually increases. This is beneficial to reducing the electric field at one end of the drift region 112 close to the channel region and improving the reliability of the device. On the other hand, it is beneficial to suppress the electric field at the drain end (drain lead-out region 115), effectively reducing the Kirk effect, and improving the on-state breakdown voltage.
[0086] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the accompanying drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.
[0087] Second, refer to Fig. 9 As shown, an embodiment of the present application provides a laterally diffused metal oxide semiconductor device 1, which includes a substrate 11, a body region 111 and a drift region 112. Among them, the body region 111 is arranged in the substrate 11. The drift region 112 is arranged in the substrate 11 and is adjacent to the body region 111. From the body region 111 to the edge of the substrate 11, the depth of the drift region 112 increases, and the concentration of the drift region 112 increases. Here, the depth of the drift region 112 refers to the size of the drift region 112 along the first direction X. The first direction X is parallel to the thickness direction of the substrate 11.
[0088] The laterally diffused metal oxide semiconductor device 1 provided in the embodiment of the present application forms a drift region 112 in the substrate 11 with increasing concentration and depth in the direction from the body region 111 to the edge of the substrate 11. On the one hand, it is beneficial to reduce the electric field at one end of the drift region 112 close to the channel region, thereby improving the reliability of the device; on the other hand, it is beneficial to reduce the Kirk effect and improve the on-state breakdown voltage.
[0089] It can be understood that the lateral diffused metal oxide semiconductor device 1 further includes a source lead-out region 114, a drain lead-out region 115, a body lead-out region 116 and a gate 12, wherein the drain lead-out region 115 is located at one end of the drift region 112 away from the body region 111, the source lead-out region 114 and the body lead-out region 116 are located in the body region 111, and the gate 12 is located on the substrate 11, and the orthographic projection of the gate 12 on the substrate 11 covers part of the body region 111 and part of the drift region 112. In the embodiment of the present application, from the body region 111 to one end of the drain lead-out region 115, the concentration of the drift region 112 gradually increases, and the depth of the drift region 112 gradually increases, so that, on the one hand, it is conducive to reducing the electric field at one end of the drift region 112 close to the channel region, and improving the reliability of the device; on the other hand, it is conducive to suppressing the electric field at the drain end (drain lead-out region 115), effectively reducing the Kirk effect, and improving the on-state breakdown voltage.
[0090] In one embodiment, the drift region 112 includes a plurality of sub-drift regions 1121 connected in sequence. Each sub-drift region 1121 extends from the surface of the substrate 11 to the inside of the substrate 11. From the body region 111 to the edge of the substrate 11 (i.e., from the body region 111 to the drain lead-out region 115), the depths of the plurality of sub-drift regions 1121 gradually increase in the first direction, so that the drift region 112 is arranged in a stepped manner. Furthermore, in two adjacent sub-drift regions 1121, the depth of the sub-drift region 1121 away from the body region 111 is greater than the depth of the sub-drift region 1121 close to the body region 111.
[0091] Here, the depth of the sub-drift region 1121 refers to the dimension of the sub-drift region 1121 along the first direction X.
[0092] By setting up a stepped drift region 112, on the one hand, it is helpful to reduce the electric field at one end of the drift region 112 close to the channel region, thereby improving the reliability of the device; on the other hand, it is helpful to suppress the electric field at the drain end (drain lead-out region 115), effectively reduce the Kirk effect, and improve the on-state breakdown voltage.
[0093] In one embodiment, the LDMOS device 1 further includes a first doped region 113, which is located at the bottom of the drift region 112 and is adjacent to the drift region 112. The first doped region 113 is provided to assist in depleting the drift region 112, thereby improving device performance.
[0094] In one embodiment, in combination Figure 8 and Fig. 9 As shown, the first doping region 113 includes a plurality of sub-doping regions 1131, and each sub-doping region 1131 is correspondingly arranged at the bottom of a sub-drift region 1121. In two adjacent sub-drift regions 1121, the sum of the depths of the sub-drift region 1121 close to the body region 111 and the sub-doping region 1131 corresponding to the sub-drift region 1121 is not less than the depth of the sub-drift region 1121 far from the body region 111.
[0095] Here, the depth of the sub-drift region 1121 refers to the size of the sub-drift region 1121 along the first direction X, and the depth of the sub-doping region 1131 refers to the size of the sub-doping region 1131 along the first direction X. Figure 8 As shown, D1 represents the depth of the sub-drift region 1121 , and D2 represents the concentration of the sub-doping region 1131 .
[0096] The above arrangement is conducive to enabling the sub-doping region 1131 to surround the sub-drift region 1121 , thereby making the first doping region 113 have a better depletion effect on the drift region 112 .
[0097] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0098] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0099] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A method for preparing a laterally diffused metal oxide semiconductor device, characterized in that: include: providing a substrate; forming a body region in the substrate; An injection masking structure is formed on the substrate, wherein the injection masking structure covers a portion of the surface of the substrate; wherein the body region is located within the orthographic projection of the injection masking structure on the substrate; and the thickness of the injection masking structure decreases along a first direction from the body region to the edge of the substrate; and the first direction is parallel to the thickness direction of the substrate; A drift region is formed in the substrate; the drift region is adjacent to the body region, and the depth of the drift region increases gradually along the first direction from the body region to the edge of the substrate.
2. The method for preparing a laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The step of forming an implantation masking structure on the substrate, wherein the implantation masking structure covers a portion of the surface of the substrate, comprises: A barrier layer is formed on the substrate; the barrier layer comprises a first portion and a second portion connected to each other, the body region is located within an orthographic projection of the first portion on the substrate, and is located outside an orthographic projection of the second portion on the substrate; forming a first photoresist layer on the barrier layer, wherein the first photoresist layer covers a surface of the first portion; The barrier layer and the first photoresist layer are etched to form the implantation masking structure.
3. The method for preparing a laterally diffused metal oxide semiconductor device according to claim 2, characterized in that: The step of etching the barrier layer and the first photoresist layer to form the implantation masking structure comprises: Etching the barrier layer so that the thickness of the second portion along the first direction is smaller than the thickness of the first portion along the first direction; The first photoresist layer is etched to form a second photoresist layer; the second photoresist layer covers a portion of the surface of the first portion; and the exposed surface of the first portion is adjacent to the second portion.
4. The method for preparing a laterally diffused metal oxide semiconductor device according to claim 3, characterized in that: The ratio of the thickness of the second portion to the thickness of the first portion is between 0.3 and 0.7; And / or, the material of the barrier layer includes at least one of nitride and oxide.
5. The method for preparing a laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The doping ions are implanted into the substrate once with the same implantation energy to form the drift region.
6. The method for preparing a laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The method for preparing the laterally diffused metal oxide semiconductor device further comprises: A first doped region is formed in the substrate; the first doped region is located at the bottom of the drift region and is adjacent to the drift region.
7. The method for preparing a laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The method for preparing the laterally diffused metal oxide semiconductor device further comprises: forming a gate on the substrate, wherein the gate covers surfaces of the body region and the drift region; A source lead-out region, a drain lead-out region and a body lead-out region are formed in the substrate, the drain lead-out region is located in the drift region, and the source lead-out region and the body lead-out region are located in the body region.
8. A laterally diffused metal oxide semiconductor device, characterized in that: include: substrate; a body region disposed in the substrate; a drift region disposed in the substrate and adjacent to the body region; From the body region to the edge of the substrate, the depth of the drift region increases along a first direction, and the concentration of the drift region increases; the first direction is parallel to the thickness direction of the substrate.
9. The laterally diffused metal oxide semiconductor device according to claim 8, characterized in that: The drift region includes a plurality of sub-drift regions connected in sequence; each of the sub-drift regions extends from the surface of the substrate to the interior of the substrate; From the body region to the edge of the substrate, the depths of the plurality of sub-drift regions gradually increase in the first direction, so that the drift regions are arranged in steps.
10. The laterally diffused metal oxide semiconductor device according to claim 8, characterized in that: The lateral diffused metal oxide semiconductor device further includes a first doped region, the first doped region is located at the bottom of the drift region and is adjacent to the drift region; Among them, the first doping region includes multiple sub-doping regions, each of which is arranged at the bottom of a sub-drift region; in two adjacent sub-drift regions, the sum of the depths of the sub-drift region close to the body region and the sub-doping region corresponding to the sub-drift region along the first direction is not less than the depth of the sub-drift region away from the body region along the first direction.