Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises a semiconductor substrate, a well region and a body end surrounding the well region are formed in the semiconductor substrate, a plurality of source regions and drain regions are formed in the well region, and the source regions and the drain regions are alternately arranged at intervals in the channel direction; a grid electrode is formed on the surface of the well region between the source region and the drain region; the electric connection region is located in the source region, the doping type of the electric connection region is opposite to that of the source region, and the electric connection region is adjacent to the adjacent grid electrode; the interlayer dielectric layer covers the semiconductor substrate and the grid electrode; the first contact structure and the second contact structure are located in the interlayer dielectric layer and electrically connected with the body end and the electric connection area respectively; and the metal layer is positioned on the surface of the interlayer dielectric layer and is electrically connected with the first contact structure and the second contact structure. The invention provides a semiconductor structure and a forming method thereof, which can solve the problem of non-uniform conduction of a multi-finger structure device BJT (Bipolar Junction Transistor).

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Transistor is an important semiconductor device in semiconductor integrated circuits, and is widely used in the field of integrated circuit technology. Multi-finger transistors are usually composed of multiple transistors, that is, multi-finger transistors include multiple gates arranged in sequence, and source and drain electrodes arranged on both sides of each gate, and the source and drain electrodes are arranged in sequence and spaced apart.

[0003] Since the parasitic bipolar junction transistor (BJT) in the Multi Finger structure device is non-uniformly turned on, the parasitic BJT at the center position is turned on first, which can easily cause the center position to burn out.

[0004] Therefore, it is necessary to provide more effective and reliable technical solutions. Summary of the invention

[0005] The present application provides a semiconductor structure and a method for forming the same, which can solve the problem of non-uniform conduction of a BJT device with a multi-finger structure and improve the reliability of the device.

[0006] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein a well region and a body end surrounding the well region are formed in the semiconductor substrate, wherein a plurality of source regions and drain regions alternately arranged along a channel direction are formed in the well region, and a gate is formed on the surface of the well region between the source region and the drain region; forming an electrical connection region in the source region, wherein the doping type of the electrical connection region is opposite to that of the source region, and the electrical connection region is adjacent to an adjacent gate; forming an interlayer dielectric layer covering the semiconductor substrate and the gate on the surface of the semiconductor substrate; forming a first contact structure and a second contact structure electrically connecting the body end and the electrical connection region, respectively, in the interlayer dielectric layer; and forming a metal layer electrically connecting the first contact structure and the second contact structure on the surface of the interlayer dielectric layer.

[0007] In some embodiments of the present application, the doping concentration of the electrical connection region is higher than the doping concentration of the well region.

[0008] In some embodiments of the present application, a ratio of a doping concentration of the electrical connection region to a doping concentration of the well region is 10 to 1000.

[0009] In some embodiments of the present application, a length of the electrical connection region in a direction perpendicular to the channel is less than or equal to a length of the source region in a direction perpendicular to the channel.

[0010] In some embodiments of the present application, a ratio of a length of the electrical connection region in a direction perpendicular to the channel to a length of the source region in a direction perpendicular to the channel is 10% to 50%.

[0011] Another aspect of the present application also provides a semiconductor structure, including: a semiconductor substrate, a well region and a body end surrounding the well region are formed in the semiconductor substrate, a plurality of source regions and drain regions are formed in the well region and are alternately arranged along the channel direction, a gate is formed on the surface of the well region between the source region and the drain region; an electrical connection region, located in the source region, the doping type of the electrical connection region is opposite to the doping type of the source region, and the electrical connection region is adjacent to an adjacent gate; an interlayer dielectric layer, covering the semiconductor substrate and the gate; a first contact structure and a second contact structure, located in the interlayer dielectric layer and electrically connected to the body end and the electrical connection region respectively; a metal layer, located on the surface of the interlayer dielectric layer and electrically connected to the first contact structure and the second contact structure.

[0012] In some embodiments of the present application, the doping concentration of the electrical connection region is higher than the doping concentration of the well region.

[0013] In some embodiments of the present application, a ratio of a doping concentration of the electrical connection region to a doping concentration of the well region is 10 to 1000.

[0014] In some embodiments of the present application, a length of the electrical connection region in a direction perpendicular to the channel is less than or equal to a length of the source region in a direction perpendicular to the channel.

[0015] In some embodiments of the present application, a ratio of a length of the electrical connection region in a direction perpendicular to the channel to a length of the source region in a direction perpendicular to the channel is 10% to 50%.

[0016] The present application provides a semiconductor structure and a method for forming the same, forming an electrical connection region in the source region so that the current generated by the BJT can flow out from the body end respectively, which can solve the problem of non-uniform conduction of the BJT of a multi-finger structure device and improve the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following figures describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale.

[0018] in:

[0019] Figures 1 to 7 It is a structural schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0021] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0022] For the problem of non-uniform conduction of BJTs in multi-finger structure devices, the following two solutions can generally be adopted: one is to solve it through circuit-level solutions, such as adding a power clamp protection circuit; the other is to add one or more doped regions between multiple gates to separate the multi-finger transistors.

[0023] However, the above solutions will increase the device area, increase costs, and reduce product competitiveness. Therefore, the present application provides a semiconductor structure and a method for forming the same, forming an electrical connection area in the source area so that the current generated by the BJT can flow out from the body end respectively, and the problem of non-uniform conduction of the BJT of the multi-finger structure device can be solved without increasing the device area, thereby improving the device reliability.

[0024] Figures 1 to 7 The following is a schematic diagram of the structure of each step in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application is described in detail in conjunction with the accompanying drawings.

[0025] refer to Figure 1 and Figure 2 As shown, Figure 1 is a top view, Figure 2 For along Figure 1 A semiconductor substrate 100 is provided, in which a well region 110 and a body terminal 120 surrounding the well region 110 are formed, in which a plurality of source regions 130 and drain regions 140 are alternately arranged along a channel direction, and a gate 150 is formed on the surface of the well region 110 between the source regions 130 and the drain regions 140.

[0026] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0027] In some embodiments of the present application, the well region 110 is formed by doping in the semiconductor substrate 100. The doping type of the well region 110 is set according to the device type of the semiconductor structure. The doping type of the well region 110 is, for example, P type.

[0028] In some embodiments of the present application, the body terminal 120 (pick up terminal) is formed by doping in the semiconductor substrate 100. The doping type of the body terminal 120 is the same as the doping type of the well region 110. The doping concentration of the body terminal 120 is higher than the doping concentration of the well region 110. The depth of the body terminal 120 is greater than or equal to the depth of the well region 110.

[0029] In some embodiments of the present application, the source region 130 and the drain region 140 are formed by doping in the semiconductor substrate 100. The doping type and doping concentration of the source region 130 and the drain region 140 are the same. The doping type of the source region 130 and the drain region 140 is opposite to the doping type of the well region 110. The doping type of the source region 130 and the drain region 140 is, for example, N-type. The doping concentration of the source region 130 and the drain region 140 is higher than the doping concentration of the well region 110.

[0030] In some embodiments of the present application, the gate 150 is made of polysilicon, for example. The gate 150 may be formed by a chemical vapor deposition process or a physical vapor deposition process, etc. Adjacent gates 150 share a source region 130 or a drain region 140 .

[0031] refer to Figure 3 and Figure 4 As shown, Figure 3 is a top view, Figure 4 For along Figure 3 A longitudinal cross-sectional view at the middle dashed line BB. An electrical connection region 160 is formed in the source region 130 . The doping type of the electrical connection region 160 is opposite to that of the source region 130 . The electrical connection region 160 is adjacent to the adjacent gate 150 .

[0032] In some embodiments of the present application, the method of forming the electrical connection region 160 is, for example, an ion implantation process.

[0033] In some embodiments of the present application, a depth of the electrical connection region 160 is lower than a depth of the source region 130 .

[0034] In some embodiments of the present application, the doping concentration of the electrical connection region 160 is higher than the doping concentration of the well region 110 .

[0035] In some embodiments of the present application, a ratio of a doping concentration of the electrical connection region 160 to a doping concentration of the well region 110 is 10 to 1000.

[0036] In some embodiments of the present application, the length of the electrical connection region 160 in the direction perpendicular to the channel is less than or equal to the length of the source region 130 in the direction perpendicular to the channel.

[0037] In some embodiments of the present application, a ratio of a length of the electrical connection region 160 in a direction perpendicular to the channel to a length of the source region 130 in a direction perpendicular to the channel is 10% to 50%.

[0038] refer to Figure 5 As shown, an interlayer dielectric layer 170 covering the semiconductor substrate 100 and the gate 150 is formed on the surface of the semiconductor substrate 100 .

[0039] In some embodiments of the present application, the material of the interlayer dielectric layer 170 includes silicon oxide. The method of forming the interlayer dielectric layer 170 includes a chemical vapor deposition process or a physical vapor deposition process.

[0040] refer to Figure 6 As shown, a first contact structure 181 and a second contact structure 182 are formed in the interlayer dielectric layer 170 to electrically connect the body terminal 120 and the electrical connection region 160 , respectively.

[0041] refer to Figure 7 As shown, a metal layer 190 electrically connecting the first contact structure 181 and the second contact structure 182 is formed on the surface of the interlayer dielectric layer 170 .

[0042] In the technical solution of the present application, an electrical connection region 160 is formed in the source region 130, and the electrical connection region 160 is electrically connected to the body terminal 120, thereby shortening the distance between the drain region 140 and the body terminal 120 in each transistor. When a voltage is applied to the drain region 140 to turn on the parasitic NPNBJT, the current generated by the parasitic NPNBJT formed between the source region 130, the drain region 140 and the well region 110 can flow out from the nearest body terminal 120, respectively, thereby preventing the central position resistance from being too large, causing the current to normalize and burn out first after the middle transistor is turned on first, and solving the problem of non-uniform conduction of BJT in multi-finger structure devices without increasing the device area.

[0043] The present application provides a semiconductor structure and a method for forming the same, forming an electrical connection region in the source region so that the current generated by the BJT can flow out from the body end respectively, which can solve the problem of non-uniform conduction of the BJT of a multi-finger structure device and improve the reliability of the device.

[0044] The embodiment of the present application also provides a semiconductor structure, referring to Figure 7 As shown, it includes: a semiconductor substrate 100, in which a well region 110 and a body terminal 120 surrounding the well region 110 are formed, in which a plurality of source regions 130 and drain regions 140 are alternately arranged along a channel direction, and a gate 150 is formed on the surface of the well region 110 between the source region 130 and the drain region 140; an electrical connection region 160, located in the source region 130, the doping type of the electrical connection region 160 is opposite to the doping type of the source region 130, and the electrical connection region 160 is adjacent to the adjacent gate 150; an interlayer dielectric layer 170, covering the semiconductor substrate 100 and the gate 150; a first contact structure 181 and a second contact structure 182, located in the interlayer dielectric layer 170 and electrically connected to the body terminal 120 and the electrical connection region 160 respectively; a metal layer 190, located on the surface of the interlayer dielectric layer 170 and electrically connected to the first contact structure 181 and the second contact structure 182.

[0045] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0046] In some embodiments of the present application, the well region 110 is formed by doping in the semiconductor substrate 100. The doping type of the well region 110 is set according to the device type of the semiconductor structure. The doping type of the well region 110 is, for example, P type.

[0047] In some embodiments of the present application, the body terminal 120 (pick up terminal) is formed by doping in the semiconductor substrate 100. The doping type of the body terminal 120 is the same as the doping type of the well region 110. The doping concentration of the body terminal 120 is higher than the doping concentration of the well region 110. The depth of the body terminal 120 is greater than or equal to the depth of the well region 110.

[0048] In some embodiments of the present application, the source region 130 and the drain region 140 are formed by doping in the semiconductor substrate 100. The doping type and doping concentration of the source region 130 and the drain region 140 are the same. The doping type of the source region 130 and the drain region 140 is opposite to the doping type of the well region 110. The doping type of the source region 130 and the drain region 140 is, for example, N-type. The doping concentration of the source region 130 and the drain region 140 is higher than the doping concentration of the well region 110.

[0049] In some embodiments of the present application, the gate 150 is made of, for example, polysilicon. Adjacent gates 150 share a source region 130 or a drain region 140 .

[0050] Continue to refer Figure 7 As shown, an electrical connection region 160 is formed in the source region 130 . The doping type of the electrical connection region 160 is opposite to that of the source region 130 . The electrical connection region 160 is adjacent to the adjacent gate 150 .

[0051] In some embodiments of the present application, a depth of the electrical connection region 160 is lower than a depth of the source region 130 .

[0052] In some embodiments of the present application, the doping concentration of the electrical connection region 160 is higher than the doping concentration of the well region 110 .

[0053] In some embodiments of the present application, a ratio of a doping concentration of the electrical connection region 160 to a doping concentration of the well region 110 is 10 to 1000.

[0054] In some embodiments of the present application, the length of the electrical connection region 160 in the direction perpendicular to the channel is less than or equal to the length of the source region 130 in the direction perpendicular to the channel.

[0055] In some embodiments of the present application, a ratio of a length of the electrical connection region 160 in a direction perpendicular to the channel to a length of the source region 130 in a direction perpendicular to the channel is 10% to 50%.

[0056] Continue to refer Figure 7 As shown, an interlayer dielectric layer 170 covering the semiconductor substrate 100 and the gate 150 is formed on the surface of the semiconductor substrate 100 .

[0057] In some embodiments of the present application, the material of the interlayer dielectric layer 170 includes silicon oxide.

[0058] Continue to refer Figure 7As shown, the interlayer dielectric layer 170 has a first contact structure 181 and a second contact structure 182 respectively formed therein to electrically connect the body terminal 120 and the electrical connection region 160. A metal layer 190 electrically connecting the first contact structure 181 and the second contact structure 182 is formed on the surface of the interlayer dielectric layer 170.

[0059] In the technical solution of the present application, an electrical connection region 160 is formed in the source region 130, and the electrical connection region 160 is electrically connected to the body terminal 120, thereby shortening the distance between the drain region 140 and the body terminal 120 in each transistor. When a voltage is applied to the drain region 140 to turn on the parasitic NPNBJT, the current generated by the parasitic NPNBJT formed between the source region 130, the drain region 140 and the well region 110 can flow out from the nearest body terminal 120, respectively, thereby preventing the central position resistance from being too large, causing the current to normalize and burn out first after the middle transistor is turned on first, and solving the problem of non-uniform conduction of BJT in multi-finger structure devices without increasing the device area.

[0060] The present application provides a semiconductor structure and a method for forming the same, forming an electrical connection region in the source region so that the current generated by the BJT can flow out from the body end respectively, which can solve the problem of non-uniform conduction of the BJT of a multi-finger structure device and improve the reliability of the device.

[0061] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0062] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can also be intermediate elements.

[0063] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there can be intervening elements. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0064] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0065] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: A semiconductor substrate is provided, wherein a well region and a body end surrounding the well region are formed in the semiconductor substrate, wherein a plurality of source regions and drain regions alternately arranged along a channel direction are formed in the well region, and a gate is formed on a surface of the well region between the source regions and the drain regions; forming an electrical connection region in the source region, wherein the doping type of the electrical connection region is opposite to the doping type of the source region, and the electrical connection region is adjacent to an adjacent gate; forming an interlayer dielectric layer covering the semiconductor substrate and the gate on the surface of the semiconductor substrate; Forming a first contact structure and a second contact structure electrically connecting the body terminal and the electrical connection area respectively in the interlayer dielectric layer; A metal layer electrically connecting the first contact structure and the second contact structure is formed on the surface of the interlayer dielectric layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The doping concentration of the electrical connection region is higher than the doping concentration of the well region.

3. The method for forming a semiconductor structure according to claim 2, wherein: The ratio of the doping concentration of the electrical connection region to the doping concentration of the well region is 10 to 1000.

4. The method for forming a semiconductor structure according to claim 1, wherein: The length of the electrical connection region in a direction perpendicular to the channel is less than or equal to the length of the source region in a direction perpendicular to the channel.

5. The method for forming a semiconductor structure according to claim 4, wherein: A ratio of a length of the electrical connection region in a direction perpendicular to the channel to a length of the source region in a direction perpendicular to the channel is 10% to 50%.

6. A semiconductor structure, characterized in that: include: A semiconductor substrate, wherein a well region and a body end surrounding the well region are formed in the semiconductor substrate, wherein a plurality of source regions and drain regions alternately arranged along a channel direction are formed in the well region, and a gate is formed on a surface of the well region between the source regions and the drain regions; An electrical connection region, located in the source region, the doping type of the electrical connection region is opposite to the doping type of the source region, and the electrical connection region is adjacent to an adjacent gate; An interlayer dielectric layer, covering the semiconductor substrate and the gate; A first contact structure and a second contact structure are located in the interlayer dielectric layer and electrically connect the body terminal and the electrical connection area respectively; The metal layer is located on the surface of the interlayer dielectric layer and electrically connects the first contact structure and the second contact structure.

7. The method for forming a semiconductor structure according to claim 6, wherein: The doping concentration of the electrical connection region is higher than the doping concentration of the well region.

8. The method for forming a semiconductor structure according to claim 7, wherein: The ratio of the doping concentration of the electrical connection region to the doping concentration of the well region is 10 to 1000.

9. The method for forming a semiconductor structure according to claim 6, wherein: The length of the electrical connection region in a direction perpendicular to the channel is less than or equal to the length of the source region in a direction perpendicular to the channel.

10. The method for forming a semiconductor structure according to claim 9, wherein: A ratio of a length of the electrical connection region in a direction perpendicular to the channel to a length of the source region in a direction perpendicular to the channel is 10% to 50%.

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