Wafer, semiconductor structure and forming method thereof

Abstract

The invention relates to a wafer, a semiconductor structure and a forming method thereof. The wafer comprises a body structure which comprises a first surface and a second surface which are oppositely distributed along a first direction; the edge structure is connected to the end of the body structure in the second direction, the edge structure at least comprises a first chamfer part connected with the first surface and a second chamfer part connected with the second surface, the first chamfer part is connected with the second chamfer part, the first chamfer part has a first breadth, and the second chamfer part has a second breadth. The first breadth length is less than 600 [mu] m, and the second direction is vertically intersected with the first direction. According to the invention, the edge collapse width of the epitaxial layer formed on the first surface of the wafer is shortened, so that the yield of the semiconductor structure is improved, the sharp-knife-shaped epitaxial chamfer edge is improved, and the cracking rate of the wafer in the thinning process is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a wafer, a semiconductor structure and a forming method thereof. Background Art

[0002] Among semiconductor devices based on wafers, MOSFET devices usually choose (100) crystal orientation substrates because the operating current is the surface majority drift current, which is affected by the surface mobility of carriers. The interface state density of (100) crystal orientation is the lowest and its surface mobility is the highest, allowing MOSFET to have a high operating current; while bipolar devices such as FRD (Fast recovery diode) usually choose (111) crystal orientation substrates. The main reasons are as follows: 1. Crystal structure: In the (111) crystal orientation, the crystal structure of silicon wafers has a special symmetry. This symmetry allows better control of the movement of electrons and holes when manufacturing bipolar devices, thereby achieving better current control and performance, and can produce very shallow doping; 2. Surface characteristics: The (111) crystal orientation has the largest atomic surface density and the slowest dissolution rate. When making PN junctions, it is relatively easy to control a flat and stable junction surface, which is beneficial to It is very important for manufacturing bipolar devices. A flat surface helps to manufacture precise electrodes and structures, reduce current leakage and electron tunneling effects, and improve device performance and reliability. In addition, the (111) crystal orientation has a higher oxidation rate, which can reduce oxidation time; 3. Coplanar device integration: Since the (111) crystal orientation silicon wafer has good surface properties and symmetry, it is easy to realize the integration of coplanar devices. Coplanar devices refer to devices in which electrons and holes operate on the same wafer. This design can reduce the resistance and capacitance between devices and improve the speed and power consumption efficiency of devices. However, when processing the (111) crystal orientation substrate, the edge of the wafer will be worn away and deviate from the crystal orientation of the substrate. After epitaxy, an orientation plane will be formed, that is, the edge of the epitaxial wafer is lower than the middle part to form a circle or a part of an inclined plane, that is, "collapsed edge". This phenomenon cannot be avoided for the time being.

[0003] In the process of wafer device manufacturing, the thinning process is to grind the back of the wafer (mainly silicon wafer) that has completed the function and remove a certain thickness of the substrate. It is a crucial and indispensable process, which is beneficial to the requirements of the subsequent packaging process and the physical strength, heat dissipation and size requirements of the chip. However, the current edge collapse width is wide, which leads to an increase in the cracking rate during the substrate thinning process, affecting the yield and yield of semiconductor products.

[0004] Therefore, how to reduce the edge collapse width after epitaxial growth on (111) oriented substrates, thereby reducing the cracking rate during substrate thinning and improving the yield and production rate of semiconductor products, is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The present invention provides a wafer, a semiconductor structure and a method for forming the same, which are used to reduce the edge collapse width after epitaxy based on a (111) crystal orientation substrate, thereby reducing the chipping rate during wafer thinning and improving the yield and production rate of semiconductor products.

[0006] According to some embodiments, the present invention provides a wafer, comprising:

[0007] The body structure comprises a first surface and a second surface which are oppositely distributed along a first direction;

[0008] An edge structure is connected to the end of the main body structure along a second direction, the edge structure at least includes a first chamfered portion connected to the first surface and a second chamfered portion connected to the second surface, the first chamfered portion is connected to the second chamfered portion, the first chamfered portion has a first length, and the first length is less than 600 μm, wherein the second direction intersects the first direction perpendicularly.

[0009] In some embodiments, the edge structure is an R-shaped chamfer structure or a T-shaped chamfer structure.

[0010] In some embodiments, the first width is 200 μm to 400 μm.

[0011] In some embodiments, the first frame length is 300 μm.

[0012] According to some other embodiments, the present invention further provides a method for forming a semiconductor structure, comprising the following steps:

[0013] Forming a wafer, the wafer comprising a main body structure and an edge structure connected to an end of the main body structure along a second direction, the main body structure comprising a first surface and a second surface relatively distributed along a first direction, the edge structure comprising at least a first chamfered portion connected to the first surface and a second chamfered portion connected to the second surface, the first chamfered portion being connected to the second chamfered portion, the first chamfered portion having a first width length, and the first width length being less than 600 μm, wherein the second direction intersects the first direction perpendicularly;

[0014] forming an epitaxial layer on the first surface, the first chamfered portion, and the second chamfered portion of the wafer;

[0015] The wafer is thinned starting from the second surface of the wafer.

[0016] In some embodiments, the specific steps of forming a wafer include:

[0017] Providing a wafer with a (111) crystal orientation;

[0018] The edge of the wafer is chamfered to form the edge structure including the first chamfered portion and the second chamfered portion.

[0019] In some embodiments, the first width is 200 μm to 400 μm.

[0020] In some embodiments, the specific steps of thinning the wafer starting from the second surface of the wafer include:

[0021] The wafer is thinned starting from the second surface of the wafer until at least the second chamfered portion is completely removed.

[0022] According to some further embodiments, the present invention further provides a semiconductor structure, comprising:

[0023] A wafer, comprising a main body structure and an edge structure connected to an end of the main body structure along a second direction, wherein the main body structure comprises a front side and a back side relatively distributed along a first direction, and the edge structure comprises at least a first chamfered portion connected to the front side, wherein the first chamfered portion has a first width length, and the first width length is less than 600 μm, wherein the second direction intersects the first direction perpendicularly;

[0024] An epitaxial layer is covered on the front side of the wafer, wherein the epitaxial layer includes a first portion covering the main structure and a second portion covering the first chamfered portion, and the second portion is lower than the first portion.

[0025] In some embodiments, the first width is 300 μm, and the width of the second portion along the second direction is less than 1.5 μm.

[0026] The wafer, semiconductor structure and formation method thereof provided by the present invention are achieved by arranging an edge structure at the edge of the wafer, and the edge structure at least includes a first chamfered portion connected to the first surface and a second chamfered portion connected to the second surface, the first chamfered portion is connected to the second chamfered portion, the first chamfered portion has a first width, and the first width is less than 600 μm. By shortening the first width, on the one hand, the collapsed width of the epitaxial layer formed on the first surface of the wafer can be shortened, thereby improving the yield of the semiconductor structure; on the other hand, the edge morphology of the epitaxial layer formed on the first surface of the wafer is improved, the knife-shaped edge of the epitaxial layer is improved, and the cracking rate during the wafer thinning process is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic cross-sectional view of a wafer in a specific embodiment of the present invention;

[0028] Figure 2is another cross-sectional schematic diagram of a wafer in a specific embodiment of the present invention;

[0029] Figure 3 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention;

[0030] Figure 4 It is a schematic diagram of the structure after an epitaxial layer is formed on a wafer according to a specific embodiment of the present invention;

[0031] Figure 5 is a schematic structural diagram of a wafer after thinning according to a specific embodiment of the present invention;

[0032] Figure 6 is a schematic diagram of the structure of a specific embodiment of the present invention after an epitaxial layer is formed on another wafer;

[0033] Figure 7 It is a schematic diagram of the structure after another wafer is thinned according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0034] The specific implementation methods of the wafer, semiconductor structure and the method for forming the same provided by the present invention are described in detail below with reference to the accompanying drawings.

[0035] This specific embodiment provides a wafer, Figure 1 is a schematic cross-sectional view of a wafer in a specific embodiment of the present invention, Figure 2 FIG. 2 is another cross-sectional schematic diagram of a wafer in a specific embodiment of the present invention. Figure 1 and Figure 2 As shown, the wafer 10 comprises:

[0036] The main body structure 11 includes a first surface 101 and a second surface 102 that are oppositely distributed along a first direction D1;

[0037] An edge structure 12 is connected to the end of the main body structure 11 along a second direction D2, and the edge structure 12 includes at least a first chamfered portion connected to the first surface 101 and a second chamfered portion connected to the second surface 102, the first chamfered portion is connected to the second chamfered portion, the first chamfered portion has a first length X1, and the first length is less than 600 μm, wherein the second direction D2 intersects the first direction D1 perpendicularly.

[0038] Specifically, the wafer 10 includes the main body structure 11 and the edge structure 12 ( Figure 1 and Figure 2Only a partial structural schematic diagram of the wafer is shown). The main structure 11 includes the first surface 101 and the second surface 102 opposite to the first surface 101 along the first direction D1. The edge structure 12 includes the first chamfered portion connected to the first surface 101, the second chamfered portion connected to the second surface 102, and a connecting portion located between the first chamfered portion and the second chamfered portion, and one end of the connecting portion is connected to the first chamfered portion and the other end is connected to the second chamfered portion, that is, the first chamfered portion and the second chamfered portion are connected through the connecting portion. The first chamfered portion has a first width length X1, and the second chamfered portion has a second width length X2. The first width length refers to the length of the orthographic projection of the first chamfered portion on the plane where the first surface 101 is located (for example, the length along the second direction D2). The second width length refers to the length of the orthographic projection of the second chamfered portion on the plane where the second surface 102 is located (for example, the length along the second direction D2). In one example, the first chamfered portion and the second chamfered portion are symmetrically distributed about the center of the edge structure 12 to further simplify the formation process of the wafer 10.

[0039] This specific embodiment shortens the length of the first width X1. On the one hand, when an epitaxial layer is formed on the first surface 101 of the wafer 10 by an epitaxial process, the shorter first width X1 can reduce the collapsed edge width of the epitaxial layer formed on the first surface 101 of the wafer 10 (i.e., the width of the inclined surface caused by the height of the edge portion of the epitaxial layer being lower than the height of the middle portion), thereby improving the yield of the semiconductor structure; on the other hand, it improves the edge morphology of the epitaxial layer formed on the first surface 101 of the wafer 10, blunts the "knife-shaped" edge of the epitaxial layer, and reduces the probability of cracking of the epitaxial wafer during thinning of the wafer.

[0040] In some embodiments, the edge structure 12 is an R-shaped chamfered structure or a T-shaped chamfered structure.

[0041] In one example, if Figure 1 As described above, the edge structure 12 is a T-shaped chamfered structure. In another example, as Figure 2As shown, the edge structure 12 is an R-type chamfer structure. For example, when the edge structure 12 is a T-type chamfer structure or an R-type chamfer structure, the first length X1 of the first chamfer portion is equal to the second length X2 of the second chamfer portion; or, considering the chamfering process error, the difference between the first length X1 of the first chamfer portion and the second length X2 of the second chamfer portion is less than a first preset value. Wherein, the first preset value is less than 100μm. There is a first angle A1 between the first chamfer portion and the first surface 101, and there is a second angle A2 between the second chamfer portion and the second surface 102, and the first angle A1 and the second angle A2 are both 10° to 12°.

[0042] In some embodiments, the first width X1 is 200 μm to 400 μm.

[0043] In some embodiments, the first width X1 is 300 μm.

[0044] For example, the first width length X1 and the second width length X2 are both 200 μm to 400 μm, so as to ensure that the chamfer structure is retained at the edge of the wafer 10, improve the chamfer morphology after the subsequent epitaxy of the wafer 10, and reduce the cracking rate of the wafer 10 during the thinning process. In one example, the first width length X1 and the second width length X2 are both 300 μm.

[0045] This specific embodiment also provides a method for forming a semiconductor structure. Figure 3 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention. Figure 1-Figure 3 As shown, the method for forming the semiconductor structure comprises the following steps:

[0046] Step S31, forming a wafer 10, wherein the wafer 10 includes a main body structure 11 and an edge structure 12 connected to an end of the main body structure 11 along a second direction D2, wherein the main body structure 11 includes a first surface 101 and a second surface 102 relatively distributed along a first direction D1, wherein the edge structure 12 includes at least a first chamfered portion connected to the first surface 101 and a second chamfered portion connected to the second surface 102, wherein the first chamfered portion is connected to the second chamfered portion, wherein the first chamfered portion has a first width length X1, and the first width length X1 is less than 600 μm, wherein the second direction D2 intersects the first direction D1 perpendicularly;

[0047] Step S32, forming an epitaxial layer on the first surface 101, the first chamfered portion, and the second chamfered portion of the wafer 10;

[0048] Step S33 , thinning the wafer 10 starting from the second surface 102 of the wafer 10 .

[0049] The schematic diagram of the wafer chamfer morphology structure formed in this specific embodiment can be seen in Figure 1 and Figure 2 In some embodiments, Figure 1 and Figure 2 As shown, the specific steps of forming a wafer include:

[0050] Providing a wafer 10 with a (111) crystal orientation;

[0051] The edge of the wafer 10 is chamfered to form the edge structure 12 including the first chamfered portion and the second chamfered portion.

[0052] In some embodiments, the first width X1 is 200 μm to 400 μm.

[0053] Figure 4 is a schematic diagram of a structure after an epitaxial layer is formed on a wafer according to a specific embodiment of the present invention. Figure 6 1 is a schematic diagram of a structure after an epitaxial layer is formed on another wafer according to a specific embodiment of the present invention. For example, by chamfering the edge of the wafer 10 with a (111) crystal orientation, the edge structure 12 of the wafer 10 has the following shape: Figure 4 The T-shaped chamfer structure shown or Figure 6 The R-type chamfer morphology structure, and the first width length X1 of the first chamfered portion 41 and the second width length X2 of the second chamfered portion 42 are both 300μm. Then, an epitaxial process is used to form an epitaxial layer 40 on the first surface 101, the first chamfered portion and the second chamfered portion of the wafer 10, and the epitaxial layer 40 extends to the surface of the first chamfered portion 41 and the surface of the second chamfered portion 42, and the thickness of the epitaxial layer 40 gradually decreases in the direction from the first chamfered portion 41 to the second chamfered portion 42. The top surface of the epitaxial layer 40 located on the first chamfered portion 41 is lower than the epitaxial layer 40 located on the first surface 101, forming a collapsed edge. Since the first width X1 of the first chamfered portion 41 is 200μm to 400μm (for example, 300μm), on the one hand, the collapsed edge width of the epitaxial layer 40 formed on the first surface 101 of the wafer 10 can be shortened, thereby improving the yield of the semiconductor structure; on the other hand, the edge morphology of the epitaxial layer 40 formed on the first surface 101 of the wafer 10 is improved, the "knife-shaped" edge of the epitaxial layer is improved, and the cracking rate of the wafer 10 during the thinning process is reduced.

[0054] In some embodiments, the specific steps of thinning the wafer 10 starting from the second surface 102 of the wafer 10 include:

[0055] The wafer 10 is thinned starting from the second surface 102 of the wafer 10 until at least the second chamfered portion 42 is completely removed.

[0056] Figure 5 is a schematic structural diagram of a wafer after thinning according to a specific embodiment of the present invention, Figure 7 is a schematic diagram of the structure of another wafer after thinning according to a specific embodiment of the present invention, wherein: Figure 5 This is a schematic diagram of the structure of a wafer with a T-shaped chamfered edge structure after thinning. Figure 7 It is a schematic diagram of the structure after the wafer with an R-type chamfered edge structure is thinned. For example, a grinding process can be used to thin the wafer 10 starting from the second surface 102 of the wafer 10 until at least the second chamfered portion 42 is completely removed, thereby ensuring that the requirements of the wafer are met and the physical strength, heat dissipation and size requirements of the wafer chip are improved. After the thinning process, the first surface 101 of the wafer 10 is used as the front side of the wafer 10, and the surface opposite to the front side of the wafer 10 along the first direction D1 is used as the back side of the wafer 10.

[0057] This specific embodiment also provides a semiconductor structure. The semiconductor structure can be used as follows Figure 3-Figure 7 The semiconductor structure is formed by the method of forming the semiconductor structure shown in FIG. Figure 5 and Figure 7 , the schematic diagram of the wafer in the semiconductor structure can be seen in Figure 1 and Figure 2 .like Figure 1-Figure 7 As shown, the semiconductor structure comprises:

[0058] A wafer 10 includes a main body structure 11 and an edge structure 12 connected to an end of the main body structure 11 along a second direction D2, wherein the main body structure 11 includes a front side and a back side relatively distributed along a first direction D1, and the edge structure 12 includes at least a first chamfered portion 41 connected to the front side, wherein the first chamfered portion 41 has a first width length X1, and the first width length X1 is less than 600 μm, wherein the second direction D2 intersects the first direction D1 perpendicularly;

[0059] The epitaxial layer 40 covers the front surface of the wafer 10 , and includes a first portion covering the main structure 11 and a second portion covering the first chamfered portion 41 , wherein the second portion is lower than the first portion.

[0060] In some embodiments, the first width X1 is 300 μm, and the width of the second portion along the second direction D2 is less than 1.5 μm.

[0061] For example, when the wafer 10 formed by the chamfering process has a T-shaped chamfer structure, and the first width X1 is 300 μm, the minimum value of the collapsed edge width (i.e., the width of the second portion) is 1.07 μm, the maximum value of the collapsed edge width is 1.193 μm, and the average value of the collapsed edge width is 1.149 μm. When the wafer 10 formed by the chamfering process has an R-shaped chamfer structure, and the first width X1 is 300 μm, the minimum value of the collapsed edge width (i.e., the width of the second portion) is 1.174 μm, the maximum value of the collapsed edge width is 1.41 μm, and the average value of the collapsed edge width is 1.285 μm.

[0062] The wafer, semiconductor structure and formation method thereof provided in this specific embodiment can reduce the collapsed edge width of the epitaxial layer formed on the first surface of the wafer by shortening the first width to less than 600 μm, thereby improving the yield of the semiconductor structure; on the other hand, it improves the edge morphology of the epitaxial layer formed on the first surface of the wafer, improves the "knife-shaped" epitaxial chamfer edge, and reduces the wafer cracking rate during the thinning process.

[0063] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A wafer, characterized in that: include: The body structure comprises a first surface and a second surface which are oppositely distributed along a first direction; An edge structure is connected to the end of the main body structure along a second direction, the edge structure at least includes a first chamfered portion connected to the first surface and a second chamfered portion connected to the second surface, the first chamfered portion is connected to the second chamfered portion, the first chamfered portion has a first length, and the first length is less than 600 μm, wherein the second direction intersects the first direction perpendicularly.

2. The wafer according to claim 1, characterized in that The edge structure is an R-shaped chamfer structure or a T-shaped chamfer structure.

3. The wafer according to claim 1, characterized in that The first width is 200 μm to 400 μm long.

4. The wafer according to claim 3, characterized in that The first width is 300 μm long.

5. A method for forming a semiconductor structure, characterized in that: The steps include: Forming a wafer, the wafer comprising a main body structure and an edge structure connected to an end of the main body structure along a second direction, the main body structure comprising a first surface and a second surface relatively distributed along a first direction, the edge structure comprising at least a first chamfered portion connected to the first surface and a second chamfered portion connected to the second surface, the first chamfered portion being connected to the second chamfered portion, the first chamfered portion having a first width length, and the first width length being less than 600 μm, wherein the second direction intersects the first direction perpendicularly; forming an epitaxial layer on the first surface, the first chamfered portion, and the second chamfered portion of the wafer; The wafer is thinned starting from the second surface of the wafer.

6. The method for forming a semiconductor structure according to claim 5, characterized in that: The specific steps to form a wafer include: Providing a wafer with a (111) crystal orientation; The edge of the wafer is chamfered to form the edge structure including the first chamfered portion and the second chamfered portion.

7. The method for forming a semiconductor structure according to claim 5, characterized in that: The first width is 200 μm to 400 μm long.

8. The method for forming a semiconductor structure according to claim 5, characterized in that: The specific steps of thinning the wafer starting from the second surface of the wafer include: The wafer is thinned starting from the second surface of the wafer until at least the second chamfered portion is completely removed.

9. A semiconductor structure, characterized in that: include: A wafer, comprising a main body structure and an edge structure connected to an end of the main body structure along a second direction, wherein the main body structure comprises a front side and a back side relatively distributed along a first direction, and the edge structure comprises at least a first chamfered portion connected to the front side, wherein the first chamfered portion has a first width length, and the first width length is less than 600 μm, wherein the second direction intersects the first direction perpendicularly; An epitaxial layer is covered on the front side of the wafer, wherein the epitaxial layer includes a first portion covering the main structure and a second portion covering the first chamfered portion, and the second portion is lower than the first portion.

10. The semiconductor structure according to claim 9, characterized in that: The first width is 300 μm, and the width of the second portion along the second direction is less than 1.5 μm.

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