Power semiconductor device and preparation method

Abstract

The invention discloses a power semiconductor device and a preparation method, the power semiconductor device comprises a field plate structure layer, an epitaxial layer and a substrate layer, the epitaxial layer is internally provided with a main junction region and a plurality of field limiting ring structure regions which are arranged at intervals and surround the main junction region, and the main junction region and the field limiting ring structure regions extend into the interior from a first surface of the epitaxial layer. The field plate structure layer is arranged on the first surface of the epitaxial layer and is connected with at least one field limiting ring structure region, and in the direction away from the main junction region, the sectional areas of the multiple field limiting ring structure regions are decreased progressively, and the spacing distances between the main junction region and the multiple field limiting ring structure regions are decreased progressively; the field plate structure layer is a metal layer, the epitaxial layer and the substrate layer are both semiconductor structures of a first conductive type, and the main junction region and the field limiting ring structure region are both semiconductor structures of a second conductive type. According to the power semiconductor device and the preparation method, low sensitivity to movable charges can be kept, high breakdown voltage is achieved, the voltage resistance of the device is guaranteed, and the reliability of the device is high.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a power semiconductor device and a preparation method thereof. Background Art

[0002] Power semiconductor devices are commonly used semiconductor devices for power conversion and processing. Their main feature is the ability to block high voltage, which is specifically reflected in the breakdown voltage and voltage resistance performance of power semiconductor devices.

[0003] In order to improve the blocking voltage of power semiconductor devices, a field limiting ring structure is usually used as the terminal structure of power semiconductor devices. The commonly used field limiting ring structure is a plurality of ring structures surrounding the main junction of the semiconductor device to reduce the high electric field caused by the curvature effect on the surface of the PN junction, and at the same time expand the width of the depletion region, thereby increasing the breakdown voltage. However, although the current field limiting ring structure can meet certain withstand voltage requirements, a larger number of field limiting ring structures are required in the high voltage field. However, the terminal structure composed of multiple field limiting rings is highly sensitive to movable charges. As the interface charge of the semiconductor device increases, the breakdown voltage decreases significantly, resulting in a sharp decrease in withstand voltage performance and low overall reliability of the device. Summary of the invention

[0004] The present application provides a power semiconductor device and a preparation method thereof, which can maintain a low sensitivity to movable charges and have a high breakdown voltage and withstand voltage performance, thereby meeting the reliability of the device.

[0005] The present application provides a power semiconductor device, which includes a stacked field plate structure layer, an epitaxial layer and a substrate layer, wherein a main junction region and a plurality of field limiting ring structure regions spaced apart and surrounding the main junction region are provided in the epitaxial layer, the main junction region and the field limiting ring structure region both extend from a first surface of the epitaxial layer to the inside, the field plate structure layer is provided on the first surface of the epitaxial layer and is connected to at least one field limiting ring structure region, and along a direction away from the main junction region, the cross-sectional areas of the plurality of field limiting ring structure regions present a decreasing trend and the spacing distances between the main junction region and the plurality of field limiting ring structure regions present a decreasing trend; wherein the field plate structure layer is a patterned metal layer, the epitaxial layer and the substrate layer are both semiconductor structures having a first conductivity type, and the main junction region and the field limiting ring structure region are both semiconductor structures having a second conductivity type.

[0006] The power semiconductor device as above, wherein the power semiconductor device further comprises an isolation layer, the isolation layer is arranged on the first surface of the epitaxial layer, the isolation layer has at least one connecting portion arranged therethrough, and the field plate structure layer is connected to at least one field limiting ring structure region through the connecting portion.

[0007] As above, the field plate structure layer includes at least one field plate structure, the field plate structure includes a field limiting ring connection portion and a first conductive connection portion connected to each other, each field limiting ring connection portion is arranged in a corresponding connecting portion and connected to a corresponding field limiting ring structure region, and the first conductive connection portion is arranged on a side of the isolation layer facing away from the field limiting ring structure region.

[0008] In the power semiconductor device as above, the outermost field plate structure also includes a second conductive connection portion, which extends in a direction away from the main junction region. The second conductive connection portion includes two stacked conductive connection layers, and the projections of the two conductive connection layers on the first surface of the epitaxial layer are overlapped.

[0009] In the power semiconductor device as above, the first conductive connection portion of the field plate structure and a projection of a field limiting ring structure region adjacent to one side of the field plate structure on the first surface of the epitaxial layer are arranged to at least partially overlap.

[0010] In the power semiconductor device as above, the field plate structure layer has two field plate structures, and the two field plate structures are respectively connected to the innermost and outermost two field limiting ring structure regions.

[0011] As above, the power semiconductor device, wherein the isolation layer includes a plurality of isolation structures spaced apart in a direction away from the main junction region, a connecting portion is formed between adjacent isolation structures, the outermost isolation structure is arranged between the second conductive connection portion and the first surface of the epitaxial layer, and the isolation structure is a stepped structure adapted to the shape of the second conductive connection portion.

[0012] In the power semiconductor device as above, in the direction away from the main junction region, the extension depths of the plurality of field limiting ring structure regions extending inward from the first surface of the epitaxial layer show a decreasing trend.

[0013] The power semiconductor device as above, wherein the power semiconductor device further comprises a cut-off region, which is arranged at intervals on a side of the plurality of field limiting ring structure regions away from the main junction region, and the cut-off region is a semiconductor structure having a first conductivity type.

[0014] On the other hand, the present application also provides a method for preparing a power semiconductor device, which comprises: Performing epitaxial growth on one side of the substrate layer to form an epitaxial layer, wherein the epitaxial layer is a semiconductor structure having a first conductivity type; Ion implantation is performed on the first surface of the epitaxial layer to form a main junction region and a plurality of field limiting ring structure regions arranged at intervals, wherein the main junction region and the plurality of field limiting ring structure regions arranged at intervals are semiconductor structures having a second conductivity type; Performing high temperature push-junction on the main junction region and multiple field limiting ring structure regions to form multiple field limiting ring structure regions with decreasing cross-sectional areas and spacing distances; An isolation layer is formed on the first surface of the epitaxial layer, and a plurality of connecting portions corresponding to the plurality of field limiting ring structure regions are formed by etching; forming a metal layer on the surfaces of the isolation layer and the plurality of connecting portions and performing patterning to form at least one field plate structure of the field plate structure layer; A passivation layer is formed on the surfaces of the field plate structure layer and the isolation layer.

[0015] The method for preparing a power semiconductor device as above, wherein ion implantation is performed on the first surface of the epitaxial layer to form a main junction region and a plurality of spaced field limiting ring structure regions, specifically includes: forming an oxide layer of uniform thickness on the first surface of the epitaxial layer; processing the thickness of the oxide layer to form an oxide layer having a plurality of oxide regions with different thicknesses; providing a plurality of isolation structures at the connection between the oxide regions and the oxide regions on both sides; implanting ions from the oxide regions between adjacent isolation structures into the epitaxial layer to form a main junction region and a plurality of field limiting ring structure regions; and removing the oxide layer and the isolation structure.

[0016] The method for preparing a power semiconductor device as above, wherein the step of performing ion implantation on the first surface of the epitaxial layer to form a main junction region and a plurality of spaced field limiting ring structure regions, specifically includes: forming an oxide layer of uniform thickness on the first surface of the epitaxial layer; providing an isolation structure on the surface of the oxide layer and forming an implantation region; performing ion implantation from the oxide layer in the implantation region toward the epitaxial layer to form a main junction region; providing isolation structures on the surface of the oxide layer in a direction away from the main junction region and forming implantation regions in different positions in sequence; performing ion implantation in the implantation regions in different positions in sequence to form a plurality of field limiting ring structure regions; and removing the oxide layer and the isolation structure.

[0017] The method for preparing a power semiconductor device as described above, wherein the step of performing high-temperature push-junction on the main junction region and multiple field limiting ring structure regions specifically includes: performing high-temperature push-junction on the main junction region and the innermost field limiting ring structure region with the same total thermal time; and performing high-temperature push-junction on each field limiting ring structure region in turn with decreasing total thermal time in a direction away from the main junction region.

[0018] The power semiconductor device of the present application includes a stacked field plate structure layer, an epitaxial layer and a substrate layer. The epitaxial layer has a main junction region and multiple field limiting ring structure regions surrounding the main junction region. In the direction away from the main junction region, the area of ​​the field limiting ring structure region is decreasing and the spacing distance between the main junction region and the multiple field limiting ring structure regions is decreasing, so that the contact area between each field limiting ring structure region and the epitaxial layer is gradually reduced. When the interface charge increases, the change rate of the breakdown voltage is small. Therefore, the power semiconductor device has a low sensitivity to movable charges and can maintain a high breakdown voltage. In addition, the field plate structure layer is also connected to at least one field limiting ring structure region. The field plate structure layer can modulate the electric field distribution, further ensuring a high breakdown voltage, thereby ensuring the voltage resistance performance of the power semiconductor device, thereby ensuring the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 A schematic diagram of the structure of a power semiconductor device according to an embodiment of the present application; Figure 2 A flowchart of a method for preparing a power semiconductor device according to an embodiment of the present application; Figure 3 A schematic diagram of the structure of multiple oxidation regions in a first method for preparing a power semiconductor device according to an embodiment of the present application; Figure 4 A schematic diagram of multiple isolation structures in a first method for preparing a power semiconductor device according to an embodiment of the present application; Figure 5 A diagram showing the relationship between the thickness of each oxide region and the junction depth of each field limiting ring structure region in the first method for preparing the power semiconductor device according to an embodiment of the present application; Figure 6 A schematic diagram of forming a main junction region and an adjacent field limiting ring structure region in a second method for preparing a power semiconductor device according to an embodiment of the present application; Figure 7 A schematic diagram of forming other field limiting ring structure regions in the second method for preparing a power semiconductor device according to an embodiment of the present application; Figure 8 A diagram showing the relationship between ion implantation energy and junction depth of a field limiting ring structure region in a second method for preparing a power semiconductor device according to an embodiment of the present application; Fig. 9 A comparison diagram of the sensitivity of the power semiconductor device according to the embodiment of the present application to variable charges with a conventional field limiting ring structure and a junction terminal extension structure.

[0021] Description of Figure Numbers: 10. Field plate structure layer; 11. Field plate structure; 111. Field limiting ring connection part; 112. First conductive connection part; 113. Second conductive connection part; 114. Conductive connection layer; 20. Epitaxial layer; 30. Substrate layer; 40. Main junction region; 50. Field limiting ring structure region; 60. Isolation layer; 61. Connecting part; 62. Isolation structure; 70. Cut-off region; 80. First electrode layer; 90. Second electrode layer; 110. Oxide layer; 120. Isolation structure; 121. Injection region; 130. Oxide region. DETAILED DESCRIPTION

[0022] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0023] like Figure 1 As shown, an embodiment of the present application provides a power semiconductor device, which includes a stacked field plate structure layer 10, an epitaxial layer 20 and a substrate layer 30, wherein a main junction region 40 and a plurality of field limiting ring structure regions 50 spaced apart and surrounding the main junction region 40 are provided in the epitaxial layer 20, the main junction region 40 and the field limiting ring structure region 50 both extend from the first surface of the epitaxial layer 20 to the inside, the field plate structure layer 10 is provided on the first surface of the epitaxial layer 20 and is connected to at least one field limiting ring structure region 50, and along the direction away from the main junction region 40, the cross-sectional areas of the plurality of field limiting ring structure regions 50 show a decreasing trend and the spacing distances between the main junction region 40 and the plurality of field limiting ring structure regions 50 show a decreasing trend; wherein the field plate structure layer 10 is a patterned metal layer, the epitaxial layer 20 and the substrate layer 30 are both semiconductor structures having a first conductivity type, and the main junction region 40 and the field limiting ring structure region 50 are both semiconductor structures having a second conductivity type.

[0024] In the embodiment of the present application, the spacing distance between the main junction region 40 and the multiple field limiting ring structure regions 50 shows a decreasing trend, that is, the spacing distance between the main junction region 40 and its adjacent field limiting ring structure region 50 is the largest, the spacing distance between each two adjacent field limiting ring structure regions 50 gradually decreases, and the spacing distance between the two field limiting ring structure regions 50 farthest from the main junction region 40 is the smallest.

[0025] It should be noted that the first conductivity type semiconductor structure of the embodiment of the present application is an N-type semiconductor, and the second conductivity type semiconductor structure is a P-type semiconductor.

[0026] In a specific implementation, the power semiconductor device of the present application includes a stacked field plate structure layer 10, an epitaxial layer 20 and a substrate layer 30. The epitaxial layer 20 has a main junction region 40 and a plurality of field limiting ring structure regions 50 surrounding the main junction region 40. In the direction away from the main junction region 40, the area of ​​the field limiting ring structure region 50 is decreasing and the spacing distance between the main junction region 40 and the plurality of field limiting ring structure regions 50 is decreasing, so that the contact area between each field limiting ring structure region 50 and the epitaxial layer 20 is gradually reduced. When the interface charge increases, the rate of change of the breakdown voltage is small. Therefore, the power semiconductor device has a low sensitivity to movable charges and can maintain a high breakdown voltage. Moreover, the field plate structure layer 10 is also connected to at least one field limiting ring structure region 50. The field plate structure layer 10 can modulate the electric field distribution, further ensuring a high breakdown voltage, thereby ensuring the withstand voltage performance of the power semiconductor device, thereby ensuring the reliability of the device.

[0027] like Fig. 9 As shown, compared with the conventional power semiconductor device having multiple field limiting ring structure regions 50 of the same area and the power semiconductor device having a junction terminal extension structure, the power semiconductor device of the embodiment of the present application has a smaller breakdown voltage drop as the interface charge increases, which shows that the power semiconductor device of the present application has a lower sensitivity to movable charge, even if it reaches 5*10 12 cm -2 The power semiconductor device of the embodiment of the present application can still maintain a relatively high breakdown voltage and has good withstand voltage performance, thereby ensuring good stability of the device.

[0028] Moreover, the area of ​​the field limiting ring structure region 50 gradually decreases and the spacing distance between the main junction region 40 and multiple field limiting ring structure regions 50 shows a decreasing trend. When the number of field limiting ring structure regions 50 is small and the extension distance is short, the demand for higher breakdown voltage can be met. There is no need to use a larger chip area to arrange the field limiting ring structure region 50. The chip can be reduced in size by about 15%, thereby meeting the miniaturization demand of the chip and reducing manufacturing costs.

[0029] Specifically, the power semiconductor device also includes a first electrode layer 80 and a second electrode layer 90. The first electrode layer 80 is arranged on the first surface of the epitaxial layer 20 and connected to the main junction region 40, serving as the source of the power semiconductor device; the second electrode layer 90 covers the surface of the substrate layer 30 facing away from the epitaxial layer 20, serving as the drain of the power semiconductor device.

[0030] The power semiconductor device of the embodiment of the present application, wherein the power semiconductor device also includes an isolation layer 60, which is arranged on the first surface of the epitaxial layer 20, and the isolation layer 60 has at least one connecting portion 61 arranged therethrough, and the field plate structure layer 10 is connected to at least one field limiting ring structure area 50 through the connecting portion 61.

[0031] The power semiconductor device of the embodiment of the present application, wherein the field plate structure layer 10 includes at least one field plate structure 11, the field plate structure 11 includes a field limiting ring connection portion 111 and a first conductive connection portion 112 connected to each other, each field limiting ring connection portion 111 is arranged in a corresponding connecting portion 61 and connected to a corresponding field limiting ring structure region 50, and the first conductive connection portion 112 is arranged on a side of the isolation layer 60 that is away from the field limiting ring structure region 50.

[0032] The isolation layer 60 is a layer structure formed by oxide, and the oxide is specifically silicon oxide. The isolation layer 60 has at least one connecting portion 61 that is arranged therethrough. The field limiting ring connecting portion 111 of each field plate structure 11 can be arranged in the connecting portion 61 and connected to the field limiting ring structure area 50. The isolation layer 60 can isolate multiple field limiting ring connecting portions 111 connected to different field limiting ring structure areas 50 to avoid conductive connections between them.

[0033] Furthermore, the first electrode layer 80 is also disposed in one of the connecting portions 61 of the isolation layer 60 . The connecting portion 61 is connected to the main junction region 40 , so that the first electrode layer 80 can contact the main junction region 40 , thereby serving as the source of the power semiconductor device.

[0034] The field limiting ring connecting portion 111 of each field plate structure 11 is used to conduction connect with the field limiting ring structure area 50, and the first conductive connecting portion 112 connected to the field limiting ring connecting portion 111 is arranged on the side of the isolation layer 60 facing away from the field limiting ring structure area 50, and can cover the surface of the isolation layer 60, thereby increasing the length and coverage area of ​​the field plate structure 11, further optimizing the overall electric field distribution, reducing the sensitivity to movable charges, and increasing the breakdown voltage of the power semiconductor device.

[0035] The power semiconductor device of the embodiment of the present application, wherein the outermost field plate structure 11 also includes a second conductive connection portion 113, the second conductive connection portion 113 extends in a direction away from the main junction region 40, and the second conductive connection portion 113 includes two stacked conductive connection layers 114, and the projections of the two conductive connection layers 114 on the first surface of the epitaxial layer 20 are partially overlapped.

[0036] In the outermost field plate structure 11, a first conductive connection portion 112 and a second conductive connection portion 113 are included, both of which are connected to the field limiting ring connection portion 111 but extend in opposite directions, and both cover the surface of the isolation layer 60, wherein the second conductive connection portion 113 extends in a direction away from the main junction region 40, and is an edge structure of the field plate structure layer 10. At the same time, since it is connected to the outermost field limiting ring structure area 50, it is also arranged at the edge of the overall depletion region. The second conductive connection portion 113 includes two stacked conductive connection layers 114, and the projections of the two conductive connection layers 114 on the first surface of the epitaxial layer 20 are arranged overlappingly, thereby forming a stepped structure of the edge. The structural setting of the stepped structure is combined with multiple gradient field limiting ring structure areas 50, which can reduce the electric field strength and surface electric field peak at the edge of the field plate structure layer 10, thereby realizing the modulation of the electric field distribution, reducing the sensitivity to movable charges, and improving the breakdown voltage of the power semiconductor device, and improving the overall withstand voltage performance and device reliability.

[0037] In the power semiconductor device of the embodiment of the present application, the first conductive connection portion 112 of the field plate structure 11 and the projection of the field limiting ring structure region 50 adjacent to one side of the field plate structure 11 on the first surface of the epitaxial layer 20 are at least partially overlapped.

[0038] It should be noted that the first conductive connection portion 112 of the field plate structure 11 is connected to the corresponding field limiting ring structure region 50 through the field limiting ring connection portion 111, and the projection of the first conductive connection portion 112 can overlap with the partial projection of the field limiting ring structure region 50 adjacent to the field limiting ring structure region 50 connected to it, that is, the projections of the two partially overlap, and the first conductive connection portion 112 can partially cover the corresponding isolation layer on this adjacent field limiting ring structure region 50.

[0039] In the power semiconductor device of the embodiment of the present application, the field plate structure layer 10 has two field plate structures 11 , and the two field plate structures 11 are respectively connected to the innermost and outermost two field limiting ring structure regions 50 .

[0040] In a specific implementation, the two field plate structures 11 of the field plate structure layer 10 are respectively connected to the two innermost and outermost field limiting ring structure areas 50, and the first conductive connection parts 112 of the two field plate structures 11 extend in opposite directions, that is, the extension directions of the two first conductive connection parts 112 are opposite, and the projections of the two first conductive connection parts 112 can overlap with the projections of the innermost second field limiting ring structure area 50 and the outermost second field limiting ring structure area 50, respectively, so that it can be ensured that the first conductive connection parts 112 can cover the adjacent field limiting ring structure areas 50 and the corresponding parts of the isolation layer 60, further optimizing the electric field distribution, reducing the sensitivity to movable charges, and improving the device breakdown voltage, thereby improving the overall reliability of the device.

[0041] The power semiconductor device of the embodiment of the present application, wherein the isolation layer 60 includes a plurality of isolation structures 62 spaced apart in a direction away from the main junction region 40, a connecting portion 61 is formed between adjacent isolation structures 62, the outermost isolation structure 62 is arranged between the second conductive connection portion 113 and the first surface of the epitaxial layer 20, and this isolation structure 62 has a stepped structure adapted to the shape of the second conductive connection portion 113.

[0042] Among the multiple isolation structures 62 of the isolation layer 60, the outermost isolation structure 62 is arranged corresponding to the second conductive connection part 113, and its structure is a stepped structure adapted to the shape of the second conductive connection part 113. It can fit with the bottom surfaces of the two conductive connection layers 114 of the second conductive connection part 113, thereby avoiding the occurrence of a peak electric field on the surface of the isolation layer 60 and improving the voltage resistance performance of the power semiconductor device.

[0043] In the power semiconductor device of the embodiment of the present application, the extension depth of the multiple field limiting ring structure regions 50 extending inward from the first surface of the epitaxial layer 20 shows a decreasing trend along the direction away from the main junction region 40, that is, the junction depth of the multiple field limiting ring structure regions 50 shows a decreasing trend. By setting the decreasing junction depth of each field limiting ring structure region 50, the decreasing area of ​​each field limiting ring structure region 50 can be achieved, thereby achieving an increase in the breakdown voltage, and only different junction depth settings are performed, the process is simple, and the operation is convenient, and there is no need to perform accurate area measurement on the first surface of the epitaxial layer 20.

[0044] Specifically, the junction depth of the innermost field limiting ring structure region 50 is the same as the junction depth of the main junction region 40 .

[0045] The power semiconductor device of the embodiment of the present application further includes a cut-off region 70 , which is arranged at intervals on one side of the plurality of field limiting ring structure regions 50 away from the main junction region 40 , and is a semiconductor structure having a first conductivity type.

[0046] In a specific implementation, the depletion region of the main junction region 40 is extended along the arrangement direction of the field limiting ring structure region 50, and a cut-off region 70 is provided on the side of the plurality of field limiting ring structure regions 50 away from the main junction region 40, which can effectively block the extension of the depletion region and prevent the depletion region from extending in a direction away from the main junction region 40, thereby avoiding affecting the breakdown voltage and withstand voltage performance of the power semiconductor device.

[0047] Specifically, the outermost isolation structure 62 can extend from the outermost field limiting ring structure region 50 to the cut-off region 70 .

[0048] The present application also provides a method for preparing a power semiconductor device, which includes: S110, performing epitaxial growth on one side of the substrate layer 30 to form an epitaxial layer 20, wherein the epitaxial layer 20 is a semiconductor structure having a first conductivity type; S120, performing ion implantation on the first surface of the epitaxial layer 20 to form a main junction region 40 and a plurality of spaced field limiting ring structure regions 50, wherein the main junction region 40 and the plurality of spaced field limiting ring structure regions 50 are semiconductor structures having a second conductivity type; The plurality of field limiting ring structure regions 50 are arranged at intervals and surround the main junction region 40, and the plurality of annular field limiting ring structure regions 50 are centered on the main junction region 40; S130, performing high temperature push-junction on the main junction region 40 and the plurality of field limiting ring structure regions 50, so as to form a plurality of field limiting ring structure regions 50 whose cross-sectional areas and spacing distances are both decreasing; In which, along the direction away from the field limiting ring structure region 50, the spacing distance between the field limiting ring structure regions 50 gradually decreases, and the cross-sectional area of ​​each field limiting ring structure region 50 gradually decreases; S140, forming an isolation layer 60 on the first surface of the epitaxial layer 20, and etching to form a plurality of connecting portions 61 corresponding to the plurality of field limiting ring structure regions 50; The isolation layer 60 is separated by a plurality of connecting portions 61 to form a plurality of isolation structures 62. At the corresponding position of the main junction region 40, the isolation layer 60 also has a correspondingly arranged connecting portion 61; and the outermost isolation structure 62 of the isolation layer 60 is etched to form a stepped structure. S150, forming a metal layer on the surfaces of the isolation layer 60 and the plurality of connecting portions 61 and performing patterning to form at least one field plate structure 11 of the field plate structure layer 10, wherein the outermost field plate structure 11 includes a first conductive connection portion 112 and a second conductive connection portion 113 extending in opposite directions, and the remaining field plate structures 11 include only the first conductive connection portion 112, and the second conductive connection portion 113 of the outermost field plate structure 11 includes two conductive connection layers 114 partially overlapping each other to form a stepped structure, and the second conductive connection layer 114 covers the stepped structure of the outermost isolation structure 62; The field plate structure 11 can be formed in the connecting portion 61 connected to the field limiting ring structure region 50, and while forming the metal layer, the first electrode layer 80 can also be formed in the connecting portion 61 connected to the main junction region 40, thereby forming the source of the power semiconductor device; S160 , forming a passivation layer on the surface of the field plate structure layer 10 and the isolation layer 60 . The passivation layer can protect the entire device and has an insulating effect.

[0049] After forming the passivation layer, the method further includes forming a second electrode layer 90 on the other side of the substrate layer 30 to serve as a drain of the power semiconductor device.

[0050] In specific implementation, the preparation method of the power semiconductor device of the embodiment of the present application is adopted to realize the preparation of the power semiconductor device, which includes a stacked field plate structure layer 10, an epitaxial layer 20 and a substrate layer 30, wherein the epitaxial layer 20 has a main junction region 40 and a plurality of field limiting ring structure regions 50 surrounding the main junction region 40, and the area of ​​the field limiting ring structure region 50 is decreasing in the direction away from the main junction region 40 and the spacing distance between the main junction region 40 and the plurality of field limiting ring structure regions 50 is decreasing, so that the contact area between each field limiting ring structure region 50 and the epitaxial layer 20 is gradually reduced, and when the interface charge increases, the change rate of the breakdown voltage is small, so the power semiconductor device has a low sensitivity to the movable charge and can maintain a high breakdown voltage, and the field plate structure layer 10 is also connected to at least one field limiting ring structure region 50, and the field plate structure layer 10 can modulate the electric field distribution, further ensuring a high breakdown voltage, thereby ensuring the withstand voltage performance of the power semiconductor device, thereby ensuring the reliability of the device.

[0051] Moreover, the area of ​​the field limiting ring structure region 50 gradually decreases and the spacing distance between the main junction region 40 and multiple field limiting ring structure regions 50 shows a decreasing trend. When the number of field limiting ring structure regions 50 is small and the extension distance is short, the demand for higher breakdown voltage can be met, and there is no need to use a larger chip area to arrange the field limiting ring structure region 50, thereby meeting the miniaturization demand of the chip and reducing the manufacturing cost.

[0052] like Figure 3 and Figure 4 As shown, the method for preparing a power semiconductor device in an embodiment of the present application, wherein the step of performing ion implantation on the first surface of the epitaxial layer 20 to form a main junction region 40 and a plurality of spaced field limiting ring structure regions 50 specifically includes: An oxide layer 110 with uniform thickness is formed on the first surface of the epitaxial layer 20 . The oxide layer 110 is used for ion implantation and is not a structure of a power semiconductor device. The thickness of the oxide layer 110 is processed to form an oxide layer 110 having a plurality of oxide regions 130 with different thicknesses; wherein the oxide layer 110 is divided into a plurality of oxide regions 130, and different oxide regions 130 have different thicknesses, and the plurality of oxide regions 130 can form a stepped surface structure, and the extension length of each oxide region 130 in the horizontal direction also tends to gradually increase or decrease; A plurality of isolation structures 120 are provided at the connection of each oxidation region 130 and the oxidation regions 130 on both sides; wherein the isolation structures 120 can be formed by using a mask, and the distance between the isolation structures 120 also tends to gradually increase or decrease; Ion implantation is performed from the oxide region 130 between adjacent isolation structures 120 toward the epitaxial layer 20 to form a main junction region 40 and a plurality of field limiting ring structure regions 50; The oxide layer 110 and the isolation structure 120 are removed.

[0053] In a specific implementation, by using the thickness difference of the oxidation region 130, under the condition of equal ion implantation dose and implantation energy, the field limiting ring structure region 50 with different junction depths can be formed, such as Figure 5 As shown, the greater the thickness of each oxide region 130 of the oxide layer 110, the smaller the junction depth of the field limiting ring structure region 50. By adopting this method to form the field limiting ring structure region 50, there is no need to calculate the ion implantation dose and implantation energy. The cross-sectional area of ​​the field limiting ring structure region 50 can be gradually changed only by the structure of the oxide layer 110, making the overall operation simple and easy to implement.

[0054] like Figure 6 and Figure 7 As shown, a method for preparing a power semiconductor device according to another embodiment of the present application, wherein the step of performing ion implantation on the first surface of the epitaxial layer 20 to form a main junction region 40 and a plurality of field limiting ring structure regions 50 arranged at intervals, specifically includes: forming an oxide layer 110 with a uniform thickness on the first surface of the epitaxial layer 20; An isolation structure 120 is disposed on the surface of the oxide layer 110 and an implantation region 121 is formed. The isolation structure 120 is a mask. Ion implantation is performed from the oxide layer 110 in the implantation region 121 toward the epitaxial layer 20 to form a main junction region 40; like Figure 7 As shown, in the direction away from the main junction region 40, the isolation structure 120 is sequentially arranged on the surface of the oxide layer 110 and the implantation region 121 is sequentially formed at different positions, and the window distance of the implantation region 121 is in a decreasing trend; wherein, when the isolation structure 120 is sequentially arranged, the isolation structure 120 that was ion implanted last time is first removed, and then a new isolation structure 120 is formed, so that the isolation structure 120 has only one implantation region 121, and the implantation region 121 is arranged at different positions; Ion implantation is sequentially performed in implantation regions 121 at different positions to form a plurality of field limiting ring structure regions 50; wherein, after the isolation structures 120 are sequentially arranged, an ion implantation is performed once in the implantation region 121 of the isolation structure 120 to form a field limiting ring structure region 50, and after the isolation structure 120 is removed and a new isolation structure 120 is arranged, the next ion implantation is performed; The oxide layer 110 and the isolation structure 120 are removed.

[0055] In a specific implementation, by using the isolation structure 120 with the implantation regions 121 at different positions, multiple independent ion implantations can be performed, and the ion implantations can be performed using different implantation energies, thereby forming field limiting ring structure regions 50 with different junction depths, such as Figure 8 As shown, the greater the implantation energy, the greater the junction depth of the field limiting ring structure region 50. This method is used to form the field limiting ring structure region 50, so that the implantation energy of each field limiting ring structure region 50 can be independently controlled, and the field limiting ring structure regions 50 will not affect each other during the formation process.

[0056] Preferably, if Figure 6 As shown, when the isolation structure 120 is set on the surface of the oxide layer 110, the isolation structure 120 has two injection regions 121 with the same width; after ion implantation is performed in the two injection regions 121, a main junction region 40 and a field limiting ring structure region 50 close to the main junction region 40 can be formed; then, along the direction away from the main junction region 40, the isolation structure 120 is sequentially set on the surface of the oxide layer 110 and injection regions 121 are sequentially formed at different positions, and after ion implantation, a plurality of spaced-apart field limiting ring structure regions 50 with a gradient junction depth are formed.

[0057] The method for preparing a power semiconductor device in an embodiment of the present application, wherein the step of performing high-temperature push-junction on the main junction region 40 and the plurality of field limiting ring structure regions 50 specifically includes: The main junction region 40 and the innermost field limiting ring structure region 50 are subjected to high temperature push-junction with the same total heating time, so that the junction depths of the main junction region 40 and the innermost field limiting ring structure region 50 can be the same; Along the direction away from the main junction region 40 , each field limiting ring structure region 50 is sequentially subjected to high temperature push junction with decreasing total thermal time, thereby forming a plurality of field limiting ring structure regions 50 with decreasing junction depth.

[0058] In specific implementation, by controlling the time of high-temperature junction pushing, the junction depth of the main junction area 40 and the field limiting ring structure area 50 can also be controlled, thereby achieving a decreasing junction depth of the field limiting ring structure area 50, reducing the sensitivity to movable charges, ensuring a higher breakdown voltage, and thus ensuring the voltage resistance performance of the power semiconductor device.

[0059] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0060] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A power semiconductor device, characterized in that: The invention comprises a stacked field plate structure layer (10), an epitaxial layer (20) and a substrate layer (30), wherein a main junction region (40) and a plurality of field limiting ring structure regions (50) spaced apart and surrounding the main junction region (40) are provided in the epitaxial layer (20), the main junction region (40) and the field limiting ring structure regions (50) both extend from a first surface of the epitaxial layer (20) to the inside, the field plate structure layer (10) is provided on the first surface of the epitaxial layer (20) and is connected to at least one of the field limiting ring structure regions (50), and in a direction away from the main junction region (40), the cross-sectional areas of the plurality of field limiting ring structure regions (50) show a decreasing trend and the spacing distances between the main junction region (40) and the plurality of field limiting ring structure regions (50) show a decreasing trend; The field plate structure layer (10) is a patterned metal layer, the epitaxial layer (20) and the substrate layer (30) are both semiconductor structures with a first conductivity type, and the main junction region (40) and the field limiting ring structure region (50) are both semiconductor structures with a second conductivity type.

2. The power semiconductor device according to claim 1, characterized in that: The power semiconductor device further comprises an isolation layer (60), the isolation layer (60) being arranged on the first surface of the epitaxial layer (20), the isolation layer (60) having at least one connecting portion (61) extending therethrough, and the field plate structure layer (10) being connected to at least one of the field limiting ring structure regions (50) via the connecting portion (61).

3. The power semiconductor device according to claim 2, characterized in that: The field plate structure layer (10) comprises at least one field plate structure (11), the field plate structure (11) comprising a field limiting ring connection portion (111) and a first conductive connection portion (112) connected to each other, each field limiting ring connection portion (111) being arranged in a corresponding connecting portion (61) and connected to a corresponding field limiting ring structure region (50), and the first conductive connection portion (112) being arranged on a side of the isolation layer (60) facing away from the field limiting ring structure region (50).

4. The power semiconductor device according to claim 3, characterized in that: The outermost field plate structure (11) further comprises a second conductive connection portion (113), the second conductive connection portion (113) extending in a direction away from the main junction region (40), the second conductive connection portion (113) comprising two stacked conductive connection layers (114), the projection portions of the two conductive connection layers (114) on the first surface of the epitaxial layer (20) being arranged to overlap.

5. The power semiconductor device according to claim 3, characterized in that: The first conductive connection portion (112) of the field plate structure (11) is arranged to at least partially overlap with the projection of the field limiting ring structure region (50) adjacent to one side of the field plate structure (11) on the first surface of the epitaxial layer (20).

6. The power semiconductor device according to claim 3, characterized in that: The field plate structure layer (10) has two field plate structures (11), and the two field plate structures (11) are respectively connected to the two innermost and outermost field limiting ring structure regions (50).

7. The power semiconductor device according to claim 4, characterized in that: The isolation layer (60) comprises a plurality of isolation structures (62) spaced apart in a direction away from the main junction region (40), the connecting portion (61) being formed between adjacent isolation structures (62), the outermost isolation structure (62) being arranged between the second conductive connection portion (113) and the first surface of the epitaxial layer (20), and the isolation structure (62) being in a stepped structure that matches the shape of the second conductive connection portion (113).

8. The power semiconductor device according to claim 1, characterized in that: Along a direction away from the main junction region (40), the extension depths of the plurality of field limiting ring structure regions (50) extending inward from the first surface of the epitaxial layer (20) show a decreasing trend.

9. The power semiconductor device according to claim 1, characterized in that: The power semiconductor device further comprises a cut-off region (70), the cut-off region (70) being arranged at intervals on a side of the plurality of field limiting ring structure regions (50) away from the main junction region (40), the cut-off region (70) being a semiconductor structure having a first conductivity type.

10. A method for preparing a power semiconductor device, characterized in that: include: Performing epitaxial growth on one side of the substrate layer (30) to form an epitaxial layer (20), wherein the epitaxial layer (20) is a semiconductor structure having a first conductivity type; Ion implantation is performed on the first surface of the epitaxial layer (20) to form a main junction region (40) and a plurality of spaced-apart field limiting ring structure regions (50), wherein the main junction region (40) and the plurality of spaced-apart field limiting ring structure regions (50) are semiconductor structures having a second conductivity type; Performing high-temperature push-junction on the main junction region (40) and the plurality of field limiting ring structure regions (50), so as to form a plurality of field limiting ring structure regions (50) whose cross-sectional areas and spacing distances both show a decreasing trend; Forming an isolation layer (60) on the first surface of the epitaxial layer (20), and etching to form a plurality of connecting portions (61) corresponding to the plurality of field limiting ring structure regions (50); Forming a metal layer on the surface of the isolation layer (60) and the plurality of connecting portions (61) and performing patterning to form at least one field plate structure (11) of the field plate structure layer (10); A passivation layer is formed on the surfaces of the field plate structure layer (10) and the isolation layer (60).

11. The method for preparing a power semiconductor device according to claim 10, characterized in that: The step of implanting ions of the second conductive type into the first surface of the epitaxial layer (20) to form a main junction region (40) and a plurality of spaced-apart field limiting ring structure regions (50) specifically comprises: forming an oxide layer (110) with uniform thickness on a first surface of the epitaxial layer (20); Processing the thickness of the oxide layer (110) to form the oxide layer (110) having a plurality of oxide regions (130) with different thicknesses; A plurality of isolation structures (120) are provided at the connection between the oxidation regions (130) and at the oxidation regions (130) on both sides; Performing ion implantation from the oxidation region (130) between adjacent isolation structures (120) toward the epitaxial layer (20) to form the main junction region (40) and a plurality of field limiting ring structure regions (50); The oxide layer (110) and the isolation structure (120) are removed.

12. The method for preparing a power semiconductor device according to claim 10, characterized in that: The step of performing ion implantation on the first surface of the epitaxial layer (20) to form a main junction region (40) and a plurality of spaced-apart field limiting ring structure regions (50) specifically comprises: forming an oxide layer (110) with uniform thickness on a first surface of the epitaxial layer (20); An isolation structure (120) is provided on the surface of the oxide layer (110) and an implantation region (121) is formed; Performing ion implantation from the oxide layer (110) in the implantation region (121) toward the epitaxial layer (20) to form the main junction region (40); In a direction away from the main junction region (40), isolation structures (120) are sequentially arranged on the surface of the oxide layer (110) and the implantation regions (121) are sequentially formed at different positions; sequentially performing ion implantation in the implantation regions (121) at different positions to form a plurality of the field limiting ring structure regions (50); The oxide layer (110) and the isolation structure (120) are removed.

13. The method for preparing a power semiconductor device according to claim 10, characterized in that: The step of performing high-temperature push-junction on the main junction region (40) and the plurality of field limiting ring structure regions (50) specifically includes: Performing high temperature push-junction on the main junction region (40) and the innermost field limiting ring structure region (50) with the same total thermal time; In a direction away from the main junction area (40), each field limiting ring structure area (50) is sequentially subjected to high temperature push-junction with a decreasing total thermal time.

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