Display panel and display device

Abstract

The invention provides a display panel and a display device, the display panel comprises a substrate and a thin film transistor switch, and the thin film transistor switch is arranged on the substrate; the thin film transistor switch comprises an active layer, a gate insulating layer, a grid electrode and a first insulating layer which are arranged in sequence, wherein the first insulating layer covers the grid electrode; the source electrode, the first flat layer and the drain electrode are sequentially arranged on the first insulating layer, the first flat layer covers the source electrode, the source electrode is electrically connected with the active layer through first through holes formed in the first insulating layer and the gate insulating layer, a stacked structure formed by the first flat layer, the first insulating layer and the gate insulating layer comprises a recess, and the drain electrode is partially arranged in the recess. According to the display panel, the phenomena of bad stains and strip-shaped Mura can be effectively avoided, so that the visual experience of a user is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and, more specifically, to a display panel and a display device. Background Art

[0002] Virtual reality (VR) products with high pixel density (pixels per inch, PPI) are currently the main development direction of low temperature polysilicon (LTPS) liquid crystal display (LCD). However, as the PPI of display devices increases, the pixel pitch becomes very small, which means that more pixels and lines (such as data lines, signal lines, etc.) must be placed in a limited space. In order to cope with the above problems, the current manufacturing process mostly uses a double insulating layer (including: ILD1 and ILD2) and a double metal conductive layer (including, source (SD1) and drain (SD2)) structure to alleviate the exposure process compatibility problem caused by the overly dense arrangement of SD drain connection blocks and SD lines.

[0003] However, in the above process, when the insulating layer covers the source, the insulating layer may break due to the large step difference of the film layer in the edge area of ​​the source, and a short circuit may occur between adjacent pixel circuits due to the residue from drain etching, which may cause stains and strip-shaped Mura on the display panel, which will seriously affect the user's visual experience. Summary of the invention

[0004] The present application provides a display panel and a display device, which can effectively prevent the display panel from having stains and strip-shaped Mura, thereby improving the user's visual experience.

[0005] In a first aspect, a display panel is provided, which includes: a base substrate and a thin film transistor switch, wherein the thin film transistor switch is arranged on the base substrate; the thin film transistor switch includes: an active layer, a gate insulating layer, a gate electrode, and a first insulating layer arranged in sequence, wherein the first insulating layer covers the gate electrode; a source electrode, a first flat layer, and a drain electrode arranged in sequence on the first insulating layer, wherein the first flat layer covers the source electrode, the source electrode is electrically connected to the active layer through a first through hole opened in the first insulating layer and the gate insulating layer, and the stacked structure composed of the first flat layer, the first insulating layer, and the gate insulating layer includes a recess, and the drain electrode is partially arranged in the recess so that the drain electrode is electrically connected to the active layer.

[0006] In a possible implementation, since the thicknesses of the first insulating layer and the gate insulating layer are fixed, by simulating optical parameters such as transmittance and contrast, it can be obtained that the thickness of the first insulating layer is 4500 to 1000 mm. The thickness of the gate insulating layer is 1000 to In order to meet the charging requirements, the thickness of the first insulating layer can be set to 2800 to

[0007] In the embodiment of the present application, by setting the first flat layer, the film layer step difference at both ends of the source can be effectively filled, thereby solving the problem of drain etching residue caused by the large film layer step difference, thereby effectively avoiding the display panel from having stains and strip Mura, and improving the user's visual experience.

[0008] In combination with the first aspect, in some implementations of the first aspect, a second insulating layer is further provided between the first planar layer and the drain electrode, and the second insulating layer is used to prevent the drain electrode from being peeled off.

[0009] When the drain electrode is arranged on the first flat layer, after the drain electrode is dry-etched, the film surface of the first flat layer is bombarded by the dry etching gas and becomes fluffy. At this time, the drain electrode is easily peeled off after the degumming process (removing the photoresist), which may lead to a decrease in the electrical performance of the display panel. In the embodiment of the present application, by arranging a second insulating layer on the first flat layer and arranging the drain electrode on the second insulating layer, the second insulating layer can play a role in curing the film layer, so that the drain electrode is not easily peeled off, thereby ensuring the performance and production quality of the display panel.

[0010] In combination with the first aspect, in some implementations of the first aspect, the thickness of the second insulating layer is

[0011] In the embodiment of the present application, by setting the thickness of the second insulating layer, on the one hand, the upper surface film layer of the first flat layer can be solidified to prevent the surface of the first flat layer from becoming fluffy due to plasma bombardment after the drain electrode is dry-etched, resulting in the film layer falling off after the photoresist stripping process of the drain electrode; on the other hand, since the drain electrode dry etching has an overetching effect on the SiNx of the second insulating layer, the overetching is about Properly increasing the thickness of the second insulating layer can prevent the SiNx of the second insulating layer from being completely removed (loss) by the drain dry etching, thereby effectively preventing the first planarization layer from being exposed.

[0012] In combination with the first aspect, in some implementations of the first aspect, the second insulating layer is disposed on the first planar layer by coating, and the temperature during the coating is 220 to 230 degrees Celsius.

[0013] Since the first flat layer is used to fill the irregular areas on the surface of the film layer to provide a flat base layer. However, this layer of material may release volatile substances (such as solvents, residual gases, etc.) under high temperature conditions. If these volatiles are not effectively controlled, they may cause bubbles, voids or particle contamination in subsequent processes, thereby affecting the adhesion and electrical properties between layers. In the embodiment of the present application, the second insulating layer is covered on the first flat layer by low-temperature coating (220 to 230 degrees Celsius), which can effectively prevent the first flat layer from volatilizing (outgas), thereby improving the reliability of the material.

[0014] In combination with the first aspect, in certain implementations of the first aspect, the thin film transistor switch further includes: a light blocking layer and a buffer layer arranged in sequence, the light blocking layer being used to block external light from entering the active layer, the buffer layer covering the light blocking layer, and the buffer layer being arranged between the active layer and the base substrate.

[0015] Since the active layer is usually made of amorphous silicon (a-Si) or polycrystalline silicon (p-Si), these materials are very sensitive to light. When ambient light or the backlight of the display panel shines on the active layer, additional photocurrent may be generated, resulting in increased leakage current, affecting the switching performance of the thin film transistor, and thus reducing the contrast and image quality of the display panel. In the embodiment of the present application, by providing a light blocking layer, it is possible to effectively block external light from entering the active layer, preventing photons from having unnecessary excitation effects on the semiconductor material in the active layer, thereby ensuring that the thin film transistor switch can work normally.

[0016] In combination with the first aspect, in certain implementations of the first aspect, the thin film transistor switch further includes: a second flat layer, a pixel electrode, a passivation layer, and a common electrode sequentially arranged on the drain; the second flat layer covers the drain, the passivation layer covers the pixel electrode, and the pixel electrode is electrically connected to the drain through a second through hole opened in the second flat layer.

[0017] In a possible implementation, since the second planarization layer needs to play the role of filling the deep holes and planarization, the thickness of the second planarization layer can be set to 1.5 to 2.3 microns.

[0018] In combination with the first aspect, in some implementations of the first aspect, the material used to prepare the first flat layer includes an acrylic material.

[0019] In combination with the first aspect, in some implementations of the first aspect, the thickness of the first planar layer in a direction perpendicular to the base substrate is 0.8 to 1.5 microns.

[0020] In the embodiment of the present application, by setting the thickness of the first flat layer to between 0.8 and 1.5 microns, the first flat layer can fully cover the film layer step formed by the gate, the light blocking layer or the source electrode. On the other hand, it can make the first flat layer easier to achieve pinhole exposure, so that the drain connection block can be more easily overlapped into the hole of the first flat layer.

[0021] In combination with the first aspect, in some implementations of the first aspect, the drain electrode includes a protrusion, the protrusion is disposed in the recess, and the protrusion is electrically connected to the active layer.

[0022] In a second aspect, a display device is provided, comprising the display panel in any one of the implementations of the first aspect.

[0023] In combination with the second aspect, in some implementations of the second aspect, the display device further includes: components such as a housing, a power supply, and control buttons.

[0024] In combination with the second aspect, in some implementations of the second aspect, the display device is a virtual reality device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a cross-sectional view of a display panel in a current design provided in an embodiment of the present application;

[0026] Figure 2 It is a planar mechanism diagram of a display panel producing a stain defect provided by an embodiment of the present application;

[0027] Figure 3 It is a cross-sectional mechanism diagram of a display panel producing a stain defect phenomenon provided by an embodiment of the present application;

[0028] Figure 4 is a cross-sectional view of a display panel during preparation provided by an embodiment of the present application;

[0029] Figure 5 is a cross-sectional view of another display panel manufacturing process provided by an embodiment of the present application;

[0030] Figure 6 is a cross-sectional view of another display panel manufacturing process provided by an embodiment of the present application;

[0031] Figure 7 is a cross-sectional view of another display panel manufacturing process provided by an embodiment of the present application;

[0032] Figure 8 is a cross-sectional view of another display panel manufacturing process provided by an embodiment of the present application;

[0033] Fig. 9 This is a plane effect diagram of a display panel provided by an embodiment of the present application for solving the problem of stains;

[0034] Fig.10 This is a cross-sectional effect diagram of a display panel provided in an embodiment of the present application for solving the problem of stains. DETAILED DESCRIPTION

[0035] In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In the present application, "at least one" means one or more, and "multiple" means two or more. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0036] The prefixes such as "first" and "second" used in the embodiments of the present application are only used to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers used to distinguish description objects in the embodiments of the present application does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and the use of such prefixes should not constitute an unnecessary limitation.

[0037] In order to better understand the technical solution in this application, the terms involved in this application are first introduced.

[0038] (1) Large thickness difference of the film layer: The film layer has significant thickness differences in different areas (especially the edge and center areas), which in turn affects the overall surface flatness of the film layer.

[0039] (2) Strip Mura: It refers to the uneven brightness or color areas in the shape of strips or bands that appear on the display screen.

[0040] (3) Thin-film transistor switch: It is a field-effect transistor manufactured based on thin-film technology. It is mainly used to drive display pixels or control the switching state of electrical signals. The function of the thin-film transistor switch is to control the on and off of the current to accurately control the brightness and color of the display pixels, or to be used for signal transmission in other circuits.

[0041] (4) Gate, source and drain: The gate can control whether the channel of the thin film transistor is turned on, thereby determining whether current can flow from the source to the drain; the source is usually grounded or connected to a low voltage power supply, as the starting point of the current. When the gate opens the channel of the transistor, the current flows from the source to the drain; the drain is usually connected to a higher voltage or load circuit. When the gate applies an appropriate voltage to turn on the channel, the current can flow from the source through the channel to the drain, driving the external circuit or device.

[0042] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application, which can be implemented in various forms, should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to enable the scope of the present application to be fully communicated to those skilled in the art.

[0043] High PPI VR products are currently the main development direction of LTPS LCD. However, as the PPI of display devices increases, the pixel pitch becomes very small, which means that more pixels and lines (such as data lines, signal lines, etc.) must be placed in a limited space. In order to cope with the above problems, the current manufacturing process mostly uses a double insulating layer (including: ILD1 and ILD2) and a double metal conductive layer (including, source (SD1) and drain (SD2)) structure to alleviate the exposure process compatibility problem caused by the overly dense arrangement of SD drain connection blocks and SD lines.

[0044] In this process, SD1 is prone to irregular etching edges (serrations) and thinning due to line thinning and etching on a silicon dioxide substrate, resulting in the inability of ILD2 to form smooth and uniform coverage on these serrations and / or thinning areas, which may increase the risk of cracks or breakage of the material. In addition, due to the large step difference of the film layer in the edge area of ​​SD1, SD2 is prone to residues at the center edge of the drain connection block and around the SD1 line during the preparation process. These residues may cause short circuits between adjacent pixel circuits, making adjacent pixels unable to work properly, especially at the boundary between black and white images. The short circuit will cause crosstalk between SD1 or SD2 signals, affecting the image quality, which is manifested as stains or abnormal display problems.

[0045] For example, Figure 1As shown in the figure, in the current design, SD1 is covered with ILD2. Since the source electrode may be jagged and thinned during etching, this will have an adverse effect on its surface morphology; the jagged or thinned part will cause ILD2 to be unable to form a smooth and uniform coverage during deposition. This discontinuous coverage will weaken the mechanical strength of the ILD2 layer, especially in the stress concentration area, which is prone to tiny cracks. These cracks may further expand with the accumulation of external stress, resulting in material fracture or delamination.

[0046] For example, Figure 2 and Figure 3 As shown, in the current design, after SD2 undergoes the drying and stripping process, "triangular" residues are easily generated at the center of the SD2 drain connection block (also called a step) and around the SD1 line. These residues may cause a short circuit between two adjacent pixels above and below, especially at the boundary between black and white images. The short circuit will cause crosstalk in the SD1 signal, causing stains and strip-shaped Mura on the display panel, thereby affecting the quality of the display image.

[0047] The embodiments of the present application provide a display panel and a display device, which can effectively prevent the display panel from having stains and strip-shaped Mura, thereby improving the user's visual experience.

[0048] The display panel provided in the present application includes: a base substrate and a thin film transistor switch, wherein the thin film transistor switch is arranged on the base substrate; the thin film transistor switch includes: an active layer, a gate insulating layer, a gate electrode, and a first insulating layer arranged in sequence, wherein the first insulating layer covers the gate electrode; a source electrode, a first flat layer, and a drain electrode arranged in sequence on the first insulating layer, wherein the first flat layer covers the source electrode, the source electrode is electrically connected to the active layer through a first through hole opened in the first insulating layer and the gate insulating layer, and the stacked structure composed of the first flat layer, the first insulating layer, and the gate insulating layer includes a recess, wherein the drain electrode is partially arranged in the recess so that the drain electrode is electrically connected to the active layer.

[0049] Optionally, the thickness of the first flat layer in a direction perpendicular to the substrate is 0.8 to 1.5 microns, so that the first flat layer can fully cover the film layer step formed by the gate, light blocking layer or source electrode. On the other hand, it can make it easier for the first flat layer to achieve small hole exposure, so that the drain connection block can be more easily overlapped into the hole of the first platform layer.

[0050] Optionally, the thickness of the first insulating layer and the gate insulating layer is fixed, and by simulating optical parameters such as transmittance and contrast, it can be obtained that the thickness of the first insulating layer is 4500 to 10000 mm. The thickness of the gate insulating layer is 1000 to In order to meet the charging requirements, the thickness of the first insulating layer can be set to 2800 to

[0051] Optionally, the material used to prepare the first flat layer includes acrylic material.

[0052] Optionally, the drain electrode includes a protrusion, which is disposed in the recess and is electrically connected to the active layer.

[0053] Optionally, the thin film transistor switch further includes: a second planar layer, a pixel electrode, a passivation layer and a common electrode sequentially arranged on the drain; the second planar layer covers the drain, the passivation layer covers the pixel electrode, and the pixel electrode is electrically connected to the drain through a second through hole opened in the second planar layer.

[0054] Optionally, since the second planarization layer needs to play the role of filling the deep holes and planarization, the thickness of the second planarization layer can be set to 1.5 to 2.3 microns.

[0055] In the embodiment of the present application, by setting the first flat layer, the film layer step difference at both ends of the source can be effectively filled, thereby solving the problem of drain etching residue caused by the large film layer step difference, thereby effectively avoiding the display panel from having stains and strip Mura, and improving the user's visual experience.

[0056] In a possible implementation manner, a second insulating layer is further provided between the first planarization layer and the drain electrode, and the second insulating layer is used to prevent the drain electrode from being stripped off.

[0057] Specifically, in this implementation, the stacked structure consisting of the first planar layer, the first insulating layer, the gate insulating layer and the second planar layer includes the above-mentioned recess, and the drain portion is arranged in the recess so that the drain is electrically connected to the active layer.

[0058] When the drain electrode is arranged on the first flat layer, after the drain electrode is dry-etched, the film surface of the first flat layer is bombarded by the dry etching gas and becomes fluffy. At this time, the drain electrode is easily peeled off after the stripping process, which may lead to a decrease in the electrical performance of the display panel. In the embodiment of the present application, by arranging a second insulating layer on the first flat layer and arranging the drain electrode on the second insulating layer, the second insulating layer can play a role in curing the film layer, so that the drain electrode is not easily peeled off, thereby ensuring the performance and production quality of the display panel.

[0059] In a possible implementation, the thickness of the second insulating layer can be set to

[0060] In the embodiment of the present application, by setting the thickness of the second insulating layer, on the one hand, the upper surface film layer of the first flat layer can be solidified to prevent the surface of the first flat layer from becoming fluffy due to plasma bombardment after the drain electrode is dry-etched, resulting in the film layer falling off after the photoresist stripping process of the drain electrode; on the other hand, since the drain electrode dry etching has an overetching effect on the SiNx of the second insulating layer, the overetching is about Properly increasing the thickness of the second insulating layer can prevent the SiNx of the second insulating layer from being completely removed (loss) by the drain dry etching, thereby effectively preventing the first planarization layer from being exposed.

[0061] In a possible implementation, the second insulating layer is disposed on the first planar layer by coating, and the temperature during coating is 220 to 230 degrees Celsius.

[0062] Since the first flat layer is used to fill the irregular areas on the surface of the film layer to provide a flat base layer. However, this layer of material may release volatile substances (such as solvents, residual gases, etc.) under high temperature conditions. If these volatiles are not effectively controlled, they may cause bubbles, voids or particle contamination in subsequent processes, thereby affecting the adhesion and electrical properties between layers. In the embodiment of the present application, the second insulating layer is covered on the first flat layer by low-temperature coating (220 to 230 degrees Celsius), which can effectively prevent the first flat layer from volatilizing (outgas), thereby improving the reliability of the material.

[0063] In a possible implementation, the thin film transistor switch further includes: a light blocking layer and a buffer layer arranged in sequence, the light blocking layer is used to block external light from entering the active layer, the buffer layer covers the light blocking layer, and the buffer layer is arranged between the active layer and the base substrate.

[0064] Since the active layer is usually made of amorphous silicon (a-Si) or polycrystalline silicon (p-Si), these materials are very sensitive to light. When ambient light or the backlight of the display panel shines on the active layer, additional photocurrent may be generated, resulting in increased leakage current, affecting the switching performance of the thin film transistor, and thus reducing the contrast and image quality of the display. In the embodiment of the present application, by providing a light blocking layer, it is possible to effectively block external light from entering the active layer, prevent photons from having unnecessary excitation effects on the semiconductor materials in the active layer, and ensure the normal operation of the thin film transistor switch.

[0065] It should be understood that in the various embodiments (implementations) of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the various embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form new embodiments according to their internal logical relationships.

[0066] Combine the following Figures 4 to 8 An exemplary structure and preparation process of the above-mentioned display panel are introduced.

[0067] like Figure 4 As shown, the cross-sectional view includes, from bottom to top, a substrate (glass), a light blocking layer (LS), a buffer layer (buffer), an active layer (P-Si), a gate insulating layer (GI), a gate (gate), a first insulating layer (ILD1) and a source (SD1).

[0068] Among them, the buffer layer (buffer) can be covered on the light blocking layer (LS); the gate insulating layer (GI) can be covered on the active layer (P-Si); the first insulating layer (ILD1) can be covered on the gate (gate); the source (SD1) can be electrically connected to the active layer (P-Si) through a first through hole opened in the first insulating layer (ILD1) and the gate insulating layer (GI).

[0069] Among them, the base substrate (glass) can provide physical support for other layers; the light blocking layer (LS) is used to block external light from entering the active layer (P-Si); the buffer layer (buffer) can fill the tiny unevenness and defects on the surface of the base substrate (glass) and the light blocking layer (LS), and can enable the gate insulating layer (GI) to be formed more evenly on the buffer layer (buffer), thereby increasing the firmness of the gate insulating layer (GI); the gate insulating layer (GI) can isolate the gate charge to ensure that each layer of electrons and holes can be normally transported and injected, thereby ensuring the normal operation of the display panel; the first insulating layer (ILD1) is used to isolate the gate (gate) and the source (SD1), which can prevent charge leakage and circuit short circuit.

[0070] exist Figure 4 Based on the source (SD1) and the first insulating layer (ILD1), a first flat layer (PLN1) is formed on the source (SD1) and the first insulating layer (ILD1) to obtain the following Figure 5 As shown in the cross-sectional view, the first flat layer (PLN1) is made of organic insulating material (for example, acrylic resin), and the thickness of the first flat layer (PLN1) can range from 0.8 to 1.5 microns. Such a film thickness can fully cover the film step difference of the light blocking layer (LS), the gate (gate) and the source (SD1). On the other hand, such a film thickness can make it easier for the first flat layer (PLN1) to achieve pinhole exposure, that is, the hole size of the first flat layer (PLN1) can be reduced to 2.6 to 3.0 microns, and the size of the high PPI VR drain (SD2) connecting block is 5×7 microns. The reduction in the hole size of the first flat layer (PLN1) can make it easier for the drain (SD2) connecting block to overlap into the hole.

[0071] Optionally, the first planar layer (PLN1) can be covered on the source (SD1) and the first insulating layer (ILD1) through coating, masking, curing (230°C / 60min), and descumming processes in sequence.

[0072] exist Figure 5 Based on the first planar layer (PLN1), a second insulating layer (ILD2) is formed on the first planar layer (PLN1) to obtain the following: Figure 6 The cross-sectional view shown in FIG. The stacked structure composed of the second insulating layer (ILD2), the first planar layer (PLN1), the first insulating layer (ILD1) and the gate insulating layer (GI) includes a recess, which can be used to place a portion of the drain (SD2).

[0073] exist Figure 6 On the basis of, a drain electrode (SD2) is prepared, the drain electrode (SD2) is partially disposed on the second insulating layer (ILD2), and the drain electrode (SD2) is partially disposed in the recess, and the following can be obtained: Figure 7 The drain electrode (SD2) may include a protrusion, which is disposed in the recess and electrically connected to the active layer (P-Si).

[0074] exist Figure 7 On the basis of the drain electrode (SD2) and the second insulating layer (ILD2), a second flat layer (PLN2), a pixel electrode (P-ITO), a passivation layer (PVX) and a common electrode (C-ITO) are sequentially arranged above the drain electrode (SD2) and the second insulating layer (ILD2), and the following can be obtained: Figure 8 The cross-sectional view shown in FIG. The second planar layer (PLN2) can cover the drain (SD2), the drain (SD2) can cover the pixel electrode (P-ITO), and the pixel electrode (P-ITO) can be electrically connected to the drain (SD2) through a second through hole opened in the second planar layer (PLN2).

[0075] exist Figures 4 to 7 In the embodiment, by setting the first flat layer, the film step difference at both ends of the source line can be effectively filled, solving the problem of drain etching residue caused by the large film step difference, thereby effectively avoiding the phenomenon of stains and strip Mura on the display panel and improving the user's visual experience.

[0076] It should be noted that the above-mentioned buffer layer (Buffer), gate insulating layer (GI), first insulating layer (ILD1), second insulating layer (ILD2) and passivation layer (PVX) can be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon nitride (SiON), and can be in various forms such as single layer, multi-layer or composite layer.

[0077] Combine the following Fig. 9 and Fig.10 The role of the first flat layer (PLN1) is introduced in detail. Fig. 9 The size range of each layer structure and the transmission route of the source (SD1) signal after adding the first flat layer (PLN1) are described in Fig.10 , the deposition state of the second insulating layer (ILD2) and the drain (SD2) after adding the first planar layer (PLN1) is described.

[0078] From Fig. 9 and Fig.10 ,and Figure 2 and Figure 3 The comparison shows that after adding the first flat layer (PLN1), the first flat layer (PLN1) fills the film step difference at both ends of the source (SD1) line, making the second insulating layer (ILD2) and the drain (SD2) coating flat, avoiding residue at both ends of the source (SD1) line, thereby avoiding short circuits between two adjacent pixels, so that the SD1 signal can be transmitted normally, thereby improving the display panel's stain and strip Mura phenomenon. In addition, the setting of the first flat layer (PLN1) can also avoid the loss of the drain (SD2) film layer due to the large film step difference, reducing the risk of cracks or breaks in the film layer.

[0079] An embodiment of the present application further provides a display device, which includes the display panel introduced in the above embodiment.

[0080] Optionally, the display device further includes components such as a housing, a power supply, and control buttons.

[0081] Optionally, the display device may be: a mobile phone, a flat-panel computer, a monitor, a virtual reality device or an augmented reality device.

[0082] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: The display panel comprises: a base substrate and a thin film transistor switch, wherein the thin film transistor switch is arranged on the base substrate; The thin film transistor switch comprises: An active layer, a gate insulating layer, a gate electrode, and a first insulating layer are sequentially arranged, wherein the first insulating layer covers the gate electrode; A source electrode, a first planar layer and a drain electrode are sequentially arranged on the first insulating layer, wherein the first planar layer covers the source electrode, the source electrode is electrically connected to the active layer through a first through hole opened in the first insulating layer and the gate insulating layer, and the stacked structure composed of the first planar layer, the first insulating layer and the gate insulating layer includes a recess, and the drain electrode is partially arranged in the recess so that the drain electrode is electrically connected to the active layer.

2. The display panel according to claim 1, wherein: A second insulating layer is further disposed between the first planar layer and the drain electrode, and the second insulating layer is used to prevent the drain electrode from being peeled off.

3. The display panel according to claim 2, wherein: The second insulating layer is disposed on the first flat layer by coating, and the temperature during coating is 220 to 230 degrees Celsius.

4. The display panel according to any one of claims 1 to 3, characterized in that: The thin film transistor switch further includes: a light blocking layer and a buffer layer which are arranged in sequence, wherein the light blocking layer is used to block external light from entering the active layer, the buffer layer covers the light blocking layer, and the buffer layer is arranged between the active layer and the base substrate.

5. The display panel according to any one of claims 1 to 4, characterized in that: The thin film transistor switch further comprises: a second flat layer, a pixel electrode, a passivation layer and a common electrode sequentially arranged on the drain electrode; The second planar layer covers the drain electrode, the passivation layer covers the pixel electrode, and the pixel electrode is electrically connected to the drain electrode through a second through hole opened in the second planar layer.

6. The display panel according to any one of claims 1 to 5, characterized in that: The material used to prepare the first flat layer includes acrylic material.

7. The display panel according to any one of claims 1 to 6, characterized in that: The thickness of the first planar layer in a direction perpendicular to the base substrate is 0.8 to 1.5 microns.

8. The display panel according to any one of claims 1 to 7, characterized in that: The drain electrode includes a protrusion, the protrusion is disposed in the recess, and the protrusion is electrically connected to the active layer.

9. A display device, characterized in that: include: A display panel as claimed in any one of claims 1 to 8.

10. The display device according to claim 9, characterized in that The display device is a virtual reality device.

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