Solar cell and photovoltaic module

Abstract

The invention is applicable to the technical field of solar cells, and provides a solar cell and a photovoltaic module, the solar cell comprises a silicon wafer, and the process temperature of the silicon wafer for processing the solar cell is lower than 1000 DEG C; after the solar cell is subjected to high-temperature treatment, at least one oxide staggered ring is distributed on the silicon wafer, and the temperature of the high-temperature treatment is more than 1000 DEG C. According to the solar cell and the photovoltaic module provided by the invention, the silicon wafer cost in the solar cell produced by a low-temperature process can be reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and in particular relates to a solar cell and a photovoltaic module. Background Art

[0002] Crystal ingots are important raw materials in the semiconductor industry. They are grown from high-purity silicon materials through a specific process. Since there may be impurities, defects or irregular shapes at the head and tail of the crystal ingot, silicon wafers are usually obtained from the middle of the crystal ingot. The crystal ingots in the middle area are relatively pure and uniform, and have a regular shape, which is conducive to the preparation of high-quality silicon wafers. However, during the growth and cutting process of the crystal ingot, certain losses and waste will occur, resulting in low utilization of the crystal ingot, which is not conducive to controlling the production cost of silicon wafers.

[0003] In existing solar cell products, due to the high temperature process of more than 1000℃ in the production process, some silicon wafers in the crystal rod cannot be used, resulting in an increase in the production cost of the battery. Summary of the invention

[0004] The present invention provides a solar cell and a photovoltaic module, aiming to solve the problem of high production cost of conventional solar cells.

[0005] The present invention provides a solar cell, comprising a silicon wafer, wherein the process temperature of the silicon wafer for processing into the solar cell is lower than 1000°C; after the solar cell is subjected to high-temperature treatment, at least one oxide layer staggered ring is distributed on the silicon wafer, and the temperature of the high-temperature treatment is above 1000°C.

[0006] In some embodiments, the minority carrier lifetime of the silicon wafer region corresponding to the oxide layer fault ring is 10 μs to 1000 μs.

[0007] In some embodiments, the minority carrier lifetime of the silicon wafer region corresponding to the oxide layer dislocation ring is 34 μs to 210 μs.

[0008] In some embodiments, the resistivity of the silicon wafer is 0.3 Ω·cm to 2 Ω·cm.

[0009] In some embodiments, the oxygen content of the silicon wafer region corresponding to the oxide layer stagger ring is greater than the oxygen content of the first region, and the first region is the non-oxide layer stagger ring region between the silicon wafer edge and the outer boundary of the oxide layer stagger ring.

[0010] In some embodiments, the oxygen content of the silicon wafer region corresponding to the oxide layer misalignment ring is less than the oxygen content of the second region, and the second region is the region formed by the inner boundary of the oxide layer misalignment ring and includes the non-oxide layer misalignment ring region in the center of the silicon wafer.

[0011] In some embodiments, the oxide layer staggered rings constitute an oxide layer staggered ring region, and the area of ​​the oxide layer staggered ring region accounts for a percentage of more than 5% of the area of ​​the silicon wafer.

[0012] The present invention also provides a photovoltaic module, comprising a plurality of solar cells, wherein the solar cells are prepared from the solar cells described in any one of the above items, and the solar cells are distributed with at least one oxide layer dislocation ring after high temperature treatment, and the temperature of the high temperature treatment is above 1000°C.

[0013] In some embodiments, the area of ​​the oxide layer fault ring of at least one solar cell is larger than the area of ​​the oxide layer fault ring of at least one solar cell among the other solar cells.

[0014] In some embodiments, the ratio of the area of ​​the oxide layer dislocation ring of the at least one solar cell to the area of ​​the oxide layer dislocation ring of at least one solar cell in the other solar cells is greater than 10:1.

[0015] In some embodiments, the ratio of the area of ​​the oxide layer dislocation ring of the at least one solar cell to the area of ​​the oxide layer dislocation ring of at least one solar cell in the other solar cells is greater than 5:1.

[0016] The solar cell and photovoltaic module provided by the present invention use a silicon wafer that exhibits oxide layer dislocation rings after high-temperature treatment at 1000°C or above. The process temperature of processing the silicon wafer into a solar cell is lower than 1000°C, and the silicon wafer will not reduce the performance of the solar cell produced by a low-temperature process below 1000°C. Moreover, the silicon wafer can be obtained from the head or tail of the crystal rod, which greatly improves the utilization rate of the crystal rod, greatly reduces the cost of the silicon wafer, and avoids the problem of oxide layer dislocation rings caused by high-temperature processes such as high-temperature TOPCon cells, which leads to a decrease in cell efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic structural diagram of a solar cell provided by an embodiment of the present invention;

[0018] Figure 2 This is one of the structural schematic diagrams of a silicon wafer in a solar cell provided by an embodiment of the present invention;

[0019] Figure 3 This is the second structural schematic diagram of the silicon wafer in the solar cell provided by the embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of a detection image of a silicon wafer in a solar cell provided by an embodiment of the present invention;

[0021] Figure 5 This is the third structural schematic diagram of the silicon wafer in the solar cell provided by the embodiment of the present invention;

[0022] Figure 6 This is the fourth structural schematic diagram of the silicon wafer in the solar cell provided by the embodiment of the present invention;

[0023] Figure 7 It is a schematic diagram of the structure of a photovoltaic module provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0025] Reference to "embodiments" or "implementations" in the present invention means that the specific features, components, or characteristics described in conjunction with the embodiments or implementations may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0026] In the description of the present invention, it should be understood that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0027] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0028] Combine the following Figures 1 to 7 , the solar cell and photovoltaic module provided by the embodiment of the present invention are described in detail through specific embodiments and their application scenarios.

[0029] Figure 1 Schematic diagram of the structure of a solar cell provided by an embodiment of the present invention. Figure 1 As shown, the present invention provides a solar cell 100, including a silicon wafer 10, wherein the process temperature of the silicon wafer 10 for processing into the solar cell 100 is lower than 1000°C; Figure 2 As shown, after the solar cell 100 is subjected to high temperature treatment, at least one oxide layer dislocation ring 20 is distributed on the silicon wafer 10, and the temperature of the high temperature treatment is above 1000°C.

[0030] It should be noted that the oxide stacking fault ring 20 is an oxidation-induced stacking fault (OISF) ring, which is a specific defect structure formed during the thermal oxidation process of the silicon wafer 10. Specifically, the oxide stacking fault ring 20 is a ring-shaped stacking fault structure formed during the thermal oxidation process by the interaction between oxygen precipitation and self-interstitial silicon atoms and vacancies in the silicon wafer 10. This stacking fault is usually distributed in a ring shape, so it is called an oxide stacking fault ring 20.

[0031] In the related art, many lattice defects will be generated in the process of growing CZ single crystal silicon, such as oxidation-induced stacking faults, vortices, twins, impurity stripes and flow pattern defects, etc. Among them, the existence of oxidation-induced stacking faults will increase the leakage current, become the nucleation center of other defects, and at the same time, as the recombination and scattering center of carriers, it will reduce the mobility and lifetime of minority carriers, increase the forward voltage drop and reverse leakage current, and lead to the reduction of device performance.

[0032] During the growth of the crystal rod, oxygen atoms will dissolve into the silicon crystal and form oxygen precipitates during the subsequent cooling and heat treatment process. These oxygen precipitates can become the nucleation center of the oxide layer dislocation ring 20. The distribution of oxygen concentration in the crystal is uneven. Usually, the oxygen concentration at the head and tail of the crystal rod is higher, while the middle of the crystal rod is relatively low. This uneven oxygen concentration distribution will affect the formation of the oxide layer dislocation ring 20. By controlling the oxygen content and heat treatment conditions during the crystal growth process, the formation of the oxide layer dislocation ring 20 can be regulated.

[0033] In the process of processing the silicon wafer 10 into the solar cell 100, a high temperature process of more than 1000°C is usually used. If the silicon wafer 10 is obtained from the head or tail of the crystal rod, an oxide layer fault ring 20 will appear when the solar cell product is finally tested for photoluminescence (PL) or electroluminescence (EL), so the silicon wafer 10 will be recycled as a low-quality wafer. Among them, more than 1000°C includes 1000°C and temperatures greater than 1000°C.

[0034] The silicon wafer 10 used in the solar cell 100 provided in the embodiment of the present invention does not present an oxide dislocation ring 20 under a low temperature process below 1000°C. However, after the solar cell 100 is subjected to a high temperature treatment above 1000°C, at least one oxide dislocation ring 20 is distributed on the silicon wafer 10. In some embodiments, when the temperature of the high temperature treatment reaches above 950°C, at least one oxide dislocation ring 20 begins to appear on the silicon wafer 10.

[0035] The silicon wafer 10 that exhibits the oxide layer dislocation ring 20 after high temperature treatment at 1000°C or above is used, and a low temperature process below 1000°C is used in the production process of the silicon wafer 10 for processing into the solar cell 100 to ensure that the cell performance does not decrease. The silicon wafer 10 can be obtained from the head or tail of the crystal rod, which improves the utilization rate of the crystal rod, greatly reduces the cost, and avoids the problem of the oxide layer dislocation ring 20 caused by the solar cell 100 using a high temperature process, which leads to a decrease in cell efficiency.

[0036] Among them, the solar cell 100 produced by the low-temperature process generally refers to the solar cell 100 using 200°C, 400°C, 600°C, 800°C, 900°C or any other temperature below 1000°C in the process treatment, such as: back contact (Interdigitated Back Contact, IBC) solar cells, heterojunction (Heterojunction Technology, HJT) solar cells and heterojunction back contact (Heterojunation Back Contact, HBC) solar cells and other solar cells that have not undergone high-temperature process treatment.

[0037] Solar cells produced by high-temperature processes generally refer to solar cells that use 1000°C, 1100°C, 1200°C or any other temperature above 1000°C in the process, such as high-temperature tunnel oxide passivated contact (TOPCon) solar cells and passivated emitter and rear cell (PERC) cells.

[0038] In some embodiments, the process temperature of the silicon wafer 10 processed into the solar cell 100 is lower than 1000°C, which means that the highest process temperature in the process after the silicon wafer 10 is lower than 1000°C, such as the processing temperature of HJT cells and HBC cells in the process is usually lower than 600°C, such as the partial tunneling oxide passivation contact cell that can control the cell temperature to be lower than 1000°C in the production process. The tunneling oxide passivation contact cell includes a tunneling oxide layer and a doped polysilicon layer, and the tunneling oxide layer and the doped polysilicon layer are arranged on the backlight surface of the silicon wafer 10.

[0039] Preferably, the tunneling oxide passivation contact cell includes P-type doped polysilicon and N-type doped polysilicon arranged on the backlight surface of the silicon wafer 10, and a first tunneling oxide layer arranged between the P-type doped polysilicon and the silicon wafer 10, and a second tunneling oxide layer arranged between the N-type doped polysilicon and the silicon wafer 10.

[0040] Preferably, the tunneling oxide passivation contact cell includes P-type doped amorphous silicon and N-type doped polycrystalline silicon arranged on the backlight surface of the silicon wafer 10, as well as intrinsic amorphous silicon arranged between the P-type doped amorphous silicon and the silicon wafer 10, and a second tunneling oxide layer arranged between the N-type doped polycrystalline silicon and the silicon wafer 10.

[0041] When the solar cell 100 in the embodiment of the present invention is not subjected to a high temperature treatment of more than 1000° C., no obvious oxide dislocation rings 20 are detected. After the solar cell 100 is subjected to a high temperature treatment of more than 1000° C., oxide dislocation rings 20 are detected.

[0042] It should be noted that if the solar cells in the above embodiments all use silicon wafers in the middle of the crystal rod, during the production process, the silicon wafers used in solar cells produced by high-temperature or low-temperature processes will not show oxide dislocation rings 20 or the area showing oxide dislocation rings 20 will be relatively small.

[0043] For silicon wafers 10 obtained from the head or tail of a crystal rod, due to high-temperature treatment above 1000°C, the silicon wafers 10 will present at least one oxide layer dislocation ring 20, so the solar cells produced by high-temperature processes will not use the silicon wafers 10 of this part. However, the solar cells 100 produced by low-temperature processes will not reach a high temperature of more than 1000°C during the entire production process, so using the silicon wafers 10 obtained from the head or tail of a crystal rod will not affect the performance of the cell.

[0044] For example, IBC cells, HBC cells or HJT cells use silicon wafers 10 obtained from the head or tail of the crystal rod. Under low-temperature treatment during the battery production process, the silicon wafer 10 will not show oxide layer dislocation rings 20. However, if the silicon wafer 10 is subjected to high-temperature treatment above 1000°C, the silicon wafer 10 will show oxide layer dislocation rings 20. IBC cells, HBC cells or HJT cells use silicon wafers in the middle of the crystal rod. Regardless of whether the silicon wafer is subjected to low-temperature treatment or high-temperature treatment, the oxide layer dislocation rings 20 will not be shown.

[0045] The heat treatment temperature and time of PERC cells or high-temperature TOPCon cells in the production process are relatively high. If silicon wafers obtained from the head or tail of the crystal rod are used, the cell performance will be affected. Since silicon wafers obtained from the head or tail of the crystal rod show oxide stacking fault defects after high-temperature treatment, the silicon wafers used in PERC cells or high-temperature TOPCon cells will not be obtained from the head or tail of the crystal rod, resulting in a waste of part of the crystal rod material.

[0046] like Figure 3 As shown, a plurality of oxide layer dislocation rings 20 with different radii are distributed on the silicon wafer 10. The ring shape of the oxide layer dislocation ring 20 can be a circle or other closed ring structure, which is not specifically limited here.

[0047] It should be noted that the oxide layer dislocation ring 20 can be detected by two methods: PL testing or EL testing.

[0048] EL testing is a photovoltaic module inspection technology that uses the principle of electroluminescence. By applying voltage to the solar cell, it emits infrared light or visible light in the working state, and capturing these lights through special camera equipment, the luminescence of the cell can be intuitively observed.

[0049] PL testing is a photovoltaic material or component inspection technology that uses the principle of photoluminescence. By applying light excitation of a specific wavelength to the photovoltaic material, the electrons in the material transition from the ground state to the excited state. The electrons emit fluorescence when they return to the ground state. By collecting and analyzing these fluorescence signals, we can understand information such as material defects, impurity distribution, and luminescence performance.

[0050] like Figure 4 As shown, the first column of images is an image obtained by performing an EL test on the silicon wafer 10, and the second column of images is an image obtained by performing a PL test on the silicon wafer 10. Figure 4It can be seen that in the images obtained by the EL test or the PL test, the first and second rows of images show that at least one oxide layer dislocation ring 20 is distributed on the corresponding silicon wafer 10, and the third row of images shows that the silicon wafer 10 corresponding to the image has almost no oxide layer dislocation ring 20. Therefore, it can be determined that the silicon wafers 10 corresponding to the first and second rows of images are obtained from the head or tail of the crystal rod, and the silicon wafer corresponding to the third row of images is obtained from the middle of the crystal rod.

[0051] The solar cell provided in the embodiment of the present invention adopts a silicon wafer that exhibits an oxide layer dislocation ring after high-temperature treatment above 1000°C. The process temperature of processing the silicon wafer into a solar cell is lower than 1000°C, and the silicon wafer will not reduce the performance of the solar cell produced by a low-temperature process below 1000°C. In addition, the silicon wafer can be obtained from the head or tail of the crystal rod, which greatly improves the utilization rate of the crystal rod, greatly reduces the cost of the silicon wafer, and avoids the problem of oxide layer dislocation rings caused by high-temperature processes such as high-temperature TOPCon cells, which leads to a decrease in cell efficiency.

[0052] Optionally, the minority carrier lifetime of the silicon wafer region corresponding to the oxide layer dislocation ring 20 is 10 μs to 1000 μs.

[0053] Among them, the minority carrier lifetime in the silicon wafer area can be determined by minority carrier lifetime scanning.

[0054] It should be noted that minority carrier lifetime scanning is a method of evaluating material quality by measuring the lifetime of minority carriers (minority carriers) in semiconductor materials. Minority carrier lifetime refers to the time that minority carriers survive in the material, which reflects the distribution of defects, impurities and recombination centers inside the material.

[0055] like Figure 4 As shown, the third column of images is the minority carrier lifetime distribution diagram, red represents the area with the shortest minority carrier lifetime, and blue represents the area with the longest minority carrier lifetime.

[0056] In the silicon wafer 10 provided in the embodiment of the present invention, the minority carrier lifetime in the region corresponding to the oxide layer fault ring 20 may range from 10 μs to 1000 μs, for example, 10 μs, 16 μs, 50 μs, 100 μs, 200 μs or 500 μs.

[0057] Optionally, the minority carrier lifetime of the silicon wafer region corresponding to the oxide layer fault ring 20 ranges from 34 μs to 210 μs, for example, it can be 34 μs, 50 μs, 100 μs, 150 μs or 210 μs.

[0058] In some embodiments, the resistivity of the silicon wafer 10 is 0.3 Ω·cm to 2 Ω·cm.

[0059] It should be noted that the resistivity of the silicon wafer 10 refers to the inherent resistance characteristics of the silicon wafer material. For semiconductor silicon materials, the resistivity is related to the concentration of electrons and holes inside the silicon wafer 10, and has nothing to do with its size and shape. The resistivity range of the silicon wafer 10 provided in the embodiment of the present invention can be 0.3Ω·cm~2Ω·cm, for example: 0.3Ω·cm, 0.5Ω·cm, 1.0Ω·cm, 1.6Ω·cm or 2Ω·cm, etc. In actual implementation, the resistivity range of the silicon wafer 10 taken out from the head of the crystal rod is usually 0.9Ω·cm~1.6Ω·cm.

[0060] In some embodiments, the oxygen content of the silicon wafer region corresponding to the oxide layer ring 20 is greater than the oxygen content of the first region 100 , and the first region 100 is a non-oxide layer ring region between the silicon wafer edge and the outer boundary of the oxide layer ring 20 .

[0061] like Figure 5 As shown, in the case where the silicon wafer 10 includes one oxide layer discrepancy ring 20, the silicon wafer 10 can be divided into four regions. The first region 100 is a non-oxide layer discrepancy ring region between the edge of the silicon wafer and the outer boundary of the oxide layer discrepancy ring 20, the second region 400 is a non-oxide layer discrepancy ring region including the center of the silicon wafer in the region formed by the inner boundary of the oxide layer discrepancy ring 20, the fourth region 300 is an intermediate region between the boundary of the second region 400 and the inner boundary of the oxide layer discrepancy ring 20, and the third region 200 is a region corresponding to the oxide layer discrepancy ring 20. Among them, the first region 100, the second region 400 and the fourth region 300 are all non-oxide layer discrepancy ring regions, and the third region 200 is the silicon wafer region corresponding to the oxide layer discrepancy ring 20.

[0062] It should be noted that the oxygen content distribution of the silicon wafer 10 region is as follows: the oxygen content is highest in the center of the silicon wafer, the oxygen content of the non-oxidized layer staggered ring region extending from the center of the silicon wafer to the surrounding area gradually decreases, and the oxygen content increases again after reaching the silicon wafer region corresponding to the oxide layer staggered ring 20, and the oxygen content of the region between the outer boundary of the silicon wafer region corresponding to the oxide layer staggered ring 20 and the edge of the silicon wafer decreases again. Therefore, the oxygen content of the second region 400 is the highest, and the oxygen content of the third region 200 is greater than the oxygen content of the first region 100.

[0063] In some embodiments, the oxygen content of the silicon wafer region corresponding to the oxide layer ring 20 is less than the oxygen content of the second region 400. The second region 400 is a region formed by the inner boundary of the oxide layer ring 20 and includes a non-oxide layer ring region in the center of the silicon wafer.

[0064] like Figure 5 As shown, the third region 200 is the silicon wafer region corresponding to the oxide layer dislocation ring 20 , and the oxygen content of the third region 200 is less than that of the second region 400 .

[0065] It is understandable that, when the silicon wafer 10 includes a plurality of oxide layer dislocation rings 20 , the oxygen content of the non-oxide layer dislocation ring region between adjacent oxide layer dislocation rings 20 is less than the oxygen content of the silicon wafer region corresponding to the oxide layer dislocation rings 20 .

[0066] In some embodiments, the oxide layer error rings 20 constitute an oxide layer error ring region, and the area of ​​the oxide layer error ring region accounts for a percentage of more than 5% of the area of ​​the silicon wafer.

[0067] In actual implementation, Figure 2 and Figure 3 As shown, one or more oxide layer fault rings 10 are distributed on the silicon wafer 10 after high temperature treatment, such as Figure 6 As shown, the oxide layer fault rings 20 distributed on the silicon wafer 10 after high temperature treatment can also be presented as a partial ring or a fan ring. One or more oxide layer fault rings 20 can form an oxide layer fault ring area, and the area of ​​the oxide layer fault ring area accounts for more than 5% of the area of ​​the silicon wafer, such as 6%, 8% or 10%.

[0068] like Figure 7 As shown, the present invention also provides a photovoltaic module 2000, including a plurality of solar cells 2001, wherein the solar cell 2001 is prepared by the solar cell 100 in any of the above embodiments; the solar cell 2001 that has been subjected to high temperature treatment is distributed with at least one oxide layer fault ring, and the temperature of the high temperature treatment is above 1000°C.

[0069] In actual implementation, the photovoltaic module 2000 is composed of a plurality of solar cells 2001. After a certain treatment of the photovoltaic module, the solar cells 2001 can be separated. If the solar cells 2001 are subjected to a high temperature treatment of more than 1000°C, the solar cells 2001 after the high temperature treatment are distributed with at least one oxide layer fault ring. In the actual production process, the production of the solar cells 2001 in the embodiment of the present invention is subjected to a low temperature process treatment of less than 1000°C.

[0070] The solar cell sheet 2001 in the embodiment of the present invention is prepared from the solar cell 100 in any of the above embodiments. The solar cell 100 has been described in detail in the above embodiments and will not be described again here.

[0071] In some embodiments, the area of ​​the oxide layer fault loop of at least one solar cell 2001 is greater than the area of ​​the oxide layer fault loop of at least one solar cell 2001 in the other solar cells 2001 .

[0072] It is understandable that in a photovoltaic module, there may be the same or different solar cells 2001. For different solar cells 2001, the area of ​​the oxide layer dislocation ring may be different, and thus, the area of ​​the oxide layer dislocation ring of at least one solar cell 2001 after high temperature treatment is greater than the area of ​​the oxide layer dislocation ring of at least one solar cell 2001 after high temperature treatment in other solar cells 2001.

[0073] The ratio of the area of ​​the oxide layer dislocation ring of at least one solar cell to the area of ​​the oxide layer dislocation ring of other solar cells is greater than 10:1 or 5:1.

[0074] Optionally, the ratio of the area of ​​the oxide layer dislocation ring of at least one solar cell 2001 to the area of ​​the oxide layer dislocation ring of at least one solar cell in the other solar cells 2001 is greater than 10:1.

[0075] Optionally, the ratio of the area of ​​the oxide layer dislocation ring of at least one solar cell 2001 to the area of ​​the oxide layer dislocation ring of at least one solar cell 2001 in other solar cells is greater than 5:1.

[0076] The photovoltaic module provided by the embodiment of the present invention uses a silicon wafer that exhibits oxide layer dislocation rings after high-temperature treatment above 1000°C. The process temperature of processing the silicon wafer into a solar cell is lower than 1000°C, and the silicon wafer will not reduce the performance of solar cells produced by a low-temperature process below 1000°C. In addition, the silicon wafer can be obtained from the head or tail of the crystal rod, which greatly improves the utilization rate of the crystal rod, greatly reduces the cost of silicon wafers, and avoids the problem of oxide layer dislocation rings caused by high-temperature processes such as high-temperature TOPCon cells, which leads to a decrease in cell efficiency, thereby ensuring the overall performance and efficiency of the photovoltaic module.

[0077] It is understandable that those skilled in the art can, under the guidance of the above embodiments, combine various implementation methods in the above embodiments to obtain technical solutions of multiple implementation methods.

[0078] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A solar cell, characterized in that: It comprises a silicon wafer, wherein the process temperature of the silicon wafer for processing into the solar cell is lower than 1000°C; after the solar cell is subjected to high temperature treatment, at least one oxide layer staggered ring is distributed on the silicon wafer, and the temperature of the high temperature treatment is above 1000°C.

2. The solar cell according to claim 1, characterized in that: The minority carrier lifetime of the silicon wafer region corresponding to the oxide layer fault ring is 10 μs to 1000 μs.

3. The solar cell according to claim 2, characterized in that: The minority carrier lifetime in the silicon wafer region corresponding to the oxide layer dislocation ring is 34 μs to 210 μs.

4. The solar cell according to claim 1, characterized in that The resistivity of the silicon wafer is 0.3Ω·cm to 2Ω·cm.

5. The solar cell according to claim 1, characterized in that: The oxygen content of the silicon wafer region corresponding to the oxide layer stagger ring is greater than the oxygen content of the first region, and the first region is the non-oxide layer stagger ring region between the edge of the silicon wafer and the outer boundary of the oxide layer stagger ring.

6. The solar cell according to claim 1, characterized in that The oxygen content of the silicon wafer region corresponding to the oxide layer stagger ring is less than the oxygen content of the second region, and the second region is a non-oxide layer stagger ring region including the center of the silicon wafer in the region formed by the inner boundary of the oxide layer stagger ring.

7. The solar cell according to claim 1, characterized in that The oxide layer staggered rings constitute an oxide layer staggered ring region, and the area of ​​the oxide layer staggered ring region accounts for a percentage of more than 5% of the area of ​​the silicon wafer.

8. A photovoltaic module, characterized in that: The invention comprises a plurality of solar cells, wherein the solar cells are prepared by the solar cells according to any one of claims 1 to 7, and the solar cells are distributed with at least one oxide layer fault ring after high temperature treatment, and the temperature of the high temperature treatment is above 1000°C.

9. The photovoltaic module according to claim 8, characterized in that: The area of ​​the oxide layer dislocation ring of at least one solar cell is larger than the area of ​​the oxide layer dislocation ring of at least one solar cell among the other solar cells.

10. The photovoltaic module according to claim 9, characterized in that: The ratio of the area of ​​the oxide layer dislocation ring of the at least one solar cell to the area of ​​the oxide layer dislocation ring of at least one solar cell in the other solar cells is greater than 10:

1.

11. The photovoltaic module according to claim 9, characterized in that: The ratio of the area of ​​the oxide layer dislocation ring of the at least one solar cell to the area of ​​the oxide layer dislocation ring of at least one solar cell in the other solar cells is greater than 5:1.

Images