Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. The display device may include: a substrate; a driving element layer disposed on the substrate; a line layer disposed on the driving element layer and including a first inorganic layer and a second inorganic layer disposed on the first inorganic layer; and a light emitting element layer disposed on the line layer and including a plurality of first electrodes, an intermediate layer, and a second electrode sequentially stacked on each other. The line layer may include a trench between the first electrodes, the first inorganic layer and the second inorganic layer being absent in the trench. The second inorganic layer may include an undercut region in the trench below the first inorganic layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority and all benefits obtained from Korean Patent Application No. 10-2023-0102176 filed in the Korean Intellectual Property Office on August 4, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0004] A wearable device in the form of glasses or a helmet presents an image at a short distance in front of the user's eyes. For example, the wearable device may be a head mounted display (HMD) device or augmented reality (AR) glasses. Such a wearable device provides the user with an augmented reality (hereinafter referred to as "AR") image or a virtual reality (hereinafter referred to as "VR") image.

[0005] Wearable devices such as HMD devices and AR glasses require a display specification of at least 2000 pixels per inch (PPI) to allow users to use it for a long time without dizziness. For this reason, organic light emitting diode on silicon (OLEDoS) technology is emerging, which is used for high-resolution small organic light emitting element display devices. OLEDoS technology is a technology for providing an organic light emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is provided.

[0006] In a display panel using OLEDoS technology, leakage current may occur between adjacent pixels because the distance between pixels is short. The leakage current may be generated by some of the multiple conductive layers provided between the pixel electrode (e.g., anode electrode) and the common electrode (e.g., cathode electrode). Such leakage current may cause undesirable color crosstalk between adjacent pixels. Summary of the invention

[0007] Aspects of the present disclosure provide a display device in which at least some of a plurality of intermediate layers disposed between a pixel electrode and a common electrode are disconnected between adjacent pixels to prevent leakage current and color crosstalk, and a method of manufacturing the display device.

[0008] According to an embodiment of the present disclosure, a display device may include: a substrate; a driving element layer, the driving element layer being disposed on the substrate; a line layer, the line layer being disposed on the driving element layer and including a first inorganic layer and a second inorganic layer disposed on the first inorganic layer; and a light-emitting element layer, the light-emitting element layer being disposed on the line layer and including a plurality of first electrodes, an intermediate layer, and a second electrode stacked sequentially on each other. The line layer may include a groove between the plurality of first electrodes, the groove being free of the first inorganic layer and the second inorganic layer. The second inorganic layer may include an undercut region below the first inorganic layer in the groove. The first portion of the intermediate layer and the second portion of the second electrode may be disposed in the groove, and the first portion of the intermediate layer may be disconnected from the third portion of the intermediate layer disposed on the first electrode, and the second portion of the second electrode may be connected to a fourth portion of the second electrode overlapping the first electrode.

[0009] The trench may include a first hole in which the first inorganic layer is removed with a first width, and a second hole in which the second inorganic layer is removed with a second width greater than the first width, the second hole including an undercut region extending beyond a sidewall of the first hole.

[0010] At least some of the plurality of conductive layers of the intermediate layer may be disconnected by the trenches.

[0011] The second electrode may be disposed continuously across the trench.

[0012] At least some of the conductive layers include at least one of a hole injection layer, a hole transport layer, an electron transport layer, a charge generation layer, and a p-doped layer.

[0013] The line layer may include an auxiliary line disposed in line with the trench, and the auxiliary line may be electrically connected to a first portion of the intermediate layer disposed on a bottom surface of the trench through a contact hole penetrating at least a portion of the line layer at the bottom surface of the trench.

[0014] The auxiliary line may be supplied with a ground voltage.

[0015] An auxiliary voltage lower than a voltage for driving a plurality of pixels may be applied to the auxiliary line.

[0016] The light emitting element layer may be configured to emit white light.

[0017] The light emitting element layer emits light of a first color in a first emission region associated with a first pixel, emits light of a second color in a second emission region associated with a second pixel, and emits light of a third color in a third emission region associated with a third pixel.

[0018] According to an embodiment of the present disclosure, a display device may include: a substrate; a driving element layer, the driving element layer being disposed on the substrate; a line layer, the line layer being disposed on the driving element layer and including a first inorganic layer and a second inorganic layer disposed on the first inorganic layer; and a light-emitting element layer, the light-emitting element layer being disposed on the line layer and including a plurality of first electrodes, a dummy inorganic film surrounding the plurality of first electrodes, an intermediate layer covering the plurality of first electrodes and the dummy inorganic film, and a second electrode covering the intermediate layer. The line layer may include a groove between first electrodes adjacent to each other, and the first inorganic layer or the second inorganic layer is removed from the groove. The dummy inorganic film may be formed on a side surface of the groove, and the thickness of the dummy inorganic film formed on an upper portion of the side surface of the groove may be greater than the thickness of the dummy inorganic film formed on a lower portion of the side surface of the groove. The first portion of the intermediate layer and the second portion of the second electrode can be set on the dummy inorganic film in the groove, and the first portion of the intermediate layer can be disconnected from the third portion of the intermediate layer set on the first electrode, and the second portion of the second electrode can be continuously connected to the fourth portion of the second electrode set to overlap with multiple first electrodes.

[0019] The trench has an inverse tapered shape in which a width of the trench increases as a thickness of a dummy inorganic film covering a side surface of the trench decreases from an entrance of the trench to a bottom surface of the trench.

[0020] At least some of the plurality of conductive layers of the intermediate layer may be disconnected by the trenches.

[0021] The second electrode may be disposed continuously across the trench.

[0022] At least some of the conductive layers include at least one of a hole injection layer, a hole transport layer, an electron transport layer, a charge generation layer, and a p-doped layer.

[0023] According to an embodiment of the present disclosure, a method for manufacturing a display device may include: forming a driving element layer on a substrate; forming a line layer on the driving element layer, the line layer including a first inorganic layer and a second inorganic layer disposed on the first inorganic layer; and forming a light-emitting element layer on the line layer. Forming the light-emitting element layer may include: forming a plurality of first electrodes on the second inorganic layer; forming a first groove having a first width by removing the second inorganic layer between adjacent first electrodes; forming a second groove having a second width greater than the first width by overetching the first inorganic layer in the first groove; depositing an intermediate layer to cover the plurality of first electrodes, the second inorganic layer, and the first and second grooves; and depositing the second electrode to cover the intermediate layer. In depositing the intermediate layer, the intermediate layer may be disconnected around the first and second grooves.

[0024] In depositing the second electrode, the second electrode may not be disconnected around the first trench and the second trench, but may be continuously connected.

[0025] The light emitting element layer may be configured to emit white light.

[0026] The light emitting element layer emits light of a first color in a first emission region associated with a first pixel, emits light of a second color in a second emission region associated with a second pixel, and emits light of a third color in a third emission region associated with a third pixel.

[0027] The substrate may include a semiconductor wafer substrate.

[0028] According to an embodiment of the present disclosure, a display device may include: a substrate; a driving element layer, the driving element layer being disposed on the substrate; a line layer, the line layer being disposed on the driving element layer and including a first inorganic layer and a second inorganic layer disposed on the first inorganic layer; and a light-emitting element layer, the light-emitting element layer being disposed on the line layer and including a plurality of first electrodes, an intermediate layer, and a second electrode stacked sequentially on each other. The line layer may include a groove between adjacent first electrodes, in which the first inorganic layer and the second inorganic layer may be removed, or the second inorganic layer may be removed. A first portion of the intermediate layer may be disposed in the groove, and the auxiliary line may be electrically connected to the first portion of the intermediate layer.

[0029] The trench has an inverse tapered shape in which a width of the trench increases as a thickness of a dummy inorganic film covering a side surface of the trench decreases from an entrance of the trench to a bottom surface of the trench.

[0030] At least some of the plurality of conductive layers of the intermediate layer may be disconnected at boundaries of the trenches.

[0031] According to an embodiment of the present disclosure, it is possible to prevent leakage current and color crosstalk in a display device by disconnecting at least some of a plurality of intermediate layers disposed between a pixel electrode and a common electrode between adjacent pixels.

[0032] However, the aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0034] Figure 1 is a perspective view showing a display device according to an embodiment of the present disclosure.

[0035] Figure 2 is a plan view showing a display panel according to an embodiment.

[0036] Figure 3 is a block diagram showing a display device according to an embodiment.

[0037] Figure 4 is a circuit diagram of a pixel of a display device according to an exemplary embodiment of the present disclosure.

[0038] Figure 5 is a cross-sectional view showing a portion of a display panel of a display device according to an embodiment of the present disclosure.

[0039] Figure 6 is a cross-sectional view showing a stacked structure of a light emitting element according to an embodiment of the present disclosure.

[0040] Figure 7 is a cross-sectional view showing a stacked structure of a light emitting element according to an embodiment of the present disclosure.

[0041] Figure 8 is a plan view schematically showing a portion of a display area of ​​a display panel according to an embodiment.

[0042] Fig. 9 It is shown Figure 8 A modified view of the shape of the first electrode shown in FIG.

[0043] Fig.10 is a plan view schematically showing a portion of a display area of ​​a display panel according to an embodiment.

[0044] Fig.11 It is shown Fig.10 A modified view of the shape of the first electrode shown in FIG.

[0045] Fig.12 is a cross-sectional view for illustrating a groove formed between adjacent pixels.

[0046] Fig.13 and Fig.14 is a cross-sectional view for illustrating a process of forming a trench according to an embodiment.

[0047] Fig.15 is a cross-sectional view for illustrating a process of depositing an intermediate layer and a second electrode according to an embodiment.

[0048] Fig.16 is a cross-sectional view for illustrating another shape of a groove formed between adjacent pixels.

[0049] Figures 17 to 19 is a cross-sectional view for illustrating a process of forming a trench according to an embodiment.

[0050] Fig. 20 is a cross-sectional view for illustrating a process of depositing an intermediate layer and a second electrode according to an embodiment.

[0051] Fig.21 and Fig. 22 is a cross-sectional view showing a display panel including an auxiliary line according to an embodiment.

[0052] Fig.23 is a view showing an example of a wearable device including a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] The inventive concept will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are shown. The present invention may be embodied in different forms and should not be construed as being limited to the exemplary embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art.

[0054] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In the specification and drawings, like reference numerals refer to like components throughout.

[0055] It will be understood that, although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present invention, the first element discussed below may be named as the second element. Similarly, the second element may also be named as the first element.

[0056] The features of each of the various embodiments of the present disclosure may be combined with each other partially or as a whole and may interact with each other differently technically, and the various embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0057] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0058] Figure 1 is a perspective view showing a display device 10 according to an embodiment of the present disclosure.

[0059] refer to Figure 1The display device 10 can be used in portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be used as a display unit of a television, a laptop computer, a monitor, an electronic billboard, or an Internet of Things (IoT) device. For another example, the display device 10 can be applied to wearable devices such as smart watches, watch phones, glasses-type displays, and head-mounted display (HMD) devices.

[0060] When viewed from the top, the display device 10 may have a shape similar to a quadrilateral shape. For example, when viewed from the top, the display device 10 may have a shape similar to a rectangle having shorter sides in the first direction DR1 and longer sides in the second direction DR2. Alternatively, when viewed from the top, the display device 10 may have a shape similar to a rectangle having longer sides in the first direction DR1 and shorter sides in the second direction DR2. Figure 1 , the third direction DR3 refers to a normal direction perpendicular to a plane defined by the first direction DR1 and the second direction DR2. An angle where the short side and the long side meet may be rounded to have a predetermined curvature or may be formed at a right angle. When viewed from the top, the display device 10 is not limited to a quadrilateral shape, but may have a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0061] The display device 10 may include a display panel 110 , a circuit board 120 , and a power supply unit 130 .

[0062] The display panel 110 uses a semiconductor wafer substrate 200 (see Figure 2 ) as a base substrate. The display panel 110 may include a main area MA and a sub area SBA.

[0063] The main area MA may include pixels PX for displaying an image (see Figure 3 ) and a non-display area NDA located around the display area DA. The non-display area NDA may refer to an area outside the display area DA in the main area MA. The display area DA may output light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 110 may include a pixel driving circuit PC including a switching element (see Figure 4 ) and the light-emitting element LEL as a self-luminous element (see Figure 5 ).

[0064] The light emitting element LEL may include but is not limited to at least one of the following: an organic light emitting diode including an organic emission layer, a quantum dot light emitting diode (quantum dot LED) including a quantum dot emission layer, an inorganic light emitting diode (inorganic LED) including an inorganic semiconductor, and a micro light emitting diode (micro LED).

[0065] The non-display area NDA may be disposed outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 110. The non-display area NDA may include fan-out lines (not shown) extending from lines (e.g., gate lines, data lines, and emission control lines) of the display area DA and connecting the fan-out lines to the display driving circuit 210 (see Figure 2 ) is connected to a display pad (not shown).

[0066] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a main pad area connected to the circuit board 120. Alternatively, the sub-area SBA may be eliminated and the main pad area may be located in the non-display area NDA.

[0067] The circuit board 120 may be attached to the main pad area of ​​the display panel 110 using an anisotropic conductive film (ACF). Leads of the circuit board 120 may be electrically connected to the main pad area of ​​the display panel 110. The circuit board 120 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film (COF).

[0068] The power supply unit 130 may be provided on the circuit board 120 to apply a supply voltage to the display driving circuit 210 and the display panel 110. The power supply unit 130 may generate a supply voltage (or a power supply voltage) to provide the supply voltage to the supply voltage line. For example, the supply voltage may include a high level voltage ( Figure 4 The first power supply voltage ELVDD in the low level voltage ( Figure 4 The second power supply voltage ELVSS in the embodiment of the present invention) and the initialization voltage VINT (see Figure 4 ).

[0069] Figure 2 is a plan view showing a display panel 110 according to an embodiment.

[0070] refer to Figure 2, the display panel 110 may be an organic light emitting diode on silicon (OLEDoS) panel using a semiconductor wafer substrate as a base substrate. For example, the display panel 110 may include a substrate 200, and the substrate 200 may be a semiconductor wafer substrate. In this document, the substrate may be referred to as, but not limited to, a semiconductor substrate, a semiconductor wafer substrate, or a wafer substrate.

[0071] According to the embodiment, the pixel driving circuit PC (see Figure 4 ) and a display driving circuit 210 for controlling the pixel driving circuit may be disposed on the front surface 201 of the substrate 200. The pixel driving circuit PC is disposed in contact with the pixels PX in the display area DA (see Figure 3 ) of the light-emitting element LEL (see Figure 5 The display driving circuit 210 is disposed in the non-display area NDA and drives the pixel driving circuit PC.

[0072] Pixel drive circuit PC (see Figure 4 ) and the display driving circuit 210 may be formed on a driving element layer 501 disposed on the front surface 201 of the substrate 200 (see Figure 5 ). The driving element layer 501 may include, for example, an n-type metal oxide semiconductor field effect transistor (MOSFET) and / or a p-type MOSFET. In this document, the driving element layer 501 (see Figure 5 ) can be called but not limited to MOSFET layer, CMOS layer, transistor layer or backplane layer, etc.

[0073] Figure 3 FIG. 1 is a diagram showing a display device 10 according to an embodiment (see FIG. Figure 1 ) block diagram.

[0074] refer to Figure 3 The display device 10 includes a display driving circuit 210 incorporated into the display panel 110. The display driving circuit 210 is formed on a front surface 201 (see FIG. 2 ) of the substrate 200. Figure 2 ) on the driving element layer 501 (see Figure 5 ). The display driving circuit 210 may include, but is not limited to, a timing controller 310, a gate driver 320, an emission control driver 330, and a data driver 340. Although not shown in the drawings, the display driving circuit 210 may further include a memory (e.g., a one-time programmable (OTP) memory), an interface circuit (e.g., an I / F circuit), an image processing circuit (e.g., a logic circuit), and / or a gamma correction circuit.

[0075] The display area DA of the display panel 110 includes a plurality of pixels PX arranged in a matrix. Each of the plurality of pixels PX may be connected to a first power supply voltage line VDL, a second power supply voltage line VSL, a gate line GL, an emission control line EML, an initialization line VIL, and a data line DL.

[0076] The first power supply voltage line VDL receives a first power supply voltage ELVDD (see FIG. Figure 4 ) is supplied to the plurality of pixels PX. The second power supply voltage line VSL receives the second power supply voltage ELVSS (see FIG. 1 ) input from the power supply unit 130. Figure 4 ) is supplied to a plurality of pixels PX. The gate line GL receives gate signals GI and GW (see Figure 4 ) is supplied to a plurality of pixels PX. The emission control line EML receives the emission control signal EM (see Figure 4 ) is supplied to the plurality of pixels PX. The initialization line VIL receives the initialization voltage VINT (see Figure 4 The data lines DL supply the analog data voltages input from the data driver 340 to the pixels PX.

[0077] The first power supply voltage ELVDD may be a high level voltage, and the second power supply voltage ELVSS may be a low level voltage. For example, the first power supply voltage ELVDD may have a higher voltage level than the second power supply voltage ELVSS. Figure 4 ) may have a pixel driving circuit PC for initializing each frame (see Figure 4 )'s potential.

[0078] Figure 3 One gate line GL shown in FIG. 1 may include, but is not limited to, a first gate line GWL and a second gate line GIL.

[0079] Each of the plurality of pixels PX may include a light emitting element LEL (see Figure 4 ) and a pixel driving circuit PC for driving the light emitting element LEL (see Figure 4 ) of multiple transistors and at least one capacitor.

[0080] The timing controller 310 can be connected to the circuit board 120 (see Figure 1) receives the data signal DATA and the timing signal. The timing controller 310 can control the operation timing of the data driver 340 by generating the data control signal DCS based on the timing signal. The timing controller 310 can control the operation timing of the gate driver 320 by generating the gate control signal GCS based on the timing signal. The timing controller 310 can control the operation timing of the emission control driver 330 by generating the emission control signal ECS based on the timing signal.

[0081] The data driver 340 may convert the data signal DATA into an analog data voltage and may provide the converted analog data voltage to the pixel PX through the data line DL. The gate signal from the gate driver 320 may be used to select the pixel PX to which the data voltage is applied, and the selected pixel PX may receive the data voltage through the data line DL.

[0082] The power supply unit 130 may be provided on the circuit board 120 to apply a power supply voltage to the display driving circuit 210 and the display panel 110. The power supply unit 130 may generate a power supply voltage to supply the power supply voltage to the first power supply voltage line VDL. The power supply unit 130 may generate a common voltage to supply the common voltage to the second electrode (e.g., Figure 5 The second electrode CAE).

[0083] The gate driver 320 may provide gate signals GI and GW to the pixels PX through the gate lines GL (see Figure 4 ).

[0084] The emission control driver 320 may provide an emission control signal EM to the pixel PX through the emission control line EML (see Figure 4 ).

[0085] Figure 4 is a display device 10 according to an exemplary embodiment of the present disclosure (see Figure 1 ) pixel circuit diagram.

[0086] refer to Figure 4 , the pixel PX may include a light emitting element LEL (e.g., an organic light emitting diode) as a display element and a pixel driving circuit PC connected to the light emitting element LEL. The pixel driving circuit PC may include, but is not limited to, a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4 and a first capacitor C1. The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be implemented as an n-type metal oxide semiconductor field effect transistor (MOSFET) and / or a p-type MOSFET. Although in Figure 4In the example shown in FIG. 1 , the first transistor T1 , the second transistor T2 , the third transistor T3 , and the fourth transistor T4 are p-type MOSFETs, but the present disclosure is not limited thereto.

[0087] The first transistor T1 may be a driving transistor that determines a source-drain current according to a gate-source voltage. Each of the second to fourth transistors T2 to T4 may be a switching transistor that is turned on / off according to a gate-source voltage (substantially a gate voltage).

[0088] The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3. The first transistor T1 is turned on or off based on the voltage level of the first node N1. In the on state, the first transistor T1 connects the second node N2 to the third node N3. The second node N2 is connected to the source electrode of the third transistor T3, and the second node N2 is supplied with the first power supply voltage ELVDD when the third transistor T3 is turned on in response to the emission control signal EM. The third node N3 is connected to the first electrode ANE of the light emitting element LEL (see Figure 5 ) and a drain electrode of the fourth transistor T4. When the fourth transistor T4 is turned on in response to the second gate signal GI, the third node N3 is supplied with the initialization voltage VINT.

[0089] The second transistor T2 includes a gate electrode connected to the first gate line GWL, a source electrode connected to the data line DL, and a drain electrode connected to the first node N1. The second transistor T2 is turned on in response to the first gate signal GW supplied from the first gate line GWL. The turned-on second transistor T2 supplies the data voltage Vdat from the data line DL to the first node N1.

[0090] The third transistor T3 includes a gate electrode connected to an emission control line EML, a source electrode connected to a first power supply voltage line VDL, and a drain electrode connected to a second node N2, and the first power supply voltage ELVDD is supplied from the first power supply voltage line VDL. The third transistor T3 is turned on in response to an emission control signal EM supplied from the emission control line EML. In the on state, the third transistor T3 supplies the first power supply voltage ELVDD to the second node N2.

[0091] The fourth transistor T4 includes a gate electrode connected to the second gate line GIL, a source electrode connected to the initialization line VIL, and a drain electrode connected to the third node N3, and the initialization voltage VINT is supplied from the initialization line VIL. The fourth transistor T4 is turned on in response to the second gate signal GI supplied from the second gate line GIL. The turned-on fourth transistor T4 supplies the initialization voltage VINT to the third node N3.

[0092] The first capacitor C1 is disposed between the first node N1 and the second node N2. The first capacitor C1 may store the data voltage Vdat input through the second transistor T2.

[0093] The light emitting element LEL may include a first electrode (eg, Figure 5 A first electrode ANE), a second electrode facing the first electrode (eg, Figure 5 The second electrode CAE) and an intermediate layer disposed between the first electrode and the second electrode. The intermediate layer may include an organic light emitting layer. The second electrode may receive a second power supply voltage ELVSS. The second electrode may be connected to a second power supply voltage line VSL that transmits the second power supply voltage ELVSS. The second electrode may be commonly connected to a plurality of pixels PX.

[0094] Figure 5 FIG. 1 is a diagram showing a display device 10 according to an embodiment (see FIG. Figure 1 ) is a cross-sectional view of a portion of the display panel 110. For example, Figure 5 1 is a view schematically illustrating a stack structure of each of the non-display area NDA and the display area DA of the display panel 110 according to an embodiment.

[0095] In reference Figure 5 In the description of the present invention, an element disposed "on" the substrate 200 may mean that the element is disposed on the front surface 201 of the substrate 200 in the third direction DR3 (see Figure 2 The front surface 201 of the substrate 200 may refer to a side of the substrate 200 in a direction in which the light emitting element LEL disposed in the display area DA emits light for displaying an image.

[0096] refer to Figure 5 , the display panel 110 according to the embodiment may include a substrate 200 , and the substrate 200 may be a semiconductor wafer substrate.

[0097] The display driver circuit 210 (see Figure 3 ) and pixel drive circuit PC (see Figure 4 ), a driving element layer 501 including at least one line layer 502, a light emitting element layer 503 including a light emitting element LEL, an encapsulation layer 504 covering the light emitting element LEL, a color filter layer 505 including a color filter CF, a light control layer 506 including a refractive film MLA, and a covering layer 507 including a covering member CV may be sequentially stacked on the front surface 201 of the substrate 200 (see Figure 2 At least some of the light emitting element layer 503, the encapsulation layer 504, the color filter layer 505, the light control layer 506, and the cover layer 507 may not be disposed in the non-display area NDA.

[0098] The substrate 200 may be a silicon substrate, a germanium substrate or a silicon germanium substrate. The substrate 200 may be a substrate doped with first type impurities.

[0099] The driving element layer 501 including n-type MOSFET and / or p-type MOSFET is disposed on the substrate 200. The first type impurity may be a p-type impurity, and the second type impurity may be an n-type impurity. Alternatively, the first type impurity may be an n-type impurity, and the second type impurity may be a p-type impurity.

[0100] In the following description, an n-type MOSFET MOS included in the driving element layer 501 will be described as an example. The n-type MOSFET MOS (also referred to as MOSFET MOS) may include a well WL doped with n-type impurities in a substrate doped with p-type impurities.

[0101] The well WL may include a first low-concentration impurity region LDD1 and a second low-concentration impurity region LDD2 having a relatively lower impurity concentration than other portions. The first low-concentration impurity region LDD1 may define a source region S1, and the second low-concentration impurity region LDD2 may define a drain region D1. A source electrode SE of the MOSFET MOS may be connected to the source region S1, and a drain electrode DE of the MOSFET MOS may be connected to the drain region D1.

[0102] A channel CH overlapping the gate G1 is defined between the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. An oxide film (not shown) may be provided between the gate G1 and the well WL as an insulating layer.

[0103] MOSFET MOS forms the display driving circuit 210 (see Figure 2 ), and the display driving circuit 210 is disposed in the non-display area NDA of the display panel 110. In addition, the MOSFET MOS forms transistors T1, T2, T3, and T4 included in the pixel driving circuit PC (see Figure 4 ), and the pixel driving circuit PC is arranged in the display area DA of the display panel 110. That is, each pixel driving circuit PC includes a combination of MOSFET MOS in the driving element layer 501 arranged in the display area DA. In addition, the display driving circuit 210 includes a combination of MOSFET MOS in the driving element layer 501 arranged in the non-display area NDA. Figure 5 In the example shown in FIG. 1 , for convenience of explanation, one MOSFET MOS of the pixel driving circuit PC provided in the display area DA of the display panel 110 is shown.

[0104] At least one wire layer 502 is disposed on the driving element layer 501. At least one wire layer 502 includes insulating layers VIA sequentially stacked on the driving element layer 501 and connection electrodes CE and a plurality of wires (not shown) connected to the MOSFET MOS by penetrating contact holes CT1 in at least some of the insulating layers VIA. That is, the wire layer 502 includes the connection electrodes CE and a plurality of connection wires that connect the MOSFET MOS of the driving element layer 501 to each other and the insulating layer VIA for insulating them from each other. In addition, the wire layer 502 may include a plurality of signal lines and a plurality of power lines for driving the display panel 110.

[0105] Figure 5 The connection electrode CE shown in FIG. 5 connects some MOSFET MOS associated with the pixel driving circuit PC among the plurality of MOSFET MOS provided in the driving element layer 501 to the light emitting element LEL provided on the line layer 502 in the vertical direction. Herein, the vertical direction refers to the normal direction of the display panel 110 (third direction DR3).

[0106] The lines (not shown) provided in the line layer 502 include lines connected to the pixel driving circuit PC (eg, Figure 3 The lines disposed in the line layer 502 may further include fan-out lines (not shown) disposed in the non-display area NDA and extending from lines connected to the pixel driving circuit PC (e.g., Figure 3 The gate line GL, the data line DL, and the emission control line EML) extend therefrom.

[0107] The wiring layer 502 may include pad electrodes PD1, PD2, PD3, PD4, PD5, PD6, and PD7 disposed in the non-display area NDA. The pad electrodes PD1, PD2, PD3, PD4, PD5, PD6, and PD7 may include a first gate pad PD1 connected to a first gate line GWL, a second gate pad PD2 connected to a second gate line GIL (see FIG. Figure 3 ) is connected to the second gate pad PD2 of the initialization line VIL (see Figure 3 ), an initialization pad PD3 connected to an emission control line EML, an emission pad PD4 connected to a data line DL, a data pad PD5 connected to a first power supply voltage line VDL (see Figure 3 ) and a first driving voltage pad PD6 connected to a second power supply voltage line VSL (see Figure 3 ) of the second driving voltage pad PD7. It should be noted that, Figure 5 The pad electrodes PD1 , PD2 , PD3 , PD4 , PD5 , PD6 , and PD7 shown in FIG. 1 are merely illustrative, and the present disclosure is not limited thereto.

[0108] In the uppermost layer of the insulating layer VIA included in the line layer 502, a planarization layer FL including an organic film and a plurality of inorganic layers 1210 disposed on the planarization layer FL may be disposed. Figures 6 to 20 As described, the inorganic layer 1210 between adjacent pixels PX is partially removed so that a groove TC is formed. Due to the groove TC, the intermediate layer ML of the light emitting element LEL is disconnected between adjacent pixels PX during the process of depositing the intermediate layer ML of the light emitting element LEL. According to an embodiment, it is possible to prevent leakage current between adjacent pixels PX and prevent color crosstalk by disconnecting the intermediate layer ML of the light emitting element LEL between adjacent pixels PX. For example, color crosstalk refers to a phenomenon in which a red pixel (e.g., the first pixel PX1) adjacent to the blue pixel (e.g., the third pixel PX3) is unintentionally turned on when a blue pixel (e.g., the third pixel PX3) emits blue light. Because color crosstalk occurs due to leakage current, if a blue pixel and a red pixel having a large difference in voltage for driving the pixel are adjacent to each other, color crosstalk may occur. For example, while a driving current is supplied to the light emitting element LEL of the blue pixel so as to turn on the blue pixel, a portion of the driving current may be transmitted to the red pixel (e.g., the first pixel PX1) through at least some conductive layers in the intermediate layer ML as a leakage current. If leakage current is generated, the red pixel may be turned on unintentionally at the same time as the blue pixel is turned on.

[0109] A light emitting element layer 503 including a light emitting element LEL may be disposed on the line layer 502. The light emitting element LEL includes a first electrode ANE, an intermediate layer ML disposed on the first electrode ANE, and a second electrode CAE disposed on the intermediate layer ML, the first electrode ANE being connected to a MOSFET MOS included in the pixel driving circuit PC through a contact hole CT1211 and a connection electrode CE.

[0110] The intermediate layer ML may include but is not limited to a hole injection layer HIL (see Figure 6 ), hole transport layer HTL (see Figure 6 ), emission layer, electron transport layer ETL (see Figure 6 ) and the electron injection layer EIL (see Figure 6). For example, the light emitting element LEL may be an RGB type light emitting element LEL that emits a first color light (e.g., red light) in a first pixel PX1 (e.g., red pixel), emits a second color light (e.g., green light) in a second pixel PX2 (e.g., green pixel), and emits a third color light (e.g., blue light) in a third pixel PX3 (e.g., blue pixel). Alternatively, the light emitting element LEL may be a white OLED (WOLED) type light emitting element LEL that equally emits white light in the first pixel PX1 (e.g., red pixel), the second pixel PX2 (e.g., green pixel), and the third pixel PX3 (e.g., blue pixel).

[0111] The stacked structure of the organic material included in the middle layer ML may have different structures depending on whether the light emitting element LEL is an RGB type light emitting element or a WOLED type light emitting element. However, it should be understood that the present disclosure is not limited thereto.

[0112] An encapsulation layer 504 including at least one organic encapsulation layer and at least one inorganic encapsulation layer may be disposed on the light emitting element layer 503. For example, the encapsulation layer 504 may include, but is not limited to, a first inorganic encapsulation film TFE1, an organic encapsulation film TFE2, and a second inorganic encapsulation film TFE3.

[0113] A color filter layer 505 including a color filter CF may be disposed on the encapsulation layer 504. The color filter CF may include, but is not limited to, a first color filter CF1 that transmits red light (see Figure 6 ), a second color filter CF2 that transmits green light (see Figure 6 ) and a third color filter CF3 that transmits blue light (see Figure 6 ). The color filter layer 505 may be provided in a display device in which the light emitting element LEL of the light emitting element layer 503 is a WOLED type light emitting element LEL. If the light emitting element LEL of the light emitting element layer 503 independently emits red light, green light, and blue light, the color filter layer 505 may be omitted.

[0114] The light control layer 506 including the refractive film MLA is disposed on the color filter layer 505. The refractive film MLA may refract light incident thereon so that light emitted from the light emitting element layer 503 is directed toward the normal direction (third direction DR3) of the display panel 110. The refractive film MLA may include a microlens array.

[0115] A cover layer 507 serving as a cover of the display panel 110 may be disposed on the light control layer 506. The cover layer 507 may include, but is not limited to, a cover member CV made of a glass material. The cover layer 507 may include, for example, a protective film.

[0116] Figure 6Schematically shows a cross-sectional view of a stacked structure of a light emitting element LEL according to an embodiment. Figure 6 In the stacked structure of the middle layer ML shown in , the light emitting element LEL of the light emitting element layer 503 is a WOLED type light emitting element LEL.

[0117] refer to Figure 6 According to an embodiment, the display panel 110 may include a plurality of pixels PX, the plurality of pixels PX including a first pixel PX1 for displaying a first color (e.g., red), a second pixel PX2 for displaying a second color (e.g., green), and a third pixel PX3 for displaying a third color (e.g., blue).

[0118] The light emitting elements LEL disposed in the first pixel PX1, the second pixel PX2, and the third pixel PX3 emit white light. The display panel 110 uses color filters to display the first color, the second color, and the third color. For example, the white light emitted from the first pixel PX1 is converted into the first color by the first color filter CF1, the white light emitted from the second pixel PX2 is converted into the second color by the second color filter CF2, and the white light emitted from the third pixel PX3 is converted into the third color by the third color filter CF3.

[0119] A first electrode ANE (eg, a pixel electrode or an anode electrode) is disposed in each of the first, second, and third pixels PX1, PX2, and PX3. An intermediate layer ML and a second electrode CAE are disposed on the first electrode ANE of each of the first, second, and third pixels PX1, PX2, and PX3.

[0120] The middle layer ML and the second electrode CAE may be a common layer commonly stacked in the first pixel PX1 , the second pixel PX2 , and the third pixel PX3 and at least partially connected to each other between the plurality of pixels PX.

[0121] The middle layer ML may include, but is not limited to, a first emission unit EU1, a charge generation layer CGL, a second emission unit EU2, a charge generation layer CGL, and a third emission unit EU3 sequentially stacked on the first electrode ANE of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. That is, the order and structure of the layers of the middle layer ML may be changed in various ways.

[0122] The first emission unit EU1 may include a hole injection layer HIL or a p-doped layer PHIL doped with a p-type semiconductor, a blue emission layer BEML, and an electron transport layer ETL. The second emission unit EU2 may include a hole transport layer HTL, a green emission layer GEML, and an electron transport layer ETL. The third emission unit EU3 may include a hole transport layer HTL, a red emission layer REML, and an electron transport layer ETL.

[0123] The charge generation layer CGL is disposed between the first emission unit EU1 and the second emission unit EU2. In addition, the charge generation layer CGL may be disposed between the second emission unit EU2 and the third emission unit EU3. The charge generation layer CGL may include a negative charge generation layer and a positive charge generation layer.

[0124] The second electrode CAE is disposed on the third emission unit EU3. The second electrode CAE may be a common layer commonly stacked in the first pixel PX1, the second pixel PX2, and the third pixel PX3 and at least partially extending across the plurality of pixels PX.

[0125] The cap layer CPL may be disposed on the second electrode CAE. Although not shown in the figure, the encapsulation layer 504 (see Figure 5 ) may be disposed on the capping layer CPL, and the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on the encapsulation layer 504. The capping layer CPL may be used to improve emission efficiency through the principle of constructive interference.

[0126] In the display panel 110 according to the embodiment, since the intermediate layer ML disposed between the first electrode ANE and the second electrode CAE is commonly stacked in the first pixel PX1, the second pixel PX2, and the third pixel PX3 and is at least partially connected to each other among the plurality of pixels PX, leakage current may occur. Figure 6 As indicated by arrows 601 in FIG. 6 , leakage current may flow between adjacent pixels PX through at least some conductive layers included in the middle layer ML.

[0127] In the display panel 110 according to the embodiment, the groove TC is formed between the pixels PX to prevent leakage current. For example, the groove TC is formed between the first electrodes ANE of the adjacent pixels PX and is formed by removing a portion of the inorganic layer included in the line layer 502. The groove TC formed between the adjacent pixels PX causes at least some of the conductive layers included in the middle layer ML to be disconnected during the process of depositing the middle layer ML. According to the embodiment of the present disclosure, as shown in FIG. Figure 6As indicated by the solid line 602 in FIG. 5 , at least some of the plurality of conductive layers included in the middle layer ML are disconnected around the trench TC formed between adjacent pixels PX, so that it is possible to prevent leakage current and color crosstalk. Herein, at least some of the conductive layers of the middle layer ML disconnected around the trench TC may include at least one of a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, a charge generation layer CGL, and a p-doped layer PHIL.

[0128] Even if the trench TC is located between adjacent pixels PX, the metal of the second electrode CAE will not be disconnected because the metal of the second electrode CAE has a step coverage ratio that is better than the step coverage ratio of the organic material forming the intermediate layer ML. Specifically, when the intermediate layer ML is disconnected around the trench TC, the second electrode CAE is not disconnected around the trench TC. Therefore, the second electrode CAE can extend continuously across adjacent pixels PX.

[0129] Will refer to later Figures 8 to 22 The structure of the trench TC and the disconnection of the middle layer ML according to an embodiment of the present disclosure are described in detail.

[0130] Figure 7 Schematically shows a cross-sectional view of a stacked structure of a light emitting element LEL according to an embodiment. Figure 7 A stacked structure of the middle layer ML of the RGB type light emitting element LEL that independently emits red light in the first pixel PX1 , green light in the second pixel PX2 , and blue light in the third pixel PX3 is shown.

[0131] refer to Figure 7 According to an embodiment, the display panel 110 may include a plurality of pixels PX, including a first pixel PX1 for displaying a first color (e.g., red), a second pixel PX2 for displaying a second color (e.g., green), and a third pixel PX3 for displaying a third color (e.g., blue).

[0132] Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may independently emit light of a predetermined color. For example, in the first pixel PX1, the light emitting element LEL includes a red emission layer REML to emit red light in the first emission region, in the second pixel PX2, the light emitting element LEL includes a green emission layer GEML to emit green light in the second emission region, and in the third pixel PX3, the light emitting element LEL includes a blue emission layer BEML to emit blue light in the third emission region. In the first emission region, the first electrode ANE disposed in the first pixel PX1 may be covered by the intermediate layer ML. In the second emission region, the first electrode ANE disposed in the second pixel PX2 may be covered by the intermediate layer ML. In the third emission region, the first electrode ANE disposed in the third pixel PX3 may be covered by the intermediate layer ML.

[0133] A first electrode ANE (e.g., a pixel electrode or an anode electrode) is disposed in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. An intermediate layer ML and a second electrode CAE are disposed on the first electrode ANE of each of the first pixel PX1, the second pixel PX2, and the third pixel PX3. In the intermediate layer ML, a first common layer (e.g., a lower common layer) CL1, an emission layer, a second common layer (e.g., an upper common layer) CL2, and a second electrode CAE are disposed.

[0134] The first common layer CL1, the second common layer CL2, and the second electrode CAE may be commonly stacked in the first pixel PX1, the second pixel PX2, and the third pixel PX3, and may extend at least partially across the pixel PX. In contrast, different emission layers REML, GEML, and BEML may be respectively disposed between the first common layer CL1 and the second common layer CL2 in the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example, a red emission layer REML may be disposed in the first pixel PX1, a green emission layer GEML may be disposed in the second pixel PX2, and a blue emission layer BEML may be disposed in the third pixel PX3. They may be disconnected from each other at the boundary of the pixel PX.

[0135] The first common layer CL1 may be disposed under the emission layers REML, GEML and BEML and may include but is not limited to a hole injection layer HIL or a p-doped layer PHIL doped with a p-type semiconductor and a hole transport layer HTL. For example, the first common layer CL1 may include at least one hole injection layer HIL and at least one hole transport layer HTL.

[0136] The second common layer CL2 may be disposed on the emission layers REML, GEML, and BEML, and may include, but is not limited to, an electron transport layer ETL and an electron injection layer EIL. For example, the second common layer CL2 may include at least one electron transport layer ETL and at least one electron injection layer EIL.

[0137] The cap layer CPL may be disposed on the second electrode CAE. The cap layer CPL may be used to improve emission efficiency through the principle of constructive interference.

[0138] and Figure 6 The embodiments are different. Figure 7 An embodiment does not include a color filter.

[0139] and Figure 6 Similar to the embodiment of Figure 7 In the display panel 110 of the embodiment shown in FIG. 1 , the first common layer CL1 and the second common layer CL2 disposed between the first electrode ANE and the second electrode CAE are commonly stacked in the first pixel PX1, the second pixel PX2, and the third pixel PX3 and are at least partially connected to each other between the plurality of pixels PX. Therefore, leakage current may be generated through the first common layer CL1 and the second common layer CL2. Figure 7 As indicated by arrows 701 in FIG. 7 , leakage current may flow between adjacent pixels PX through at least some conductive layers included in the first common layer CL1 and the second common layer CL2 .

[0140] In the display panel 110 according to the embodiment, the groove TC is formed between the pixels PX to prevent leakage current. For example, the groove TC is formed between the first electrodes ANE of the adjacent pixels PX and is formed by removing a portion of the inorganic layer included in the line layer 502. The groove TC formed between the adjacent pixels PX causes at least some of the conductive layers included in the middle layer ML to be disconnected during the process of depositing the middle layer ML. According to the embodiment of the present disclosure, as shown in FIG. Figure 7 As indicated by the solid line 702 in FIG. 1 , at least some of the conductive layers included in the middle layer ML are disconnected around the trench TC formed between adjacent pixels PX, so that leakage current and color crosstalk can be prevented. Herein, at least some of the conductive layers of the middle layer ML disconnected around the trench TC may include at least one of a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, and an electron injection layer EIL.

[0141] Even if the trench TC is located between adjacent pixels PX, the metal of the second electrode CAE is not disconnected because the metal of the second electrode CAE has a step coverage ratio that is better than the step coverage ratio of the organic material forming the middle layer ML. Specifically, when the middle layer ML is disconnected around the trench TC, the second electrode CAE is not disconnected near the trench TC. Therefore, the second electrode CAE can extend continuously across adjacent pixels PX.

[0142] As is well known, a driving voltage for driving a blue pixel is higher than a driving voltage for driving a red pixel. Therefore, leakage current and color crosstalk may occur between blue pixels and red pixels adjacent to each other. According to an embodiment, in order to prevent a blue pixel and a red pixel from being adjacent to each other, a first pixel PX1 (e.g., a red pixel), a second pixel PX2 (e.g., a green pixel), and a third pixel PX3 (e.g., a blue pixel) are arranged as follows: Figures 8 to 11 Arranged as shown in .

[0143] Figure 8 is a plan view schematically showing a portion of the display area DA of the display panel 110 according to the embodiment.

[0144] refer to Figure 8 , the display panel 110 includes a plurality of pixels PX including a first pixel PX1, a second pixel PX2, and a third pixel PX3. The pixels PX are arranged in a matrix in the display area DA of the display panel 110 so that the first pixel PX1 emitting red light and the third pixel PX3 emitting blue light are arranged adjacent to each other in a diagonal direction. The first pixel PX1 and the second pixel PX2 are alternately arranged in each odd row 811, and the second pixel PX2 and the third pixel PX3 may be alternately arranged in each even row 812. In addition, the first pixel PX1 disposed in the odd row 811 and the second pixel PX2 disposed in the even row 812 may be disposed adjacent to each other in a column direction (i.e., a vertical direction), and the second pixel PX2 disposed in the odd row 811 and the third pixel PX3 disposed in the even row 812 may be disposed adjacent to each other in a column direction (i.e., a vertical direction). According to an embodiment of the present disclosure, leakage current and color crosstalk may be suppressed by arranging the first pixel PX1 and the third pixel PX3 so that they are located as far as possible relative to each other.

[0145] According to an embodiment, the trench TC is formed between the pixels PX by removing some of the plurality of inorganic layers included in the line layer 502. Figure 8 , a solid line (eg, Figure 8The line 801 of FIG. 8 indicates first electrodes ANE disposed in the first pixel PX1, the second pixel PX2, and the third pixel PX3, respectively. Therefore, the trench TC according to the embodiment may be defined to be located between the first electrodes ANE of adjacent pixels PX.

[0146] According to an embodiment, since the pixels PX are arranged in a matrix, the trenches TC may be formed in a mesh topology to surround the first electrodes ANE of the pixels PX.

[0147] Figure 8 At least some of the first pixel PX1, the second pixel PX2, and the third pixel PX3 shown in FIG. 3 may be replaced with a fourth pixel emitting white light. For example, the fourth pixel emitting white light and the third pixel PX3 emitting blue light may be alternately arranged in each even-numbered row.

[0148] Fig. 9 It is shown Figure 8 . In addition to each first electrode ANE having a hexagonal shape when viewed from the top, Fig. 9 Examples and Figure 8 That is, the display panel 110 according to the embodiment of the present disclosure is not limited to having the first electrode ANE in a rectangular shape, but may have a first electrode ANE in a rectangular shape. Fig. 9 The first electrode ANE shown in FIG. 1 is hexagonal in shape.

[0149] Fig.10 is a plan view schematically showing a portion of the display area DA of the display panel 110 according to the embodiment. Fig.11 It is shown Fig.10 A modified view of the shape of the first electrode ANE shown in FIG.

[0150] refer to Fig.10, the display panel 110 includes a plurality of pixels PX including a first pixel PX1, a second pixel PX2, and a third pixel PX3. The pixels PX are arranged in a matrix in the display area DA of the display panel 110 so that the second pixel PX2 emitting green light is arranged between the first pixel PX1 emitting red light and the third pixel PX3 emitting blue light. For example, the first pixel PX1 is arranged in the first column 1011, the second pixel PX2 is arranged in the second column 1012, and the third pixel PX3 is arranged in the third column 1013. Therefore, the first pixel PX1 arranged in the first column 1011 and the third pixel PX3 arranged in the third column 1013 are spaced apart from each other. Similarly, the second pixel PX2 may be arranged in the fourth column 1014, and the first pixel PX1 may be arranged in the fifth column (not shown). According to an embodiment of the present disclosure, leakage current and color crosstalk may be suppressed by arranging the first pixel PX1 and the third pixel PX3 so that they are positioned as far as possible relative to each other.

[0151] According to an embodiment, the trench TC is formed between the pixels PX by removing some of the plurality of inorganic layers included in the line layer 502. Fig.10 , the solid lines (e.g., line 1001) defining the first pixel PX1, the second pixel PX2, and the third pixel PX3 respectively indicate the first electrodes ANE disposed in the first pixel PX1, the second pixel PX2, and the third pixel PX3. Therefore, the trench TC according to the embodiment may be defined as being located between the first electrodes ANE of adjacent pixels PX.

[0152] According to an embodiment, since the pixels PX are arranged in a matrix, the trenches TC may be formed in a mesh topology to surround the first electrodes ANE of the pixels PX.

[0153] Fig.11 It is shown Fig.10 . In addition to each first electrode ANE having a hexagonal shape when viewed from the top, Fig.11 Examples and Fig.10 That is, the display panel 110 according to the embodiment of the present disclosure is not limited to having the first electrode ANE in a rectangular shape, but may have a first electrode ANE in a rectangular shape. Fig.11 The first electrode ANE shown in FIG. 1 is hexagonal in shape.

[0154] Will refer to Figures 12 to 22 The features of the groove TC according to the embodiment are described in detail. The term groove TC used herein may be used interchangeably with other similar terms. Figures 12 to 22 The description of Figure 8 The features of the groove TC of the embodiment, but this feature of the groove TC can also be applied to Figures 9 to 11 Embodiment of the invention.

[0155] Fig.12 is a cross-sectional view for illustrating a trench TC formed between adjacent pixels PX. For example, Fig.12 It is along Figure 8 and Fig.10 The cross-sectional view of some layers of the line layer 502 and the light emitting element LEL taken along the line AA′ shown in FIG.

[0156] refer to Fig.12 , the display panel 110 (see Figure 5 ) may include a first inorganic layer 1211 and a second inorganic layer 1212 disposed on the first inorganic layer 1211. For example, the first inorganic layer 1211 and the second inorganic layer 1212 may be in the uppermost layer of the line layer 502 and may be located at a boundary between the line layer 502 and the light emitting element layer 503.

[0157] According to an embodiment, the first inorganic layer 1211 may include silicon nitride (SiN x ), the second inorganic layer 1212 may include silicon oxide (SiO x ). A third inorganic layer 1213 made of the same material as that of the second inorganic layer 1212 may be further disposed under the first inorganic layer 1211. For example, the third inorganic layer 1213 may include silicon oxide (SiO x ).

[0158] Although the first inorganic layer 1211 , the second inorganic layer 1212 , and / or the third inorganic layer 1213 are disposed in the uppermost layer of the wire layer 502 in the drawing, the inorganic layer 1210 may be regarded as disposed in the lowermost layer of the light emitting element layer 503 .

[0159] The light emitting element layer 503 may be disposed on the inorganic layer 1210 of the line layer 502 , and the first electrode ANE, the middle layer ML, and the second electrode CAE of the light emitting element layer 503 may be sequentially disposed on the inorganic layer 1210 .

[0160] The first electrode ANE of the light emitting element layer 503 may be electrically connected to the driving element layer 501 disposed below the line layer 502 through a contact hole CT1211 penetrating the inorganic layer 1210 (see Figure 5 ).

[0161] The line layer 502 may include a trench TC between the first electrodes ANE of adjacent pixels PX, from which the first inorganic layer 1211 and / or the second inorganic layer 1212 have been removed. According to an embodiment, the first inorganic layer 1211 may include an undercut region inside the trench TC, which is an empty space below the second inorganic layer 1212. The undercut region UC causes at least some of the conductive layers included in the middle layer ML to be disconnected during the process of depositing the middle layer ML.

[0162] According to an embodiment, the trench TC may include a first hole H1 and a second hole H2, the second inorganic layer 1212 is removed from the first hole H1 with a first width W1, and the first inorganic layer 1211 is removed from the second hole H2 with a second width W2. Because the second width W2 is greater than the first width W1, undercut regions UC are formed on both sides of the second hole H2, respectively. Such undercut regions UC may be formed by over-etching the first inorganic layer 1211. For example, in order to form the trench TC, the etching rate for etching the first inorganic layer 1211 and the etching rate for etching the second inorganic layer 1212 may be adjusted.

[0163] According to an embodiment, a portion of the intermediate layer ML formed during a process of depositing the intermediate layer ML and the second electrode CAE may be disposed in the trench TC. For example, a first portion ML1 as a portion of the intermediate layer ML and a second portion CAE1 as a portion of the second electrode CAE are disposed in the trench TC. The first portion ML1 of the intermediate layer ML disposed in the trench TC is disconnected from the third portion ML2 of the intermediate layer ML disposed on the first electrode ANE. On the other hand, the second portion CAE1 of the second electrode CAE disposed in the trench TC is continuously connected to the fourth portion CAE2 of the second electrode CAE overlapping the first electrode ANE. That is, the intermediate layer ML is disconnected around the trench TC without continuously extending from the third portion ML2 disposed on the first electrode ANE to the first portion ML1 disposed in the trench TC. The second electrode CAE continuously extends from the fourth portion CAE2 overlapping the first electrode ANE to the second portion CAE1 disposed in the trench TC. According to an embodiment, the intermediate layer ML of the light emitting element LEL is disconnected using the trench TC between adjacent first electrodes ANE, and leakage current is prevented.

[0164] Fig.13 and Fig.14 is a cross-sectional view for illustrating a process of forming trench TC according to an embodiment. Fig.15 is a cross-sectional view for illustrating a process of depositing an intermediate layer ML and a second electrode CAE according to an embodiment. For example, Figures 13 to 15 It can be shown sequentially according to Fig.12 Manufacturing of the display panel 110 (see Figure 5)'s process view.

[0165] In the following, reference will be made to Figures 13 to 15 A process for manufacturing the display panel 110 according to an embodiment is described. It should be noted that only some of the manufacturing processes of the display panel 110 will be described. Other processes for forming the elements described herein may be additionally performed before or after the manufacturing process described below. In addition, a manufacturing process of the display panel 110 known in the art may be additionally performed before or after the manufacturing process described below.

[0166] refer to Fig.13 , driving element layer 501 (see Figure 5 ) may be formed on the substrate 200 (see Figure 5 ), and the line layer 502 can be stacked on the driving element layer 501. Fig.13 In the figure, parts of the substrate 200, the driving element layer 501 and the line layer 502 are not shown. In the uppermost layer of the line layer 502, a first inorganic layer 1211, a second inorganic layer 1212 on the first inorganic layer 1211 and / or a third inorganic layer 1213 below the first inorganic layer 1211 are provided.

[0167] Subsequently, a first electrode ANE may be formed on the wire layer 502 . The first electrode ANE may be individually provided in the pixel PX, and may be electrically connected to the driving element layer 501 through a contact hole CT1211 extending through the wire layer 502 .

[0168] Subsequently, a photoresist pattern (not shown) having an opening may be formed between adjacent first electrodes ANE, and the second inorganic layer 1212 may be etched using the photoresist pattern thus formed as a mask. In this manner, a first trench TC1 having a first width W1 is formed between adjacent first electrodes ANE.

[0169] Then, refer to Fig.14 , the first inorganic layer 1211 may be etched in the first trench TC1 using a photoresist pattern (not shown) having an opening between adjacent first electrodes ANE as a mask. The etching rate for etching the first inorganic layer 1211 may be adjusted to be different from the etching rate for etching the second inorganic layer 1212, and thus, the first inorganic layer 1211 may be overetched compared to the second inorganic layer 1212. A person of ordinary skill in the art will know how to adjust the etching rates of the first inorganic layer 1211 and the second inorganic layer 1212. Thus, a layer having a width greater than the first width W1 (see Fig.13 ) The second trench TC2 having the larger second width W2 is formed. Therefore, the trench TC is formed between the adjacent first electrodes ANE, and the trench TC includes an undercut region UC under the second inorganic layer 1212.

[0170] Then, refer to Fig.15 , the middle layer ML may be deposited to cover the plurality of first electrodes ANE, the second inorganic layer 1212, and the trench TC. At least some of the plurality of conductive layers included in the middle layer ML may be disconnected around the trench TC. Specifically, since the trench TC includes the undercut region UC, the step coverage of the middle layer ML may be degraded around the trench TC, and thus the middle layer ML may be disconnected around the trench TC. In this article, at least some of the conductive layers of the middle layer ML may include at least one of a hole injection layer HIL, a hole transport layer HTL, an electron transport layer ETL, a charge generation layer CGL, and a p-doped layer PHIL.

[0171] Subsequently, the second electrode CAE may be deposited to cover the middle layer ML. Unlike the middle layer ML, the second electrode CAE may extend continuously around the trench TC without being disconnected. This is because the metal of the second electrode CAE has a step coverage ratio that is better than the step coverage ratio of the organic material of the middle layer ML.

[0172] Fig.16 2 is a cross-sectional view for illustrating another shape of the trench TC formed between adjacent pixels PX. For example, Fig.16 It is along Figure 8 and Fig.10 The cross-sectional view of some layers in the line layer 502 and the light emitting element LEL taken along the line AA′ shown in FIG.

[0173] In addition to the dummy inorganic film 1611 covering the inversely tapered groove TC, Fig.16 Examples and Fig.12 The embodiments are basically the same.

[0174] refer to Fig.16 , the display panel 110 (see Figure 5 ) further includes a dummy inorganic film 1611 disposed around the first electrode ANE. The dummy inorganic film 1611 may include silicon oxide (SiO x ). The dummy inorganic film 1611 is disposed around the first electrode ANE but is not disposed on the first electrode ANE. The dummy inorganic film 1611 covers a portion of the inversely tapered groove TC, so that the thickness of the dummy inorganic film 1611 covering the side surface of the groove TC narrows from the entrance of the groove TC to the bottom surface of the groove TC. However, the dummy inorganic film 1611 may cover the base of the groove TC. The dummy inorganic film 1611 may cause at least some of the conductive layers included in the intermediate layer ML to be disconnected around the groove TC during the process of depositing the intermediate layer ML of the light emitting element LEL.

[0175] The process of depositing the dummy inorganic film 1611 by chemical vapor deposition (CVD) can be performed as follows: In the chemical vapor deposition process, deposition and growth can be performed isotropically. Specifically, as the deposition process proceeds, the film may grow in the lateral direction at the boundary of the trench TC. The film grown in the lateral direction at the boundary of the trench TC can play the role of a deposition shadow that blocks the entrance of the trench TC and prevents deposition inside the trench TC. As deposition and growth continue, this phenomenon is further aggravated, and therefore, the dummy inorganic film 1611 may have an inverted tapered shape in the trench TC.

[0176] According to an embodiment, a portion of the dummy inorganic film 1611 is disposed on the bottom surface of the trench TC. In the trench TC, a first portion ML1 as a portion of the intermediate layer ML and a second portion CAE1 as a portion of the second electrode CAE are disposed on the dummy inorganic film 1611 at the base of the trench TC. The first portion ML1 of the intermediate layer ML disposed in the trench TC is disconnected from the third portion ML2 of the intermediate layer ML disposed on the first electrode ANE. On the other hand, the second portion CAE1 of the second electrode CAE disposed in the trench TC is continuously connected to the fourth portion CAE2 of the second electrode CAE overlapping the first electrode ANE. In contrast, the first portion ML1 of the intermediate layer ML is disconnected around the trench TC by the dummy inorganic film 1611, and does not extend continuously from the third portion ML2 disposed on the first electrode ANE to the first portion ML1 located in the trench TC. The second electrode CAE is continuously disposed downward from the fourth portion CAE2 overlapping the first electrode ANE along the sidewall of the trench TC to the second portion CAE1 located in the trench TC. According to the embodiment, the middle layer ML of the light emitting element LEL is disconnected using the trench TC between the adjacent first electrodes ANE, and leakage current is prevented.

[0177] Figures 17 to 19 is a cross-sectional view for illustrating a process of forming trench TC according to an embodiment. Fig. 20 is a cross-sectional view for illustrating a process of depositing an intermediate layer ML and a second electrode CAE according to an embodiment. For example, Figures 17 to 20 It can be shown sequentially according to Fig.16 Manufacturing of the display panel 110 (see Figure 5 )'s process view.

[0178] In the following, reference will be made to Figures 17 to 20The process of manufacturing the display panel 110 according to the embodiment is described. It should be noted that only some manufacturing processes of the display panel 110 will be described. Other processes for forming the elements described herein may be additionally performed before or after the manufacturing process described below. In addition, the manufacturing process of the display panel 110 known in the art may be additionally performed before or after the manufacturing process described below.

[0179] refer to Fig.17 , driving element layer 501 (see Figure 5 ) may be formed on the substrate 200 (see Figure 5 ), and the line layer 502 can be stacked on the driving element layer 501. Fig.17 , parts of the substrate 200, the driving element layer 501, and the line layer 502 are omitted, and only the inorganic layer 1210 in the uppermost layer among the plurality of insulating layers VIA included in the line layer 502 is shown. As shown in the drawing, the inorganic layer 1210 disposed in the uppermost layer of the line layer 502 includes a first inorganic layer 1211 and / or a second inorganic layer 1212 on the first inorganic layer 1211.

[0180] Subsequently, a first electrode ANE may be formed on the wire layer 502 . The first electrode ANE may be individually provided in the pixel PX, and may be electrically connected to the driving element layer 501 through a contact hole CT1211 extending through the wire layer 502 .

[0181] Subsequently, a photoresist pattern (not shown) having an opening may be formed between adjacent first electrodes ANE, and the second inorganic layer 1212 may be etched using the photoresist pattern thus formed as a mask. In this manner, a first width W1 (see FIG. 1 ) is formed between adjacent first electrodes ANE. Fig.13 ) of groove TC.

[0182] Then, refer to Fig.18, a dummy inorganic film 1611 may be deposited on the first electrode ANE and the trench TC. The dummy inorganic film 1611 may be deposited by chemical vapor deposition (CVD) and may be deposited and grown isotropically. As the deposition process proceeds, the film may grow in a lateral direction at the boundary of the trench TC. The film grown in a lateral direction at the boundary of the trench TC may play the role of a deposition shadow that blocks the entrance of the trench TC and prevents deposition inside the trench TC. As deposition and growth continue, this phenomenon is further exacerbated, and therefore, the dummy inorganic film 1611 covers the trench TC so that the thickness of the dummy inorganic film 1611 covering the side surface of the trench TC narrows from the entrance of the trench TC to the bottom surface of the trench TC. For example, the dummy inorganic film 1611 may be formed on the side surface of the trench TC, and the thickness of the dummy inorganic film 1611 formed on the upper portion of the side surface of the trench TC may be greater than the thickness of the dummy inorganic film 1611 formed on the lower portion of the side surface of the trench TC.

[0183] Then, refer to Fig.19 The photoresist pattern thus formed may be used as a mask to etch the photoresist pattern (not shown) associated with the plurality of first electrodes ANE and the dummy inorganic film 1611. Thus, the dummy inorganic film 1611 deposited on the first electrode ANE may be removed, and the upper surface of the first electrode ANE may be exposed.

[0184] Then, refer to Fig. 20 , an intermediate layer ML may be deposited to cover the first electrode ANE, the dummy inorganic film 1611, and the trench TC. At least some of the multiple conductive layers included in the intermediate layer ML may be disconnected around the trench TC. Specifically, as the thickness of the dummy inorganic film 1611 covering the side surface of the trench TC becomes thinner from the entrance of the trench TC to the bottom surface of the trench TC, the step coverage of the intermediate layer ML deteriorates around the trench TC. Therefore, the intermediate layer ML may be disconnected around the trench TC. In this article, at least some of the multiple conductive layers of the intermediate layer ML may include a hole injection layer HIL (see Figure 6 ), hole transport layer HTL (see Figure 6 ), electron transport layer ETL (see Figure 6 ), charge generation layer CGL (see Figure 6 ) and the p-doped layer PHIL (see Figure 6 )

[0185] Subsequently, the second electrode CAE may be deposited to cover the middle layer ML. Unlike the middle layer ML, the second electrode CAE may extend continuously around the trench TC without being disconnected. This is because the metal of the second electrode CAE has a step coverage better than that of the organic material of the middle layer ML.

[0186] Fig.21 and Fig. 22 FIG. 1 is a diagram showing a display panel 110 including auxiliary lines 2111 according to an embodiment (see FIG. Figure 5 ). For example, Fig.21 Shown with Fig.12 Compared with the embodiment of the embodiment of the present invention, an auxiliary line 2111 which is in line with the bottom surface of the trench TC is further provided. For example, Fig. 22 Shown with Fig.16 Compared with the embodiment of the embodiment of the present invention, an auxiliary line 2111 which is in line with the bottom surface of the trench TC is further provided.

[0187] In addition to the differences, Fig.21 and Fig. 22 Examples and Fig.12 Embodiments or Fig.16 The embodiments are substantially the same; and therefore, redundant descriptions will be omitted.

[0188] refer to Fig.21 and Fig. 22 , the line layer 502 includes an auxiliary line 2111 arranged in a straight line with the groove TC. The auxiliary line 2111 may be arranged in the same layer as the signal line or the power line included in the line layer 502. The auxiliary line 2111 arranged in the line layer 502 may be arranged to overlap the groove TC between adjacent pixels PX. The auxiliary line 2111 may be electrically connected to the first portion ML1 of the middle layer ML arranged on the bottom surface of the groove TC via a contact hole CT2111 penetrating at least a portion of the line layer 502 via the bottom surface of the groove TC. Fig. 22 In the embodiment shown in , the contact hole CT2111 may not only penetrate at least a portion of the line layer 502 , but also penetrate the dummy inorganic film 1611 deposited on the bottom surface of the trench TC.

[0189] In the display device 10 (see Figure 1 ), when the display panel 110 (see Figure 1 )When displaying an image, a ground voltage is applied to the auxiliary line 2111. The auxiliary line 2111 to which the ground voltage is applied can be electrically connected to the middle layer ML of the light emitting element LEL through the groove TC between adjacent pixels PX. Therefore, the leakage current flowing between adjacent pixels PX through the middle layer ML can flow to the outside through the auxiliary line 2111. According to this embodiment of the present disclosure, even if the middle layer ML fails to be disconnected around the groove TC in the deposition process of the middle layer ML, the auxiliary line 2111 can be used to prevent the leakage current. As a result, reliability can be increased.

[0190] The ground voltage may not be supplied to the auxiliary line 2111, and a voltage different from the ground voltage may be applied to the auxiliary line 2111. For example, an auxiliary voltage lower than a voltage for driving the plurality of pixels PX may be supplied to the auxiliary line 2111.

[0191] Although not shown in the drawings, Fig.21 Unlike the embodiment of the present invention, the undercut region UC may not be formed inside the trench TC. For example, in the display panel 110 including the auxiliary line 2111, the leakage current flowing between adjacent pixels PX may be blocked by using the auxiliary line 2111, so that the undercut region UC may be eliminated from the inside of the trench TC.

[0192] Fig.23 FIG. 1 is a diagram showing a display device 10 (see FIG. 1 ) according to an embodiment of the present disclosure. Figure 1 ) is a view of an example of a wearable device.

[0193] The display device 10 according to the embodiment may be included in a mobile electronic device. The display device 10 according to the embodiment may be included in a wearable device developed in the form of glasses or a helmet and forming a focus at a position close to the user's eyes. For example, the wearable device may be an HMD device or AR glasses. Such a wearable device provides an AR image or a VR image to the user.

[0194] Fig.23 A virtual reality device 2300 using a display device 2360 according to an embodiment is shown. The display device 2360 may include, for example Figures 1 to 22 of the above elements.

[0195] refer to Fig.23 The virtual reality device 2300 according to the embodiment may be an AR glasses in the form of glasses. The virtual reality device 2300 according to the embodiment of the present disclosure may include a display device 2360, a left-eye lens 2311, a right-eye lens 2312, a support frame 2320, temples 2331 and 2332, a reflective member 2340, and a housing 2350.

[0196] The housing 2350 may house the display device 2360 and the reflective member 2340. The image displayed in the display device 2360 may be reflected by the reflective member 2340 and provided to the right eye of the user through the right eye lens 2312. Therefore, the user may view the virtual reality image displayed in the display device 2360 through the right eye.

[0197] Despite Fig.23In the example shown in , the housing 2350 is disposed at the right end of the supporting frame 2320, but the embodiments of the present disclosure are not limited thereto. For example, the housing 2350 may be disposed at the left end of the supporting frame 2320. In this case, the image displayed on the display device 2360 is reflected by the reflective member 2340 and provided to the left eye of the user through the left eye lens 2311. Therefore, the user can view the virtual reality image displayed in the display device 2360 through the left eye. Alternatively, the housing 2350 may be disposed at both the left and right ends of the supporting frame 2320, respectively. In this case, the user can view the virtual reality image displayed in the display device 2360 through both the left eye and the right eye.

[0198] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the present invention. Therefore, the preferred embodiments of the present invention disclosed are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, wherein: The display device comprises: substrate; A driving element layer, wherein the driving element layer is disposed on the substrate; a line layer disposed on the driving element layer and including a first inorganic layer and a second inorganic layer disposed on the first inorganic layer; and a light emitting element layer provided on the line layer and including a plurality of first electrodes, an intermediate layer, and a second electrode sequentially stacked on each other, wherein the line layer comprises a groove between the plurality of first electrodes, the groove being free of the first inorganic layer and the second inorganic layer, wherein the second inorganic layer comprises an undercut region below the first inorganic layer in the groove, wherein a first portion of the intermediate layer and a second portion of the second electrode are disposed in the groove, and The first portion of the intermediate layer is disconnected from a third portion of the intermediate layer disposed on the first electrode, and the second portion of the second electrode is connected to a fourth portion of the second electrode overlapping the first electrode.

2. The display device according to claim 1, wherein: The trench includes: a first hole in which the first inorganic layer is removed with a first width; and a second hole in which the second inorganic layer is removed with a second width greater than the first width, the second hole including the undercut region extending beyond the sidewall of the first hole.

3. The display device according to claim 1, wherein: At least some of the plurality of conductive layers of the intermediate layer are disconnected by the trenches.

4. The display device according to claim 3, wherein: The second electrode is disposed continuously across the trench.

5. The display device according to claim 3, wherein: The at least some conductive layers include at least one of a hole injection layer, a hole transport layer, an electron transport layer, a charge generation layer, and a p-doped layer.

6. The display device according to claim 1, wherein: The line layer includes an auxiliary line arranged in a straight line with the groove, and wherein the auxiliary line is electrically connected to the first portion of the intermediate layer arranged on the bottom surface of the groove through a contact hole, and the contact hole penetrates at least a portion of the line layer at the bottom surface of the groove.

7. The display device according to claim 6, wherein: A ground voltage is supplied to the auxiliary line.

8. The display device according to claim 6, wherein: An auxiliary voltage lower than a voltage for driving a plurality of pixels is applied to the auxiliary line.

9. The display device according to claim 1, wherein: The light emitting element layer is configured to emit white light.

10. The display device according to claim 1, wherein: The light emitting element layer emits light of a first color in a first emission region associated with a first pixel, emits light of a second color in a second emission region associated with a second pixel, and emits light of a third color in a third emission region associated with a third pixel.

11. A display device, wherein: The display device comprises: substrate; A driving element layer, wherein the driving element layer is disposed on the substrate; a line layer disposed on the driving element layer and including a first inorganic layer and a second inorganic layer disposed on the first inorganic layer; and a light emitting element layer, the light emitting element layer being disposed on the line layer and comprising a plurality of first electrodes, a dummy inorganic film surrounding the plurality of first electrodes, an intermediate layer covering the plurality of first electrodes and the dummy inorganic film, and a second electrode covering the intermediate layer, The line layer may include a groove between the plurality of first electrodes adjacent to each other, and the first inorganic layer or the second inorganic layer is removed from the groove. wherein the dummy inorganic film is formed on the side surface of the groove, and the thickness of the dummy inorganic film formed on the upper portion of the side surface of the groove is greater than the thickness of the dummy inorganic film formed on the lower portion of the side surface of the groove, wherein the first portion of the intermediate layer and the second portion of the second electrode are disposed on the dummy inorganic film in the groove, and The first portion of the intermediate layer is disconnected from a third portion of the intermediate layer disposed on the first electrode, and the second portion of the second electrode is continuously connected to a fourth portion of the second electrode disposed to overlap with the plurality of first electrodes.

12. The display device according to claim 11, wherein: The trench has an inverse tapered shape in which a width of the trench increases as a thickness of the dummy inorganic film covering the side surface of the trench decreases from an entrance of the trench to a bottom surface of the trench.

13. The display device according to claim 11, wherein: At least some of the plurality of conductive layers of the intermediate layer are disconnected by the trenches.

14. The display device according to claim 13, wherein: The second electrode is disposed continuously across the trench.

15. The display device according to claim 13, wherein: The at least some conductive layers include at least one of a hole injection layer, a hole transport layer, an electron transport layer, a charge generation layer, and a p-doped layer.

16. A method for manufacturing a display device, wherein: The method comprises: forming a driving element layer on a substrate; forming a line layer on the driving element layer, the line layer comprising a first inorganic layer and a second inorganic layer disposed on the first inorganic layer; and forming a light emitting element on the line layer, Wherein, forming the light emitting element layer comprises: forming a plurality of first electrodes on the second inorganic layer; forming a first trench having a first width by removing the second inorganic layer between adjacent first electrodes among the plurality of first electrodes; forming a second trench having a second width greater than the first width by overetching the first inorganic layer in the first trench; depositing an intermediate layer to cover the plurality of first electrodes, the second inorganic layer, and the first and second trenches; and depositing a second electrode to cover the intermediate layer, Wherein, in the step of depositing the intermediate layer, the intermediate layer is disconnected around the first trench and the second trench.

17. The method according to claim 16, wherein: In the depositing of the second electrode, the second electrode is not separated around the first trench and the second trench but is continuously connected.

18. The method according to claim 16, wherein: The light emitting element layer is configured to emit white light.

19. The method according to claim 18, wherein: The light emitting element layer emits light of a first color in a first emission region associated with a first pixel, emits light of a second color in a second emission region associated with a second pixel, and emits light of a third color in a third emission region associated with a third pixel.

20. The method according to claim 16, wherein: The substrate includes a semiconductor wafer substrate.

21. A display device, wherein: The display device comprises: substrate; A driving element layer, wherein the driving element layer is disposed on the substrate; a line layer disposed on the driving element layer and including a first inorganic layer and a second inorganic layer disposed on the first inorganic layer; and a light emitting element layer provided on the line layer and including a plurality of first electrodes, an intermediate layer, and a second electrode sequentially stacked on each other, The line layer includes a groove between adjacent first electrodes among the plurality of first electrodes, in which the first inorganic layer and the second inorganic layer are removed, or the second inorganic layer is removed. wherein the first portion of the intermediate layer is disposed in the groove, and Wherein, the auxiliary line is electrically connected to the first portion of the intermediate layer.

22. The display device according to claim 21, wherein: The trench has an inverse tapered shape in which a width of the trench increases as a thickness of a dummy inorganic film covering a side surface of the trench decreases from an entrance of the trench to a bottom surface of the trench.

23. The display device according to claim 21, wherein: At least some of the plurality of conductive layers of the intermediate layer are disconnected at boundaries of the trenches.

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