Semiconductor device including tapered dielectric layer and method of forming same

Abstract

The invention relates to a semiconductor device including a tapered dielectric layer and a method of forming the same. A semiconductor device may include a plurality of active regions defined on a substrate. A plurality of bit line structures may be provided through over the plurality of active regions. A plurality of storage node contacts may be disposed between the plurality of bit line structures. A plug isolation pattern may be disposed between the plurality of storage node contacts. The plug isolation pattern may include: an isolation insulating layer between the plurality of memory node contacts; and a tapered dielectric layer between the isolation insulating layer and the plurality of memory node contacts.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0100367, filed on August 1, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure generally relate to semiconductor devices including tapered dielectric layers and methods of forming the same. Background Art

[0004] With the high integration of semiconductor devices, the spacing between interconnects becomes narrower and narrower. Multiple horizontal interconnect structures and multiple vertical interconnect structures can be arranged in an insulating layer. The reduction of the spacing between multiple horizontal / vertical interconnect structures increases leakage current and causes interference between interconnect structures. Summary of the invention

[0005] Various embodiments of the present disclosure relate to a semiconductor device that prevents interference and leakage current between a plurality of interconnect structures and facilitates high integration. Various embodiments of the present disclosure also relate to a method of forming the semiconductor device.

[0006] According to an embodiment of the present disclosure, a semiconductor device may include a plurality of active regions defined on a substrate. A plurality of bit line structures passing through the plurality of active regions may be provided. A plurality of storage node contacts may be disposed between the plurality of bit line structures. A plug isolation pattern may be disposed between the plurality of storage node contacts. The plug isolation pattern may include: an isolation insulating layer between the plurality of storage node contacts; and a tapered dielectric layer between the isolation insulating layer and the plurality of storage node contacts.

[0007] In an embodiment of the present disclosure, a semiconductor device may include a plurality of interconnect structures disposed on a substrate and spaced apart from each other. Each of the plurality of contact plugs may be disposed between a corresponding pair of adjacent interconnect structures. A plug isolation pattern may be disposed between the plurality of contact plugs. The plug isolation pattern may include: an isolation insulating layer between the plurality of contact plugs; and a tapered dielectric layer between the isolation insulating layer and the plurality of contact plugs.

[0008] According to an embodiment of the disclosed technology, a plurality of storage node contacts and a plurality of plug isolation patterns arranged between a plurality of bit line structures may be provided. The plug isolation pattern may include an isolation insulating layer and a tapered dielectric layer. The tapered dielectric layer may play a role in preventing the formation of seams in the isolation insulating layer. The tapered dielectric layer may play a role in preventing defects such as Y bridges. The tapered dielectric layer may play a role in improving hydrogen passivation characteristics and row hammer characteristics. It may be possible to prevent interference and leakage current between a plurality of interconnect structures and facilitate highly integrated semiconductor devices.

[0009] These and other features and advantages of the present disclosure will be better understood from the following drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the disclosed technology.

[0011] Figures 2 to 5 It is shown Figure 1 A partial view of a part of .

[0012] Figure 6 is a layout diagram showing a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 7 It is omitted Figure 6 Layout diagram of some components.

[0014] Figures 8 to 22 is a cross-sectional view illustrating a method of forming a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present disclosure, Figures 2 to 5 It is shown Figure 1 A partial view of a portion 100 . Figure 6 is a layout diagram showing a semiconductor device according to an embodiment of the present disclosure, Figure 7 It is omitted Figure 6 Layout diagram of some components. Figure 1 It can be along Figure 6 In an embodiment, a semiconductor device according to an embodiment of the present disclosure may include a memory device such as a cell array of a dynamic random access memory (DRAM).

[0016] refer to Figure 1 The semiconductor device based on the embodiment of the present disclosure may include a substrate 21, multiple active areas 23, an isolation layer 25, a gate dielectric layer 32, multiple word lines WL, a gate cover layer 34, multiple source / drain areas 36, an interlayer insulating layer 39, a bit plug 43, multiple bit lines 45, a bit cover layer 46, a first spacer 49, a filling gap spacer 50, a second spacer 53, a third spacer 54, a plurality of lower contact plugs 62, a tapered dielectric layer 71, an isolation insulating layer 73, an upper spacer 79, a plurality of upper contact plugs 82 and a plurality of storage elements 90.

[0017] The plurality of bit lines 45, the bit cover layer 46, the first spacer 49, the filling gap spacer 50, the second spacer 53, and the third spacer 54 may configure a plurality of bit line structures BLS. The plurality of lower contact plugs 62 and the plurality of upper contact plugs 82 may configure a plurality of storage node contacts SNC. The tapered dielectric layer 71, the isolation insulating layer 73, and the upper spacer 79 may configure a plurality of plug isolation patterns 89. In an embodiment, the plurality of bit line structures BLS may be referred to as a plurality of interconnect structures. The plurality of storage node contacts SNC may be referred to as a plurality of contact plugs.

[0018] A first direction FD, a second direction SD, and a third direction VD may be defined. The second direction SD may intersect the first direction FD. The third direction VD may intersect the first direction FD and the second direction SD. In an embodiment, the first direction FD and the second direction SD may be parallel to the upper surface and the lower surface of the substrate 21. The third direction VD may be perpendicular to the upper surface and the lower surface of the substrate 21. The second direction SD may be perpendicular to the first direction FD. The third direction VD may be perpendicular to the first direction FD and the second direction SD.

[0019] Reference Figure 1 and Figure 6 , an isolation layer 25 defining a plurality of active regions 23 may be disposed in the substrate 21. The plurality of active regions 23 may be spaced apart from one another in the first direction FD and the second direction SD. A plurality of word line structures may be disposed to intersect the plurality of active regions 23 and extend in the isolation layer 25. A gate capping layer 34 may be disposed on the plurality of word line structures. The gate dielectric layer 32 may be disposed to surround the side surfaces and the lowermost (bottom) surface of the plurality of word line structures. The plurality of word line structures may be disposed at a level lower than the upper surfaces of the plurality of active regions 23 in the third direction VD. A plurality of source / drain regions 36 may be disposed adjacent to the plurality of word line structures in the plurality of active regions 23 adjacent to the plurality of word line structures.

[0020] An interlayer insulating layer 39 may be disposed on the isolation layer 25, the gate capping layer 34, and the plurality of source / drain regions 36. At least one bit plug 43 may be disposed to contact the plurality of source / drain regions 36 by passing through the interlayer insulating layer 39. Each of the plurality of active regions 23 may be electrically connected to the at least one bit plug 43 through the corresponding source / drain region 36.

[0021] A plurality of bit line structures BLS passing over the plurality of active regions 23 may be disposed on the interlayer insulating layer 39. Each of the plurality of bit line structures BLS may include a bit line 45 and a bit cover layer 46 formed on the bit line 45. The bit cover layer 46 may cover at least a portion of or the entire top surface of the top (or uppermost) surface of the bit line 45. The bit line 45 may contact at least one bit plug 43. The bit line 45 may be formed over at least one bit plug 43 and may cover at least a portion of or the entire top surface of the bit plug 43.

[0022] The first spacer 49 may be disposed on the side surfaces of the bit line 45 and the bit cover layer 46, and may extend to the side surfaces of the bit plug 43 and the interlayer insulating layer 39. The filling gap spacer 50 may be disposed on the first spacer 49 adjacent to the side surface of the bit plug 43. The first spacer 49 may extend between the filling gap spacer 50 and the isolation layer 25. The second spacer 53 may be disposed on the first spacer 49. The side surface of the second spacer 53 may contact the side surface of the first spacer 49. The bottom surface of the second spacer 53 may contact the first spacer 49. The first spacer 49 may include an L-shape. The second spacer 53 may contact the upper surface of the filling gap spacer 50.

[0023] The third spacer 54 may be disposed on the second spacer 53. A side surface of the third spacer 54 may contact a side surface of the second spacer 53. The third spacer 54 may extend into the plurality of source / drain regions 36 by passing through the interlayer insulating layer 39. A side surface of the third spacer 54 may contact the first spacer 49 and the interlayer insulating layer 39. The lowermost surface (or bottom surface) of the third spacer 54 may be disposed at a level lower than the uppermost surface (or top surface) of the plurality of source / drain regions 36 in the third direction VD.

[0024] In an embodiment, the second spacer 53 may be disposed on an outer surface of the first spacer 49. The first spacer 49 may be disposed between the second spacer 53 and the plurality of bit lines 45 and between the second spacer 53 and the bit cover layer 46. The third spacer 54 may be disposed on an outer surface of the second spacer 53. The second spacer 53 may be disposed between the third spacer 54 and the first spacer 49. The filling gap spacer 50 may be surrounded by the first spacer 49, the second spacer 53, and the third spacer 54.

[0025] A plurality of storage node contacts SNC and a plurality of plug isolation patterns 89 may be disposed between the plurality of bit line structures BLS. Each of the plurality of plug isolation patterns 89 may be disposed between the plurality of storage node contacts SNC.

[0026] Each of the plurality of storage node contacts SNC may include: a lower contact plug 62 contacting a corresponding source / drain region among the plurality of source / drain regions 36 in the plurality of active regions 23; and an upper contact plug 82 contacting the lower contact plug 62. The lower contact plug 62 may be arranged on top of a corresponding active region among the plurality of active regions 23 along the third direction VD. At least a portion of the lower contact plug 62 may overlap an upper portion of the corresponding active region among the plurality of active regions 23. The horizontal width of the upper contact plug 82 may be greater than the horizontal width of the lower contact plug 62.

[0027] The lowermost surface (or bottom surface) of the lower contact plug 62 may be disposed at a level lower than the uppermost surface (or top surface) of the plurality of source / drain regions 36 in the third direction VD. The lowermost surface (or bottom surface) of the lower contact plug 62 may be disposed at a level lower than the lowermost surface (or bottom surface) of the third spacer 54 in the third direction VD. The uppermost surface (or top surface) of the lower contact plug 62 may be disposed at a level higher than the upper surface of the adjacent bit line 45 in the third direction VD.

[0028] A plurality of plug isolation patterns 89 may overlap with a plurality of word lines WL and a gate capping layer 34. An isolation insulating layer 73 may be disposed between a plurality of storage node contacts SNC. A tapered dielectric layer 71 may surround a side surface and a bottom surface of the isolation insulating layer 73. An uppermost surface (or top surface) of the tapered dielectric layer 71 may be disposed at a level lower than an upper surface of the isolation insulating layer 73 in a third direction VD. An upper spacer 79 may be disposed on the tapered dielectric layer 71 and may surround a side surface of the isolation insulating layer 73. An upper spacer 79 may be disposed between the isolation insulating layer 73 and an upper contact plug 82. The upper spacer 79 may extend between the bit capping layer 46 and the upper contact plug 82.

[0029] The tapered dielectric layer 71 may extend between the isolation insulating layer 73 and the lower contact plug 62. The horizontal width of the tapered dielectric layer 71 in the second direction SD may gradually increase from the top surface to the bottom surface. The isolation insulating layer 73 may include an inverted trapezoidal shape, and its horizontal width gradually increases from the bottom surface to the top surface. In an embodiment, the isolation insulating layer 73 may include a material having an etching selectivity relative to the tapered dielectric layer 71. The isolation insulating layer 73 may include a nitride, and the tapered dielectric layer 71 may include an oxide. The tapered dielectric layer 71 may extend between the isolation insulating layer 73 and the gate cap layer 34 and between the isolation insulating layer 73 and the isolation layer 25. The uppermost surface (or top surface) of the tapered dielectric layer 71 may be set at a level higher than the upper surface of the bit line 45 in the third direction VD.

[0030] A plurality of storage elements 90 may be arranged on a plurality of storage node contacts SNC. Each of the plurality of storage elements 90 may include a cell capacitor of a DRAM, a magnetic tunnel junction (MTJ) of a magnetoresistive random access memory (MRAM), a phase change random access memory (PRAM), a ferroelectric random access memory (FRAM), a resistive random access memory (RRAM), or a combination thereof. In an embodiment, when each of the plurality of storage elements 90 includes a cell capacitor of a DRAM, the cell capacitor may include a capacitor dielectric layer between a first electrode and a second electrode. The first electrode of the cell capacitor may be referred to as a storage node. The storage node may be connected to a plurality of storage node contacts SNC. The storage node may include a columnar, a barrel, a box, or a combination thereof.

[0031] According to an embodiment of the present disclosure, the tapered dielectric layer 71 can mitigate and / or prevent the formation of gaps in the isolation insulating layer 73. In an embodiment, when the formation of gaps is not completely suppressed, the tapered dielectric layer 71 can play a role in mitigating the formation of gaps. For example, a relatively small seam can be formed in the isolation insulating layer 73, but the tapered dielectric layer 71 can prevent the smaller gap from becoming a defect such as a Y bridge. In addition, the tapered dielectric layer 71 can improve the hydrogen passivation characteristics and the line hammer characteristics of the semiconductor.

[0032] Reference Figure 1 and Figure 2 According to an embodiment, the upper surfaces of the tapered dielectric layer 71 and the lower contact plug 62 may be substantially located in the same plane. The horizontal width of the tapered dielectric layer 71 may gradually increase from the top surface to the bottom surface. The tapered dielectric layer 71 may have a first horizontal width W1 between the lower contact plug 62 and the isolation insulating layer 73 in the second direction SD at a position of 85% of the total vertical height from the bottom thereof in the third direction VD. The tapered dielectric layer 71 may have a second horizontal width W2 between the lower contact plug 62 and the isolation insulating layer 73 in the second direction SD at a position of 50% of the total vertical height in the third direction VD. The second horizontal width W2 may be greater than the first horizontal width W1.

[0033] Reference Figure 3 , the tapered dielectric layer 71 may surround the side surface and the bottom surface of the isolation insulating layer 73. The tapered dielectric layer 71 may include a bottom 71B and a side 71S. The bottom 71B of the tapered dielectric layer 71 may extend between the isolation insulating layer 73 and the gate cap layer 34. The side 71S of the tapered dielectric layer 71 may extend between the isolation insulating layer 73 and the lower contact plug 62. In an embodiment, the thickness of the bottom 71B in the third direction VD may be greater than the horizontal width of the side 71S in the second direction SD.

[0034] Reference Figure 4In an embodiment, the uppermost surface (or top surface) of the tapered dielectric layer 71 may protrude to a level higher than the upper surface of the lower contact plug 62 in the third direction VD.

[0035] Reference Figure 5 In an embodiment, an upper surface of the tapered dielectric layer 71 may be recessed to a level lower than an upper surface of the lower contact plug 62 in the third direction VD.

[0036] Reference Figure 6 , the semiconductor device according to the embodiment of the present disclosure may include a plurality of active regions 23 , a plurality of word line structures, a plurality of bit line structures BLS, a plurality of storage node contacts SNC, and a plurality of plug isolation patterns 89 .

[0037] The plurality of word line structures may intersect the plurality of active regions 23. Each of the plurality of word line structures may extend along the first direction FD. The plurality of word line structures may be arranged parallel to each other along the second direction SD. In an embodiment, corresponding two word line structures among the plurality of word line structures may intersect each of the plurality of active regions 23.

[0038] Each of the plurality of bit line structures BLS may extend along the second direction SD. The plurality of bit line structures BLS may be arranged parallel to each other along the first direction FD. The plurality of bit line structures BLS may pass through the top of the plurality of active regions 23. Each of the plurality of bit line structures BLS may pass through the top of the plurality of word line structures. Each of the plurality of bit line structures BLS may be orthogonal to the plurality of word line structures. In an embodiment, a corresponding bit line structure among the plurality of bit line structures BLS may intersect each of the plurality of active regions 23.

[0039] A plurality of storage node contacts SNC and a plurality of plug isolation patterns 89 may be disposed between the plurality of bit line structures BLS. The plurality of storage node contacts SNC may overlap with the plurality of active regions 23. The plurality of plug isolation patterns 89 may overlap with the plurality of word line structures.

[0040] Reference Figure 6 and Figure 7 , a plurality of storage node contacts SNC and a plurality of plug isolation patterns 89 may be disposed between a plurality of bit line structures BLS. For example, a plurality of storage node contacts SNC and a plurality of plug isolation patterns 89 may be alternately and repeatedly disposed between a pair of bit line structures BLS along the second direction SD.

[0041] Figures 8 to 22 is a cross-sectional view illustrating a method of forming a semiconductor device according to an embodiment of the present disclosure. Figures 8 to 22 is along Figure 6 Cross-sectional views taken along line II and line II-II.

[0042] Reference Figure 6 and Figure 8 , an isolation layer 25 defining a plurality of active regions 23 may be formed in the substrate 21. In addition, a gate dielectric layer 32 and a plurality of word lines WL may be formed to cross the plurality of active regions 23 and extend in the isolation layer 25. In addition, a gate cap layer 34 may be formed on the plurality of word line structures. A plurality of source / drain regions 36 may be formed in the plurality of active regions 23.

[0043] The substrate 21 may include a semiconductor substrate such as a silicon wafer or a silicon-on-insulator (SOI) wafer. The substrate 21 may include a III-V semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The substrate 21 may include single crystal silicon, polycrystalline silicon, amorphous silicon, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, or a combination thereof.

[0044] A plurality of active regions 23 and isolation layer 25 may be formed using trench isolation techniques such as shallow trench isolation (STI). In an embodiment, the plurality of active regions 23 may include single crystal silicon with P-type impurities. The P-type impurities may include B, BF, BF2, or a combination thereof. The isolation layer 25 may include a single layer or multiple layers. The isolation layer 25 may include at least two selected from the group consisting of Si, O, N, C, and H. The isolation layer 25 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof.

[0045] In an embodiment, isolation layer 25 may include insulating liner 26 and buried insulating layer 27. Insulating liner 26 may include a single layer or multiple layers. Insulating liner 26 may include an oxide layer and a nitride layer on the oxide layer. Buried insulating layer 27 may include silicon oxide or a low-k dielectric.

[0046] A plurality of word line structures may be formed to intersect with the plurality of active regions 23 and the isolation layer 25. The plurality of word line structures may be buried in the plurality of active regions 23 and the isolation layer 25. In the third direction VD, the upper surfaces of the plurality of word line structures may be formed at a level lower than the upper surfaces of the plurality of active regions 23 and the upper surfaces of the isolation layer 25. Each of the plurality of word line structures may correspond to a buried gate or a buried word line. A gate dielectric layer 32 may be formed between the plurality of word line structures and the plurality of active regions 23 and between the plurality of word line structures and the isolation layer 25. A gate cap layer 34 may cover the plurality of word line structures.

[0047] The gate dielectric layer 32 may include silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric, or a combination thereof. The plurality of word lines WL may include a conductive material such as metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or a combination thereof. The gate cap layer 34 may include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, high-k dielectric, or a combination thereof.

[0048] A plurality of source / drain regions 36 may be formed in the plurality of active regions 23 adjacent to the plurality of word line structures. In an embodiment, the plurality of source / drain regions 36 may include single crystalline silicon with N-type impurities. The N-type impurities may include P, As, or a combination thereof.

[0049] Reference Figure 6 and Fig. 9 , the interlayer insulating layer 39 may be formed to cover the isolation layer 25, the gate cover layer 34 and the plurality of source / drain regions 36. A first contact hole 41 exposing a corresponding source / drain region among the plurality of source / drain regions 36 may be formed through the interlayer insulating layer 39. Forming the first contact hole 41 may include an anisotropic etching process. While forming the first contact hole 41, the upper surface of the corresponding source / drain region among the plurality of source / drain regions 36 may be etched and recessed downward. In an embodiment, the isolation layer 25 may be exposed on the sidewall of the first contact hole 41. The interlayer insulating layer 39 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric or a combination thereof.

[0050] Reference Figure 6 and Fig.10 , a bit plug 43 may be formed in the first contact hole 41. The bit plug 43 may contact the corresponding source / drain region 36. The bit plug 43 may include a conductive material such as metal, metal oxide, metal nitride, metal silicide, polysilicon, conductive carbon, or a combination thereof.

[0051] Reference Figure 6 and Fig.11 , a plurality of bit lines 45 and a bit cover layer 46 may be formed on the interlayer insulating layer 39 and the bit plug 43. The bit cover layer 46 may cover the plurality of bit lines 45. Forming the plurality of bit lines 45 and the bit cover layer 46 may include a thin film formation process and a patterning process. The side surfaces of the plurality of bit lines 45 may be vertically aligned with the side surfaces of the bit cover layer 46. Each of the side surfaces of the plurality of bit lines 45 may form the same plane as a corresponding side surface among the side surfaces of the bit cover layer 46 in the third direction VD.

[0052] The bit plug 43 may contact the lower surface of the corresponding bit line among the plurality of bit lines 45. The bit plug 43 may be partially etched while the plurality of bit lines 45 are formed. The bit plug 43 may be limited to the bottom surface of the corresponding bit line among the plurality of bit lines 45. The gap region 41G may be formed on both sides of the bit plug 43. The side surface of the bit plug 43 may be vertically aligned with the side surfaces of the plurality of bit lines 45.

[0053] Each of the plurality of bit lines 45 may extend in the second direction SD. The plurality of bit lines 45 may be formed to be parallel to each other in the first direction FD. The plurality of bit lines 45 may pass over the plurality of active regions 23. Each of the plurality of bit lines 45 may pass over the plurality of word line structures. Each of the plurality of bit lines 45 may be orthogonal to the plurality of word line structures.

[0054] In an embodiment, a corresponding bit line among the plurality of bit lines 45 may cross each of the plurality of active regions 23. A bit plug 43 may be formed at each intersection of the plurality of active regions 23 and the plurality of bit lines 45.

[0055] The plurality of bit lines 45 may include a conductive material, such as a metal, a metal oxide, a metal nitride, a metal silicide, polysilicon, conductive carbon, or a combination thereof. The bit cover layer 46 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. In an embodiment, the bit cover layer 46 may include a nitride layer, such as a silicon nitride layer.

[0056] Reference Figure 6 and Fig.12 , a first spacer 49 may be formed on the interlayer insulating layer 39, the bit plug 43, the plurality of bit lines 45, and the bit cover layer 46. The first spacer 49 may conformally cover the inside of the gap region 41G. The first spacer 49 may cover the side surfaces of the bit plug 43, the plurality of bit lines 45, and the bit cover layer 46. A filling gap spacer 50 may be formed on the first spacer 49 in the gap region 41G. Forming the filling gap spacer 50 may include a thin film formation process and an etch-back process. The filling gap spacer 50 may fill the gap region 41G.

[0057] Each of the first spacers 49 and the filling gap spacers 50 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. Each of the first spacers 49 and the filling gap spacers 50 may include SiO, SiCO, SiOCN, SiON, or a combination thereof.

[0058] The filling gap spacer 50 may include a material having an etch selectivity with respect to the first spacer 49. The first spacer 49 may include a material having an etch selectivity with respect to the bit capping layer 46. In an embodiment, the first spacer 49 may include a low-k dielectric.

[0059] Reference Figure 6 and Fig.13, the second spacer 53 may be formed on the first spacer 49. Forming the second spacer 53 may include a thin film forming process and an anisotropic etching process. The second spacer 53 may be formed on the side surfaces of the plurality of bit lines 45 and the bit capping layer 46. When forming the second spacer 53, the first spacer 49 and the interlayer insulating layer 39 may be partially removed to expose the plurality of source / drain regions 36 and the isolation layer 25.

[0060] The first spacer 49 may remain between the bit cap layer 46 and the side surface of the second spacer 53, between the plurality of bit lines 45 and the side surface of the second spacer 53, between the upper surface of the interlayer insulating layer 39 and the second spacer 53, between the filling gap spacer 50 and the bit plug 43, and between the filling gap spacer 50 and the isolation layer 25. The first spacer 49 may include an L shape. The upper surfaces of the plurality of source / drain regions 36 and the isolation layer 25 exposed outside the plurality of bit lines 45, the first spacer 49, and the second spacer 53 may be etched and recessed downward.

[0061] The second spacer 53 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. The second spacer 53 may include a material having an etch selectivity relative to the bit cover layer 46. In an embodiment, the second spacer 53 may include a material having an etch selectivity relative to the bit cover layer 46 and the first spacer 49. The second spacer 53 may include an oxide layer such as a silicon oxide layer.

[0062] Reference Figure 6 and Fig.14 , a third spacer 54 may be formed on the side surfaces of the second spacer 53 and the interlayer insulating layer 39. Forming the third spacer 54 may include a thin film forming process and an anisotropic etching process. The upper surfaces of the plurality of source / drain regions 36 and the isolation layer 25 exposed outside the plurality of bit lines 45, the first spacer 49, the second spacer 53, and the third spacer 54 may be etched and recessed downward.

[0063] The side surface of the third spacer 54 may contact the side surface of the second spacer 53, the first spacer 49, and the side surface of the interlayer insulating layer 39. The lowermost surface (or bottom surface) of the third spacer 54 may be formed at a level lower than the lower surface of the interlayer insulating layer 39 and the uppermost surface (or top surface) of the plurality of source / drain regions 36 in the third direction VD. The lower surface of the third spacer 54 may contact the plurality of source / drain regions 36 and the isolation layer 25.

[0064] The third spacer 54 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. The third spacer 54 may include SiO, SiCO, SiOCN, SiON, or a combination thereof. The third spacer 54 may include a material having an etch selectivity relative to the second spacer 53 and the bit cover layer 46. In an embodiment, the third spacer 54 may include a low-k dielectric.

[0065] Reference Figure 6 and Fig.15 , the lower contact layer 62L may be formed on the plurality of source / drain regions 36 and the isolation layer 25 exposed outside the plurality of bit lines 45, the first spacer 49, the second spacer 53, and the third spacer 54. The lower contact layer 62L may contact the plurality of source / drain regions 36. The lower contact layer 62L may include a conductive material, such as a metal, a metal oxide, a metal nitride, a metal silicide, polysilicon, conductive carbon, or a combination thereof. In an embodiment, the lower contact layer 62L may include a doped polysilicon layer.

[0066] Forming the lower contact layer 62L may include a thin film forming process and a planarization process. The planarization process for forming the lower contact layer 62L may include a chemical mechanical polishing (CMP) process, an etch-back process, or a combination thereof. The upper surfaces of the lower contact layer 62L and the bit cap layer 46 may form substantially the same plane.

[0067] Reference Figure 6 and Fig.16 , a mask pattern 63 may be formed on the lower contact layer 62L and the bit cap layer 46. A plurality of lower contact plugs 62 and a plurality of isolation trenches 62T may be formed by etching the lower contact layer 62L using the mask pattern 63 as an etching mask. The isolation layer 25 and the gate cap layer 34 may be exposed at the bottom of the plurality of isolation trenches 62T. Each of the plurality of lower contact plugs 62 may contact a corresponding source / drain region among the plurality of source / drain regions 36.

[0068] Reference Figure 6 and Fig.17 , a tapered dielectric layer 71 may be formed in the plurality of isolation trenches 62T. Forming the tapered dielectric layer 71 may include an atomic layer deposition (ALD) process or a cyclic deposition process. The tapered dielectric layer 71 may include a material having an etch selectivity relative to the bit cap layer 46. In an embodiment, the tapered dielectric layer 71 may include an oxide such as SiO, SiCO, SiON, SiOCN, or a combination thereof.

[0069] In the plurality of isolation trenches 62T, the tapered dielectric layer 71 may be formed to gradually become thicker in the downward direction. In an embodiment, the thickness of the tapered dielectric layer 71 on the side surfaces of the plurality of lower contact plugs 62 in the second direction SD may gradually increase from the top surface to the bottom surface in the third direction VD. Due to the formation of the tapered dielectric layer 71, the inner regions of the plurality of isolation trenches 62T may present a positive profile. Due to the formation of the tapered dielectric layer 71, each remaining space of the plurality of isolation trenches 62T may present an inverted trapezoidal shape in which the horizontal width gradually increases from the bottom surface to the top surface.

[0070] In an embodiment, forming the tapered dielectric layer 71 may include loading a substrate 21 having a plurality of lower contact plugs 62 and a plurality of isolation trenches 62T into a process chamber and repeatedly performing a tapered dielectric layer deposition cycle a plurality of times. The tapered dielectric layer deposition cycle may include sequentially supplying a first reaction gas on the substrate 21 in the process chamber, supplying a first purge gas into the process chamber, supplying a second reaction gas on the substrate 21 in the process chamber, supplying a second purge gas into the process chamber, supplying an inhibitor gas on the substrate 21 in the process chamber, and supplying a third purge gas into the process chamber.

[0071] The first reaction gas may include dichlorosilane (DCS), hexachlorodisilane (HCDS), bis(diethylamino)silane (BDEAS), or a combination thereof. The second reaction gas may include N2O, O2, N2, Ar, He, plasma thereof, or a combination thereof. The inhibitor gas may include NH3, NF3, F2, N2, Ar, He, plasma thereof, or a combination thereof. Each of the first to third purge gases may include an inert gas, such as argon, nitrogen, helium, neon, or a combination thereof.

[0072] Reference Figure 6 and Fig.18 , an isolation insulating layer 73 filling a plurality of isolation trenches 62T may be formed on the tapered dielectric layer 71. The isolation insulating layer 73 may include a material having an etching selectivity relative to the tapered dielectric layer 71. In an embodiment, the isolation insulating layer 73 may include a nitride such as silicon nitride. Due to the presence of the tapered dielectric layer 71, the isolation insulating layer 73 may densely fill the interior of the plurality of isolation trenches 62T. The tapered dielectric layer 71 may play a role in preventing gaps from being formed in the isolation insulating layer 73.

[0073] Reference Figure 6 and Fig.19By using a planarization process, the upper surfaces of the bit cover layer 46, the plurality of lower contact plugs 62, the tapered dielectric layer 71, and the isolation insulating layer 73 can be exposed on the same plane. The planarization process may include a chemical mechanical polishing (CMP) process, an etch-back process, or a combination thereof. When the planarization process is performed, the mask pattern 63 may be removed.

[0074] The tapered dielectric layer 71 and the isolation insulating layer 73 may remain in the plurality of isolation trenches 62T. The tapered dielectric layer 71 may be formed to surround the side surface and the lower surface of the isolation insulating layer 73. The isolation insulating layer 73 may have an inverted trapezoidal shape whose horizontal width gradually increases from the bottom surface to the top surface.

[0075] Reference Figure 6 and Fig. 20 , a plurality of recessed regions 62R may be formed by removing upper regions of the first spacer 49, the second spacer 53, the third spacer 54, the plurality of lower contact plugs 62, and the tapered dielectric layer 71. Upper surfaces of the first spacer 49, the second spacer 53, the third spacer 54, the plurality of lower contact plugs 62, and the tapered dielectric layer 71 may be formed at a level lower than upper ends of the bit cover layer 46 and the isolation insulating layer 73 in the third direction VD. In an embodiment, upper surfaces of the plurality of lower contact plugs 62 may be formed at a level higher than upper surfaces of the plurality of bit lines 45 in the third direction VD. Side surfaces of the isolation insulating layer 73 and the bit cover layer 46 may be exposed in the plurality of recessed regions 62R.

[0076] Reference Figure 6 and Fig.21 , the upper spacer 79 may be formed on the side surfaces of the isolation insulating layer 73 and the bit cover layer 46. Forming the upper spacer 79 may include a thin film formation process and an anisotropic etching process. A plurality of lower contact plugs 62 may be exposed in a plurality of recessed regions 62R. The upper spacer 79 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, a high-k dielectric, or a combination thereof. In an embodiment, the upper spacer 79 may include a nitride such as silicon nitride.

[0077] Reference Figure 6 and Fig. 22 , a plurality of upper contact plugs 82 may be formed in a plurality of recessed regions 62R. Each of the plurality of upper contact plugs 82 may contact a corresponding lower contact plug among the plurality of lower contact plugs 62. The plurality of upper contact plugs 82 may include a conductive material, such as a metal, a metal oxide, a metal nitride, a metal silicide, polysilicon, conductive carbon, or a combination thereof. In an embodiment, each of the plurality of upper contact plugs 82 may include a barrier layer and a metal layer on the barrier layer. In an embodiment, a metal silicide layer may be formed between the plurality of upper contact plugs 82 and the plurality of lower contact plugs 62, but will be omitted for simplicity of description.

[0078] The plurality of bit lines 45, the bit cover layer 46, the first spacer 49, the filling gap spacer 50, the second spacer 53 and the third spacer 54 may configure a plurality of bit line structures BLS. The plurality of lower contact plugs 62 and the plurality of upper contact plugs 82 may configure a plurality of storage node contacts SNC. The tapered dielectric layer 71, the isolation insulating layer 73 and the upper spacer 79 may configure a plurality of plug isolation patterns 89.

[0079] Refer again Figure 1 , a plurality of storage elements 90 may be formed on a plurality of storage node contacts SNC.

[0080] Although the embodiments of the disclosed technology are described for illustrative purposes, it will be appreciated by those skilled in the art that multiple modifications, additions and substitutions are possible without departing from the scope and spirit of the disclosed technology. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered only as descriptive, rather than for limiting the scope of the technology. The technical scope of the disclosed technology is not limited by the embodiments and the accompanying drawings. The spirit and scope of the disclosed technology should be interpreted in conjunction with the attached claims and encompass all equivalents within the scope of the attached claims. In addition, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device, comprising: a plurality of active regions defined on the substrate; a plurality of bit line structures passing over the plurality of active regions; a plurality of storage node contacts disposed between the plurality of bit line structures; as well as a plug isolation pattern disposed between the plurality of storage node contacts, The plug isolation pattern comprises: an isolation insulating layer disposed between the plurality of storage node contacts; as well as A tapered dielectric layer is disposed between the isolation insulating layer and the plurality of storage node contacts.

2. The semiconductor device according to claim 1, wherein The tapered dielectric layer surrounds a bottom surface and side surfaces of the isolation insulating layer.

3. The semiconductor device according to claim 1, wherein The horizontal width of the tapered dielectric layer gradually increases from the top surface to the bottom surface thereof.

4. The semiconductor device according to claim 1, wherein: The isolation insulating layer includes an inverted trapezoidal shape in which a horizontal width gradually increases from a bottom surface to a top surface.

5. The semiconductor device according to claim 1, wherein The isolation insulating layer includes a material having an etching selectivity with respect to the tapered dielectric layer.

6. The semiconductor device according to claim 1, wherein The isolation insulating layer includes nitride, and the tapered dielectric layer includes oxide.

7. The semiconductor device according to claim 1, in, Each of the plurality of storage node contacts comprises: a lower contact plug disposed on the plurality of active regions; and an upper contact plug disposed on the lower contact plug, and Wherein, the tapered dielectric layer is disposed between the lower contact plug and the isolation insulating layer.

8. The semiconductor device according to claim 7, further comprising: An upper spacer is disposed between the upper contact plug and the isolation insulating layer and is located on the tapered dielectric layer.

9. The semiconductor device according to claim 7, wherein: Each of the plurality of bit line structures includes a bit line and a bit cover layer disposed on the bit line, and An uppermost surface of the tapered dielectric layer is disposed at a higher level than an upper surface of the bit line.

10. The semiconductor device according to claim 9, wherein An uppermost surface of the tapered dielectric layer is disposed at a level higher than an upper surface of the lower contact plug.

11. The semiconductor device according to claim 9, wherein: An upper surface of the tapered dielectric layer is recessed to a level lower than an upper surface of the lower contact plug.

12. The semiconductor device according to claim 1, further comprising: a plurality of word lines crossing the plurality of active regions and intersecting the plurality of bit line structures, The plug isolation pattern overlaps the plurality of word lines.

13. The semiconductor device according to claim 1, further comprising: a plurality of storage elements disposed on the plurality of storage node contacts, Each of the plurality of storage elements includes a cell capacitor of a DRAM, a magnetic tunnel junction MTJ of an MRAM, a PRAM, a FRAM, an RRAM, or a combination thereof.

14. A semiconductor device comprising: a plurality of interconnect structures disposed on the substrate and spaced apart from each other; a plurality of contact plugs, each contact plug being disposed between a corresponding pair of adjacent interconnect structures; as well as a plug isolation pattern disposed between the plurality of contact plugs, Wherein, the plug isolation pattern comprises: an isolation insulating layer disposed between the plurality of contact plugs; and A tapered dielectric layer is disposed between the isolation insulating layer and the plurality of contact plugs.

15. The semiconductor device according to claim 14, wherein: The horizontal width of the tapered dielectric layer gradually increases from the top surface to the bottom surface thereof.

16. The semiconductor device according to claim 14, wherein The isolation insulating layer includes an inverted trapezoidal shape in which a horizontal width gradually increases from a bottom surface to a top surface thereof.

17. The semiconductor device according to claim 14, wherein: The isolation insulating layer includes nitride, and the tapered dielectric layer includes oxide.

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