Semiconductor device, memory and memory system

Abstract

The invention relates to a semiconductor device, a memory and a memory system, the semiconductor device comprises a gate layer with a bidirectional threshold switching characteristic, and the material of the gate layer comprises a main body material and a first doping material doped in the main body material. Both the main body material and the first doping material contain chalcogenide compounds, and the first doping material has a stable tetrahedral structure in an amorphous state. According to the semiconductor device, the first doping material with the stable tetrahedral structure in the amorphous state is doped in the main body material of the gate layer, so that the amorphous thermal stability of the gate layer material can be effectively improved, the stability of the electrical property of the gate layer is improved, and the reliability of the semiconductor device is further improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a memory and a storage system. Background Art

[0002] Phase Change Memory (PCM) includes multiple phase change memory cells. In order to prevent the leakage current of the read, erase and write operations of the target phase change memory cell from affecting the adjacent phase change memory cells, a selector that acts as a switch is configured for each phase change memory cell.

[0003] The phase change memory based on one-selector one-resistor (1S1R) uses the gate tube to select addresses and is conducive to reducing the leakage current of the storage unit. Therefore, the stability of the electrical characteristics of the gate tube directly determines the reliability of the storage unit. Usually, the gate layer in the gate tube is an Ovonic Threshold Switching (OTS) made of sulfur compounds, and its gating function can only be realized in an amorphous structure state. Therefore, the material selection of the gate layer needs to have strong amorphous thermal stability.

[0004] Amorphous sulfur compounds with GeAsSe as the main body are commonly used materials for the gating layer. However, the amorphous sulfur compounds are mainly unstable hexacoordinate structures. This hexacoordinate structure (i.e., defective octahedral structure) is easily transformed into a stable tetrahedral or octahedral structure, resulting in poor amorphous thermal stability of the material, thereby resulting in poor stability of the electrical characteristics of the gating tube and affecting the reliability of the phase change memory. Summary of the invention

[0005] The purpose of the present application is to provide a semiconductor device, a memory and a storage system, aiming to provide an amorphous gating layer material with high thermal stability, thereby improving the stability of the electrical characteristics of the gating layer and further improving the reliability of the semiconductor device.

[0006] In order to achieve the above object, according to a first aspect of the present application, a semiconductor device is provided, the semiconductor device comprising a gating layer having a bidirectional threshold switching characteristic, the gating layer comprising a main material and a first doping material doped in the main material;

[0007] The main material and the first doping material both contain sulfur compounds, and the first doping material has a stable tetrahedral structure in an amorphous state.

[0008] Optionally, the first doping material includes gallium tritelluride.

[0009] Optionally, the main material contains As and Se elements; the chemical formula of the material of the gating layer is (Ga 0.4 Te 0.6 ) m (As x Se (1-x) ) (1-m) , wherein m is the molar percentage of the first doping material, and x is the molar percentage of the element;

[0010] In the material of the gating layer, the molar percentages of the Ga element and the Te element are both greater than 0 and less than 10%, the molar percentage of the As element is greater than 20% and less than 40%, and the molar percentage of the Se element is greater than 40% and less than 60%.

[0011] Optionally, the main material contains Ge, As and Se elements; the chemical formula of the material of the gating layer is (Ga 0.4 Te 0.6 ) m (Ge x As y Se (1-x-y) ) (1-m) , wherein m is the molar percentage of the first doping material, and x and y are both molar percentages of elements;

[0012] In the material of the gating layer, the molar percentages of the Ga element and the Te element are both greater than 0 and less than 10%, the molar percentage of the Ge element is greater than 5% and less than 30%, the molar percentage of the As element is greater than 20% and less than 40%, and the molar percentage of the Se element is greater than 40% and less than 60%.

[0013] Optionally, the chemical formula of the material of the gating layer is (Ga 0.4 Te 0.6 ) 0.075 (Ge 0.2 As 0.35 Se 0.45 ) 0.925 .

[0014] Optionally, the material of the gating layer further includes a second doping material doped in the main material, an element in the second doping material forms a chemical bond with the tellurium element, and a bond energy of the chemical bond is greater than a bond energy of a chemical bond formed between any two tellurium elements.

[0015] Optionally, the second doping material includes Si element, and the molar percentage of the Si element is greater than 0 and less than 10%.

[0016] Optionally, when the main material contains Ge, As and Se, the chemical formula of the material of the gating layer is Si 0.05 -(Ga 0.4 Te 0.6 ) 0.15 (Ge 0.2 As 0.35 Se 0.45 ) 0.80 .

[0017] According to a second aspect of the present application, a memory is provided, the memory comprising a peripheral circuit and the semiconductor device described above, wherein the peripheral circuit is connected to the semiconductor device.

[0018] According to a third aspect of the present application, a storage system is also provided, comprising a controller and the memory described above, wherein the controller is connected to the peripheral circuit.

[0019] The present application provides a semiconductor device, a memory and a storage system. Since the first doping material and the main material are both sulfur compounds, and the first doping material has a tetrahedral structure that is more stable than the unstable six-coordinate structure in the amorphous state, by doping the first doping material in the main material of the gating layer, the content of the more stable four-coordinate structure (tetrahedral structure) in the gating layer material is increased, and the crystallization temperature of the gating layer material is increased, which is beneficial to improving the amorphous thermal stability of the gating layer material, thereby helping to improve the stability of the electrical characteristics of the gating layer, and further helping to improve the reliability of the semiconductor device. In addition, the present application improves the amorphous thermal stability of the gating layer material by improving the composition of the gating layer material, without changing the architecture of the semiconductor device, and is friendly to system design and process, and has a wider range of applications.

[0020] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0022] Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor device provided in an embodiment of the present application.

[0023] Figure 2 It is a schematic diagram of the transformation of the GaTe material from an amorphous state to a crystalline state provided in an embodiment of the present application.

[0024] Figure 3 It is a schematic diagram of the temperature-dependent XRD results of the GaTe material provided in the examples of the present application.

[0025] Figure 4 It is a schematic diagram of the relationship between the leakage current index of the gating layer provided in the embodiment of the present application and the molar percentage of the doped Te element.

[0026] Figure 5 This is a Raman spectrum diagram of the gating layer material when doped with different contents of Si element provided in the embodiment of the present application.

[0027] Figure 6 It is a schematic diagram of the structure of a memory provided in an embodiment of the present application.

[0028] Figure 7 It is a schematic diagram of the cross-sectional structure of another semiconductor device provided in an embodiment of the present application.

[0029] Figure 8 It is a schematic diagram of a partial structure of a phase change memory provided in an embodiment of the present application.

[0030] Fig. 9 It is a schematic diagram of the partial structure of another phase change memory provided in an embodiment of the present application.

[0031] Fig.10 It is a schematic diagram of the partial structure of another phase change memory provided in an embodiment of the present application.

[0032] Fig.11 It is a structural diagram of a storage system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0034] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present application.

[0035] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0036] As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and a contact layer and one or more dielectric layers.

[0037] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0038] See also Figure 1 , Figure 1 1 is a schematic diagram of a partial structure of a semiconductor device 100 provided in an embodiment of the present application. The semiconductor device 100 may be a wafer or a memory (e.g., a three-dimensional memory), or a part of a memory. The memory may be applied to communication products, consumer electronics products, automotive products, aerospace products, artificial intelligence products, or big data, etc. Among them, consumer electronics products include but are not limited to mobile phones, computers, tablets, cameras, smart glasses, or gaming products, etc.

[0039] The semiconductor device 100 includes a first electrode 101, a second electrode 102 arranged opposite to the first electrode 101, and a gating layer 103 sandwiched between the first electrode 101 and the second electrode 102 and having a bidirectional threshold switching characteristic; the material of the gating layer 103 includes a main material and a first doping material doped in the main material; wherein the main material and the first doping material both contain sulfur compounds, and the first doping material has a stable tetrahedral structure in an amorphous state.

[0040] In some embodiments, the main material of the gate layer 103 is Ge x As y Se 1-x-y / As x Se 1-x Amorphous sulfur compounds of the system.

[0041] It can be understood that Ge represents germanium element, As represents arsenic element, and Se represents selenium element.

[0042] Because Ge x As y Se 1-x-y / As x Se 1-x The amorphous sulfur compounds in the system are mainly unstable hexacoordinate structures, so the material has a large number of defective octahedral structures; x As y Se 1-x-y / As x Se 1-x The amorphous instability of the sulfur compounds of the system mainly comes from the transformation from the defective octahedral structure to the stable tetrahedral or stable octahedral structure. In order to improve the amorphous stability of such materials, the present application increases the energy required for atomic migration in the material by doping the main material with a first doping material having a stable tetrahedral structure in the amorphous state, that is, increasing the crystallization temperature of the gating layer material.

[0043] Of course, the main material of the gating layer 103 provided in the embodiment of the present application is not limited thereto, and may also be a sulfur compound containing other elements.

[0044] Since the first doping material and the main material are both sulfur compounds, and the first doping material has a four-coordination structure (tetrahedral structure) in the amorphous state that is more stable than the six-coordination structure in the amorphous sulfur compound with GeAsSe as the main body, by doping the first doping material into the main material of the gating layer 103, the content of the more stable tetrahedral structure in the material of the gating layer 103 is increased, thereby improving the crystallization temperature of the material of the gating layer 103, which is beneficial to improving the amorphous thermal stability of the material of the gating layer 103, thereby helping to improve the stability of the electrical characteristics of the gating layer 103, and further helping to improve the reliability of the semiconductor device 100 and the memory using the semiconductor device 100.

[0045] Moreover, the present application improves the amorphous stability of the gating layer material by improving the composition of the gating layer material, which is equivalent to improving the thermal stability of the gating layer material from the source. It does not require changing the structural architecture of the semiconductor device, is friendly to system design and process, has flexible application and a wider range of applicability.

[0046] In some embodiments, the semiconductor device 100 is an OTS-type gate transistor, that is, the semiconductor device 100 is a gate transistor with a bidirectional threshold switching characteristic.

[0047] Specifically, the working principle of the OTS type gate tube is as follows: when the applied voltage or the applied current is less than the threshold voltage or the threshold current, the gate tube maintains high resistance, so that the gate tube is in a closed state, thereby effectively suppressing leakage current; when the applied voltage or the applied current is greater than the threshold voltage or the threshold current, the gate tube quickly changes to low resistance, so that the gate tube is in an open state. When the OTS type gate tube is used in a phase change memory, the OTS type gate tube realizes the change from high resistance to low resistance through the threshold switching of the sulfur-based amorphous material, thereby controlling the cutoff and opening of the current to complete the process of writing (SET), erasing (RESET), reading (READ) and other processes in the phase change storage layer.

[0048] In some embodiments, the first doping material includes gallium tritelluride (Ga2Te3), which has an abnormal tetrahedral structure (four-coordinate structure) main body and good stability. By doping Ga2Te3 in the main material of the gating layer 103, the four-coordinate structure with stronger stability in the material of the gating layer 103 is increased, which is conducive to increasing the crystallization temperature of the material of the gating layer 103, thereby improving the amorphous thermal stability of the material of the gating layer 103.

[0049] It can be understood that Ga represents gallium element, and Te represents tellurium element.

[0050] It should be noted that other amorphous sulfur compounds with a stable tetrahedral structure similar to Ga2Te3 can also be used as the first doping material. The embodiments of the present application only use Ga2Te3 as an example for illustration, but are not limited to this material.

[0051] See also Figure 2 , Figure 2 This is a schematic diagram of the transition of GaTe material from amorphous to crystalline. Figure 2 It can be seen that GaTe material is mainly in a stable four-coordinate structure in the amorphous state, indicating that Ga2Te3 has a stable tetrahedral structure in the amorphous state. When the temperature T of the GaTe material is greater than its crystallization temperature Tx, the GaTe material will transform from the amorphous state to the crystalline state, and this process can also be called crystallization. Figure 2 As shown, the crystallized GaTe material is mainly a stable hexa-coordinated structure. It can be understood that the higher the crystallization temperature Tx of the GaTe material, the higher the amorphous thermal stability of the GaTe material.

[0052] It should be noted that the GaTe material described in the embodiments of the present application refers to a compound composed of Ga elements including Ga2Te3 and Te elements.

[0053] See also Figure 3 , Figure 3This is a schematic diagram of the temperature-dependent XRD results of GaTe materials, taking Ga2Te5 material as an example, where: Figure 3 (b) is the temperature-dependent XRD result of Ga2Te5. Figure 3 (a) and (c) are the XRD curves of Ga2Te5 at different temperatures, and Figure 3 The data of (a) and (c) in the figure come from the specific temperature point corresponding to the vertical coordinate in (b). Figure 3 From (a) and (c), we can see that Ga2Te5 has no obvious crystallization signal at 473K, a weak crystallization signal appears at 483K, and an obvious crystallization peak appears at 663K, which shows that Ga2Te5 material has a higher crystallization temperature.

[0054] pass Figure 3 This indicates that GaTe material has a higher crystallization temperature, and also proves that Ga2Te3 has a higher crystallization temperature Tx. Therefore, in the embodiment of the present application, doping Ga2Te3 into the main material can effectively increase the crystallization temperature of the gating layer material, thereby improving its amorphous thermal stability.

[0055] In some embodiments, in the material of the gating layer, the molar percentages of Ga and Te are both greater than 0 and less than 10%. For example, in the material of the gating layer, the molar percentage of Ga is 1%, 3%, 5%, 7% or 9%, and the molar percentage of Te is 1%, 3%, 5%, 7% or 9%.

[0056] See also Figure 4 , Figure 4 It is a schematic diagram of the relationship between the leakage current index of the gating layer and the molar percentage of the doped Te element. Figure 4 The vertical axis Ioff in represents the current value of the device in the off state. Therefore, the change in the leakage current index of the device can be determined based on the change in the size of Ioff. Figure 4 As can be seen from the curve in, as the content of the doped Te element increases, the leakage current index of the gating layer gradually increases, and when the molar percentage of the doped Te element is greater than 10%, the growth rate of the leakage current index of the gating layer increases. Therefore, the embodiment of the present application controls the molar percentage of the Te element in the material of the gating layer 103 within the range of 0 to 10%, which can effectively improve the leakage current problem of the gating layer 103 caused by doping the Te element.

[0057] It can be understood that controlling the molar percentage of Ga and Te to be less than 10% can improve the thermal stability of the gate layer 103 and improve the leakage current problem.

[0058] In a specific embodiment, the main material includes As and Se elements, and the chemical formula of the material of the gate layer 103 is (Ga 0.4 Te 0.6 ) m (As x Se (1-x) ) (1-m) , wherein m is the molar percentage of the first doping material, and x is the molar percentage of the As element in the main material. In the material of the gating layer represented by the chemical formula, the molar percentages of the Ga element and the Te element are both greater than 0 and less than 10%, the molar percentage of the As element is greater than 20% and less than 40%, and the molar percentage of the Se element is greater than 40% and less than 60%. For example, in the material of the gating layer represented by the chemical formula, the molar percentage of the Ga element is 1%, 3%, 5%, 7% or 9%, the molar percentage of the Te element is 1%, 3%, 5%, 7% or 9%, the molar percentage of the As element is 21%, 23%, 25%, 28%, 30%, 32%, 34%, 36% or 39%, and the molar percentage of the Se element is 41%, 43%, 45%, 48%, 50%, 52%, 54%, 56% or 59%.

[0059] In another specific embodiment, the main material includes Ge, As and Se; the chemical formula of the material of the gate layer 103 is (Ga 0.4 Te 0.6 ) m (Ge x As y Se (1-x-y) ) (1-m) , where m is the molar percentage of the first doping material, x is the molar percentage of the Ge element in the main material, and y is the molar percentage of the As element in the main material. In the material of the gating layer represented by the chemical formula, the molar percentages of the Ga element and the Te element are both greater than 0 and less than 10%, the molar percentage of the Ge element is greater than 5% and less than 30%, the molar percentage of the As element is greater than 20% and less than 40%, and the molar percentage of the Se element is greater than 40% and less than 60%. For example, in the material of the gating layer represented by the chemical formula, the molar percentage of Ga element is 1%, 3%, 5%, 7% or 9%, the molar percentage of Te element is 1%, 3%, 5%, 7% or 9%, the molar percentage of Ge element is 6%, 10%, 15%, 20%, 25% or 29%, the molar percentage of As element is 21%, 23%, 25%, 28%, 30%, 32%, 34%, 36% or 39%, and the molar percentage of Se element is 41%, 43%, 45%, 48%, 50%, 52%, 54%, 56% or 59%.

[0060] In a specific embodiment, the chemical formula of the material of the gate layer 103 is (Ga 0.4 Te 0.6 ) 0.075 (Ge 0.2 As 0.35 Se 0.45 ) 0.925 , but not limited to this.

[0061] Since the amorphous structure is a long-range disordered structure, after Ga2Te3 is doped into the main material of the gating layer 103, non-polar chemical bonds such as Te-Te will inevitably appear in the material of the amorphous gating layer 103, and the presence of such chemical bonds will lead to the deterioration of the leakage current (LKG) of the gating layer 103. In order to solve this problem, the embodiment of the present application further dopes the main material of the gating layer 103 with a second doping material, and a chemical bond is formed between the element in the second doping material and the Te element, and the bond energy of the formed chemical bond is greater than the bond energy of the chemical bond (Te-Te bond) formed between the Te element and the Te element.

[0062] It can be understood that since the bond energy of the chemical bond formed between the elements in the second doping material and the Te element is greater than the bond energy of the chemical bond formed between the Te element and the Te element, by doping the second doping material, the atoms in the second doping material can snatch the Te atoms to form bonds, thereby inhibiting the formation of Te-Te bonds, thereby improving the problem of leakage current in the gating layer caused by the Te-Te bond.

[0063] In a specific embodiment, the second doping material includes Si element, and the molar percentage of Si element is greater than 0 and less than 10%. Of course, the second doping material may include other non-metallic elements without affecting the function of the gating layer 103 .

[0064] Table 1 is a table of bond energy data of Te-Te bond, Si-Si bond and Si-Te bond. As can be seen from Table 1, the bond energy of Si-Te bond is the largest, and the bond energy of Si-Te bond is much greater than the bond energy of Te-Te bond, indicating that the bonding ability of Si-Te bond is the strongest and most stable.

[0065] Table 1 Bond energy data of Te-Te bond, Si-Si bond and Si-Te bond

[0066] Chemical Bond Te-Te Si-Si Si-Te Bond energy (KJ / mol) 257.6+ / -4.1 310 429.2

[0067] Therefore, after Si is further doped into the material of the gating layer 103 doped with Ga2Te3, Si atoms can rob Te atoms to form bonds, thereby inhibiting the formation of Te-Te bonds, thereby improving the problem of leakage current of the gating layer 103 caused by Te-Te bonds.

[0068] See also Figure 5 , Figure 5 This is the Raman spectrum of the gating layer material when doped with different contents of Si elements. Figure 5 It can be seen that when the molar percentage of doped Si is 0%, 3%, 6% and 10%, 155cm -1 The intensity of the Te-Te structure corresponding to the peak changes, and the peak at 155 cm -1 The Te-Te structure corresponding to the peak is significantly weakened, which indicates that doping Si will inhibit the formation of Te-Te bonds.

[0069] In a specific embodiment, the chemical formula of the material of the gate layer 103 is Si 0.05 -(Ga 0.4 Te 0.6 ) 0.15 (Ge 0.2 As 0.35 Se 0.45 ) 0.80 , but not limited to this.

[0070] In some embodiments, the doping method of the first doping material includes a physical deposition method or a chemical deposition method. Of course, the entire gating layer 103 can be formed by a physical deposition method or a chemical deposition method.

[0071] Among them, the physical deposition method includes using a single or multiple target materials of the target component to grow a thin film with the target component on a wafer by magnetron sputtering, or using multiple target materials containing the target component to grow a thin film with the target component by magnetron sputtering. The difference between these two physical deposition methods is that each target material of the former contains the same component, while the target materials of the latter contain different components. For example, it can be formed by using a target material containing Ga2Te3 / As x Se 1-x The target material is used in a co-sputtering process. By adjusting the power, deposition temperature, chamber pressure and other parameters of each target material during magnetron sputtering, a thin film with the target composition is deposited.

[0072] Of course, the physical deposition method can also be to grow a thin film having a target component on a wafer through a pulsed laser deposition process using a target material having a single target component.

[0073] Specifically, the chemical deposition method includes using chemical precursors having various elements in the target component to deposit thin films through chemical reaction deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE).

[0074] In order to ensure the uniformity of the thin film and avoid crystallization, a commonly used method at present is to form a gating layer using a single-target or multi-target magnetron sputtering / pulse laser deposition process.

[0075] It should be noted that in the embodiments of the present application, the above-mentioned target component refers to the main material and the first doping material mentioned above, and even includes the second doping material described below.

[0076] In some embodiments, the first doping material (e.g., Ga2Te3) can also be doped by particle / atom implantation. x As y Se 1-x-y / As x Se 1-x The film is doped by injecting Ga / Te / Ga2Te3 to form a gate layer 103.

[0077] In some embodiments, the second doping material may be doped using the same method as the first doping material, or may be doped using a method different from the first doping material, which is not limited in the present application.

[0078] In some embodiments, the material of the first electrode 101 and the second electrode 102 includes but is not limited to at least one of platinum (Pt), titanium (Ti), tungsten (W), gold (Au), ruthenium (Ru), aluminum (Al), titanium tungsten (TiW), titanium nitride (TiN), tantalum nitride (TaN), iridium dioxide (IrO2), indium tin oxide (ITO), and indium zinc oxide (IZO).

[0079] It can be understood that the electrode materials used for the first electrode 101 and the second electrode 102 can be the same or different, and can be adaptively selected according to the actual application scenario.

[0080] In some embodiments, Figure 1 As shown, when the semiconductor device 100 is a gate tube, the semiconductor device 100 also includes a substrate layer 104 and an insulating dielectric layer 105, the first electrode 102, the gate layer 103 and the second electrode 102 are stacked in sequence on the substrate layer 104, and the insulating dielectric layer 105 covers the side wall of the gate layer 103.

[0081] It can be understood that two oppositely disposed ends of the gating layer 103 are electrically connected to the first electrode 101 and the second electrode 102 respectively, and the gating function can be achieved by applying a voltage or a current to the first electrode 101 and the second electrode 102 .

[0082] In some embodiments, the substrate layer 104 may be a semiconductor substrate. For example, the material of the substrate layer 104 includes but is not limited to silicon dioxide, silicon carbide, silicon wafer, sapphire or diamond.

[0083] In some embodiments, the insulating dielectric layer 105 has insulating properties, which can prevent the first electrode 101 and the second electrode 102 from short-circuiting; and when the insulating dielectric layer 105 is a heat-insulating material, it can have a heat-insulating effect on the gating layer, which is beneficial to improving its thermal stability. In some embodiments, the material of the insulating dielectric layer 105 includes but is not limited to silicon dioxide (SiO2), silicon nitride (Si3N4), etc.

[0084] Specifically, the material of the gating layer 103 provided in the embodiment of the present application is suitable for phase change memory of various structures, for example, the phase change memory has any one of the following structures: a cross-lattice structure, a small-size electrode contact structure, a sinker contact structure, a sidewall vertical structure, etc. Among them, the phase change memory with a cross-lattice structure connects and leads out the two ends of the storage unit through mutually crossed electrode wires; the phase change memory with a small-size electrode contact structure leads out at least one end of the gating layer through a small-size contact electrode on at least one side to achieve the size definition of the device; the phase change memory with a sinker contact structure achieves the size definition of the device through a small-size sinker hole.

[0085] As can be seen from the above, the embodiment of the present application does not limit the size of the selection layer 103, the first electrode 101 and the second electrode 102 that are actually grown; and the first electrode 101 and the second electrode 102 can lead out the two ends of the selection layer 103 through multilayer films of different sizes and different materials to achieve electrical connection with other devices.

[0086] It can be understood that the semiconductor device 100 provided in the embodiment of the present application can be a gate tube, or a storage unit or memory including a gate tube, but is not limited thereto.

[0087] In the embodiment of the present application, since the first doping material and the main material are both sulfur compounds, and the first doping material has a four-coordinate structure (tetrahedral structure) that is more stable than the unstable six-coordinate structure in the amorphous state, by doping the first doping material in the main material of the gate layer 103, the content of the tetrahedral structure with stronger stability in the material of the gate layer 103 is increased, and the crystallization temperature of the material of the gate layer 103 is increased, which is conducive to improving the amorphous thermal stability of the material of the gate layer 103, thereby helping to improve the stability of the electrical characteristics of the gate layer 103, and further helping to improve the reliability of the semiconductor device 100 and the memory using the semiconductor device 100. In addition, the present application improves the amorphous thermal stability of the material of the gate layer 103 by improving the composition of the material of the gate layer 103, without changing the structural architecture of the semiconductor device 100, which is friendly to system design and process, flexible in application and has a wider range of applications. Finally, doping the second doping material on the basis of doping the first doping material is conducive to further improving the amorphous thermal stability of the material of the gate layer 103, and is conducive to reducing the leakage current of the gate layer 103.

[0088] Therefore, the material of the gating layer 103 in the semiconductor device 100 provided in the embodiment of the present application has high amorphous thermal stability, which is beneficial to improving the stability of the electrical characteristics of the gating layer 103, thereby helping to improve the reliability of the semiconductor device 100 and the memory using the semiconductor device 100.

[0089] See also Figure 6 The embodiment of the present application also provides a memory 200, which includes a peripheral circuit 300 and the semiconductor device 100 described in the above embodiment, and the peripheral circuit 300 is electrically connected to the semiconductor device 100, for example, the peripheral circuit 300 is electrically connected to the first electrode and / or the second electrode of the semiconductor device 100, and is used to provide a driving signal to the semiconductor device.

[0090] In some embodiments, the memory 200 includes a phase change memory, such as a three-dimensional phase change memory, but is not limited thereto. When the memory 200 is a phase change memory, the semiconductor device 100 may be a phase change memory unit or a gate transistor in the phase change memory unit.

[0091] like Figure 7As shown, taking the semiconductor device as a phase change memory unit as an example, the embodiment of the present application also provides a semiconductor device 400, which is different from the semiconductor device 100 provided in the aforementioned embodiment in that the semiconductor device 400 also includes a phase change memory layer 401 and a third electrode 402 connected in series with the selection layer 102, the phase change memory layer 401 is located on the side of the first electrode 101 away from the selection layer 103 or on the side of the second electrode 102 away from the selection layer 103, and the third electrode 402 is located on the side of the phase change memory layer 401 away from the selection layer 103.

[0092] The structure of the memory 200 will be described in detail below by taking the memory 200 as a phase change memory, the memory 200 including the peripheral circuit 300 and the semiconductor device 400 electrically connected to each other, and the semiconductor device 400 being a phase change memory unit as an example.

[0093] In a specific embodiment, Figure 7 As shown, the semiconductor device 400 includes a first electrode 102 , a gating layer 103 , a second electrode 102 , a phase change memory layer 401 and a third electrode 402 which are sequentially stacked from bottom to top.

[0094] It can be understood that the first electrode 101 is a bottom electrode (BE), the second electrode 102 is an intermediate electrode, and the third electrode 402 is a top electrode (TE); correspondingly, the gating layer 103 is located between the first electrode 101 and the second electrode 102, and the phase change memory layer 401 is located between the second electrode 102 and the third electrode 402. It can be understood that the phase change memory layer 401 and the gating layer 103 are connected in series through the intermediate electrode.

[0095] In some embodiments, the memory 200 also includes a bit line (BL) and a word line (WL) for address selection; the first electrode 101 is electrically connected to the bit line (BL), and the second electrode 102 is electrically connected to the word line (WL); or, the first electrode 101 is electrically connected to the word line (WL), and the second electrode 102 is electrically connected to the bit line (BL).

[0096] In some embodiments, the memory 200 may have any one of a cross-lattice structure, a small-size electrode contact structure, a countersunk hole contact structure, and a sidewall vertical structure.

[0097] See also Figure 8 , Figure 8 FIG. 5 is a schematic diagram of a partial structure of a phase change memory 500 having a cross-point lattice structure. Figure 8As shown, the phase change memory 500 includes a first address line 501, a first phase change memory unit 502, and a second address line (which may include Figure 8 The first phase-change memory unit 502 and the second phase-change memory unit 504 have the same structure and are both Figure 7 In the semiconductor device 400 shown, for example, the first phase change memory unit 502 and the second phase change memory unit 504 each include a first electrode 101 , a gating layer 103 , a second electrode 102 , a phase change memory layer 401 and a third electrode 402 stacked sequentially from bottom to top.

[0098] The phase change memory 500 can be based on heating and quenching the phase change memory layer 401 in the first phase change memory unit 502 and the second phase change memory unit 504, so that the phase change memory layer 401 in the first phase change memory unit 502 and the second phase change memory unit 504 can be converted between the amorphous state and the crystalline state, and then the difference between the resistivity of the phase change memory layer 401 in the first phase change memory unit 502 and the second phase change memory unit 504 in the amorphous state and the crystalline state can be used to implement data writing, erasing, reading and other processes. In addition, in order to prevent the leakage current of the read, erase, and write operations of the target phase change memory unit from affecting the adjacent phase change memory unit, it is necessary to use the threshold switching of the selection layer 103 to achieve the change from high resistance to low resistance, so as to control the switching of the current in the selected phase change memory unit.

[0099] like Figure 8 As shown, the first address line 501 is parallel to the third address line 505, and the first address line 501 and the third address line 505 are both perpendicular to the second address line 503; at the same time, the first phase change memory unit 502 is located at the intersection of the first address line 501 and the second address line 503, and the second phase change memory unit 504 is located at the intersection of the second address line 503 and the third address line 505.

[0100] Specifically, the first address line 501 and the third address line 505 can be used as bit lines (BL), and the second address line 503 can be used as word lines (WL); or, the first address line 501 and the third address line 505 can be used as word lines (WL), and the second address line 503 can be used as bit lines (BL).

[0101] In practical applications, the phase-change memory cells connected to both the selected word line and the selected bit line are selected by activating the selected word line and the selected bit line.

[0102] See also Fig. 9 , Fig. 9 FIG. 6 is a schematic diagram of a partial structure of a phase change memory 600 having a small-size electrode contact structure. Fig. 9 As shown, the phase change memory 600 includes a die 601, a first electrode (also called a connection contact (CT)) 101, a gating layer 103 and a second electrode 102; the first electrode 101 is located inside the die 601 and is led out from the side wall of the die 601; the gating layer 103 is formed on the surface of the die 601 and is electrically connected to the first electrode 101; the second electrode 102 is formed on the side of the gating layer 103 away from the die.

[0103] Understandably, Fig. 9 The structure and Figure 1 The difference between the semiconductor device 100 shown in FIG. 1 is that the first electrode 101 is formed at a different position. Fig. 9 The structure shown is advantageous in reducing the overall size of the device.

[0104] See also Fig.10 , Fig.10 FIG. 7 is a schematic diagram of a partial structure of a phase change memory 700 having a countersunk hole contact structure. Fig.10 As shown, the phase change memory 700 includes a wafer 701, a first electrode 101, a gating layer 103 and a second electrode 102; the first electrode 101 is located inside the wafer 701 and is led out from the side wall of the wafer 701; a countersunk hole 702 exposing the first electrode 101 is formed on one side of the wafer 701, the gating layer 103 is formed on the surface of the wafer 701 and in the countersunk hole 702 and is electrically connected to the first electrode 101; a groove is formed on the side of the gating layer 103 away from the first electrode 101, and the second electrode 102 is formed on the side of the gating layer 103 away from the wafer 701 and filled in the groove.

[0105] It can be understood that the first electrode 101 and the second electrode 102 are the bottom electrode and the top electrode respectively, and the material of the gating layer 103 is selected from the gating layer materials described in the above embodiments; Fig.10 The structure shown is Figure 1 The difference between the semiconductor device 100 shown in FIG. 1 is that the first electrode 101 and the gate layer 103 are formed at different positions. Fig.10 The structure shown is advantageous in reducing the overall size of the device.

[0106] It should be noted that the memory 200 provided in the embodiment of the present application can be Figures 8 to 10 Any phase change memory shown in the figure, and the material of the gating layer of these phase change memories is Figure 1 The materials of the gate layers 103 in the semiconductor device 100 are the same.

[0107] In the embodiment of the present application, since the material of the gating layer 103 in the memory 200 has high amorphous thermal stability, the reliability of the memory 200 is effectively improved.

[0108] See also Fig.11 The embodiment of the present application also provides a storage system 800, which includes a controller 801 and a memory 802, and the memory 802 is any one of the memories provided in the aforementioned embodiments; the controller 801 is electrically connected to the memory 802, and is used to control the memory 802 to store data; the memory 802 can perform operations to store data based on the control of the controller 801.

[0109] Specifically, the controller 801 is electrically connected to the peripheral circuit in the memory 802 , and controls the change of the working state of the memory 802 by providing a control signal to the peripheral circuit.

[0110] In some embodiments, the storage system 800 may be implemented as a storage device such as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a Personal Computer Memory Card International Association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card or a memory stick, etc.

[0111] In the embodiment of the present application, since the material of the selection layer in the memory has high amorphous thermal stability, the reliability of the memory is effectively improved, thereby improving the reliability of the storage system.

[0112] In the above embodiments, the description of each embodiment has its own emphasis. For parts not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments. The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0113] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A semiconductor device, characterized in that: A gating layer having a bidirectional threshold switching characteristic is included, wherein the gating layer includes a main material and a first doping material doped in the main material; The main material and the first doping material both contain sulfur compounds, and the first doping material has a stable tetrahedral structure in an amorphous state.

2. The semiconductor device according to claim 1, wherein: The first doping material includes gallium tritelluride.

3. The semiconductor device according to claim 2, characterized in that The main material contains As and Se elements, and the chemical formula of the material of the gating layer is (Ga 0.4 Te 0.6 ) m (As x Se (1-x) ) (1-m) , wherein m is the molar percentage of the first doping material, and x is the molar percentage of the As element in the main material; In the material of the gating layer, the molar percentages of the Ga element and the Te element are both greater than 0 and less than 10%, the molar percentage of the As element is greater than 20% and less than 40%, and the molar percentage of the Se element is greater than 40% and less than 60%.

4. The semiconductor device according to claim 2, characterized in that The main material contains Ge, As and Se elements; the chemical formula of the material of the gating layer is (Ga 0.4 Te 0.6 ) m (Ge x As y Se (1-x-y) ) (1-m) , wherein m is the molar percentage of the first doping material, and x and y are the molar percentages of the elements in the main material; In the material of the gating layer, the molar percentages of the Ga element and the Te element are both greater than 0 and less than 10%, the molar percentage of the Ge element is greater than 5% and less than 30%, the molar percentage of the As element is greater than 20% and less than 40%, and the molar percentage of the Se element is greater than 40% and less than 60%.

5. The semiconductor device according to claim 4, characterized in that The chemical formula of the material of the gating layer is (Ga 0.4 Te 0.6 ) 0.075 (Ge 0.2 As 0.35 Se 0.45 ) 0.925 .

6. The semiconductor device according to claim 2, wherein: The material of the gating layer also includes a second doping material doped in the main material, an element in the second doping material forms a chemical bond with the tellurium element, and the bond energy of the chemical bond is greater than the bond energy of the chemical bond formed between any two tellurium elements.

7. The semiconductor device according to claim 6, characterized in that The second doping material includes Si element, and the molar percentage of the Si element is greater than 0 and less than 10%.

8. The semiconductor device according to claim 7, characterized in that When the main material contains Ge, As and Se, the chemical formula of the material of the gating layer is Si 0.05 -(Ga 0.4 Te 0.6 ) 0.15 (Ge 0.2 As 0.35 Se 0.45 ) 0.80 .

9. A memory, characterized in that: The memory includes a peripheral circuit and the semiconductor device according to any one of claims 1 to 8, wherein the peripheral circuit is connected to the semiconductor device.

10. A storage system, characterized in that: The memory system includes a controller and the memory according to claim 9, wherein the controller is connected to the peripheral circuit.

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