Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a first dielectric film, a resistor element disposed on the first dielectric film, and a second dielectric film disposed on the resistor element. The resistor element includes silicon, chromium, and carbon. The silicon concentration in the resistor element increases from a central portion of the resistor element toward an upper surface of the resistor element, and also increases from the central portion of the resistor element toward a lower surface of the resistor element.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-124526 filed on Jul. 31, 2023 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and can be suitably used for, for example, a semiconductor device including a resistance element and a method for manufacturing the semiconductor device. Background Art

[0004] The disclosed techniques are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No.: 2023-56630

[0006] [Patent Document 2] Japanese Unexamined Patent Application Publication No.: 2023-58091

[0007] Patent Document 1 and Patent Document 2 disclose semiconductor devices including a resistor element including silicon, chromium, and carbon. Summary of the invention

[0008] In a semiconductor device including a resistor element including silicon, chromium, and carbon, improvement in performance is desired.

[0009] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0010] According to one embodiment, a semiconductor device includes a first dielectric film, a resistor element disposed on the first dielectric film, and a second dielectric film disposed on the resistor element. The resistor element includes silicon, chromium, and carbon. The silicon concentration of the resistor element increases from a central portion of the resistor element toward an upper surface of the resistor element, and increases from a central portion of the resistor element toward a lower surface of the resistor element.

[0011] According to one embodiment, the performance of a semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a cross-sectional view of a main portion of the semiconductor device of the first embodiment.

[0013] Figure 2 is a main portion cross-sectional view during a manufacturing step of the semiconductor device of the first embodiment.

[0014] Figure 3 yes Figure 2A cross-sectional view of a main portion during a subsequent manufacturing step of the semiconductor device.

[0015] Figure 4 yes Figure 3 A cross-sectional view of a main portion during a subsequent manufacturing step of the semiconductor device.

[0016] Figure 5 yes Figure 4 A cross-sectional view of a main portion during a subsequent manufacturing step of the semiconductor device.

[0017] Figure 6 yes Figure 5 A cross-sectional view of a main portion during a subsequent manufacturing step of the semiconductor device.

[0018] Figure 7 yes Figure 6 A cross-sectional view of a main portion during a subsequent manufacturing step of the semiconductor device.

[0019] Figure 8 yes Figure 7 A cross-sectional view of a main portion during a subsequent manufacturing step of the semiconductor device.

[0020] Fig. 9 yes Figure 8 A cross-sectional view of a main portion during a subsequent manufacturing step of the semiconductor device.

[0021] Fig.10 yes Fig. 9 A cross-sectional view of a main portion during a subsequent manufacturing step of the semiconductor device.

[0022] Fig.11 yes Fig.10 A cross-sectional view of a main portion during a subsequent manufacturing step of the semiconductor device.

[0023] Fig.12 yes Fig.11 A cross-sectional view of a main portion during a subsequent manufacturing step of the semiconductor device.

[0024] Fig.13 yes Fig.12 A cross-sectional view of a main portion during a subsequent manufacturing step of the semiconductor device.

[0025] Fig.14 is a graph showing the resistivity and the temperature coefficient of resistance of the Si-Cr-C resistor element.

[0026] Fig.15 is a graph showing the relationship between the annealing temperature and the resistivity and the temperature coefficient of resistance.

[0027] Fig.16 is a partially enlarged cross-sectional view of a semiconductor device of an examined example.

[0028] Fig.17 is a partially enlarged cross-sectional view of a semiconductor device of an examined example.

[0029] Fig.18 yes Figure 1 Partially enlarged cross-sectional view.

[0030] Fig.19 It shows Fig.18 Graph of the concentration profiles of silicon, chromium, and carbon in the laminate structure shown.

[0031] Fig. 20 is a graph showing the result of analyzing the concentration distributions of silicon, chromium, and carbon when no crystallization annealing process is performed.

[0032] Fig.21 is a graph showing the correlation between the annealing temperature and the temperature coefficient of resistance.

[0033] Fig. 22 is a plan view of a resistor element.

[0034] Fig.23 is a cross-sectional view of a resistor element.

[0035] Fig.24 is a graph showing the correlation between the width and resistance value of a resistor element.

[0036] Fig.25 is a graph showing the correlation between the width of a resistor element and the temperature coefficient of resistance.

[0037] Fig.26 is a plan view of a resistor element of a modified example.

[0038] Fig. 27 is a cross-sectional view of a resistor element of a modified example.

[0039] Fig.28 is a cross-sectional view of a resistor element of a modified example.

[0040] Fig.29 is a main portion cross-sectional view during a manufacturing step of the semiconductor device of the second embodiment.

[0041] Fig.30 yes Fig.29 A cross-sectional view of a main portion during a subsequent manufacturing step of the semiconductor device.

[0042] Fig.31 yes Fig.30 A cross-sectional view of a main portion during a subsequent manufacturing step of the semiconductor device.

[0043] Fig.32 yes Fig.31 A cross-sectional view of a main portion during a subsequent manufacturing step of the semiconductor device.

[0044] Fig.33 yes Fig.32 A cross-sectional view of a main portion during a subsequent manufacturing step of the semiconductor device.

[0045] Fig.34 is a cross-sectional view of a resistor element.

[0046] Fig.35 is a graph showing the carbon content and the temperature coefficient of resistance of the resistor element. DETAILED DESCRIPTION

[0047] In the following embodiments, when it is necessary for convenience, it is described by being divided into a plurality of parts or embodiments, but unless otherwise specified, they are not independent of each other, and one embodiment is related to a modified example, details, supplementary description or similar part or all of another embodiment. In the following embodiments, except that the quantity is specifically indicated and is clearly limited to a specific quantity in principle, the number of elements, etc. (including the number of elements, numerical value, amount, range, etc.) is not limited to a specific number, but may not be less than or equal to a specific number. In addition, in the following embodiments, it is obvious that unless they are specifically specified and they are considered to be obviously necessary in principle, the constituent elements (including element steps, etc.) are not necessarily necessary. Similarly, in the following embodiments, except that they are clearly specified and they are considered to be obvious in principle, when the shape, positional relationship, etc. of the reference component, etc., it is assumed that the shape, etc. are substantially similar to or similar to the shape, etc. This also applies to the above-mentioned numerical value and range.

[0048] Hereinafter, the embodiments are described in detail with reference to the accompanying drawings. In all the figures, for the purpose of explaining the embodiments, the same reference numerals are given to the components having the same functions, and repeated descriptions are omitted. In addition, in the following embodiments, the description of the same or similar parts will not be repeated in principle unless it is particularly necessary.

[0049] In the drawings used in the embodiments, hatching may be omitted even in the case of a cross-sectional view to make the drawings easier to see. In addition, hatching may be used even in the case of a plan view to make the drawings easier to see.

[0050] First embodiment

[0051] The structure of semiconductor devices

[0052] Herein, a semiconductor device of the present embodiment will be described with reference to the accompanying drawings. Figure 1 is a main portion cross-sectional view of the semiconductor device according to the present embodiment.

[0053] like Figure 1 As shown, the semiconductor device of the present embodiment includes a semiconductor substrate SB, dielectric films IL1, IL2, IL3, a plurality of wirings M1, M2, a plurality of plugs V1, V2, and a resistor element RS.

[0054] A dielectric film IL1 is formed on the main surface of the semiconductor substrate SB. A plurality of wirings M1 are formed on the dielectric film IL1 to contact the upper surface of the dielectric film IL1. A dielectric film IL2 is formed on the dielectric film IL1 to cover the plurality of wirings M1. A resistor element RS is formed on the dielectric film IL2 to contact the upper surface of the dielectric film IL2. A dielectric film IL3 is formed on the dielectric film IL2 to cover the resistor element RS. The upper surface and the side surface of the resistor element RS are in contact with the dielectric film IL3. The lower surface of the resistor element RS is in contact with the dielectric film IL2.

[0055] A plurality of wirings M2 are formed on the dielectric film IL3 to contact the upper surface of the dielectric film IL3. Each of the plurality of plugs V1 has conductivity. Each of the plurality of plugs V2 has conductivity. Each of the plurality of plugs V1 is disposed in the dielectric film IL2. Specifically, each of the plurality of plugs V1 is buried in an opening penetrating the dielectric film IL2. Each of the plurality of plugs V2 is buried in an opening penetrating the dielectric films IL2, IL3.

[0056] Each of the dielectric films IL1, IL2, IL3 is a single-layer dielectric film or a laminated dielectric film. The laminated dielectric film is a laminated film in which a plurality of dielectric films are laminated.

[0057] The resistor element RS includes silicon (Si), chromium (Cr) and carbon (C) as constituent elements. Specifically, the resistor element RS is made of a material layer (resistor layer) MT including silicon (Si), chromium (Cr) and carbon (C) as constituent elements. The planar shape of the material layer MT is, for example, rectangular. The thickness of the material layer MT is preferably less than 10 nm, and more preferably less than 2 nm and less than 10 nm.

[0058] The plurality of plugs V1 include plugs V1a and plugs V1b. The plurality of plugs V2 include plugs V2a and plugs V2b. The plurality of wirings M1 include wirings M1a and wirings M1b. The plurality of wirings M2 include wirings M2a and wirings M2b. The wirings M1a and M1b are spaced apart from each other. The wirings M2a and M2b are spaced apart from each other.

[0059] Wiring M1a and wiring M1b are provided on dielectric film IL1 to be covered by dielectric film IL2. Plug V1a is provided in dielectric film IL2 and connected to wiring M1a. Plug V1b is provided in dielectric film IL2 and connected to wiring M1b. Resistor element RS connects plug V1a and plug V1b.

[0060] Specifically, near one end of the material layer MT, the upper surface of the plug V1a is covered by the material layer MT and contacts the lower surface of the material layer MT. The plug V1a is electrically connected to the material layer MT. The plug V1a is disposed on the wiring M1a, and the lower surface of the plug V1a contacts the upper surface of the wiring M1a. The plug V1a is electrically connected to the wiring M1a.

[0061] The plug V2a is provided on the wiring M1a, and the lower surface of the plug V2a contacts the upper surface of the wiring M1a. The plug V2a is electrically connected to the wiring M1a. The upper surface of the plug V2a is covered by the wiring M2a and contacts the lower surface of the wiring M2a. The plug V2a is electrically connected to the wiring M2a.

[0062] Near the other end of the material layer MT, the upper surface of the plug V1b is covered by the material layer MT and is in contact with the lower surface of the material layer MT. The plug V1b is electrically connected to the material layer MT. The plug V1b is provided on the wiring M1b, and the lower surface of the plug V1b is in contact with the upper surface of the wiring M1b. The plug V1b is electrically connected to the wiring M1b.

[0063] The plug V2b is provided on the wiring M1b, and the lower surface of the plug V2b contacts the upper surface of the wiring M1b. The plug V2b is electrically connected to the wiring M1b. The upper surface of the plug V2b is covered by the wiring M2b and contacts the lower surface of the wiring M2b. The plug V2b is electrically connected to the wiring M2b.

[0064] Therefore, one end of the resistor element RS is connected to the plug V1a, and the other end of the resistor element RS is connected to the plug V1b. The wiring M2a is electrically connected to one end of the resistor element RS via the plug V2a, the wiring M1a, and the plug V1a. The wiring M2b is electrically connected to the other end of the resistor element RS via the plug V2b, the wiring M1b, and the plug V1b.

[0065] Illustration and description of the structures over the dielectric film IL3 and the wiring M2 are omitted.

[0066] Semiconductor device manufacturing steps

[0067] The manufacturing steps of the semiconductor device of this embodiment are explained with reference to the drawings. Figures 2 to 13 is a main portion cross-sectional view during a manufacturing step of the semiconductor device of the present embodiment.

[0068] First, if Figure 2 As shown, a semiconductor substrate SB is prepared. The semiconductor substrate SB is made of, for example, single-crystal silicon into which p-type or n-type impurities are introduced.

[0069] Next, if necessary, a semiconductor element such as a MISFET (Metal Insulator Semiconductor Field Effect Transistor) or a diode (not shown) is formed on the semiconductor substrate SB.

[0070] Next, if Figure 3 As shown, a dielectric film IL1 is formed on the main surface of the semiconductor substrate SB. The dielectric film IL1 is an interlayer dielectric film. The dielectric film IL1 can be made of, for example, a silicon oxide thin film and can be formed using a method such as a CVD (chemical vapor deposition) method. After the dielectric film IL1 is formed, the upper surface of the dielectric film IL1 can also be planarized using a method such as a CMP (chemical mechanical polishing) method.

[0071] Next, if Figure 3 As shown, a plurality of wirings M1 are formed on the dielectric film IL1. For example, a conductive film is formed on the dielectric film IL1. Thereafter, by patterning the conductive film using a photolithography technique and an etching technique, a plurality of wirings M1 made of the conductive film can be formed. The plurality of wirings M1 are, for example, aluminum wirings, but wirings using other metal materials can also be applied. The plurality of wirings M1 include wirings M1a and wirings M1b.

[0072] Next, if Figure 4 As shown, a dielectric film IL2 is formed on the dielectric film IL1 so as to cover the plurality of wirings M1. The dielectric film IL2 is an interlayer dielectric film. The dielectric film IL2 is made of, for example, a silicon oxide film. After the dielectric film IL2 is formed, the upper surface of the dielectric film IL2 may be planarized using a CMP method or the like.

[0073] Next, if Figure 5 As shown, by etching the dielectric film IL2 using a photoresist pattern (not shown) formed on the dielectric film IL2 as an etching mask, a plurality of openings OP1 penetrating the dielectric film IL2 are formed.

[0074] Next, if Figure 6 As shown in FIG. 1 , a conductive film CD1 is formed on the dielectric film IL2 to fill the plurality of openings OP1 in the dielectric film IL2. The conductive film CD1 is, for example, a laminated film configured of a barrier conductive film and a main conductive film on the barrier conductive film. The main conductive film is, for example, a tungsten film. Then, as shown in FIG. Figure 7As shown, the conductive film CD1 provided outside the plurality of openings OP1 in the dielectric film IL2 is removed by a CMP method or the like. As a result, a plurality of plugs V1 are formed. The plurality of plugs V1 are each buried in the plurality of openings OP1. The plurality of plugs V1 includes plugs V1a and plugs V1b.

[0075] Next, if Figure 8 As shown, the material layer MTa is formed on the dielectric film IL2 using a sputtering method or the like to cover the upper surface of each plug V1. The material layer MTa is formed on the entire upper surface of the dielectric film IL2 and on the upper surfaces of the plurality of plugs V1. The material layer MTa includes silicon (Si), chromium (Cr) and carbon (C) as constituent elements. The material layer MTa is an amorphous film.

[0076] Next, if Fig. 9 As shown, the material layer MT is formed by patterning the material layer MTa using photolithography technology and etching technology. The material layer MT is made of the patterned material layer MTa. The material layer MT configures the resistor element RS.

[0077] Next, if Fig.10 As shown, a dielectric film IL3 is formed on the dielectric film IL2 so as to cover the material layer MT. The dielectric film IL3 is an interlayer dielectric film. The dielectric film IL3 is made of, for example, a silicon oxide film. The dielectric film IL3 is formed to contact the upper surface and the side surface of the material layer MT. After the dielectric film IL3 is formed, the upper surface of the dielectric film IL3 can be planarized using a CMP method or the like.

[0078] Next, heat treatment (annealing treatment) is performed to crystallize the material layer MT. Through this heat treatment, the material layer MT is heated, and a part or all of the amorphous material layer MT is crystallized.

[0079] Next, if Fig.11 As shown, by etching the dielectric films IL3 and IL2 using a photoresist pattern (not shown) formed on the dielectric film IL3 as an etching mask, a plurality of openings OP2 penetrating the dielectric films IL3 and IL2 are formed.

[0080] Next, if Fig.12 As shown, a plurality of plugs V2 are formed. For example, a conductive film is formed on the dielectric film IL3 to fill the plurality of openings OP2. The conductive film is, for example, a laminated film configured by a barrier layer conductive film and a main conductive film on the barrier layer conductive film. The main conductive film is, for example, a tungsten film. Then, the conductive film provided outside the plurality of openings OP2 is removed by a CMP method or the like. As a result, a plurality of plugs V2 are formed. Each of the plurality of plugs V2 is buried in the plurality of openings OP2. The plurality of plugs V2 includes a plug V2a and a plug V2b.

[0081] Next, if Fig.13 As shown, a plurality of wirings M2 are formed on the dielectric film IL3. For example, a conductive film is formed on the dielectric film IL1. Then, by patterning the conductive film using photolithography and etching techniques, a plurality of wirings M2 made of the conductive film can be formed. The plurality of wirings M2 are made of, for example, aluminum wirings, but wirings of other metal materials can also be applied. The plurality of wirings M2 include wirings M2a and wirings M2b.

[0082] Illustration and explanation of steps of forming other upper-layer dielectric films and wirings are omitted.

[0083] Background

[0084] The inventor is studying a resistor element including silicon (Si), chromium (Cr) and carbon (C) as constituent elements. Hereinafter, a resistor element including silicon (Si), chromium (Cr) and carbon (C) as constituent elements is referred to as a Si-Cr-C resistor element. The above-mentioned resistor element RS is also a Si-Cr-C resistor element. In addition, a film including silicon (Si), chromium (Cr) and carbon (C) as constituent elements is referred to as a Si-Cr-C film. The above-mentioned material layer MTa is also a Si-Cr-C film.

[0085] In Si-Cr-C resistor elements, it is desirable that the resistivity is high and the absolute value of the temperature coefficient of resistance (TCR) is small. If the resistivity of the resistor element is high, the resistance value can be increased while reducing the plane dimension of the resistor element, so the semiconductor device including the resistor element can be miniaturized. If the absolute value of the temperature coefficient of resistance is small, the change in the resistance value of the resistor element due to temperature change can be suppressed, so the performance of the semiconductor device including the resistor element can be improved.

[0086] Fig.14 is a graph showing the resistivity and temperature coefficient of resistance of Si-Cr-C resistor elements. Based on the atomic number, Fig.14 The horizontal axis of corresponds to the ratio of silicon to chromium in the Si-Cr-C resistor element. Hereinafter, the ratio of silicon to chromium in the Si-Cr-C resistor element is referred to as the Si / Cr ratio. The Si / Cr ratio is a content ratio based on the number of atoms. Fig.14 The vertical axis of corresponds to the resistivity or temperature coefficient of resistance (TCR) of the Si-Cr-C resistor element. Fig.14 , the resistivity and the temperature coefficient of resistance of the Si-Cr-C resistor element when the Si / Cr ratio is changed are shown, and the carbon content in the Si-Cr-C resistor element is 15-25 atomic percent based on the atomic number. In addition, Fig.14 The graph in is based on measured data of Si-Cr-C resistor elements that have not undergone a crystallization annealing process.

[0087] from Fig.14 As can be seen from the graph in , the resistivity of the Si-Cr-C resistor element increases with the increase of the Si / Cr ratio.

[0088] On the other hand, from Fig.14 It can be seen from the graph in that when the Si / Cr ratio exceeds 1.2, the resistance temperature coefficient of the Si-Cr-C resistor element gradually decreases, and when the Si / Cr ratio exceeds 1.5, the resistance temperature coefficient of the Si-Cr-C resistor element decreases more. And when the Si / Cr ratio exceeds 2.5, the absolute value of the resistance temperature coefficient of the Si-Cr-C resistor element increases to an undesirable level (200ppm / degree or more) along with the resistance material.

[0089] In Si-Cr-C resistor elements, resistivity and resistance temperature coefficient are in a trade-off relationship. Therefore, if resistivity increases, the absolute value of resistance temperature coefficient increases. Therefore, it is difficult to simply adjust the composition ratio of Si-Cr-C resistor elements to increase resistivity and suppress the absolute value of resistance temperature coefficient.

[0090] Fig.15 is a graph showing the relationship between the annealing temperature and the resistivity and the temperature coefficient of resistance when a crystallization annealing process is applied to a Si-Cr-C resistor element. Fig.15 The horizontal axis of the graph corresponds to the annealing temperature. Fig.15 The vertical axis of the graph in corresponds to the resistivity or temperature coefficient of resistance (TCR) of the Si-Cr-C resistor element.

[0091] from Fig.15 As can be seen from the graph in Figure 1, the resistivity and temperature coefficient of resistance of the Si-Cr-C resistor element change by applying the crystallization annealing treatment. Fig.15 In the curve graph of , when the annealing temperature is in the range of 520 degrees Celsius to 530 degrees Celsius, the absolute value of the resistance temperature coefficient is small.

[0092] However, annealing at a temperature higher than 500 degrees Celsius is not desirable. This is because annealing at a temperature higher than 500 degrees Celsius may affect wiring or semiconductor devices formed on a semiconductor substrate. Therefore, in order to improve the reliability of semiconductor devices, it is desirable to perform a crystallization annealing process on the Si-Cr-C resistor element at a temperature lower than 500 degrees Celsius.

[0093] Fig.16 and Fig.17 It is a partially enlarged cross-sectional view of a semiconductor device of an inspection example studied by the present inventors.

[0094] Fig.16 and Fig.17The semiconductor device of the inspection example shown in includes a dielectric film IL2, a Si-Cr-C resistor element RS101 formed on the dielectric film IL2, and a dielectric film IL3 formed on the Si-Cr-C resistor element RS101. However, Fig.16 The case where the thickness of the Si-Cr-C resistor element RS101 is large is shown, and Fig.17 The figure shows the case where the thickness of the Si-Cr-C resistor element RS101 is small. Fig.16 In the case of , the thickness of the Si-Cr-C resistor element RS101 is about 300nm. On the other hand, in Fig.17 In this case, the thickness of the Si—Cr—C resistor element RS101 is less than 10 nm.

[0095] The upper surface and lower surface of Si-Cr-C resistor element RS101 are not completely flat, but have unevenness, reflecting surface roughness. Therefore, each of the upper surface and lower surface of Si-Cr-C resistor element RS101 has multiple protrusions (protrusions). This is because it is difficult to form a Si-Cr-C film with a completely flat upper surface and lower surface. The same applies to the upper surface and lower surface of the resistor element RS of the present embodiment. The upper surface and lower surface of the resistor element RS are not completely flat, but have unevenness, reflecting surface roughness. Therefore, each of the upper surface and lower surface of the resistor element RS of the present embodiment has multiple protrusions (protrusions).

[0096] When current passes through the Si-Cr-C resistor element RS101, electrons are conducted through the inside of the Si-Cr-C resistor element RS101. Fig.16 and Fig.17 In each of the figures, arrow YG1 indicates a conduction path passing through the inside of the Si-Cr-C resistor element RS101. However, when current passes through the Si-Cr-C resistor element RS101, electron conduction through the dielectric film IL2 or the dielectric film IL3 also occurs due to unevenness on the upper and lower surfaces of the Si-Cr-C resistor element RS101.

[0097] Specifically, in Fig.16 and Fig.17In each of the figures, the current flows between the protrusions on the upper surface of the Si-Cr-C resistor element RS101 along the path schematically indicated by the arrow YG2. The arrow YG2 indicates the conduction path through the dielectric film IL3. In addition, the current flows between the protrusions on the lower surface of the Si-Cr-C resistor element RS101 along the path schematically indicated by the arrow YG3. The arrow YG3 indicates the conduction path through the dielectric film IL2. That is, near the upper surface of the Si-Cr-C resistor element RS101, a portion of the dielectric film IL3 also contributes as an electron conduction path, and near the lower surface of the Si-Cr-C resistor element RS101, a portion of the dielectric film IL2 also contributes as an electron conduction path.

[0098] like Fig.16 As shown in FIG. 1 , when the thickness of the Si-Cr-C resistor element RS101 is large, most of the current flows through the inside of the Si-Cr-C resistor element RS101, and therefore the contribution of the conduction path indicated by the arrow YG2 or the arrow YG3 is small. Therefore, the resistance value of the conduction path through the dielectric film IL2 or the dielectric film IL3 hardly contributes to the total resistance value of the Si-Cr-C resistor element RS101.

[0099] However, with Fig.16 Compared with the case where the thickness of the Si-Cr-C resistor element RS101 is large, Fig.17 As shown, when the thickness of the Si-Cr-C resistor element RS101 is small, the current flowing through the inside of the Si-Cr-C resistor element RS101 decreases, so the contribution of the conduction path indicated by the arrow YG2 or the arrow YG3 becomes larger. Therefore, the ratio of the resistance value of the conduction path through the dielectric film IL2 or the dielectric film IL3 to the total resistance value of the Si-Cr-C resistor element RS101 increases.

[0100] In the conduction path (YG2) through the dielectric film IL3 and the conduction path (YG3) through the dielectric film IL2, the resistance value changes greatly due to temperature change, the resistance temperature coefficient becomes negative, and the absolute value of the resistance temperature coefficient increases. Therefore, as the thickness of the Si-Cr-C resistor element RS101 decreases, the influence of the conduction path through the dielectric film IL2 or the dielectric film IL3 becomes greater, and thus the absolute value of the resistance temperature coefficient increases. Even if the thickness of the Si-Cr-C resistor element is reduced, it is desirable to suppress the absolute value of the resistance temperature coefficient.

[0101] Resistor Components

[0102] Fig.18 is the above Figure 1 A partially enlarged cross-sectional view of a portion of . Fig.19 It shows Fig.18Graph of the concentration distribution of silicon (Si), chromium (Cr) and carbon (C) in the laminate structure shown. Fig.19 The horizontal axis of the middle graph corresponds to depth position. Fig.19 The vertical axis of the graph corresponds to the atomic fraction (concentration) of silicon (Si), chromium (Cr), or carbon (C). Fig.19 In the graph of , the concentration distribution of silicon (Si) is shown by a solid line, the concentration distribution of carbon (C) is shown by a dotted line, and the concentration distribution of chromium (Cr) is shown by a dotted line. Fig.19 The graph in is based on the analysis results of EDX (Energy Dispersive X-ray Spectroscopy).

[0103] In the present embodiment, in the manufacturing steps of the semiconductor device, as described above, the crystallization annealing treatment is applied to the material layer MT. Fig.19 The graph in is a graph of the result of analyzing the concentration distribution of each element when the crystallization annealing treatment is applied to the material layer MT as in the present embodiment.

[0104] from Fig.19 As can be seen from the curve graph in , in this embodiment, the composition ratio of silicon (Si), chromium (Cr) and carbon (C) in the resistor element RS is not uniformly distributed in the thickness direction, but has the following distribution. The thickness direction refers to the direction from the lower surface to the upper surface of the resistor element RS, or from the upper surface to the lower surface of the resistor element RS. The upper surface of the resistor element RS is the interface between the resistor element RS and the dielectric film IL3. The lower surface of the resistor element RS is the interface between the resistor element RS and the dielectric film IL2. Fig.19 The concentration distribution in the thickness direction is shown.

[0105] like Fig.19 As shown in the graph in , in the resistor element RS, a peak P1 of the silicon (Si) concentration is formed at a position near the upper surface of the resistor element RS, and a peak P2 of the silicon concentration is formed at a position near the lower surface of the resistor element RS.

[0106] The concentration of silicon (Si) in the resistor element RS (material layer MT) increases from the central part of the resistor element RS toward the upper surface of the resistor element RS. In addition, the concentration of silicon (Si) in the resistor element RS (material layer MT) increases from the central part of the resistor element RS toward the lower surface of the resistor element RS. That is, the concentration of silicon (Si) in the resistor element RS is lowest at the central part of the resistor element RS, increases from the central part toward the upper surface, and increases from the central part toward the lower surface. Therefore, in the resistor element RS, the concentration of silicon (Si) near the upper surface of the resistor element RS and near the lower surface of the resistor element RS is greater than the concentration of silicon (Si) at the central part of the resistor element RS. The central part of the resistor element RS refers to the central part in the thickness direction of the resistor element RS.

[0107] like Fig.19 As shown in the graph in , in the resistor element RS, a peak P3 of the carbon (C) concentration is formed at a position near the upper surface of the resistor element RS, and a peak P4 of the carbon concentration is formed at a position near the lower surface of the resistor element RS.

[0108] The carbon (C) concentration in the resistor element RS (material layer MT) increases from the central portion of the resistor element RS toward the upper surface of the resistor element RS. In addition, the carbon (C) concentration in the resistor element RS (material layer MT) increases from the central portion of the resistor element RS toward the lower surface of the resistor element RS. That is, the carbon (C) concentration in the resistor element RS is lowest at the central portion of the resistor element RS, increases from the central portion toward the upper surface, and increases from the central portion toward the lower surface. Therefore, in the resistor element RS, the carbon (C) concentration near the upper surface of the resistor element RS and near the lower surface of the resistor element RS is greater than the carbon (C) concentration at the central portion of the resistor element RS.

[0109] like Fig.19 As shown in the graph in , in the resistor element RS, a peak P5 of the chromium (Cr) concentration is formed at the central portion of the resistor element RS.

[0110] The chromium (Cr) concentration in the resistor element RS (material layer MT) decreases from the central portion of the resistor element RS toward the upper surface of the resistor element RS. In addition, the chromium (Cr) concentration in the resistor element RS (material layer MT) decreases from the central portion of the resistor element RS toward the lower surface of the resistor element RS. That is, the chromium (Cr) concentration in the resistor element RS is highest at the central portion of the resistor element RS, decreases from the central portion toward the upper surface, and also decreases from the central portion toward the lower surface. Therefore, in the resistor element RS, the chromium (Cr) concentration near the upper surface of the resistor element RS and near the lower surface of the resistor element RS is less than the silicon (Si) concentration in the central portion of the resistor element RS.

[0111] The concentrations of silicon (Si), chromium (Cr), and carbon (C) are all based on atomic number and expressed in atomic percent.

[0112] Reflecting the concentration distributions of silicon (Si) and chromium (Cr) in the resistor element RS, the Si / Cr ratio in the resistor element RS shows the following distribution.

[0113] The Si / Cr ratio in the resistor element RS (material layer MT) increases from the central portion of the resistor element RS toward the upper surface of the resistor element RS. In addition, the Si / Cr ratio in the resistor element RS (material layer MT) increases from the central portion of the resistor element RS toward the lower surface of the resistor element RS. That is, the Si / Cr ratio in the resistor element RS is lowest in the central portion of the resistor element RS, increases from the central portion toward the upper surface, and also increases from the central portion toward the lower surface. Therefore, in the resistor element RS, the Si / Cr ratio near the upper surface of the resistor element RS and near the lower surface of the resistor element RS is greater than the Si / Cr ratio in the central portion of the resistor element RS.

[0114] from Fig.14 As can be understood from the graph of , in the Si-Cr-C resistor element, the greater the Si / Cr ratio, the greater the resistivity. Therefore, reflecting the Si / Cr ratio distribution in the resistor element RS, the resistivity in the resistor element RS shows the following distribution.

[0115] The resistivity in the resistor element RS (material layer MT) increases from the central portion of the resistor element RS toward the upper surface of the resistor element RS. In addition, the resistivity in the resistor element RS (material layer MT) increases from the central portion of the resistor element RS toward the lower surface of the resistor element RS. That is, the resistivity in the resistor element RS is lowest at the central portion of the resistor element RS, increases from the central portion toward the upper surface, and also increases from the central portion toward the lower surface. Therefore, in the resistor element RS, the resistivity near the upper surface of the resistor element RS and near the lower surface of the resistor element RS is greater than the resistivity at the central portion of the resistor element RS.

[0116] Fig. 20 : is a graph showing the result of analyzing the concentration distribution of silicon (Si), chromium (Cr), and carbon (C) when the material layer MT is not subjected to the crystallization annealing process as an inspection example. Fig. 20 The horizontal and vertical axes of Fig.19 Same. Similar to Fig.19 , Fig. 20 The graph is based on EDX analysis results.

[0117] Different from the present embodiment, when the material layer MT is not subjected to the crystallization annealing treatment, as in Fig. 20 It can be seen from the curve that the concentration distribution of silicon (Si) in the material layer MT is almost uniform in the thickness direction. In addition, the concentration distribution of carbon (C) in the material layer MT is almost uniform in the thickness direction. In addition, by comparing Fig.19 The curve graph and Fig. 20 It can be seen from the curve graph that Fig. 20 The distribution curve of chromium concentration in Fig.19 The distribution curve of chromium concentration in is wider. Fig.19 Compared with the case of the curve graph, Fig. 20 In the case of the curve graph of , the concentration distribution of chromium (Cr) in the material layer MT is considered to be almost uniform.

[0118] Therefore, the composition ratio of chromium (Cr) and carbon (C) is considered to be almost uniform in the thickness direction when the material layer MT is not subjected to the crystallization annealing treatment, compared with when the material layer MT is subjected to the crystallization annealing treatment.

[0119] On the other hand, in the present embodiment, during the manufacturing steps of the semiconductor device, a crystallization annealing treatment is applied to the material layer MT. The crystallization annealing treatment is performed while the material layer MT is sandwiched between the dielectric film IL2 and the dielectric film IL3. That is, the lower surface of the material layer MT is covered by the dielectric film IL2 and the upper surface of the material layer MT is covered by the dielectric film IL3, and the crystallization annealing treatment is performed on the material layer MT. Therefore, during the crystallization annealing treatment, silicon (Si) and carbon (C) in the material layer MT diffuse toward the interface between the material layer MT and the dielectric film IL3, separate near the upper surface of the material layer MT in the resistor element RS, and also diffuse toward the interface between the material layer MT and the dielectric film IL2, separate near the lower surface of the material layer MT in the resistor element RS. This is considered to have formed Fig.19 The concentration distribution is shown in the graph.

[0120] Unlike this embodiment, when the crystallization annealing process is performed in a state where the upper surface of the material layer MT is not covered by the dielectric film, Fig.19 The concentration distribution shown in the graph of is not formed. This is because, during the crystallization annealing process, silicon (Si) and carbon (C) in the material layer MT diffuse toward the interface between the material layer MT and the dielectric film IL2, but hardly diffuse toward the upper surface of the material layer MT, and silicon (Si) and carbon (C) are not separated near the upper surface of the material layer MT in the resistor element RS.

[0121] In the present embodiment, the upper surface of the material layer MT is covered with the dielectric film IL3 and a crystallization annealing process is performed. During the crystallization annealing process, silicon (Si) and carbon (C) in the material layer MT may diffuse toward the interface between the material layer MT and the dielectric film IL3, and may also diffuse toward the interface between the material layer MT and the dielectric film IL2. As a result, silicon (Si) and carbon (C) are separated near the upper surface and near the lower surface of the material layer MT, forming a structure such as Fig.19 The concentration distribution is shown in the graph.

[0122] In the present embodiment, as described above, the concentration of silicon (Si) in the resistor element RS (material layer MT) increases from the central portion of the resistor element RS toward the upper surface of the resistor element RS. In addition, the concentration of silicon (Si) in the resistor element RS (material layer MT) increases from the central portion of the resistor element RS toward the lower surface of the resistor element RS. The Si / Cr ratio in the central portion of the resistor element RS is low, and the Si / Cr ratios near the upper surface and near the lower surface of the resistor element RS are high compared to the central portion of the resistor element RS. Therefore, the absolute value of the temperature coefficient of resistance of the resistor element RS can be suppressed due to the following two reasons.

[0123] The first reason is explained. In the resistor element RS, the Si / Cr ratio increases near the upper surface and the lower surface of the resistor element RS, resulting in a higher resistivity near the upper surface and the lower surface of the resistor element RS, making it difficult for current to flow. As a result, the current flowing through the conduction path (YG1) inside the resistor element RS increases, and the current flowing through the conduction path (YG2) of the dielectric film IL3 and the conduction path (YG3) of the dielectric film IL2 decrease. Therefore, the proportion of the resistance value of the conduction path (YG2, YG3) through the dielectric film IL2 or IL3 to the total resistance value of the resistor element RS can be reduced. As described above, in the conduction path (YG2) through the dielectric film IL3 and the conduction path (YG3) through the dielectric film IL2, the temperature coefficient of resistance becomes negative, and the absolute value of the temperature coefficient of resistance increases. In this embodiment, since the ratio of the resistance value of the conduction path ( YG2 , YG3 ) through the dielectric film IL2 or IL3 to the total resistance value of the resistor element RS can be reduced, the absolute value of the resistance temperature coefficient of the resistor element RS can be suppressed.

[0124] The second reason is explained. In the central portion of the resistor element RS, the resistivity decreases due to the low Si / Cr ratio, so the current passing through the central portion of the resistor element RS increases. Fig.14 It can be seen from the graph that when the Si / Cr ratio increases, the absolute value of the resistance temperature coefficient of the Si-Cr-C resistor element tends to increase. In the present embodiment, by increasing the current flowing through the central portion of the resistor element RS and reducing the Si / Cr ratio in the central portion, the absolute value of the resistance temperature coefficient of the resistor element RS can be suppressed.

[0125] As reference Fig.16 and Fig.17 As explained, when the thickness of the Si—Cr—C resistor element RS101 becomes smaller, the influence of the conduction path ( YG2 , YG3 ) through the dielectric film IL2 or IL3 becomes larger, and as a result, the absolute value of the temperature coefficient of resistance increases.

[0126] In the present embodiment, even if the thickness of the resistor element RS is reduced, the absolute value of the resistance temperature coefficient of the resistor element RS can be suppressed due to the first and second reasons mentioned above. Therefore, in the present embodiment, the thickness of the resistor element RS can be reduced while suppressing the absolute value of the resistance temperature coefficient of the resistor element RS. By reducing the thickness of the resistor element RS, the plane dimension of the resistor element RS can be reduced while increasing the resistance value of the resistor element RS, thereby realizing the miniaturization of the semiconductor device including the resistor element RS. By suppressing the absolute value of the resistance temperature coefficient of the resistor element RS, the resistance value of the resistor element RS can be suppressed from changing due to temperature changes, thereby improving the performance of the semiconductor device including the resistor element RS.

[0127] Therefore, the present embodiment is very effective when applied to a case where the thickness of the resistor element RS is reduced. Specifically, the present embodiment is very effective when applied to a case where the thickness of the resistor element RS is less than 10 nm.

[0128] Fig.21 is a graph showing the correlation between the crystallization annealing temperature and the temperature coefficient of resistance (TCR) of the resistor element RS. Fig.21 The horizontal axis of the middle graph corresponds to the crystallization annealing temperature of the resistor element RS (material layer MT). Fig.21 The vertical axis of the graph corresponds to the temperature coefficient of resistance (TCR) of the resistor element RS. Fig.21 The graph in shows a case where the thickness of the resistor element RS is 300 nm and a case where the thickness of the resistor element RS is 5.5 nm.

[0129] from Fig.21 It can be seen from the graph in that when the thickness of the resistor element RS is 5.5 nm, the absolute value of the temperature coefficient of resistance (TCR) can be suppressed compared to when it is 300 nm. Fig.21 It can be seen from the graph in that when the thickness of the resistor element RS is 5.5 nm, if the crystallization annealing temperature is lower than 500 degrees Celsius, the absolute value of the temperature coefficient of resistance (TCR) of the resistor element RS can be sufficiently suppressed.

[0130] Therefore, in the present embodiment, it is preferred to set the thickness of the resistor element RS to less than 10 nm, and set the crystallization annealing temperature of the resistor element RS (material layer MT) to less than 500 degrees C. It is more preferred to set the crystallization annealing temperature to be higher than 300 degrees C and lower than 500 degrees C. This can further suppress the absolute value of the temperature coefficient of resistance of the resistor element RS.

[0131] Furthermore, by setting the crystallization annealing temperature to be lower than 500 degrees Celsius, it is possible to suppress or prevent the crystallization annealing from affecting the plurality of wirings M1 or semiconductor elements formed on the semiconductor substrate SB. Therefore, the reliability of the semiconductor device can be improved.

[0132] It is also preferred that the ratio of silicon (Si) to chromium (Cr) (Si / Cr ratio) in the resistor element RS is greater than 2 and the carbon (C) content in the resistor element RS is higher than 15 atomic percent and lower than 30 atomic percent. By satisfying such contents, a good balance can be obtained between the absolute value of the resistivity and the temperature coefficient of resistance of the resistor element RS when the crystallization annealing treatment is performed.

[0133] Fig. 22 is a plan view of the resistor element RS. Fig.23 is a cross-sectional view of the resistor element RS. Fig. 22 The cross-sectional view along line A1-A1 corresponds to Fig.23 . Fig. 22 The X direction and Y direction shown are orthogonal to each other. Fig. 22 The X direction and the Y direction shown are substantially parallel to the main surface of the semiconductor substrate SB. The X direction is the long side direction of the resistor element RS, and the Y direction is the short side direction of the resistor element RS.

[0134] like Fig. 22 As shown, the resistor element RS has a length L1 and a width W1. The length L1 is the dimension of the resistor element RS in the X direction. The width W1 is the dimension of the resistor element RS in the Y direction. In the resistor element RS, the current flows in the X direction.

[0135] like Fig.23 As schematically shown, the resistor element RS has a low resistance region RG1 and a high resistance region RG2. The resistivity of the high resistance region RG2 is higher than the resistivity of the low resistance region RG1.

[0136] like Fig.23 As shown, in a cross-sectional view orthogonal to the X direction, the low resistance region RG1 is surrounded by the high resistance region RG2. In the resistor element RS, the high resistance region RG2 is formed by the region adjacent to the upper surface of the resistor element RS, the region adjacent to the lower surface of the resistor element RS, and the region adjacent to the side surface of the resistor element RS. In other words, in the resistor element RS, the high resistance region RG2 is configured by the region near the upper surface of the resistor element RS, the region near the lower surface of the resistor element RS, and the region near the side surface of the resistor element RS. The central portion of the resistor element RS is included in the low resistance region RG1.

[0137] Compared with the low resistance region RG1, in the high resistance region RG2, the silicon (Si) concentration is high, the carbon (C) concentration is high, and the chromium (Cr) concentration is low. That is, compared with the central portion of the resistor element RS, in the region near the upper surface of the resistor element RS, in the region near the lower surface of the resistor element RS, and in the region near the side surface of the resistor element RS in the resistor element RS, the silicon (Si) concentration is high, the carbon (C) concentration is high, and the chromium (Cr) concentration is low. This is because the resistor element RS has a Fig.19 It can be seen that the Si / Cr ratio in the high resistance region RG2 is greater than that in the low resistance region RG1, and thus the resistivity of the high resistance region RG2 is greater than that of the low resistance region RG1.

[0138] In the present embodiment, after the material layer MTa is patterned to form the material layer MT, a dielectric film IL3 is formed to cover the material layer MT, and then a crystallization annealing process is performed. Therefore, the lower surface of the material layer MT is covered by the dielectric film IL2, and the upper surface and the side surface of the material layer MT are covered by the dielectric film IL3, and the crystallization annealing process is performed on the material layer MT. Therefore, during the crystallization annealing process, the silicon (Si) and the carbon (C) in the material layer MT diffuse toward the upper surface of the material layer MT, forming a high resistance region RG2 in a region adjacent to the upper surface of the resistor element RS. In addition, during the crystallization annealing process, the silicon (Si) and the carbon (C) in the material layer MT diffuse toward the lower surface of the material layer MT, forming a high resistance region RG2 in a region adjacent to the lower surface of the resistor element RS. During the crystallization annealing process, the silicon (Si) and the carbon (C) in the material layer MT diffuse toward the side surface of the material layer MT, forming a high resistance region RG2 in a region adjacent to the side surface of the resistor element RS. As a result, a structure such as the following is formed. Fig.23 The cross-sectional structure is shown.

[0139] By forming the low resistance region RG1 and the high resistance region RG2 in the resistor element RS, the absolute value of the temperature coefficient of resistance of the resistor element RS can be suppressed due to the first reason and the second reason.

[0140] Not only the high resistance region RG2 adjacent to the upper surface of the resistor element RS and the high resistance region RG2 adjacent to the lower surface of the resistor element RS, but also the high resistance region RG2 adjacent to the side surface of the resistor element RS also contributes to the effect of suppressing the absolute value of the resistance temperature coefficient of the resistor element RS. As the width W1 of the resistor element RS decreases, the effect of forming the low resistance region RG1 and the high resistance region RG2 in the resistor element RS increases. This is because even if the width W1 of the resistor element RS is reduced, the size of the high resistance region RG2 adjacent to the side surface of the resistor element RS does not change.

[0141] Fig.24 is a graph showing the correlation between the width W1 of the resistor element RS and the resistance value of the resistor element RS. Fig.25 is a graph showing the correlation between the width W1 of the resistor element RS and the temperature coefficient of resistance of the resistor element RS. Fig.24 and Fig.25 The horizontal axis of each graph in corresponds to the width W1 of the resistor element RS. Fig.24 The vertical axis of the graph corresponds to the resistance value of the resistor element RS. Fig.25 The vertical axis of the graph corresponds to the temperature coefficient of resistance of the resistor element RS. Fig.24 and Fig.25 Each of the graphs in is based on simulation analysis.

[0142] from Fig.24 It can be seen from the curve graph in that the smaller the width W1 of the resistor element RS is, the greater the resistance value of the resistor element RS is. Fig.25 It can be seen from the graph in that the smaller the width W1 of the resistor element RS, the higher the resistance temperature coefficient of the resistor element RS, and the smaller the absolute value of the resistance temperature coefficient of the resistor element RS.

[0143] Therefore, the smaller the width W1 of the resistor element RS is, the greater the effect of the present embodiment is. Specifically, when the width W1 of the resistor element RS is less than 40nm, the effect of the present embodiment is significant, and when the width W1 of the resistor element RS is less than 10nm, the effect of the present embodiment is even greater.

[0144] When the width W1 of the resistor element RS is greater than 10 nm and less than 40 nm, when the width W1 of the resistor element RS changes, changes in the resistance value of the resistor element RS and changes in the resistance temperature coefficient of the resistor element RS are small, making the design of the resistor element RS easy.

[0145] When the width W1 of the resistor element RS is less than 10 nm, an increase in the resistance value of the resistor element RS and a decrease in the absolute value of the temperature coefficient of resistance of the resistor element RS can be increased.

[0146] Modified Example

[0147] Fig.26 is a plan view of the resistor element RS of a modified example. Fig. 27 yes Fig.26 0 is a cross-sectional view of the resistor element RS along line A2-A2 of the modified example. Fig.28 yes Fig.26 0 is a cross-sectional view of the resistor element RS along line A3-A3 of the modified example.

[0148] Fig.26 The resistor element RS of the modified example shown is Fig. 22 The resistor element RS shown is different in that the resistor element RS has a slit SL.

[0149] The number of slits SL formed in the resistor element RS may be one or more, but it is preferable to have a plurality of slits. Fig.26 In the case of , each slit SL extends in the X direction. Fig.28 As can be seen in FIG. 1 , the slit SL of the resistor element RS is formed to penetrate from the upper surface to the lower surface of the resistor element RS. In other words, the slit SL of the resistor element RS is formed to expose the dielectric film IL1. A through hole penetrating the resistor element RS may also be used as the slit SL.

[0150] like Fig. 27 and Fig.28 As shown, in a cross-sectional view orthogonal to the X direction, the low resistance region RG1 is surrounded by the high resistance region RG2. In the resistor element RS, the high resistance region RG2 is formed by a region adjacent to the upper surface of the resistor element RS, a region adjacent to the lower surface of the resistor element RS, a region adjacent to the side surface of the resistor element RS, and a region adjacent to the inner wall of the slit SL. In other words, in the resistor element RS, the high resistance region RG2 is formed by a region near the upper surface of the resistor element RS, a region near the lower surface of the resistor element RS, a region near the side surface of the resistor element RS, and a region near the inner wall of the slit SL. Compared with the low resistance region RG1, the silicon (Si) concentration in the high resistance region RG2 is high, the carbon (C) concentration is high, and the chromium (Cr) concentration is low.

[0151] The silicon concentration of the portion of the resistor element RS in contact with the slit SL is higher than the silicon concentration of the portion of the resistor element RS away from the slit SL, the upper surface of the resistor element RS, the side surface of the resistor element RS, and the lower surface of the resistor element RS. In addition, the carbon concentration of the portion of the resistor element RS in contact with the slit SL is higher than the carbon concentration of the portion of the resistor element RS away from the slit SL, the upper surface of the resistor element RS, the side surface of the resistor element RS, and the lower surface of the resistor element RS. In addition, the chromium concentration of the portion of the resistor element RS in contact with the slit SL is lower than the chromium concentration of the portion of the resistor element RS away from the slit SL, the upper surface of the resistor element RS, the side surface of the resistor element RS, and the lower surface of the resistor element RS.

[0152] Not only the high resistance region RG2 adjacent to the upper surface of the resistor element RS, the high resistance region RG2 adjacent to the lower surface of the resistor element RS, and the high resistance region RG2 adjacent to the side surface of the resistor element RS, but also the high resistance region RG2 adjacent to the inner wall of the slit SL contributes to the effect of suppressing the absolute value of the resistance temperature coefficient of the resistor element RS. Fig. 22 and Fig.23 The resistor element RS shown is compared to Fig.26 , Fig. 27 and Fig.28 The resistor element RS of the modified example shown can further increase the effect of suppressing the absolute value of the temperature coefficient of resistance of the resistor element RS.

[0153] Second embodiment

[0154] The manufacturing steps of the semiconductor device of the present second embodiment will be described with reference to the drawings. Figure 29 to Figure 33 is a cross-sectional view of a main portion during a manufacturing step of the semiconductor device of the present Second Embodiment.

[0155] In the second embodiment, similar to the first embodiment, Figures 2 to 8 The steps are executed.

[0156] After forming the material layer MTa in the same manner as in the first embodiment, in the second embodiment, as Fig.29 As shown, the dielectric film HM is formed on the material layer MTa.

[0157] The dielectric film HM is a dielectric film used as a hard mask. The dielectric film HM may be formed of a material such as a silicon oxide thin film and formed using a method such as a CVD method.

[0158] Next, if Fig.30 As shown, a photoresist pattern PR is formed on the dielectric film HM using a photolithography technique.

[0159] Next, if Fig.31 As shown, the dielectric film HM is etched using the photoresist pattern PR as an etching mask. This results in patterning of the dielectric film HM.

[0160] Next, if Fig.31 As shown, the material layer MTa is etched using the photoresist pattern PR and the dielectric film HM as an etching mask. This results in patterning of the material layer MTa to form the material layer MT. The material layer MT is formed by the patterned material layer MTa. Subsequently, the photoresist pattern PR is removed by ashing or the like. A dielectric film HM having the same planar shape as the material layer MT is disposed on the upper surface of the material layer MT. The upper surface of the material layer MT is in contact with the dielectric film HM.

[0161] Alternatively, after etching the dielectric film HM using the photoresist pattern PR as an etching mask, the photoresist pattern PR may be removed, and then the material layer MTa may be etched using the dielectric film HM as an etching mask.

[0162] Next, if Fig.32 As shown, the dielectric film IL3 is formed on the dielectric film IL2 so as to cover the laminated film MT formed of the material layer MT and the dielectric film HM on the material layer MT. The dielectric film IL3 is formed so that the side surface of the material layer MT, the upper surface of the dielectric film HM, and the side surface of the dielectric film HM are in contact. After the dielectric film IL3 is formed, the upper surface of the dielectric film IL3 may be planarized using a method such as a CMP method.

[0163] Next, in the second embodiment, similar to the first embodiment, Fig.33 As shown, a plurality of openings OP2 penetrating the dielectric films IL3 and IL2 are formed. Next, similar to the first embodiment, as shown in FIG. Fig.33 As shown, a plurality of plugs V2 are formed. Next, similar to the first embodiment, as shown in FIG. Fig.33 As shown, a plurality of wirings M2 are formed.

[0164] Illustration and explanation of the steps of forming an upper dielectric film and wiring are omitted.

[0165] In the first embodiment, the crystallization annealing treatment for the material layer MT is performed after the dielectric film IL3 is formed. As a result, since the crystallization annealing treatment is performed using the dielectric film IL3 provided on the material layer MT, as shown in FIG. Fig.19 A graph showing the concentration distribution is formed.

[0166] In the second embodiment, the crystallization annealing process is performed after the dielectric film HM is formed. As a result, since the crystallization annealing process is performed using the material layer MTa or the dielectric film HM provided on the material layer MT, as shown in FIG. Fig.19 A graph showing the concentration distribution is formed.

[0167] In the second embodiment, the crystallization annealing treatment may be performed at any time explained below.

[0168] In the second embodiment, the crystallization annealing process may be performed after the dielectric film IL3 is formed. The crystallization annealing process crystallizes a part or all of the amorphous material layer MT. Since the crystallization annealing process is performed using the upper surface of the material layer MT covered by the dielectric film HM and the side surface of the material layer MT covered by the dielectric film IL3, as shown in FIG. Fig.19 A concentration distribution as shown in the graph is formed. In addition, it is possible to obtain Fig.23 The cross-sectional structure is shown.

[0169] Alternatively, in the second embodiment, the crystallization annealing treatment may be performed after patterning the material layer MTa to form the material layer MT and before forming the dielectric film IL3. Through this crystallization annealing treatment, a part or all of the amorphous material layer MT is crystallized. Since the crystallization annealing treatment is performed using the upper surface of the material layer MT covered by the dielectric film HM, as shown in FIG. Fig.19 A concentration distribution as shown in the graph is formed. In addition, it is possible to obtain Fig.23 The cross-sectional structure is shown.

[0170] Alternatively, in the second embodiment, the crystallization annealing process may be performed after forming the dielectric film HM and before forming the photoresist pattern PR. Through this crystallization annealing process, a part or all of the amorphous material layer MTa is crystallized. Since the crystallization annealing process is performed using the upper surface of the material layer MTa covered by the dielectric film HM, as shown in FIG. Fig.19 A concentration distribution as shown in the graph is formed. In addition, it is possible to obtain Fig.34 The cross-sectional structure is shown.

[0171] Fig.34 is a cross-sectional view of the resistor element RS, showing the Fig.23 If the crystallization annealing treatment is performed before patterning the material layer MTa, then Fig.34 As shown, the high resistance region RG2 is not formed in the region (material layer MT) adjacent to the side surface of the resistor element RS.

[0172] When the high resistance region RG2 is formed in the region adjacent to the side surface of the resistor element RS, the effect of suppressing the absolute value of the resistance temperature coefficient of the resistor element RS is greater than when the high resistance region RG2 is not formed in the region adjacent to the side surface of the resistor element RS. Fig.34 Compared with the cross-sectional structure, Fig.23 When the cross-sectional structure is formed, the effect of suppressing the absolute value of the temperature coefficient of resistance of the resistor element RS is greater.

[0173] Third embodiment

[0174] According to the research of the present inventors, it was found that carbon (C) adheres to the upper surface of the dielectric film IL2 before forming the material layer MTa, and the carbon changes the resistance temperature coefficient of the resistor element RS. The carbon adhered to the upper surface of the dielectric film IL2 is believed to come from organic matter present in various manufacturing equipment or transportation equipment. When the material layer MTa is formed on the dielectric film IL2 with the carbon (C) adhered to the upper surface of the dielectric film IL2, the carbon (C) adhered to the upper surface of the dielectric film IL2 diffuses into the material layer MTa or the material layer MT during the crystallization annealing. Since the amount of carbon (C) adhered to the upper surface of the dielectric film IL2 and the amount of carbon (C) diffused into the material layer MTa or the material layer MT during the crystallization annealing are different, the carbon (C) content of the resistor element RS is also different. Therefore, the resistance temperature coefficient of the resistor element RS is unstable and changes.

[0175] Therefore, in the present embodiment, after forming a plurality of plugs V1 and before forming the material layer MTa, a cleaning process is performed on the upper surface of the dielectric film IL2. Through this cleaning process, the carbon adhering to the upper surface of the dielectric film IL2 can be removed. Therefore, the carbon (C) content of the resistor element RS can be suppressed or prevented from changing. This can suppress the change of the resistance temperature coefficient of the resistor element RS. Therefore, the reliability of the semiconductor device including the resistor element RS can be improved.

[0176] Plasma cleaning treatment is preferable as the cleaning treatment. For example, after plasma treatment is performed using argon (Ar) plasma on the upper surface of the dielectric film IL2, the material layer MTa is formed on the dielectric film IL2.

[0177] It is preferable to continuously perform the plasma cleaning process and the film forming step of the material layer MTa without exposing the semiconductor substrate SB to the atmosphere. That is, the semiconductor substrate SB is loaded into the chamber of the plasma equipment, and after the plasma cleaning process is performed on the upper surface of the dielectric film IL2, the semiconductor substrate SB is unloaded from the chamber of the plasma equipment. Then, the semiconductor substrate SB that has been unloaded from the chamber of the plasma equipment is loaded into the chamber of the film forming equipment without being exposed to the atmosphere, and the material layer MTa is formed on the dielectric film IL2. This can prevent carbon (C) from re-adhering to the upper surface of the dielectric film IL2 after the plasma cleaning process and before the film forming step of the material layer MTa.

[0178] Fig.35 is a graph showing the carbon (C) content and the temperature coefficient of resistance of the resistor element RS. Fig.35 The horizontal axis of the graph corresponds to the carbon (C) content of the resistor element RS, and Fig.35 The vertical axis of the graph corresponds to the temperature coefficient of resistance of the resistor element RS. Fig.35The graph in is plotted when the plasma cleaning process is performed on the upper surface of the dielectric film IL2, the carbon (C) content of the resistor element RS and the temperature coefficient of resistance measurement results, and when the cleaning process is not performed on the upper surface of the dielectric film IL2, the carbon (C) content of the resistor element RS and the temperature coefficient of resistance measurement results. When the plasma cleaning process is performed on the upper surface of the dielectric film IL2, the number of samples is 4. In addition, when the cleaning process is not performed on the upper surface of the dielectric film IL2, the number of samples is 4.

[0179] from Fig.35 As can be seen from the graph in , when the cleaning process is not performed on the upper surface of the dielectric film IL2, the carbon (C) content and the resistance temperature coefficient of the resistor element RS fluctuate. It is believed that during the crystallization annealing, the carbon (C) adhered to the upper surface of the dielectric film IL2 diffuses into the material layer MTa or the material layer MTa, causing the carbon (C) content of the resistor element RS to fluctuate, and therefore, the resistance temperature coefficient of the resistor element RS fluctuates.

[0180] On the other hand, when the plasma cleaning process is performed on the upper surface of the dielectric film IL2, as shown in FIG. Fig.35 As can be seen from the graph in , fluctuations in the carbon (C) content and the temperature coefficient of resistance of the resistor element RS are suppressed.

[0181] As a cleaning process for the upper surface of the dielectric film IL2, a wet cleaning process may be performed instead of a plasma cleaning process. In the wet cleaning process, a chemical solution is used to effectively remove the carbon adhering to the upper surface of the dielectric film IL2. Specifically, SPM (sulfuric acid-hydrogen peroxide mixture), APM (ammonia-hydrogen peroxide mixture) or ozone water may be used for the wet cleaning process. After the carbon (C) adhering to the upper surface of the dielectric film IL2 is removed by the wet cleaning process, by forming a material layer MTa on the dielectric film IL2, the fluctuation of the carbon (C) content and the resistance temperature coefficient of the resistor element RS can be suppressed. In addition, by properly managing the time from the wet cleaning process to the formation of the material layer MTa, the re-adhesion of carbon (C) to the upper surface of the dielectric film IL2 can be suppressed.

[0182] However, when the plasma cleaning treatment is used as the cleaning treatment for the upper surface of the dielectric film IL2, after the plasma cleaning treatment, the film formation step of the material layer MTa can be continuously performed without exposing the semiconductor substrate SB to the atmosphere. Therefore, after the cleaning treatment and before the film formation step of the material layer MTa, carbon (C) can be prevented from re-adhering to the upper surface of the dielectric film IL2.

[0183] The present invention made by the present inventors has been described in detail above based on the embodiments, but the present invention is not limited to the above-described embodiments, and it is apparent that various modifications can be made without departing from the gist thereof.

Claims

1. A semiconductor device, comprising: a first dielectric film; a resistor element disposed on the first dielectric film, the resistor element comprising silicon, chromium, and carbon; as well as a second dielectric film disposed on the resistor element so as to be in contact with the resistor element, wherein a silicon concentration of the resistor element increases from a central portion of the resistor element toward an upper surface of the resistor element, and increases from the central portion of the resistor element toward a lower surface of the resistor element.

2. The semiconductor device according to claim 1, wherein the chromium concentration of the resistor element decreases from the central portion of the resistor element toward the upper surface of the resistor element, and decreases from the central portion of the resistor element toward the lower surface of the resistor element.

3. The semiconductor device according to claim 2, wherein the carbon concentration of the resistor element increases from the central portion of the resistor element toward the upper surface of the resistor element, and increases from the central portion of the resistor element toward the lower surface of the resistor element.

4. The semiconductor device according to claim 1, The thickness of the resistor element is less than 10 nm.

5. The semiconductor device according to claim 4, wherein the ratio of silicon to chromium is greater than 2, and The carbon content in the resistor element is higher than 15 atomic percent and lower than 30 atomic percent.

6. The semiconductor device according to claim 4, The width of the resistor element is greater than 10 nm and less than 40 nm.

7. The semiconductor device according to claim 4, The width of the resistor element is less than 10 nm.

8. The semiconductor device according to claim 7, wherein each of the upper surface and the lower surface of the resistor element has a plurality of protrusions.

9. The semiconductor device according to claim 1, wherein in the resistor element, a silicon concentration in a region close to a side surface of the resistor element is higher than a silicon concentration in the central portion of the resistor element.

10. The semiconductor device according to claim 9, wherein in the resistor element, a chromium concentration in the region close to the side surface of the resistor element is lower than a chromium concentration in the central portion of the resistor element, and wherein in the resistor element, a carbon concentration in the region close to the side surface of the resistor element is higher than a carbon concentration in the central portion of the resistor element.

11. The semiconductor device according to claim 1, comprising: a first wiring arranged to be covered by the first dielectric film; a second wiring arranged to be covered by the first dielectric film; a first plug provided in the first dielectric film and connected to the first wiring; as well as a second plug provided in the first dielectric film and connected to the second wiring, The resistor element connects the first plug and the second plug.

12. A method for manufacturing a semiconductor device, comprising: (a) forming a first dielectric film; (b) forming a resistor element on the first dielectric film, the resistor element comprising silicon, chromium and carbon; (c) forming a second dielectric film on the first dielectric film so as to cover the resistor element and contact the resistor element; as well as (d) after (c), performing an annealing process on the resistor element in a state where the second dielectric film is provided on the resistor element, Wherein after (d), the silicon concentration of the resistor element increases from a central portion of the resistor element toward an upper surface of the resistor element, and increases from the central portion of the resistor element toward a lower surface of the resistor element.

13. The method according to claim 12, wherein said (b) comprises: (b1) forming a first film on the first dielectric film, the first film including silicon, chromium, and carbon; as well as (b2) After the step (b1), the first film is patterned to form the resistor element.

14. The method according to claim 12, The temperature of the annealing treatment is higher than 300 degrees Celsius and lower than 500 degrees Celsius.

15. The method according to claim 12, comprising: (a1) After (a) and before (b), plasma treatment is performed on the upper surface of the first dielectric film.

16. The method according to claim 12, comprising: (a1) After (a) and before (b), the upper surface of the first dielectric film is cleaned using SPM, APM or ozone water.

17. The method according to claim 12, The thickness of the resistor element is less than 10 nm.

18. The method according to claim 12, wherein after (d), the chromium concentration of the resistor element decreases from the central portion of the resistor element toward the upper surface of the resistor element, and decreases from the central portion of the resistor element toward the lower surface of the resistor element.

19. The method according to claim 12, wherein after (d), the carbon concentration of the resistor element increases from the central portion of the resistor element toward the upper surface of the resistor element, and increases from the central portion of the resistor element toward the lower surface of the resistor element.

20. A method for manufacturing a semiconductor device, comprising: (a) forming a first dielectric film; (b) forming a first film on the first dielectric film, the first film comprising silicon, chromium, and carbon; (c) forming a second dielectric film on the first film so as to be in contact with the first film; (d) after (c), patterning the second dielectric film and the first film to form a resistor element from the patterned first film; as well as (e) after (c), in a state where the second dielectric film is provided on the first film or the resistor element, performing an annealing process on the first film or the resistor element, Wherein after (c), the silicon concentration of the resistor element increases from a central portion of the resistor element toward an upper surface of the resistor element, and increases from the central portion of the resistor element toward a lower surface of the resistor element.

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