Display pixel comprising light emitting diodes and display screen having such display pixel

Abstract

A display pixel including a light emitting diode and a display screen having such a display pixel. The present disclosure relates to a display pixel comprising at least one light emitting diode, and an electronic circuit comprising a storage circuit for storing at least one digital signal, and a driver circuit configured to: in a first mode of operation, drive the at least one digital signal in a first different time duration (TA5, TA4, TA3, TA2, TA3, TA4, TA5, TA6, TA7, TA7, TA8, TA8, TA8, TA8, TA8, TA8, TA8, TA8, TA8); in a first operating mode, the light-emitting diodes are turned on or off in accordance with the logic state of the bits of the digital signal during a first duration (TB5, TB4, TB3, TB2, TB1), or in a second operating mode, the light-emitting diodes are turned on or off in accordance with the logic state of the bits of the digital signal during a second different duration (TB5, TB4, TB3, TB2, TB1), which is at least partially different from the first duration. Therefore, the light emitting diode is driven through pulse width modulation.

Description

[0001] This application claims the benefit of priority to French patent application No. 22 / 06567, filed on June 29, 2022, entitled “Display pixel comprising light-emitting diodes and display screen having such display pixels,” which is hereby incorporated by reference to the maximum extent permitted by law. Technical Field

[0002] The present disclosure relates to display pixels including light emitting diodes and display screens having such display pixels. Background Art

[0003] A pixel of an image corresponds to a unit element of an image displayed by a display screen. For the display of a color image, the display screen typically comprises at least three elements (also referred to as display sub-pixels) for each pixel of the displayed image, each of which emits light radiation, referred to as an image pixel color element, of essentially a single color (e.g. red, green and blue). The superposition of the image pixel color elements emitted by the three display sub-pixels provides the observer with a colored sensation corresponding to the pixel of the displayed image. In this case, an assembly formed by three display sub-pixels used for displaying a pixel of an image is referred to as a display pixel of the display screen. Each display sub-pixel may comprise a light source, in particular a light emitting diode.

[0004] The display pixels may be arranged in an array, with each display pixel located at the intersection of a row (also referred to as a line) and a column of the array. Electrodes are provided along the rows and columns to connect each display pixel to a control circuit. Typically, each row of display pixels is sequentially selected by signals transmitted along the row electrodes, and the display pixels of the selected row are programmed to display the desired image pixels by signals transmitted along the column electrodes.

[0005] The human eye is much more sensitive to changes in dark tones than to similar changes in light tones. Photodetectors typically provide analog electrical image pixel signals that have a substantially linear relationship to the number of photons striking the sensor. If the display system is operated using a digital drive method such as pulse width modulation operation, a large number of bits are required for the digital image pixel signal to describe the dark tones with sufficient accuracy. Digitization using a low number of bits can result in posterization of the displayed image in dark tones.

[0006] In order to optimize the use of bits when encoding an image and / or to optimize the bandwidth used to transmit the image, a nonlinear operation (commonly referred to as gamma encoding or gamma compression) is applied to the image pixel signals provided by the photodetector to redistribute the native image sensor tonal levels to tonal levels that are more uniform to the human eye. Gamma encoding is defined, for example, by the following power law expression:

[0007] Vout=Vin γ

[0008] Wherein a non-negative real input value Vin is raised to a power γ to obtain an output value Vout, for example, where Vin and Vout are in the range 0-1. The exponent γ is typically equal to 1 / 2.2. To display the image pixels, an inverse nonlinear operation known as gamma decoding or gamma expansion is applied to the image pixel signal to effectively convert it back into light from the original scene.

[0009] Figure 1 An example of an ideal gamma decoding function Igam corresponding to a power law expression with exponent equal to 2.2 is shown, and in contrast, it is a linear function Lin. Figure 1 In , the y-axis indicates the number of levels of the output and the number of levels of brightness L of the image pixels is indicated on the x-axis. In order for the tones to appear smooth and continuous in the image, it is usually sufficient to be able to encode at least 256 different levels for the brightness L, which in theory should only require 8 bits.

[0010] However, when gamma encoding and gamma decoding are used, multi-tone separation may still occur on the displayed image for very dark tones when the display system is operated with a digital drive method such as pulse width modulation operation.

[0011] Figure 2 Shows Figure 1 An enlarged view of the ideal gamma decoding function Igam and the gamma decoding function Rgam10 actually obtained by encoding on 10 bits. Figure 2 As shown, the curve Rgam10 is a step curve. This means that, for example, an image pixel with an ideal brightness L in the range 0-8 results in the display of an image pixel with a real brightness L equal to 0, or an image pixel with an ideal brightness L in the range 9-13 results in the display of an image pixel with a real brightness L of a constant value. Even when gamma encoding and gamma decoding are used, at least 16 bits of encoding should be used to correctly display dark tones. However, the increase in the number of bits of the digital image pixel signal requires a higher bandwidth interface for the video data, which is undesirable. Summary of the invention

[0012] An object of an embodiment is to provide a display pixel including a light emitting diode and a display screen including such a display pixel, which overcome all or part of the disadvantages of existing display pixels including a light emitting diode and display screens including such a display pixel.

[0013] Another object is to reduce or even suppress multi-tone separation of displayed images for dark tones.

[0014] Another goal is that the number of bits of the digital image pixel signal be kept low.

[0015] One embodiment provides a display pixel comprising at least one light emitting diode, and an electronic circuit comprising a storage circuit and a driver circuit, the storage circuit being used to store at least one digital signal, the driver circuit being configured to drive the light emitting diode by pulse width modulation by turning the light emitting diode on or off during a first different duration according to the logic state of a bit of the digital signal in a first operating mode, or by turning the light emitting diode on or off during a second different duration at least partially different from the first duration according to the logic state of a bit of the digital signal in a second operating mode.

[0016] This allows increasing the number of different durations for controlling the light emitting diodes by pulse width modulation without increasing the number of bits of the digital signal and thus without increasing the bandwidth interface for the video data.

[0017] According to an embodiment, the electronic circuit is configured to switch between the first operating mode and the second operating mode depending on the logic state of the first binary signal. This allows increasing the precision of the encoding of the pixel image only for dark tones to which the human eye is most sensitive.

[0018] According to an embodiment, the electronic circuit is configured to receive a first binary signal from outside the display pixel.The first binary signal may advantageously be determined by a control circuit of a display screen comprising the display pixel.

[0019] According to an embodiment, the digital signal comprises NB bits b i , i is in the range from 1 to NB, bit b NB is the most significant bit, and bit b1 is the least significant bit, the first duration includes NB first durations TA of increasing value i , the second duration includes NB second durations TB of increasing value i , the driver circuit is configured to operate in the first operation mode by a first duration TA of NB i The light emitting diode is driven by pulse width modulation by turning on or off the light emitting diode during the bit b i In the first logic state, for a first duration TAi is turned on during bit b i In a second logic state different from the first logic state, the i is turned off during the period, and the driver circuit is configured to operate in the second operation mode by operating in the second duration TB at NB i The light emitting diode is driven by pulse width modulation by turning on or off the light emitting diode during the bit b i In the first logic state, the i is turned on during bit b i In the second logic state, the i Closed during the period.

[0020] According to an embodiment, wherein at least some of the second durations are lower than the first durations. According to an embodiment, at least one of the second durations lasts as long as one of the first durations. According to an embodiment, at least the longest second duration lasts as long as one of the first durations.

[0021] According to an embodiment, the display pixel comprises at least a first conductive pad, which is intended to receive a second binary signal comprising pulses, and is connected to the electronic circuit, some of the pulses being away from the first duration and some of the pulses being away from the second duration, the electronic circuit being configured to switch the light emitting diode on or off during the first duration or the second duration based on the pulses. The electronic circuit of each display pixel can advantageously generate a pulse width modulation control signal based on the pulses in the first operating mode and in the second operating mode. According to an embodiment, the pulses comprise a first pulse and further comprise a second pulse, the first pulse being away from the first duration, each first pulse being followed by a second pulse, the first pulse and the subsequent second pulse being away from the second duration. The duration of a period in the pulse width modulation control in the first operating mode or the second operating mode is advantageously not increased relative to the pulse width modulation control in the single operating mode.

[0022] According to an embodiment, the electronic circuit is configured to generate a third binary signal from the second binary signal, whose logic state is modified at each first pulse and each second pulse.The third binary signal may thus be set at logic level "1" during the second duration.

[0023] According to an embodiment, the storage circuit comprises a shift register having the digital signal stored therein and configured to provide consecutive bits of the stored digital signal clocked by a third binary signal.

[0024] According to an embodiment, the display pixel comprises a controllable current source supplying the light emitting diode and controlled by a fourth binary signal.

[0025] According to an embodiment, the electronic circuit comprises a first logic gate of the NOR type having a first input receiving the third binary signal and having a second input receiving the first binary signal and a second logic gate of the NOR type having a first input receiving the third binary signal. i The first input of the logic complement of the first logic gate has a second input connected to the output of the first logic gate and provides a fourth binary signal.

[0026] According to an embodiment, the display pixel comprises at least a second electrically conductive pad intended to receive a fifth binary signal and connected to said electronic circuit, said electronic circuit being configured to update said stored digital signal in the storage circuit depending on the second signal.

[0027] Another embodiment provides a display screen, comprising:

[0028] - display pixels arranged in rows and columns as previously disclosed;

[0029] - first conductive tracks extending along the rows and connected to the electronic circuitry of the display pixels;

[0030] - second conductive tracks extending along the columns and connected to the electronic circuitry of the display pixels; and

[0031] - A control circuit connected to the first conductive track and the second conductive track.

[0032] According to an embodiment, the electronic circuit of each display pixel is configured to switch between a first operation mode and a second operation mode depending on a logic state of the first binary signal. The control circuit is configured to determine a first binary signal for each digital signal and provide the first binary signal to the display pixel.

[0033] According to an embodiment, the control circuit is configured to provide a timing signal on each first conductive track, and the electronic circuit of each display pixel is configured to generate a drive signal according to the timing signal to drive the light emitting diode by pulse width modulation by switching the light emitting diode on or off during a first different duration in a first operating mode or by switching the light emitting diode on or off during a second different duration in a second operating mode. The generation of the first duration and the second duration is performed by each display pixel from the timing signal. The structure of the electronic circuit can advantageously be simple.

[0034] According to an embodiment, the control circuit is configured to provide a timing signal equal to a second binary signal on each first conductive track, the second binary signal comprising at least a first pulse and a second pulse, the first pulse being spaced apart from the first duration, each first pulse being followed by a second pulse, the first pulse and the subsequent second pulse being spaced apart from the second pulse duration. A single timing signal is advantageously used by the display pixel to obtain the first duration and the second duration. This allows advantageously reducing the number of conductive pads of the display pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The foregoing features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0036] Already public Figure 1 An example of an ideal gamma decoding function is shown;

[0037] Already public Figure 2 Shows Figure 1 An enlarged view of the ideal gamma decoding function and the real gamma decoding function with 10-bit encoding;

[0038] Figure 3 An embodiment of a display screen is partially and schematically shown;

[0039] Figure 4 Shows Figure 3 A block diagram of an embodiment of a display pixel of a display screen;

[0040] Figure 5 According to the known pulse width modulation method, Figure 4 A timing diagram of a signal used by a display pixel to control a light emitting diode;

[0041] Figure 6 An embodiment of a pulse width modulation method is shown. Figure 4 A timing diagram of a signal used by a display pixel to control a light emitting diode;

[0042] Figure 7 Shows Figure 4 A block diagram of an embodiment of a portion of a display pixel;

[0043] Figure 8 Shows Figure 7 A block diagram of a portion of a circuit;

[0044] Fig. 9 Shows Figure 1 and a magnified view of an ideal gamma decoding function of and a real gamma decoding function with 9-bit encoding using a known method of displaying an image;

[0045] Fig.10Shows Figure 1 An enlarged view of an ideal gamma decoding function and a real gamma decoding function obtained using an embodiment of a method for displaying an image;

[0046] Fig.11 is a very simplified cross-sectional view of a display pixel; and

[0047] Fig.12 yes Fig.11 Bottom view of the display pixel. DETAILED DESCRIPTION

[0048] Similar features have been designated by similar reference numerals in the various drawings. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be provided with the same structure, size, and material properties. For clarity, only steps and elements useful for understanding the embodiments described herein are illustrated and described in detail.

[0049] Unless otherwise stated, when referring to two elements connected together, this means a direct connection without any intermediate element except a conductor, and when referring to two elements coupled together, this means that the two elements can be connected or they can be coupled via one or more other elements. In addition, the signal alternating between a first constant state (e.g., a low logic state, denoted as "0") and a second constant state (e.g., a high logic state, denoted as "1") is referred to as a "binary signal". The high and low states of different binary signals of the same electronic circuit may be different. In practice, a binary signal may correspond to a voltage or current, which may not be completely constant in a high or low state. In addition, in the following description, the source and drain of a MOS transistor are referred to as "power terminals" of an insulated gate field effect transistor or a MOS transistor.

[0050] In addition, unless otherwise stated, when referring to a voltage at a conductive pad, the difference between the potential at the conductive pad and a reference potential (eg, ground potential, taken to be equal to 0 V) ​​is considered.

[0051] Unless otherwise specified, the expressions "about", "approximately", "substantially" and "approximately" mean within 10%, and preferably within 5%. In addition, the expression "substantially constant" means that it changes less than 10% over time relative to a reference value.

[0052] In the following description, embodiments are disclosed for color display screens comprising color display pixels, each display pixel comprising a light emitting diode adapted to emit radiation of a different color. However, these embodiments are also applicable to monochrome display screens comprising monochrome display pixels, each monochrome display pixel comprising a light emitting diode or a light emitting diode adapted to emit radiation of only a single color.

[0053] Figure 3 An embodiment of a display screen 10 is partially and schematically shown. The display screen 10 includes display pixels 12 i,j , for example, which are arranged in M ​​rows and N columns, M is an integer varying from 1 to 8,000, and N is an integer varying from 1 to 16,000, i is an integer varying from 1 to M, and j is an integer varying from 1 to N. As an example, in Figure 3 In this example, M and N are equal to 6. Each display pixel has 12 i,j Via electrode 14 i is coupled to a source of low reference potential Gnd, such as ground, and via electrode 16 j is coupled to a source of high reference potential Vcc. As an example, electrode 14 i is shown along Figure 3 The rows in the electrode are aligned, and the electrode 16 j is shown along Figure 3 The columns in the display are aligned, a reverse layout is possible. The supply voltage of the display corresponds to a voltage between a high reference potential Vcc and a low reference potential Gnd. The supply voltage depends in particular on the arrangement of the light-emitting diodes and on the technology according to which the light-emitting diodes are manufactured. As an example, the supply voltage can be approximately from 4V to 5V.

[0054] For each row, the display pixels 12 in the row i,j is coupled to at least one row electrode 18 i For each column, the display pixels 12 in the column i,j is coupled to at least one column electrode 20 j Display screen 10 includes a timing circuit 22 coupled to row electrodes 18. i And suitable for each row electrode 18 i Com i Display screen 10 includes data delivery circuit 24, which is coupled to column electrodes 20 j And it is suitable for each column electrode 20 j Data signal j The timing circuit 22 and the data delivery circuit 24 are controlled by a circuit 26, which may include, for example, a microprocessor. In particular, the circuit 26 receives the data to be transmitted by the display pixel 12. i,j Display video data.

[0055] Typically, each row of display pixels is selected in turn, and the display pixels of the selected row are programmed to display the desired image pixels. In a known method for selecting display pixels, the timing circuit 22 is adapted to clock the row electrodes 18 i Com i To select display pixels 12 in sequencei,j Each row, and the data delivery circuit 24 is adapted to each column electrode 20 j Data signal j , which represents the selected display pixel 12 i,j The color digital data stored in.

[0056] Figure 4 The display pixel 12 of the display screen 10 is shown i,j For a color display, the display pixel 12 i,j It comprises at least three light emitting diodes emitting radiation of different colors, a single light emitting diode LED such as Figure 4 As shown. Each light emitting diode LED is coupled in series to a controllable current source CS, which comprises, for example, a MOS transistor. In this example, for each light emitting diode LED, the anode of the light emitting diode LED receives a high reference potential Vcc, which is applied to the display pixel 12. i,j The cathode of the light emitting diode LED is coupled to a terminal of a controllable current source CS, for example, which receives a low reference potential Gnd at the display pixel 12. i,j As a variant, the cathode of the light emitting diode LED receives the low reference potential Gnd and the anode of the light emitting diode LED is coupled to a terminal of a controllable current source CS, the other terminal of which receives the high reference potential Vcc.

[0057] Display Pixel 12 i,j A circuit 40 for driving a controllable current source CS is also included. The driver circuit 40 may include electronic components such as MOS transistors. It may be desirable to use a reduced supply voltage, less than 4V, such as approximately 1V or approximately 1.8V, to power the electronic components of the driver circuit 40, such a reduced supply voltage corresponding to, for example, a voltage that may be applied between the supply terminals of a MOS transistor. For this purpose, the display pixel 12 i,j A circuit 42 (Vdd generation) may be included for delivering from the supply voltage Vcc a reduced supply voltage Vdd which is used in particular for the power supply of the driver circuit 40. The circuit 42 comprises, for example, a voltage divider.

[0058] According to an embodiment, in each display pixel 12 i,j The timing signal Com received at the conductive pad P_Row iIt is a binary signal that alternates between a low logic state "0" corresponding to a low reference potential Gnd and a high logic state "1" corresponding to a low voltage less than the reduced power supply voltage Vdd, for example, about 1V. i,j The conductive pad P_Col receives the data signal Data j is a binary signal alternating between a low logic state "0" corresponding to a low reference potential Gnd and a high logic state "1" corresponding to a low voltage less than a reduced power supply voltage Vdd, for example about 1V.

[0059] The driver circuit 40 includes a circuit coupled to receive the data signal Data j The conductive pad P_Col is coupled to the receiving timing signal Com i The circuit 46 (mode selection) of the conductive pad P_Row is configured to receive the timing signal Com i Or data signal Data j The clock signal Clk and the data signal Data j The data signal Data is delivered to the storage circuit 48 (color data register) or the timing signal Com i The modulation timing signal PWM is delivered to the circuit 50 (LED driver) for controlling the controllable current source CS associated with each light emitting diode LED. During the display phase, the modulation timing signal PWM can be equal to the timing signal Com i During the programming phase, the clock signal Clk may be equal to the timing signal Com i .

[0060] The storage circuit 48 is configured to store the digital color signals R, G, B based on the received digital data Data when clocked by the clock signal Clk. The digital color signals R, G, B are elements representing the color of the image pixels to be displayed. Each color digital signal R, G, B includes NB bits, called bit j , where j is in the range of 1 to NB, where bit NB The circuit 50 (LED driver) is configured to control a controllable current source CS coupled to the light emitting diode LED using binary signals I_red, I_green and I_blue obtained from the digital color signals R, G, B and from the modulation timing signal PWM.

[0061] For driving display pixels 12 i,jA known method of driving a light emitting diode LED is pulse width modulation, wherein the display pixel 12 i,j Each light emitting diode LED is supplied with a current pulse having a constant intensity, the duration of the pulse being dependent on the stored digital color signal R, G, B.

[0062] Figure 5 The modulation timing signal PWM and the signals I_red_1, I_red_2, I_red_3 and I_red_4 (corresponding to the Figure 4 Display pixels 12 i,j A timing diagram of the signal I_red provided by the circuit 50 of FIG. 5 for displaying four different digital color signals R) using a known pulse width modulation drive. For this purpose, during the display phase, the timing signal PWM presents a series of pulses PA at a logic state "1", which rates the operation of the circuit 50 for controlling each light emitting diode by pulse width modulation. The number of pulses PA in the succession of pulses may be equal to NB+1.

[0063] As an example, when the current source CS corresponds to a MOS transistor, according to the logic value "0" or "1" of each bit of the color signal R, starting from the most significant bit of the color signal R, this transistor is turned on or off at the pulse rate of the modulation timing signal PWM, and this transistor is kept on or off until the next pulse of the modulation timing signal PWM. The duration TA between two consecutive pulses PA of the modulation timing signal PWM i (i is in the range from 1 to NB) divided by 2 each time, so that the total duration that the light emitting diode is in depends on the value of the digital color signal R. The succession of pulses PA of the modulation timing signal PWM can be repeated until another image pixel is displayed. In that case, the succession of pulses PA of the modulation timing signal PWM from the most significant bit of the color signal R to the least significant bit of the color signal R forms a display cycle and the display phase includes more than one display cycle.

[0064] exist Figure 5 , as an example, the number of pulses PA in a display period of the modulation timing signal PWM is equal to 8 and only one display period is shown. The signal I_red_1 is obtained for the display of an image pixel color element corresponding to the digital color signal R equal to "1010101". The signal I_red_2 is obtained for the display of an image pixel color element corresponding to the digital color signal R equal to "0101010". The signal I_red_3 is obtained for the display of an image pixel color element corresponding to the digital color signal R equal to "1111111". The signal I_red_4 is obtained for the display of an image pixel color element corresponding to the digital color signal R equal to "0000000".

[0065] According to an embodiment, the modulation timing signal PWM is modified relative to the known modulation timing signal PWM so that more than NT different durations for turning on / off the light emitting diode are available, wherein NT is an integer strictly higher than NB, preferably higher than NB+1, more preferably higher than NB+2. The display method according to this embodiment with the modified modulation timing signal PWM (providing NT different durations) and the digital color signal (comprising NB bits) is equivalent to the display method in which the known modulation timing signal PWM would provide NT different durations and the digital color signal would comprise NT bits.

[0066] Figure 6 shows the drive Figure 4 Pixel 12 i,j The timing diagram of the signals PWM, PWM2, I_red_W and I_red_B of an embodiment of the method for controlling a light emitting diode LED, wherein the light emitting diode LED is controlled by pulse width modulation. The signals I_red_W and I_red_B correspond to the Figure 4 Display pixels 12 i,j The circuit 50 provides a signal I_red for displaying two different digital color signals R. The signal PWM2 is composed of Figure 4 Display pixels 12 i,j The circuit 40 generates a signal. Figure 6 , the digital color signal R includes 5 bits, bit1 to bit5, bit5 is the most significant bit and bit1 is the least significant bit.

[0067] According to an embodiment, for one display period, the modulation timing signal PWM includes alternating first pulses and second pulses, each first pulse PA being followed by a second pulse PB. The first pulse PA corresponds to the first pulse PA previously described. Figure 5 The pulses PA of the modulation timing signal disclosed, that is to say the duration TA between two consecutive first pulses PA of the modulation timing signal PWM in the display period i (i is in the range from NB to 1) divided by two each time. The duration TB between a first pulse PA and a consecutive second pulse PB of the modulation timing signal PWM j (j is in the range from NB to 1) relative to the duration between the previous consecutive first pulse PA and the second pulse PB divided by two. The signal PWM2 includes a rising edge at each first pulse PA and a falling edge at each second pulse PB. Therefore, the pulse of the signal PWM2 has a duration TB NB To TB1.

[0068] According to an embodiment, a period comprises NB+1 first pulses PA and NB+1 second pulses PB. Thus, there is a duration TA between pairs of consecutive first pulses PA that decreases by NB. i , i is in the range from NB to 1, and there is a duration TB between pairs of consecutive first pulses PA and second pulses PB that decreases NB i , i is in the range from NB to 1.

[0069] More generally, the timing signal PWM comprises pulses, some of which are separated from the first duration TA by i , i is in the range from 1 to NB, and some of the pulses are away from the second duration TB i , i is in the range from 1 to NB. For example, it is used to determine the first duration TA i The pulse can be used to determine the second duration TB i However, the previously disclosed embodiments in which the first pulses PA and the second pulses PB alternate advantageously allow for a change in the pulse duration TA relative to the use of only the first pulse duration TA. i The duration of the display period is not increased.

[0070] According to an embodiment, in the display period, the durations TB1 to TB NB One or more but not all of the durations are equal to the duration TA NB According to an embodiment, the duration TB between the first pulse PA at the beginning of the display period and the consecutive second pulse PB is NB The duration TA between two consecutive first pulses PA that lasts until the end of the display period NB to TA1, for example, the duration between the second to last first pulse and the last first pulse of the display period, or the duration between the third to last first pulse and the second to last first pulse of the display period. NB To TA1 and TB NB There are NT durations of different values ​​in the group to TB1, where NT is strictly above NB and strictly below 2*NB.

[0071] exist Figure 6 In the embodiment, the modulation timing signal PWM includes 6 first pulses PA, which are alternately connected with 6 second pulses PB. The duration TB between the first consecutive first pulses PA and the second pulses PB from the beginning of the display period is NBlasts as long as the duration TA2 between the third last first pulse and the second last first pulse of the display period, and the duration TB between the second successive first pulses PA and PB from the start of the display period NB-1 The duration is as long as the duration TA1 between the second to last first pulse and the last first pulse of the display period. Figure 6 As shown, the last second pulse PB after the last first pulse PA is not used so that it may not be present, although in practice it may be easier to generate a second pulse PB after each first pulse PA to simplify the generation of the signal PWM2.

[0072] According to an embodiment, an index IB is associated with each value of the digital color signal R, G, B. The index IB may be a binary value. During a display operation, the value of the digital color signal R, G, B may be determined according to the logic state of the index IB, or the duration TA. NB to TA1 or duration TB NB TB1 is used to drive the light emitting diode LED.

[0073] According to an embodiment, circuit 26 provides a digital color signal for each initial digital color signal (corresponding to a pixel 12 to be displayed) determined by circuit 26. i,j The index IB is determined by the image pixel to be displayed, and the index IB is then sent to the display pixel 12 i,j . Display pixel 12 i,j The received index IB may be stored in the display pixel 12 i,j According to an embodiment, the index IB may be determined by the circuit 26 based on bits 1 to 2 of the initial digital color signal R, G or B determined by the circuit 26. NB The most significant bit of the initial digital color signal R, G or B determined by circuit 26 is determined by one or more bits, for example. NB , the second most significant bit NB-1 and the third most significant bit NB-2 At least one of. The index IB may be determined by the circuit 26 using a logic gate. According to an embodiment, for image pixels with light tones, the index IB is in a first logic state, such as a logic state "1", and for image pixels with dark tones, the index IB is in a second logic state, such as a logic state "0". According to an embodiment, if all bits b of the initial digital color signal R, G, or B determined by the circuit 26 are equal, NB To b NB-NIB (NIB is an integer, such as 0, 1, or 2) are all in logic state "0", then index IB can be set to logic state "0", and if bit b of the initial digital color signal R, G, or B determined by circuit 26 isNB To b NB-NIB If at least one of (NIB is an integer, for example equal to 0, 1 or 2) is in the logic state "1", the index IB can be set to the logic state "1".

[0074] According to an embodiment, according to the index IB determined based on the initial digital color signal R, G or B, the circuit 26 can calculate a new digital color signal R, G or B and send it to the pixel 12. i,j Data signal j Then, corresponding to the new digital color signal R, G, or B. According to an embodiment, when the index IB corresponds to an image pixel with a dark tone, a new digital color signal R, G, or B is determined, and when the index IB corresponds to an image pixel with a light tone, no new digital color signal R, G, or B is determined. When no new digital color signal R, G, or B is determined, it is sent to the pixel 12. i,j Data signal j Then corresponds to the initial digital color signal R, G, or B. According to an embodiment, when the index IB corresponds to an image pixel with a dark tone, a new digital color signal R, G, or B is determined based on the initial digital color signal R, G, or B. As an example, when the index IB corresponds to an image pixel with a dark tone, the new digital color signal R, G, or B is determined by the circuit 26 so that the image pixel information content is encoded on all NB bits of the digital color signal R, G, or B.

[0075] According to an embodiment, in addition to the bits of the original or new digital color signals R, G, B, the data signal Data j Send index IB to display pixel 12 i,j As an example, when the digital color signals R, G, B are encoded on NB bits and the index IB is encoded on one bit, the data signal Data j Used to send NB+1 bits for each digital color signal R, G, B to the display pixel 12 i,j According to another embodiment, the data signal Data j and timing signal Com i Both send index IB to display pixel 12 i,j For example, by providing a data signal Data j and timing signal Com i According to another embodiment, by determining one or more bits of the digital color signal R, G, B (for example, one of the least significant bit bit1, the second least significant bit bit2, or the third least significant bit bit2 of the digital color signal R, G, B) according to a determined logic, using the data signal Dataj Send index IB to display pixel 12 i,j . Display Pixel 12 i,j It is then suitable to extract the index IB from the stored digital color signal R, G, B.

[0076] According to an embodiment, for image pixels with light tones, the index IB is at a logic state "1", and for image pixels with dark tones, the index IB is at a logic state "0". More precisely, in the first operating mode, in order to display image pixels with light tones (index IB at a logic state "1"), the duration TA NB TA1 is used to drive the light emitting diode LED according to the most significant bit b of the digital color signal R, G or B. NB Each bit b of the digital color signal R, G or B at the beginning NB The logic value "0" or "1" of b1 is continuously changed for a duration of TA. NB The current source CS that supplies the light emitting diode LED is turned on or off during TA1, and in the second operation mode, in order to display an image pixel with a dark tone (index IB in the logic state "0"), the duration TB NB TB1 is used to drive the light emitting diode LED according to the most significant bit b from the digital color signal R NB Each bit b of the digital color signal R, G or B at the beginning NB to the logical value "0" or "1" of b1 for a continuous duration TB NB The current source CS that supplies the light-emitting diode LED is turned on or off during TB1, and during two consecutive durations TB NB To TB1, the current source CS is turned off. Figure 6 By using the duration TA NB to TA1 to obtain the signal I_red_W and by using the duration TB NB Go to TB1 to obtain signal I_red_B.

[0077] As a variation, when the current source CS corresponds to a MOS transistor, the current source CS is switched to the MOS transistor for a duration TA according to the logic value "0" or "1" of each bit of the color signal R, G or B from the least significant bit to the most significant bit of the color signal R, G or B. i or TB j During this period, this transistor can be turned on or off. In that case, the duration TA between two consecutive first pulses PA of the modulation timing signal PWM in the display period i (i is in the range from NB to 1) is multiplied by 2 each time, and the duration TB between the first pulse PA and the consecutive second pulse PB of the modulation timing signal PWMj (j is in the range from NB to 1) multiplied by 2 relative to the duration between the previous consecutive first pulse PA and second pulse PB.

[0078] According to the display method of this embodiment, the modulation timing signal PWM includes the first pulse PA and the second pulse PB and the digital color signal includes NB bits, which is equivalent to the modulation timing signal PWM including only the first pulse and the digital color signal including NT bits b j '(j is in the range from 1 to NT). Therefore, a color digital image encoded on NB bits advantageously obtains a color depth of NT bits. Figure 6 Indicates bit b i (i is in the range from 1 to 5) and bit b j '(j is in the range from 1 to 8).

[0079] Figure 7 Shows Figure 4 4. A block diagram of an embodiment of a portion of circuit 40.

[0080] The circuit 40 comprises:

[0081] - a circuit 60 configured to receive the modulated timing signal PWM and to provide a signal PWM2;

[0082] - a storage circuit 48 comprising a shift register clocked by the signal PWM2, in which the digital color signal R, G or B is stored and which provides a binary signal / b at its output QB j ,;

[0083] - a circuit 62 configured to provide a binary index IB; and

[0084] - logic circuit 64, which is configured to receive the signal / b i , IB and PWM2 and provide control binary signals I_red, I_green or I_blue.

[0085] Binary signal / b i is the binary bit b of the digital color signal R, G or B i When clocked by signal PWM2, shift register 48 shifts from the most significant bit b at its output QB to the most significant bit b. NB The complement of the code starts with providing bits / b i , i.e. bit b i The logic complement of , i is in the range of NB to 1. The circuit 60 will provide a signal PWM2 which includes a rising edge at each first pulse PA and a falling edge at each second pulse PB.

[0086] According to an embodiment, the circuit 62 includes a memory, when the pixel 12 is displayed i,j When received, the index IB is stored in the memory. According to an embodiment, the index IB is stored in the shift register 48 and is used to drive the light emitting diode LED by pulse width modulation with the shortest duration of the duration TA1 or TB1, so that it does not substantially affect the total lighting duration of the light emitting diode LED. As an example, when the index IB is equal to the logic state "1" for light tones and is stored in the shift register 48, driving the light emitting diode LED by pulse width modulation with the shortest duration TA1 associated with the index IB being equal to "1" does not substantially affect the total duration that the light emitting diode LED is turned on. The shortest duration TA1 is advantageously set as low as possible.

[0087] Figure 8 Show Figure 7 Logic circuit 64 includes:

[0088] a first logic gate NOR1 of the NOR type having a first input receiving the binary signal PWM2 and having a second input receiving the binary index IB; and

[0089] - a second logic gate NOR2 of the NOR type having a receiving binary signal / b i and has a first input receiving the binary signal provided at the output of the first logic gate NOR1 and providing a control binary signal I_red (or I_green or I_blue).

[0090] In this embodiment, in the first operation mode, for light tones, the binary index IB is set at a logic value of "1". Therefore, the output of the first logic gate NOR1 remains at a logic value of "0" during the entire display period, and the output I_red (or I_green or I_blue) of the second logic gate NOR2 is equal to the binary signal / b i The binary complement of i .

[0091] Since the shift register 48 is clocked by the signal PWM2, the logic circuit 64 preferably sequentially provides NB bits of the digital color signal R clocked by the signal PWM2 at each rising edge of the signal PWM2. The rising edge of the signal PWM2 is simultaneous with the rising edge of the first pulse PA of the modulation timing signal PWM. Then a pulse width modulation is obtained in the first operating mode, with a duration of TA NB To TA1.

[0092] In the present embodiment, in the second operating mode, for dark tones, the binary index IB is set at the logic value "0". Therefore, the output of the first logic gate NOR1 is equal to the logic complement of the binary signal PWM2. When the signal PWM2 is in the logic state "0", the output of the first logic gate NOR1 is equal to the logic state "1", and the output I_red of the second logic gate NOR2 is equal to the logic state "0". The light emitting diode LED is then turned off. When the signal PWM2 is in the logic state "1", that is, between each first pulse PA and a consecutive second pulse PB, the output of the first logic gate NOR1 is set to the logic value "0", and the output I_red of the second logic gate NOR2 is equal to the binary signal / b i The logical complement of the digital color signal R is equal to bit b of the digital color signal R stored in the shift register 48. i The second operation mode then obtains pulse width modulation, where the duration is TB NB To TB1.

[0093] As an example, Table 1 below includes:

[0094] - In the first column entitled "Grayscale (8 bits)", 256 grayscale values ​​in decimal notation coded with 8 bits are available;

[0095] - in the second column entitled "Ideal Linear (9 bits)", the corresponding ideally obtained value in decimal notation after linear conversion;

[0096] - in the third column entitled "Ideal 2.2 (9 bits)", the corresponding ideally obtained value in decimal notation after gamma conversion with γ equal to 2.2;

[0097] - in the fourth column entitled "Real (9 bits)", the corresponding real value in 9-bit coded decimal representation is available after gamma conversion with γ equal to 2.2;

[0098] - in the fifth column entitled "Unmodified True (9-bit) Binary", the same value as in the fourth column under Binary Representation;

[0099] - in the sixth column entitled "Index IB", the index value IB associated with the value corresponding to the fifth column;

[0100] - In the seventh column entitled "Modified True (9-bit) Binary", the i,j 9-bit digital color signal; and

[0101] - In the eighth column entitled "Real (9+1 bit)", the real obtained value in decimal notation of the 9-bit digital color signal corresponding to the seventh column.

[0102] For Table 1, if all bits b of the digital color signal R, G or B NB To b NB-2 are both in the logic state “0”, the index IB is set to the logic state “0”, and if bit b of the digital color signal R, G or B is NB To b NB-2 At least one of the digital color signals R, G or B is in the logic state "1", the index IB is set to the logic state "1". When the index IB is set to the logic state "0", a new digital color signal R, G or B is determined, and when the index IB is set to the logic state "0", the digital color signal R, G or B is unchanged. When the index IB is set to the logic state "0", the image pixel information content is encoded on all 9 bits of the digital color signal R, G or B, that is, by also using the bit b of the digital color signal R, G or B. NB To b NB-2 (which should originally be equal to the logic state "0") to generate more values ​​on the dark tone, thereby determining the new digital color signal R, G or B. As an example, when the second duration TB i Corresponding to the first duration TA i When divided by 8, the new digital color signal R, G, or B is determined by increasing the original image pixel value by 8 times.

[0103] [Table 1]

[0104]

[0105]

[0106]

[0107]

[0108]

[0109]

[0110]

[0111]

[0112]

[0113]

[0114] Fig. 9 is similar to Figure 2 The figure shows Figure 2A magnified view of the ideal gamma decoding function Igam and the actual gamma decoding function Rgam9 obtained using encoding on 9 bits.

[0115] Fig.10 Shows Figure 1 The ideal gamma decoding function Igam and the previous combination Figure 6 An enlarged view of the gamma decoding function Rgam9+1 actually obtained by the embodiment of the method for displaying an image disclosed and corresponding to Table 1. The curve Rgam9+1 is larger than the curve Rgam9 and also larger than Figure 2 The curve Rgam10 shown in follows the curve Igam more closely.

[0116] according to Figure 3 In the embodiment of the display screen 10 shown, for each row, the display pixels 12 in the row i,j is coupled to a single row electrode 18 i For each column, the display pixels 12 in the column i,j is coupled to a single column electrode 20 j .

[0117] Fig.11 Display Pixel 12 i,j A very simplified cross-sectional view of a known example of Fig.12 Display Pixel 12 i,j Bottom view of the display. Each display pixel is 12 i,j A control circuit 30 is included which is covered with a display circuit 32. The display circuit 32 includes at least one light emitting diode LED, preferably at least three light emitting diodes LED. The display pixel includes a lower surface 34 and an upper surface 35 opposite to the lower surface 34, and the surfaces 34 and 35 are preferably planar and parallel. The control circuit 30 also includes conductive pads P_Gnd, P_Vcc, P_Col, P_Row on the lower surface 34. The control circuit 30 may correspond to an integrated circuit including electronic components, in particular insulated gate field effect transistors (also referred to as MOS transistors), or thin film transistors (also referred to as TFTs). Preferably, the display circuit 32 includes only light emitting diodes LED and conductive elements of these light emitting diodes LED, and the control circuit 30 includes all electronic components necessary for controlling the light emitting diodes LED of the display circuit 32. As a variant, the display circuit 32 may also include other electronic components in addition to the light emitting diodes LED. The light emitting diodes LED may be 2D light emitting diodes (also referred to as planar light emitting diodes) or 3D light emitting diodes including a stack of planar layers, each of which includes a three-dimensional semiconductor element covered with an active area. In Fig.11In the embodiment, the light emitting diodes are shown to be connected to a common anode. However, it may be desirable to arrange the light emitting diodes LED according to another configuration. As an example, the light emitting diodes may be connected to a common cathode, or may be connected independently of each other.

[0118] According to an embodiment, the display pixel 12 i,j The display pixel 12 includes three display sub-pixels emitting light at first, second and third wavelengths. According to an embodiment, the first wavelength corresponds to blue light and is in the range from 430nm to 490nm. According to an embodiment, the second wavelength corresponds to green light and is in the range from 510nm to 570nm. According to an embodiment, the third wavelength corresponds to red light and is in the range from 600nm to 720nm. As a variant, the display pixel 12 i,j Only one light source emitting light of the first, second or third wavelength may be included, or only two light sources emitting light of two wavelengths among the first, second and third wavelengths may be included.

[0119] Each conductive pad P_Gnd, P_Vcc, P_Col, P_Row is intended to be connected to Fig.11 The electrode 14 schematically shown in i , 16 j , 18 i , 20 j The first conductive pad P_Gnd is coupled to the source of the low reference potential Gnd. The second conductive pad P_Vcc is coupled to the source of the high reference potential Vcc. The third conductive pad P_Row is coupled to the row electrode 18. i And receive the timing signal Com i The fourth conductive pad P_Col is coupled to the column electrode 20 j And receive data signal Data j The sizes of the conductive pads P_Gnd, P_Vcc, P_Col, P_Row and the layout of the conductive pads P_gnd, P_Vcc, P_Col, P_Row on the surface 34 are determined in particular by the display pixel 12. i,j The design rules and the display pixels 12 are assembled in the display screen 10 i,j method to apply.

[0120] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined and those skilled in the art will readily conceive of other variations.

[0121] Ultimately, actual implementation of the embodiments and variations described herein is well within the capabilities of those skilled in the art based on the functional description provided herein.

Claims

1. A display pixel (12 i,j ), comprising at least one light emitting diode (LED), and an electronic circuit (40), the electronic circuit (40) comprising a storage circuit (48) and a driver circuit (50), the storage circuit (48) being used to store at least one digital signal (R, G, B), the driver circuit (50) being configured to: in a first operating mode, turn on or off the light emitting diode according to the logic state of the bit of the digital signal during a first different duration (TA5, TA4, TA3, TA2, TA1), or in a second operating mode, turn on or off the light emitting diode according to the logic state of the bit of the digital signal during a second different duration (TB5, TB4, TB3, TB2, TB1) that is at least partially different from the first duration, thereby driving the light emitting diode by pulse width modulation.

2. The display pixel according to claim 1, wherein: The electronic circuit (40) is configured to switch between the first operation mode and a second operation mode depending on the logic state of a first binary signal (IB).

3. The display pixel according to claim 2, wherein: The electronic circuit (40) is configured to receive the first binary signal (IB) from outside the display pixel.

4. The display pixel according to any one of claims 1 to 3, wherein: The digital signal (R, G, B) includes NB bits b i , i is in the range from 1 to NB, bit b NB is the most significant bit, and bit b1 is the least significant bit, wherein the first duration includes NB first durations TA of increasing value i (TA5, TA4, TA3, TA2, TA1), wherein the second duration includes NB second durations TB of increasing value i (TB5, TB4, TB3, TB2, TB1), wherein the driver circuit (50) is configured to operate in the first operation mode by operating for NB first durations TA i The light emitting diode (LED) is driven by pulse width modulation by turning on or off the light emitting diode during the period (TA5, TA4, TA3, TA2, TA1). i In the first logic state, for a first duration TA i is turned on during bit b i In a second logic state different from the first logic state for a first duration TA i The driver circuit (50) is configured to be closed during the NB second duration TB in the second operation mode. i During the period (TB5, TB4, TB3, TB2, TB1), the light emitting diode is turned on or off and driven by pulse width modulation. i In the first logic state, the i is turned on during bit b i In the second logic state, the i Closed during the period.

5. The display pixel according to any one of claims 1 to 4, wherein: At least some of the second time durations (TB5, TB4) are lower than the first time durations (TA2, TA1).

6. The display pixel according to any one of claims 1 to 5, wherein: At least one of the second durations (TB5, TB4) lasts as long as one of the first durations (TA2, TA1).

7. The display pixel according to claim 6, wherein: At least said longest second duration (TB5) lasts as long as one of said first durations (TA2).

8. A display pixel according to any one of claims 1 to 7, comprising at least a first conductive pad (P_Row) intended to receive a second binary signal (Common) comprising pulses (PA, PB) i ) and is connected to the electronic circuit (40), some of the pulses are away from the first duration (TA5, TA4, TA3, TA2, TA1) and some of the pulses are away from the second duration (TB5, TB4, TB3, TB2, TB1), and the electronic circuit is configured to turn on or off the light emitting diode (LED) during the first duration or the second duration based on the pulses.

9. The display pixel according to claim 8, wherein: The pulses include a first pulse (PA), which is far away from the first duration (TA5, TA4, TA3, TA2, TA1), and also include a second pulse (PB), each first pulse (PA) is followed by a second pulse (PB), and the first pulse and the subsequent second pulse are far away from the second duration (TB5, TB4, TB3, TB2, TB1).

10. The display pixel according to claim 9, wherein: The electronic circuit (40) is configured to obtain a second binary signal (Com i ) generates a third binary signal (PWM2) whose logic state is modified at each first pulse (PA) and at each second pulse (PB).

11. The display pixel according to claim 10, wherein: The storage circuit (48) includes a shift register having the digital signal (R, G, B) stored therein and configured to provide successive bits of the stored digital signal clocked by the third binary signal (PWM2).

12. A display pixel according to any one of claims 1 to 11, comprising a controllable current source (CS) supplying the light emitting diode (LED) and controlled by a fourth binary signal (I_red, I_green, I_blue).

13. A display pixel according to claims 2, 4 and 12, wherein: The electronic circuit (40) comprises a first logic gate (NOR1) of the NOR type having a first input for receiving the third binary signal (PWM2) and a second input for receiving the first binary signal (IB), and a second logic gate (NOR2) of the NOR type having a first input for receiving the third binary signal (PWM2) and a second input for receiving the first binary signal (IB). i ( / b i ) and has a first input connected to the logic complement of the first logic gate (NOR1) and provides a fourth binary signal (I_red, I_green, I_blue).

14. A display pixel (12) according to any one of claims 1 to 13. i,j ), including at least a second conductive pad (P_Col) intended to receive a fifth binary signal (Data j ) and is connected to the electronic circuit (40), which is configured to update the stored digital signal (R, G, B) in the storage circuit (48) according to the second signal.

15. A display screen (10), comprising: - Display pixels (12) according to any one of claims 1 to 14 arranged in rows and columns i,j ); - a first conductive track (18 i ) which extend along the rows and are connected to the electronic circuitry (40) of the display pixels; - a second conductive track (20 i ) extending along the columns and connected to the electronic circuitry (40) of the display pixels; and - a control circuit (22, 24, 26) connected to said first conductive track (18 i ) and the second conductive track (20 i ).

16. The display screen according to claim 15, wherein: Each display pixel (12 i,j ) is configured to switch between the first operation mode and the second operation mode according to the logic state of the first binary signal (IB), and wherein the control circuit (22, 24, 26) is configured to determine the first binary signal (IB) for each digital signal (R, G, B) and provide the first binary signal to the display pixel (12 i,j ).

17. The display screen according to claim 15 or 16, wherein: The control circuit (22, 24, 26) is configured to provide a first conductive track (18 i ) provides a timing signal (Com i ), and wherein each display pixel (12 i,j ) is configured to generate a drive signal (I_red, I_green, I_blue) based on the timing signal to drive the light emitting diode (LED) by pulse width modulation: in a first operating mode, by turning on or off the light emitting diode during first different durations (TA5, TA4, TA3, TA2, TA1), or in a second operating mode, by turning on or off the light emitting diode during second different durations (TB5, TB4, TB3, TB2, TB1).

18. The display screen according to claim 17, wherein: The control circuit (22, 24, 26) is configured to provide a first conductive track (18 i ) provides a second binary signal (Com i ) timing signal (Com i ), the second binary signal (Com i ) comprises at least a first pulse (PA) and a second pulse (PB), the first pulse being away from the first duration (TA5, TA4, TA3, TA2, TA1), each first pulse (PA) being followed by a second pulse (PB), the first pulse and the subsequent second pulse being away from the second pulse duration (TB5, TB4, TB3, TB2, TB1).

Images