Semiconductor device

Abstract

A semiconductor device having a novel structure is provided. The semiconductor device includes a first element layer and a plurality of second element layers in which a temperature detection circuit, a voltage generation circuit, and a memory cell are provided in each layer. The plurality of second element layers are stacked on the first element layer. The memory cell includes a transistor in which a semiconductor layer having a channel formation region includes an oxide semiconductor. The transistor includes a back gate. A voltage generation circuit provided in each layer has a function of generating a back gate voltage supplied to a back gate of a transistor included in a memory cell provided in the same layer. The temperature detection circuit has a function of controlling the back gate voltage according to the detected temperature. In the second element layer, a back gate voltage supplied to a transistor included in the second element layer disposed in an upper layer is greater than a back gate voltage supplied to a transistor included in the second element layer disposed in a lower layer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and the like.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product, or a composition of matter. Therefore, specifically, as examples of the technical field of one embodiment of the present invention disclosed in this specification, semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, methods for driving these devices, or methods for manufacturing these devices can be cited. Background Art

[0003] In recent years, research and development on a structure in which a plurality of crystal grains (eg, silicon crystal grains) including circuits having different functions such as SRAM cells and DRAM cells are three-dimensionally stacked has been actively conducted (eg, Non-Patent Documents 1 and 2).

[0004] In addition, in recent years, by using a transistor using an oxide semiconductor for a channel formation region (hereinafter, an OS transistor), a semiconductor device capable of holding a charge according to data has been technically developed. A layer including an OS transistor can be provided in a manner stacked on a crystal grain including a transistor using silicon for a channel formation region (hereinafter, a Si transistor). Patent document 1 discloses a structure in which a layer including a plurality of OS transistors is provided in a manner stacked three-dimensionally on a crystal grain including a Si transistor.

[0005] [Prior technical literature]

[0006] [Patent Document]

[0007] [Patent Document 1] International Patent Application Publication No. 2020 / 152522

[0008] [Non-patent literature]

[0009] [Non-patent document 1] W. Gomes et al., ISSCC Dig. Tech. Papers, pp. 42-43, 2022.

[0010] [Non-patent document 2] M. Park et al., ISSCC Dig. Tech. Papers, pp. 444-445, 2022. Summary of the invention

[0011] Technical problem to be solved by the invention

[0012] When a grain (component layer) including a Si transistor generates heat due to circuit operation, the electrical characteristics of the transistor included in the upper component layer vary due to the heat. In a structure in which a component layer including a plurality of OS transistors is three-dimensionally stacked on a component layer including a Si transistor, the temperature of each layer including a plurality of OS transistors is different, for example, the temperature of the upper layer is different from the temperature of the lower layer. Therefore, there is a concern that the amount of variation in the electrical characteristics of each transistor in the layer including a plurality of OS transistors is different. In other words, there is a concern that the electrical characteristics such as the threshold voltage of the OS transistors in each layer are not uniform in a structure in which the transistor density is increased by stacking layers including a plurality of OS transistors. As a result, there is a concern that power consumption may increase or the reliability of the semiconductor device may be lost due to the non-uniform electrical characteristics of the transistors.

[0013] One of the purposes of one embodiment of the present invention is to provide a semiconductor device in which the influence of uneven electrical characteristics of transistors is reduced. One of the purposes of one embodiment of the present invention is to provide a semiconductor device that is excellent in reducing power consumption. One of the purposes of one embodiment of the present invention is to provide a semiconductor device that is excellent in improving storage density. One of the purposes of one embodiment of the present invention is to provide a semiconductor device having a novel structure.

[0014] Note that the purpose of one embodiment of the present invention is not limited to the above-mentioned purpose. The above-mentioned purposes do not prevent the existence of other purposes. Other purposes refer to purposes other than those mentioned above to be described in the following description. Those skilled in the art can derive and appropriately extract purposes not mentioned above from the description of the specification or drawings, etc. Note that one embodiment of the present invention achieves at least one of the above-mentioned purposes and / or other purposes.

[0015] Solutions to technical problems

[0016] One embodiment of the present invention is a semiconductor device, comprising: a first element layer in which a temperature detection circuit and a voltage generating circuit are provided; and a plurality of second element layers in which storage cells are provided, wherein the plurality of second element layers are stacked on the first element layer, the storage cell includes a transistor having a semiconductor layer with a channel formation region including an oxide semiconductor, the transistor includes a back gate, the voltage generating circuit has a function of generating a back gate voltage supplied to the back gate, the temperature detection circuit has a function of controlling the back gate voltage according to the detected temperature, and the voltage generating circuit has a function of supplying the back gate voltage as a different voltage to each of the plurality of second element layers.

[0017] In one embodiment of the present invention, it is preferable that a back gate voltage supplied to a transistor included in a second element layer provided in an upper layer is larger than a back gate voltage supplied to a transistor included in a second element layer provided in a lower layer.

[0018] In one embodiment of the present invention, preferably, the first element layer includes an arithmetic circuit, and the stacked second element layer is provided to overlap in a region where the arithmetic circuit is provided.

[0019] In one embodiment of the present invention, the oxide semiconductor preferably contains In, Ga, and Zn.

[0020] One embodiment of the present invention is a semiconductor device, comprising: a first element layer; and a plurality of second element layers in each of which a temperature detection circuit, a voltage generating circuit and a storage unit are provided, wherein the plurality of second element layers are stacked on the first element layer, the storage unit includes a transistor having a semiconductor layer with a channel formation region including an oxide semiconductor, the transistor including a back gate, the voltage generating circuit provided in each layer has a function of generating a back gate voltage supplied to the back gate of the transistor included in the storage unit provided in the same layer, and the temperature detection circuit has a function of controlling the back gate voltage according to the detected temperature.

[0021] In one embodiment of the present invention, it is preferable that a back gate voltage supplied to a transistor included in a second element layer provided in an upper layer is larger than a back gate voltage supplied to a transistor included in a second element layer provided in a lower layer.

[0022] In one embodiment of the present invention, preferably, the first element layer includes an arithmetic circuit, and the stacked second element layer is provided to overlap in a region where the arithmetic circuit is provided.

[0023] In one embodiment of the present invention, the oxide semiconductor preferably contains In, Ga, and Zn.

[0024] In one embodiment of the present invention, the temperature detection circuit preferably includes a transistor in which a semiconductor layer having a channel formation region includes an oxide semiconductor.

[0025] One embodiment of the present invention is a semiconductor device, comprising: a first element layer having a temperature detection circuit and a voltage generating circuit; a second element layer including an amplifier circuit; and a plurality of third element layers having storage cells, wherein the plurality of second element layers are stacked on the first element layer, and the plurality of third element layers are stacked on the second element layer, the amplifier circuit has a function of amplifying a signal of the storage cell, the amplifier circuit and the storage cell include a transistor having a semiconductor layer having a channel formation region and including an oxide semiconductor, the transistor including a back gate, the voltage generating circuit having a function of generating a back gate voltage supplied to the back gate, the temperature detection circuit having a function of controlling the back gate voltage according to the detected temperature, and the voltage generating circuit having a function of supplying the back gate voltage as a different voltage to each of the second element layer and the plurality of third element layers.

[0026] In one embodiment of the present invention, preferably, among the plurality of second element layers, a back gate voltage supplied to a transistor included in a second element layer disposed in an upper layer is larger than a back gate voltage supplied to a transistor included in a second element layer disposed in a lower layer.

[0027] In one embodiment of the present invention, the oxide semiconductor preferably contains In, Ga, and Zn.

[0028] In one embodiment of the present invention, preferably, the first element layer includes an operation circuit having a scan trigger, the scan trigger is electrically connected to a backup circuit having a function of maintaining data of the scan trigger, and the backup circuit is arranged in an area of ​​the second element layer overlapping with an area where the scan trigger is set.

[0029] Note that other aspects of the present invention are described in the description and drawings of the embodiment modes described below.

[0030] Effects of the Invention

[0031] One embodiment of the present invention can provide a semiconductor device in which the influence of uneven electrical characteristics of a transistor is reduced. One embodiment of the present invention can provide a semiconductor device that is excellent in reducing power consumption. One embodiment of the present invention can provide a semiconductor device that is excellent in improving storage density. One embodiment of the present invention can provide a semiconductor device having a novel structure.

[0032] Note that the description of these effects does not prevent the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of the above effects. Note that effects other than the above can be known and extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1A and Figure 1B A diagram illustrating a structural example of a semiconductor device.

[0034] Figure 2 A diagram illustrating a structural example of a semiconductor device.

[0035] Figure 3A and Figure 3B It is a diagram for explaining a semiconductor device.

[0036] FIG. 4A to FIG. 4C It is a diagram for explaining a semiconductor device.

[0037] Figure 5A and Figure 5B It is a diagram for explaining a semiconductor device.

[0038] Figure 6 A diagram illustrating a structural example of a semiconductor device.

[0039] Fig. 7A and Figure 7B A diagram illustrating a structural example of a semiconductor device.

[0040] Figure 8 A diagram illustrating a structural example of a semiconductor device.

[0041] 9A to 9C A diagram illustrating a structural example of a semiconductor device.

[0042] FIG. 10A to FIG. 10D A diagram illustrating a structural example of a semiconductor device.

[0043] FIG. 11A to FIG. 11E A diagram illustrating a structural example of a semiconductor device.

[0044] Fig.12 A diagram illustrating a structural example of a semiconductor device.

[0045] Fig.13A and Fig. 13B A diagram illustrating a structural example of a semiconductor device.

[0046] Fig.14A and Fig. 14B A diagram illustrating a structural example of a semiconductor device.

[0047] FIG. 15A to FIG. 15D A diagram illustrating a structural example of a semiconductor device.

[0048] Fig.16A and Fig. 16B A diagram illustrating a structural example of a semiconductor device.

[0049] Fig.17 A diagram illustrating a structural example of a semiconductor device.

[0050] Fig.18 A diagram illustrating a structural example of a semiconductor device.

[0051] Fig.19 A diagram illustrating a structural example of a semiconductor device.

[0052] Fig. 20A and Fig. 20B A diagram illustrating a structural example of a semiconductor device.

[0053] Fig.21A and Fig. 21B A diagram illustrating a structural example of a semiconductor device.

[0054] Fig. 22 A diagram illustrating a structural example of a semiconductor device.

[0055] FIG. 23A to FIG. 23CA diagram illustrating a structural example of a semiconductor device.

[0056] Fig.24 A diagram illustrating a structural example of a semiconductor device.

[0057] Fig.25 It is a diagram for explaining a configuration example of a storage unit.

[0058] Fig.26A A diagram illustrating a structural example of a storage layer. Fig.26B is a diagram illustrating an equivalent circuit of a storage layer.

[0059] FIG. 27A to FIG. 27D A diagram illustrating a structural example of a semiconductor device.

[0060] Fig.28 A diagram illustrating a structural example of a semiconductor device.

[0061] Fig.29 It is a diagram for explaining a configuration example of a storage unit.

[0062] Fig. 30A It is a diagram for explaining a structural example of a storage layer. Fig. 30B is a diagram illustrating an equivalent circuit of a storage layer.

[0063] Fig.31 A diagram illustrating a structural example of a semiconductor device.

[0064] Fig.32A and Fig.32B It is a diagram showing an example of an electronic component.

[0065] Fig.33A and Fig.33B is a diagram showing an example of an electronic device, FIG. 33C to FIG. 33E This is a diagram showing an example of a large computer.

[0066] Fig.34 is a diagram showing an example of space equipment.

[0067] Fig.35 This is a diagram showing an example of a storage system that can be used in a data center.

[0068] Fig.36 It is a diagram illustrating the structure of a cross section of a semiconductor device.

[0069] Fig.37 A diagram illustrating the layout of a semiconductor chip.

[0070] FIG. 38A to FIG. 38D This is a diagram illustrating an operation simulation of a semiconductor chip.

[0071] FIG. 39A to FIG. 39DThis is a diagram illustrating an operation simulation of a semiconductor chip. DETAILED DESCRIPTION

[0072] The following describes the embodiments with reference to the accompanying drawings. However, a person skilled in the art can easily understand that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the following embodiments.

[0073] In the accompanying drawings, for the sake of clarity, the size, thickness of the layer or the region are sometimes exaggerated. Therefore, the present invention is not necessarily limited to the above-mentioned dimensions. In addition, in the accompanying drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or numerical values ​​shown in the accompanying drawings.

[0074] In addition, in this specification, etc., unless otherwise specified, the off-state current refers to the drain current when the transistor is in the off state (also called the non-conducting state or the blocking state). Unless otherwise specified, in an n-channel transistor, the off state refers to the voltage V between the gate and the source. gs Below the threshold voltage V th (In a p-channel transistor, V gs Higher than V th ) status.

[0075] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor may refer to a transistor containing a metal oxide or an oxide semiconductor.

[0076] (Implementation Method 1)

[0077] In this embodiment, a configuration example of a semiconductor device is described. The semiconductor device described in one embodiment of the present invention has a function of a SoC (System on a chip) including a plurality of synchronous circuits such as a memory and a peripheral circuit in addition to a CPU and a cache memory.

[0078] Figure 1A This is a schematic perspective view of a semiconductor device according to one embodiment of the present invention. Figure 1AThe semiconductor device 10 shown includes a device layer 20 and a plurality of device layers (as an example, Figure 1A Component layers 30_1 to 30_4 are shown in the figure. Figure 1B So in Figure 1A The device layer 20 and the plurality of device layers 30_1 to 30_4 are separated from each other in the structure. Figure 2 Yes Description Figure 1A , Figure 1B Block diagram of the structure shown.

[0079] The element layer 20 is a layer including a transistor (Si transistor) in which a semiconductor layer including a channel formation region contains silicon. As an example, the element layer 20 includes a voltage control circuit 21, a peripheral circuit 22, and an operation circuit 23. Each of the element layers 30_1 to 30_4 includes a memory cell array 31. The memory cell array 31 includes a memory cell 32. The memory cell 32 includes a transistor 37 having a back gate.

[0080] The voltage control circuit 21 has a function of supplying a voltage (back gate voltage) to be applied to the back gate of the transistor 37 included in the memory cell array 31 to each layer of the element layers 30_1 to 30_4. The back gate voltage is a voltage that is different for each layer of the element layers 30_1 to 30_4. In addition, the back gate voltage is controlled according to the temperature detected by the voltage control circuit 21. By adopting this structure, since different back gate voltages are supplied to the element layer 30_1 close to the element layer 20 and the element layer 30_4 far from the element layer 20, the influence of uneven electrical characteristics of transistors that are different for each layer of the element layers 30_1 to 30_4 can be reduced.

[0081] The peripheral circuit 22 has a function of controlling data writing or reading of the memory cells 32 included in the memory cell array 31 provided in each layer of the element layers 30_1 to 30_4. The peripheral circuit 22 includes a plurality of drive circuits and control circuits for driving signal lines such as word lines and bit lines connected to the memory cells 32. For example, when an element layer 30 having n layers (n is an integer greater than or equal to 2) is used, it is preferable to provide n drive circuits for driving the word lines and bit lines connected to the memory cells 32.

[0082] The operation circuit 23 has a function of performing operation processing using data stored in the memory cells 32 of the stacked memory cell arrays 31. For example, the operation circuit 23 can perform operation using data read from all memory cell arrays 31, can perform operation using data read from one memory cell array 31, or can perform operation using data read from a plurality of memory cell arrays 31. Note that the operation circuit 23 is described as an example, and may be a circuit having other functions such as a cache memory or a controller circuit.

[0083] exist Figure 1A , Figure 1B and Figure 2 The element layer 20 including the Si transistor in the structure can have a structure forming a CMOS circuit (SiCMOS circuit). Since the voltage control circuit 21, the peripheral circuit 22 and the operation circuit 23 can be formed by a CMOS circuit, high-speed operation can be performed.

[0084] In addition, the semiconductor layer including the channel formation region of the Si transistor can use one or a combination of a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor or an amorphous semiconductor. The semiconductor material is not limited to silicon, for example, germanium can also be used. In addition, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide or nitride semiconductors can also be used.

[0085] exist Figure 1A , Figure 1B and Figure 2 In the structure of , the path from the memory cell array 31 of the element layer 30_1 to 30_4 to the operation circuit 23 or the path from the amplifier circuit of the data output from the memory cell array 31 to the operation circuit 23 can be shorter than the case where a plurality of memory cell arrays 31 are arranged in parallel in the element layer 20. In other words, in Figure 1A , Figure 1B and Figure 2 In the structure, the path difference between the memory cell array 31 of the element layer 30_1 located near the element layer 20 (the memory cell array 31 in the lowest element layer) and the memory cell array 31 in the element layer 30_4 located farther from the surface of the element layer 20 (the memory cell array in the highest memory layer) to the operation circuit 23 can be reduced.

[0086] The difference in path length between the memory cell array 31 and the operation circuit 23 leads to differences in parasitic capacitance and parasitic resistance, which in turn leads to differences in signal delay and power consumption. Figure 1A , Figure 1B and Figure 2 In the structure, no matter which memory cell array 31 of each element layer 30_1 to 30_4 data is read from, data can be read with the same degree of signal delay and power consumption. Therefore, no matter which memory cell array 31 data is stored in, there is little difference in computing performance, power consumption and computing efficiency, thereby improving the degree of freedom when storing data.

[0087] Note that by overlapping the operation circuit 23 and the element layers 30_1 to 30_4, heat generated by driving the operation circuit 23 is transferred to the element layers 30_1 to 30_4. As a result, the field effect mobility of the OS transistors included in the element layers 30_1 to 30_4 can be improved. In addition, high-speed operation of the element layers 30_1 to 30_4 can be achieved.

[0088] The element layers 30_1 to 30_4 are element layers including transistors (hereinafter referred to as OS transistors) using an oxide semiconductor for a channel formation region. The element layers 30_1 to 30_4 are stacked on the element layer 20 . Figure 1A , Figure 1B The Z direction in φ represents a direction perpendicular to the surface of the substrate on which the element layer 20 is provided (a plane represented by the X direction−Y direction) or a direction in which the element layers 30_1 to 30_4 are stacked on the element layer 20 .

[0089] Figure 1A , Figure 1B and Figure 2 The semiconductor device 10 shown shows a case where element layers 30_1 to 30_4 including a memory cell array 31 are stacked on the element layer 20. By providing the element layer 30 including the memory cell array 31 on the element layer 20, the occupied area of ​​the semiconductor device 10 can be reduced. In addition, by stacking the element layer 30 including the memory cell array 31, the storage capacity per unit area can be increased.

[0090] The memory cell 32 is preferably a DOSRAM which is a memory circuit (sometimes also referred to as an "OS memory") including an OS transistor. DOSRAM (registered trademark) is an abbreviation of "Dynamic Oxide Semiconductor Random Access Memory". DOSRAM is a RAM including a 1T (transistor) 1C (capacitor) type memory cell. DOSRAM is a DRAM formed using OS transistors, and DOSRAM is a memory that temporarily stores information sent from the outside. DOSRAM is a memory that utilizes the low off-state current characteristic of OS transistors.

[0091] The current flowing between the source and drain of the OS transistor in the off state, i.e., the off-state current, is extremely small. In DOSRAM, by turning off the access transistor (making it non-conductive), the charge according to the data stored in the capacitor (capacitor) (sometimes also referred to as "cell capacitor") can be maintained for a long time. Therefore, compared with DRAM composed of transistors containing silicon in the channel formation region (hereinafter also referred to as "Si transistors"), the refresh frequency of DOSRAM can be lower. As a result, low power consumption can be achieved.

[0092] The memory cell 32 can stack the element layers 30_1 to 30_4 including the memory cell array 31 by stacking the OS transistors. The element layers 30_1 to 30_4 included in the element layer 30 can be arranged in a direction perpendicular to the substrate surface on which the element layer 20 is arranged, so that the storage density of the memory cell 32 can be increased. In addition, the element layer 30 can be repeatedly manufactured using the same manufacturing process in the vertical direction. The semiconductor device 10 can reduce the manufacturing cost of the element layer 30.

[0093] Note that although the present embodiment describes a structure that can be used for the storage cell 32 by taking DOSRAM as an example, other structures that can form a storage layer in a stacked manner on the element layer 20 can also be used. For example, NOSRAM, which is a storage circuit including an OS transistor, can also be used. NOSRAM (registered trademark) is an abbreviation for "Nonvolatile Oxide Semiconductor Random Access Memory (RAM)". The storage cell of NOSRAM is a two-transistor type (2T) or three-transistor type (3T) gain cell.

[0094] In addition, it is preferred that all transistors included in the memory cell 32 are OS transistors. When the OS transistor is in the off state, the current flowing between the source and the drain (i.e., the off-state current) is extremely small. NOSRAM can be used as a non-volatile memory by maintaining the charge corresponding to the data in the memory cell 32 by utilizing the characteristic that the off-state current is extremely small. In particular, NOSRAM can be read out in a manner that does not destroy the retained data (non-destructive reading), and is therefore suitable for arithmetic processing that only performs a large number of repeated data reading operations.

[0095] exist Figure 1A , Figure 1B and Figure 2 , the first element layer 30 is shown as the element layer 30_1, the second element layer 30 is shown as the element layer 30, and the third element layer 30 is shown as the element layer 30_3. In addition, the element layer 30 of the k-th layer (k is an integer greater than 1 and less than n) is referred to as the element layer 30_k, and the element layer 30 of the n-th layer is referred to as the element layer 30_n. Note that in this embodiment and the like, when describing matters related to the entire n-layer element layer 30, or when describing matters common to each layer of the n-layer element layer 30, sometimes only "element layer 30" is referred to.

[0096] Figure 1A , Figure 1B and Figure 2 The voltage control circuit 21 shown includes a temperature detection circuit 15 and a plurality of voltage generation circuits 16_1 to 16_4. Figure 2The transistor 37 included in the memory cell 32 shown is a transistor including a first gate (also referred to as a "front gate" or simply a "gate") and a second gate (also referred to as a "back gate"). The first gate and the second gate have a region overlapping each other across the semiconductor layer. The second gate has, for example, a function of controlling the threshold voltage of the transistor 37.

[0097] Figure 2 The temperature detection circuit 15 shown in the figure has a function of outputting a signal T corresponding to the temperature of the element layer 20. 20 The temperature detection circuit 15 includes, for example, a temperature sensor. As the temperature sensor, for example, a temperature measuring resistor made of platinum, nickel, or copper, a thermistor, a thermocouple, an IC temperature sensor, etc. can be used.

[0098] The temperature detection circuit 15 may also include an analog-to-digital conversion circuit. By converting the temperature information of the analog signal detected by the temperature detection circuit 15 into a digital signal and outputting it, the influence of signal attenuation or noise caused by wiring resistance and parasitic capacitance can be reduced. Therefore, even if the temperature detection circuit 15 is set at a position far away from the voltage generation circuits 16_1 to 16_4, the temperature information can be accurately transmitted to the voltage generation circuits 16_1 to 16_4.

[0099] The electrical characteristics such as the threshold voltage of the transistors in the element layers 30_1 to 30_4 change according to the temperature change of the element layer 20. For example, the temperature of the element layers 30_1 to 30_4 above the operation circuit 23 changes due to the heat generated by the driving current flowing through the operation circuit 23 in the element layer 20. In the temperature detection circuit 15, by measuring the temperature change of the element layer 20, a signal for controlling the change of the electrical characteristics caused by the temperature change of the element layers 30_1 to 30_4 is output.

[0100] Figure 2 The voltage generating circuits 16_1 to 16_4 shown have the function of generating back gate voltages VBG_1 to VBG_4 supplied to the back gates of the transistors 37 in the memory cells 32 included in the element layers 30_1 to 30_4. The voltage generating circuits 16_1 to 16_4 may be, for example, circuits that generate desired back gate voltages in combination with a reference voltage generating circuit and a buck (or boost) charge pump.

[0101] The back gate voltages VBG_1 to VBG_4 generated by the voltage generating circuits 16_1 to 16_4 are generated according to the change in electrical characteristics caused by the temperature change of the element layers 30_1 to 30_4. For example, in the case where the driving element layer 20 of the operation circuit 23 is at a high temperature, since the temperature of the lower element layer 30_1 is the same high temperature as the element layer 20, and the upper element layer 30_4 is far away from the element layer 20, the temperature of the element layer 30_4 is lower than that of the element layer 30_1. In other words, in order to reduce the uneven electrical characteristics caused by the temperature gradient of the element layers 30_1 to 30_4 generated by the temperature of the corresponding element layer 20, the back gate voltages VBG_1 to VBG_4 are generated.

[0102] When the driving element layer 20 of the above-mentioned operation circuit 23 is at a high temperature, the electrical characteristics of the transistors between the lower element layer 30_1 and the upper element layer 30_4 are different. Therefore, the voltage control circuit 21 including the temperature detection circuit 15 and multiple voltage generating circuits 16_1 to 16_4 applies a back gate voltage of VBG_1 to the back gate of the transistor 37 included in the lower element layer 30_1 and applies a back gate voltage of VBG_4 (>VBG_1) to the back gate of the transistor 37 included in the upper element layer 30_4, thereby controlling to reduce the unevenness of the electrical characteristics.

[0103] Note that it is preferable that the back gate voltages VBG_1 to VBG_4 are supplied to the transistors 37 of each element layer so as to satisfy VBG_4>VBG_3>VBG_2>VBG_1. By adopting this structure, the electrical characteristics of the transistors 37 included in the upper element layer 30_4 can be made close to the electrical characteristics of the transistors 37 included in the lower element layer 30_1, thereby reducing the variation in electrical characteristics.

[0104] Metal oxides used for OS transistors include, for example, indium oxide, gallium oxide, and zinc oxide. In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, element M is preferably one or more selected from aluminum, gallium, yttrium, and tin.

[0105] In particular, as the metal oxide, an oxide containing indium (In), gallium (Ga) and zinc (Zn) (also referred to as IGZO) is preferably used. Alternatively, an oxide containing indium, tin and zinc (also referred to as ITZO (registered trademark)) is preferably used. Alternatively, an oxide containing indium, gallium, tin and zinc is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al) and zinc (Zn) is preferably used (also referred to as IAZO). Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga) and zinc (Zn) is preferably used (also referred to as IAGZO). Alternatively, an oxide containing indium (In), gallium (Ga), zinc (Zn) and tin (Sn) (also referred to as IGZTO) is preferably used.

[0106] In addition, the metal oxide used for the OS transistor may include two or more metal oxide layers with different compositions. For example, a stacked structure of a first metal oxide layer having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto and a second metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto provided on the first metal oxide layer may be appropriately used.

[0107] Alternatively, for example, a stacked-layer structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO may be used.

[0108] In addition, the metal oxide used for the OS transistor preferably has crystallinity. Examples of crystalline oxide semiconductors include CAAC (c-axis-aligned crystalline)-OS and nc (nanocrystalline)-OS. By using crystalline oxide semiconductors, a semiconductor device with high reliability can be provided.

[0109] In addition, the OS transistor can also operate stably in a high temperature environment, and the characteristics change less. For example, the off-state current hardly increases even in a high temperature environment. Specifically, the off-state current hardly increases even at an ambient temperature above room temperature and below 200°C. In addition, the on-state current is not easy to drop even in a high temperature environment. Therefore, a memory cell with an OS transistor can also operate stably in a high temperature environment and has high reliability.

[0110] Here, the temperature dependence of Id-Vg characteristics, which is one of the electrical characteristics of a transistor, will be described. Figure 3A The Id-Vg characteristics of the OS transistor (OS-FET) are shown. Figure 3B The Id-Vg characteristics of Si transistor (Si-FET) are shown. Note that Figure 3A and Figure 3BBoth show the Id-Vg characteristics of an n-channel transistor. The Id-Vg characteristics represent changes in drain current (Id) with respect to changes in gate voltage (Vg). Figure 3A and Figure 3B The horizontal axis of shows Vg on a linear scale. In addition, Figure 3A and Figure 3B The vertical axis shows Id in a logarithmic scale.

[0111] like Figure 3A As shown in FIG. 1 , the off-state current of the OS transistor is not easy to increase even when the OS transistor is operated at a high temperature. In addition, as the operating temperature increases, the Vth of the OS transistor drifts in the negative direction, and the on-state current of the operating voltage VG increases as the operating temperature increases. On the other hand, as Figure 3B As shown, the off-state current of the Si transistor increases with the increase of the operating temperature. In addition, the Vth of the Si transistor drifts in the positive direction with the increase of the operating temperature, and the on-state current of the operating voltage VG decreases with the increase of the operating temperature.

[0112] By using an OS transistor as the transistor 37 included in the stacked element layer 30, a low off-state current can be achieved even when operating at a high temperature. Even when operating at a high temperature, the power consumption of the entire semiconductor device including the transistor 37 can be reduced.

[0113] Figure 4A It shows that according to Figure 3A The relationship between the temperature change of the Id-Vg characteristic of the OS transistor and the temperature change of the on-state current Ion (the drain current Id flowing at the operating voltage VG). Figure 4A As shown, since the on-state current Ion varies depending on the temperature, the electrical characteristics of the element layers 30_1 to 30_4 vary due to the temperature variation.

[0114] The voltage control circuit 21 generates back gate voltages VBG_1 to VBG_4 supplied to the back gates of the transistors 37 of the memory cells 32 included in the element layers 30_1 to 30_4 in order to reduce the change in electrical characteristics caused by the temperature change of the element layers 30_1 to 30_4. Specifically, Figure 4B As shown in FIG. 1 , when the temperature distribution of the element layers 30_1 to 30_4 is such that the temperature of the lower layer is higher, the voltage of the lower layer among the back gate voltages VBG_1 to VBG_4 is lower. 30_4 , T 30_3 , T 30_2 , T 30_1 The higher the temperature, the higher the voltage can be supplied in the order of VBG1, VBG2, VBG3, and VBG4. Figure 4CThe Id-Vg characteristics shown can alleviate the non-uniformity of electrical characteristics caused by the non-uniformity of temperature changes in the device layers 30_1 to 30_4.

[0115] Note that Figure 4B As shown, in the structure of the element layer on the low temperature side, as Figure 5A As shown in FIG. 1 , a structure is adopted in which the on-state current of the transistor of the upper element layer (low temperature side) is corrected in such a way as to increase it (the electrical characteristics of the dotted line are corrected to the electrical characteristics of the solid line), but other structures may also be adopted. Figure 5B As shown, a structure may be adopted in which the on-state current of the transistor of the lower element layer (high temperature side) is reduced (the electrical characteristics of the dotted line are corrected to the electrical characteristics of the solid line). By adopting this structure, the unevenness of the on-state current between the upper and lower element layers 30 can be reduced.

[0116] Figure 6 An example of an integrated circuit (also referred to as an IC chip) including the semiconductor device 10 is shown. The semiconductor device 10 can be configured as an IC chip by mounting a plurality of element layers on a package substrate. Figure 6 An example of its structure is shown.

[0117] Figure 6 The schematic cross-sectional view of the IC chip 100 shown shows an element layer 20 including a base die on a package substrate 101, and as an example shows a semiconductor device 10 in which four element layers 30_1 to 30_4 are stacked on the element layer 20. A solder ball 102 for connecting the IC chip 100 to a printed circuit board or the like is provided on the package substrate 101. The electrode 39 for connecting the element layer 20 and the element layers 30_1 to 30_4 can be provided in the process of manufacturing the transistor 49 of the Si transistor or the transistor 37 of the OS transistor.

[0118] Figure 6 The structure may be a monolithic structure in which the connection between the element layer 20 including the transistor 49 and the element layers 30_1 to 30_4 including the transistor 37 does not utilize a through-electrode technology such as TSV (Through Silicon Via) or a Cu-Cu direct bonding technology. The element layers 30_1 to 30_4 on the element layer 20 may have a structure in which wiring provided together with the transistor 37 included in the element layers 30_1 to 30_4 is used as an electrode 39 for connecting the upper or lower element layers.

[0119] The spacing of the wiring provided together with the transistor 37 can be microfabricated compared with the through-electrodes used in TSV or Cu-Cu direct bonding technology. Figure 6In the structure of the semiconductor device 10 shown, the number of electrodes used to connect the upper or lower element layers can be increased. Therefore, the number of wirings (number of signal lines) between the storage circuit including the storage cells provided in the element layers 30_1 to 30_4 and the operation circuit 23 provided in the element layer 20 can be increased. In other words, the number of channels between the operation circuit and the storage circuit can be increased. Therefore, the transmission amount (bandwidth) of the signal sent and received between the element layer 20 and the element layer 30 can be increased. By increasing the bandwidth, the amount of data transmission per unit time can be increased.

[0120] Fig. 7A Is the description and Figure 1A Schematic diagram of a three-dimensional semiconductor device of a different structural example of the semiconductor device according to one embodiment of the present invention described in FIG. Fig. 7A The semiconductor device 10A shown includes an element layer 20 and a plurality of element layers (as an example, Fig. 7A Component layers 30_1 to 30_4 in the embodiment. Figure 7B Yes Fig. 7A The device layer 20 and the plurality of device layers 30_1 to 30_4 in the structure are separated and shown in a three-dimensional diagram. In addition, Figure 8 Yes Description Fig. 7A , Figure 7B In addition, in the following Fig. 7A , Figure 7B and Figure 8 In the description of Figure 1A , Figure 1B and Figure 2 The same parts are represented by the same symbols and their description is omitted.

[0121] Fig. 7A , Figure 7B and Figure 8 The structure shown is Figure 1A , Figure 1B and Figure 2 The difference is that each of the element layers 30_1 to 30_4 includes the temperature detection circuit 15 and the voltage generation circuit 16. That is, each element layer 30 includes the temperature detection circuit 15 and the voltage generation circuit 16. Note that the voltage generation circuit 16 may also be provided in the element layer 20.

[0122] like Figure 7B and Figure 8 As shown, the temperature detection circuits 15_1 to 15_4 provided in each layer have a function of outputting a signal T corresponding to the temperature of the element layer 30_1 to 30_4. 30_1 To T 30_4 As an example, the temperature detection circuits 15_1 to 15_4 include temperature sensors having OS transistors.

[0123] like Figure 7B and Figure 8 As shown, the voltage generating circuits 16_1 to 16_4 provided in each layer generate back gate voltages VBG_1 to VBG_4 included in the transistor 37 provided in the same layer according to changes in electrical characteristics caused by changes in temperature of the element layers 30_1 to 30_4 .

[0124] The back gate voltages VBG_1 to VBG_4 generated by the voltage generating circuits 16_1 to 16_4 are generated according to the change in electrical characteristics caused by the temperature change of the element layers 30_1 to 30_4. For example, in the case where the driving element layer 20 of the operation circuit 23 is at a high temperature, since the temperature of the lower element layer 30_1 is the same high temperature as the element layer 20, and the upper element layer 30_4 is far away from the element layer 20, the temperature of the element layer 30_4 is lower than that of the element layer 30_1. In other words, in order to reduce the uneven electrical characteristics caused by the temperature gradient of the element layers 30_1 to 30_4 generated by the temperature of the corresponding element layer 20, the back gate voltages VBG_1 to VBG_4 are generated.

[0125] When the driving element layer 20 of the above-mentioned operation circuit 23 is at a high temperature, the back gate voltage of VBG_1 is applied to the back gate of the transistor 37 included in the lower element layer 30_1 and the back gate voltage of VBG_4 (>VBG_1) is applied to the back gate of the transistor 37 included in the upper element layer 30_4, thereby reducing the unevenness of the electrical characteristics. Note that it is preferable to supply the back gate voltages VBG_1 to VBG_4 to the transistors 37 of each element layer in such a manner that VBG_4>VBG_3>VBG_2>VBG_1. By adopting this structure, the electrical characteristics of the transistor 37 included in the upper element layer 30_4 can be close to the electrical characteristics of the transistor 37 included in the lower element layer 30_1, thereby reducing the unevenness of the electrical characteristics.

[0126] A structural example of a temperature sensor including an OS transistor is described. Fig. 9A A configuration example of the temperature detection circuit 15 including transistors 18A and 18B which are OS transistors is shown.

[0127] exist Fig. 9A In the temperature detection circuit 15 shown, the gate and drain of transistor 18A are supplied with a potential of V1 and the gate of transistor 18B is supplied with 0V. The source and drain of transistor 18A become conductive (on), and the source and drain of transistor 18B become non-conductive (off). Since transistor 18A becomes conductive, the potential of output VOUT rises from 0V to V1 (>0V). The rise of the potential stops when the threshold voltage of transistor 18A is VTH and the output VOUT becomes V1-VTH.

[0128] Temperature detection is performed based on the change in the threshold voltage VTH of transistor 18A. Since the output VOUT includes VTH, it can be an output corresponding to the temperature. In addition, the output VOUT can be reset (0V) by setting the gate of transistor 18B to V1 and turning on transistor 18B. The output VOUT can be output as a digital signal through an analog-to-digital conversion circuit.

[0129] As another structure of the temperature detection circuit 15, Fig. 9B FIG. 1 shows a configuration example of a temperature detection circuit 15A composed of a transistor 18A and a constant current source 19 which are OS transistors. The constant current source 19 can be composed of an OS transistor. Fig. 9B In the structure shown, temperature detection is performed using the change in threshold voltage VTH of transistor 18A based on temperature. Since output VOUT includes VTH, it can be an output corresponding to the temperature.

[0130] Fig. 9C The voltage generating circuit 16 includes a logic circuit 34, a plurality of buffers ( Fig. 9C BF1 to BF4) and a plurality of capacitor elements ( Fig. 9C 1, C1, C2, C4, and C8 are shown in FIG. 1 ). The logic circuit 34 has a function of supplying voltage to the buffers BF1 to BF4 according to the output signal (temperature information) supplied from the temperature detection circuit 15. For example, the serial signal supplied from the temperature detection circuit 15 is converted into a parallel signal and supplied to the buffers BF1 to BF4.

[0131] One electrode of the capacitor C1 is connected to the output of the buffer BF1, and the other electrode is connected to a wiring for supplying the back gate voltage VBG to the back gate of the transistor 37. One electrode of the capacitor C2 is connected to the output of the buffer BF2, and the other electrode is connected to a wiring for supplying the back gate voltage VBG to the back gate of the transistor 37. One electrode of the capacitor C4 is connected to the output of the buffer BF3, and the other electrode is connected to a wiring for supplying the back gate voltage VBG to the back gate of the transistor 37. One electrode of the capacitor C8 is connected to the output of the buffer BF4, and the other electrode is connected to a wiring for supplying the back gate voltage VBG to the back gate of the transistor 37.

[0132] The voltage applied to the wiring that supplies the back gate voltage VBG from the voltage generating circuit 16 to the back gate of the transistor 37 is determined according to the ratio of the combined capacitance of the capacitor element C1, the capacitor element C2, the capacitor element C4, and the capacitor element C8 to the parasitic capacitance generated in the wiring that supplies the back gate voltage VBG to the back gate of the transistor 37. The capacitance value of the capacitor element C1 is preferably sufficiently greater than the capacitance value of the parasitic capacitance. Specifically, the capacitance value of the capacitor element C1 is preferably more than 5 times the capacitance value of the parasitic capacitance, and more preferably more than 10 times. In this way, by configuring the temperature detection circuit 15 and the voltage generating circuit 16 in each element layer including the storage unit 32, the back gate voltage VBG can be changed in accordance with the temperature change in each element layer.

[0133] The structure of the voltage generating circuit 16 is not limited to Fig. 9C The structure shown may also adopt other structures. For example, a structure using a charge pump circuit or the like may also be adopted.

[0134] Alternatively, a configuration may be adopted in which a voltage holding circuit having a function of holding the back gate voltage VBG is provided between the voltage generating circuit 16 and a wiring for supplying the back gate voltage VBG to the back gate of the transistor 37. FIG. 10A to FIG. 10D A configuration example of a voltage holding circuit will be described.

[0135] Fig. 10A The example of the structure including the voltage holding circuit 35 between the voltage generating circuit 16 and the wiring supplying the back gate voltage VBG to the back gate of the transistor 37 is shown. The voltage holding circuit 35 includes a transistor 36. The first terminal (one of the source and the drain) of the transistor 36 is connected to the voltage generating circuit 16, and the second terminal (the other of the source and the drain) of the transistor 36 is connected to the wiring supplying the back gate voltage VBG to the back gate of the transistor 37.

[0136] The voltage holding circuit 35 has a function of turning on the transistor 36 and supplying the voltage VBG0 generated by the voltage generating circuit 16 to the wiring that supplies the back gate voltage VBG to the back gate of the transistor 37. When the threshold voltage of the transistor 36 is set to Vth1 and the transistor 36 is turned on, it is preferable to apply a voltage of VBG0+Vth1 or more to the gate of the transistor 36. In addition, the voltage holding circuit 35 has a function of holding the voltage of the wiring that turns the transistor 36 off and supplies the back gate voltage VBG to the back gate of the transistor 37. By holding the back gate voltage VBG, the voltage generating circuit 16 can be stopped intermittently, thereby achieving low power consumption.

[0137] When a negative potential is supplied as the voltage VBG0, a transistor including a first gate and a second gate may be used as the transistor 36, and the first gate and the second gate may be connected to the second terminal (see Fig. 10B ). In this case, the transistor 36A can be used as a diode. In addition, when the voltage output from the transistor 36A is recorded as the voltage VBG1, the relationship VBG1=VBG+Vth1 is established. By setting the first terminal of the transistor 36A to GND, the negative potential written to the wiring that supplies the back gate voltage VBG to the back gate of the transistor 37 can be maintained.

[0138] exist Fig. 10B In the transistor 36A shown, when the first terminal is set to GND after a negative potential is supplied to the wiring supplying the back gate voltage VBG to the back gate of the transistor 37, the gate voltage (Vg) becomes 0 V. Therefore, it is preferable that Id (also referred to as "cutoff current") is small when Vg is 0 V. By sufficiently reducing the cutoff current, the negative potential written to the wiring supplying the back gate voltage VBG to the back gate of the transistor 37 can be maintained for a long period of time.

[0139] The channel length of transistor 36A is preferably longer than the channel length of transistor 37. For example, when the channel length of transistor 37 is less than 1 μm, the channel length of transistor 36A is 1 μm or more, more preferably 3 μm or more, further preferably 5 μm or more, and further preferably 10 μm or more. By extending the channel length of transistor 36A, transistor 36A is not affected by the short channel effect, and the cut-off current can be suppressed. In addition, the withstand voltage between the source and the drain of transistor 36A can be increased. When the withstand voltage between the source and the drain of transistor 36A is high, even if the voltage generated by the voltage generating circuit 16 is a high voltage, it can be easily connected to transistor 37, so it is preferred.

[0140] It is preferable to use an OS transistor as the transistor 36A. The OS transistor has a small off-state current and a high withstand voltage between the source and the drain.

[0141] like Fig. 10C , Fig. 10D As shown in FIG. 1 , the voltage holding circuit 35 may use the structure of the voltage holding circuits 35B and 35C. Fig. 10C , Fig. 10D The structure in which the voltage holding circuit is formed using a plurality of transistors 36B and 36C connected in series is shown.

[0142] exist FIG. 11A to FIG. 11E 2, a structural example of a memory cell including an OS transistor which can be used for the memory cell 32 is described. As an example of the structure of a memory cell including an OS transistor, DOSRAM or NOSRAM can be cited as described above.

[0143] Fig.11A An example of a memory cell of a 1T1C (capacitor) type DOSRAM that can be used for the memory cell 32 is shown. Fig.11A The memory cell 32 shown is connected to a wiring WL used as a word line, a wiring BL used as a bit line, a wiring CDL used as a capacitor line, and a wiring BGL used as a wiring for supplying a back gate voltage. The memory cell 32 includes a transistor 37 and a capacitor 38. The back gate of the transistor 37 is connected to the wiring BGL.

[0144] The transistor 37 is an OS transistor. The off-state current of the OS transistor is extremely small. Therefore, the memory cell 32 can reduce the frequency of data refresh. Thus, the power consumption required for data retention can be reduced.

[0145] Fig. 11B An example of a memory cell of a NOSRAM of a two-transistor type (2T) gain cell that can be used for the memory cell 32 is shown. Fig. 11B The memory cell 32A shown includes transistors 37A, 37B, and a capacitor 38. In addition, the capacitor 38 included in the memory cell of the NOSRAM can be omitted by utilizing parasitic capacitance such as the gate capacitance of the transistor. The transistor 37A is a write transistor, and the transistor 37B is a read transistor. The back gates of the transistors 37A and 37B are connected to the wiring BGL.

[0146] Since the write transistor is composed of an OS transistor, the charge corresponding to the data can be continuously retained by turning off the write transistor. Therefore, the memory cell 32A does not consume power when retaining data. Therefore, the memory cell 32A can be used as a low-power memory cell capable of retaining data for a long period of time.

[0147] Reference FIG. 11C to FIG. 11E Other structural examples of memory cells that can be used in NOSRAM are described.

[0148] Fig. 11C The memory cell 32B shown is a 3T-type gain cell and includes transistors 37A, 37B, 37C and a capacitor 38. The transistors 37A, 37B, and 37C are respectively a write transistor, a read transistor, and a select transistor. The back gates of the transistors 37A, 37B, and 37C are connected to the wiring BGL. The memory cell 32B is connected to the wirings RWL, WWL, the wirings RBL, WBL, the wiring CDL, and the power supply line PL2. For example, the wiring CDL and the wiring PL2 are input with a voltage GND (a low-level side power supply voltage).

[0149] Fig.11D Another structural example of a 2T-type gain unit is shown. Fig.11D The storage unit 32C is shown with Fig. 11BThe illustrated memory cell 32A differs in that the readout transistor is composed of an OS transistor that does not include a back gate.

[0150] Fig.11E Another structural example of a 3T-type gain cell is shown. Fig.11E The storage unit 32D is shown with Fig. 11B The memory cell 32A shown is different in that the read transistor and the select transistor are composed of OS transistors that do not include a back gate.

[0151] In the above-mentioned gain cell, a bit line serving also as the wiring RBL and the wiring WBL may be provided.

[0152] When the memory cell 32 is a DOSRAM or NOSRAM, the transistor ( FIG. 11A to FIG. 11E The gate of transistor 37, 37A) is connected to the wiring ( FIG. 11A to FIG. 11E The wiring WL, WWL) of the transistor is applied with a voltage that turns off the transistor and makes other parts power-gated. By adopting this structure, the supply of power supply voltage can be stopped in the state where the memory cell 32 stores data.

[0153] This embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0154] (Implementation Method 2)

[0155] In this embodiment, a structure example is described in which an element layer including an amplifier circuit having a function of amplifying and outputting a data potential retained in the memory cell is provided between element layers of stacked memory cells in a structure using DOSRAM as a memory cell included in the semiconductor device described in the above embodiment.

[0156] [Structural Example of Semiconductor Device]

[0157] Fig.12 1 is a block diagram showing a configuration example of a semiconductor device 10D according to one embodiment of the present invention. Fig.12 The semiconductor device 10D shown includes the element layer 20 and a stacked element layer 70. The stacked element layer 70 includes an element layer 50 including an amplifier circuit 51 in addition to the stacked element layers 30[1] to 30[m].

[0158] Fig.12 The example in which the element layers 30[1] to 30[m] include a plurality of memory cells 32 arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 2) is shown. In addition, as an example, an amplifier circuit 51 is provided for each wiring BL used as a bit line. Fig.12An example is shown in which a plurality of amplifier circuits 51 (amplifier circuit 51 [ 1 ] to amplifier circuit 51 [ n ]) are provided corresponding to n wirings BL.

[0159] exist Fig.12 , the 1st row and 1st column storage cell 32 is represented as storage cell 32[1, 1], and the mth row and nth column storage cell 32 is represented as storage cell 32[m, n]. In addition, in the present embodiment, etc., sometimes "row i" is written to represent an arbitrary row. In addition, sometimes "column j" is written to represent an arbitrary column. Therefore, i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n. In addition, in the present embodiment, etc., the i-th row and j-th column storage cell 32 is represented as storage cell 32[i, j]. In the present embodiment, etc., when expressed as "i+α" (α is a positive integer or a negative integer), "i+α" is not less than 1 and not greater than m. Similarly, when expressed as "j+α", "j+α" is not less than 1 and not greater than n.

[0160] In addition, the element layers 30[1] to 30[m] include m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In the present embodiment and the like, the first (1st row) wiring WL is represented as wiring WL[1], and the mth (mth row) wiring WL is represented as wiring WL[m]. Similarly, the first (1st row) wiring PL is represented as wiring PL[1], and the mth (mth row) wiring PL is represented as wiring PL[m]. Similarly, the first (1st column) wiring BL is represented as wiring BL[1], and the nth (nth column) wiring BL is represented as wiring BL[n].

[0161] The plurality of memory cells 32 arranged in the i-th row are connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The plurality of memory cells 32 arranged in the j-th column are connected to the j-th column wiring BL (wiring BL[j]).

[0162] Wiring BL is used as a bit line for writing and reading data. Wiring WL is used as a word line for controlling the opening or closing (conduction state or non-conduction state) of an access transistor used as a switch. Wiring PL has a function of transmitting a back gate potential to the back gate of an OS transistor used as an access transistor in addition to a function as a constant potential line connected to a capacitor. Wiring CL (not shown) can be separately provided as a wiring for transmitting a back gate potential.

[0163] The memory cells 32 included in the element layers 30[1] to 30[m] are connected to the amplifier circuit 51 through the wiring BL. The wiring BL can be arranged in a direction perpendicular to the surface of the substrate on which the element layer 20 is provided. By arranging the wiring BL extending from the memory cells 32 included in the element layers 30[1] to 30[m] in a direction perpendicular to the substrate surface, the length of the wiring between the element layer 30 and the amplifier circuit 51 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the bit line can be shortened and the resistance and parasitic capacitance of the bit line can be greatly reduced, power consumption and signal delay can be reduced. In addition, even if the capacitance of the capacitor included in the memory cell 32 is reduced, it is possible to operate.

[0164] The amplifier circuit 51 has a function of amplifying the data potential held in the memory cell 32 and outputting it to the sense amplifier 66 included in the element layer 20 through the wiring GBL (not shown) described later. By adopting this structure, a small potential difference of the wiring BL can be amplified when reading data. The wiring GBL can be arranged in a direction perpendicular to the surface of the substrate on which the element layer 20 is provided, similarly to the wiring BL. By arranging the wiring BL and the wiring GBL extending from the memory cell 32 included in the element layers 30[1] to 30[m] in a direction perpendicular to the substrate surface, the length of the wiring between the amplifier circuit 51 and the sense amplifier 66 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the wiring GBL can be shortened and the resistance and parasitic capacitance of the wiring GBL can be greatly reduced, power consumption and signal delay can be reduced.

[0165] The wiring BL is provided in such a manner as to be in contact with the semiconductor layer of the transistor included in the memory cell 32. Alternatively, the wiring BL is provided in such a manner as to be in contact with a region of the semiconductor layer of the transistor included in the memory cell 32 that functions as a source or a drain. Alternatively, the wiring BL is provided in such a manner as to be in contact with a conductor that is in contact with a region of the semiconductor layer of the transistor included in the memory cell 32 that functions as a source or a drain. That is, the wiring BL can be said to be a wiring that vertically connects one of the source and the drain of the transistor included in the memory cell 32 in each layer of the element layer 30 to the amplifier circuit 51.

[0166] The stacked element layer 70 can be overlapped on the element layer 20. By overlapping the element layer 20 and the stacked element layer 70, the signal transmission distance between the element layer 30 and the element layer 50 and between the element layer 20 and the element layer 50 can be shortened. Therefore, the resistance and parasitic capacitance between the element layers are reduced, and the power consumption and signal delay can be reduced. In addition, the miniaturization of the semiconductor device 10D can be achieved.

[0167] By forming the amplifier circuit 51 with OS transistors similarly to the transistors included in the memory cell 32 of the DOSRAM, the amplifier circuit 51 can be freely arranged on a circuit using Si transistors similarly to the element layers 30[1] to 30[m], thereby making it easy to integrate. By adopting a structure in which the amplifier circuit 51 amplifies the signal, the circuit of the subsequent circuit such as the sense amplifier 66 can be miniaturized, thereby miniaturizing the semiconductor device 10D.

[0168] The element layer 20 includes a PSW 71 (power switch), a PSW 72 , and a peripheral circuit 22 . The peripheral circuit 22 includes a drive circuit 61 , a control circuit 73 (control circuit), and a voltage generation circuit 74 .

[0169] In the semiconductor device 10D, the above-mentioned circuits, signals and voltages can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1 and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0170] In addition, the signal BW, the signal CE and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signals PON1 and PON2 are power gating control signals. In addition, the signals PON1 and PON2 can also be generated in the control circuit 73.

[0171] The control circuit 73 is a logic circuit that has the function of controlling the overall operation of the semiconductor device 10D. For example, the control circuit performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, writing operation, reading operation) of the semiconductor device 10D. Alternatively, the control circuit 73 generates a control signal for the drive circuit 61 to execute the above operation mode.

[0172] The voltage generating circuit 74 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 74. For example, when the signal WAKE is applied with an H level signal, the signal CLK is input to the voltage generating circuit 74, and the voltage generating circuit 74 generates a negative voltage.

[0173] The driving circuit 61 is a circuit for writing and reading data to the memory cell 32. In addition, the driving circuit 61 is a circuit for outputting various signals for controlling the amplifier circuit 51. The driving circuit 61 includes a row decoder 62 (RowDecoder), a column decoder 64 (Column Decoder), a row driver 63 (Row Driver), a column driver 65 (ColumnDriver), an input circuit 67 (Input Cir.), an output circuit 68 (Output Cir.), and a sense amplifier 66 (SenseAmplifier).

[0174] The row decoder 62 and the column decoder 64 have the function of decoding the signal ADDR. The row decoder 62 is a circuit for specifying a row to be accessed, and the column decoder 64 is a circuit for specifying a column to be accessed. The row driver 63 has the function of selecting the wiring WL specified by the row decoder 62. The column driver 65 has the following functions: a function of amplifying writing data into the memory cell 32; a function of reading data from the memory cell 32; a function of holding the read data, etc.

[0175] The input circuit 67 has a function of holding a signal WDA. The data held in the input circuit 67 is output to the column driver 65. The output data of the input circuit 67 is the data (Din) written to the memory cell 32. The data (Dout) read from the memory cell 32 by the column driver 65 is output to the output circuit 68. The output circuit 68 has a function of holding Dout. In addition, the output circuit 68 has a function of outputting Dout to the outside of the semiconductor device 10D. The data output from the output circuit 68 is a signal RDA.

[0176] PSW71 has a function of controlling the supply of VDD to the peripheral circuit 22. PSW72 has a function of controlling the supply of VHM to the row driver 63. Here, the high power supply voltage of the semiconductor device 10D is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage for making the word line high, which is higher than VDD. The on / off of PSW71 is controlled by the signal PON1, and the on / off of PSW72 is controlled by the signal PON2. Fig.12 In the embodiment, the number of power domains to which VDD is supplied in the peripheral circuit 22 is one, but it may be more than one. In this case, a power switch may be provided for each power domain.

[0177] The device layers 30 [ 1 ] to 30 [ m ] and the device layer 50 may be overlapped and disposed on the device layer 20 . Fig.13A 1 is a perspective view of a semiconductor device 10D showing a state in which five (m=5) element layers 30 [ 1 ] to 30 [ 5 ] and an element layer 50 are stacked on an element layer 20 .

[0178] exist Fig.13A , the element layer 30 provided in the first layer is referred to as element layer 30[1], the element layer 30 provided in the second layer is referred to as element layer 30[2], and the element layer 30 provided in the fifth layer is referred to as element layer 30[5]. Fig.13A The wiring WL, wiring PL and wiring CL extending in the X direction and the wiring BL extending in the Z direction (a direction perpendicular to the substrate surface on which the driver circuit is provided) are shown. Note that for easier understanding of the drawings, a part of the wiring WL and wiring PL included in each element layer 30 is omitted.

[0179] Fig. 13B Show instructions Fig.13A FIG. 1 is a schematic diagram showing an example of a structure of an amplifier circuit 51 connected to the wiring BL and a memory cell 32 included in the element layers 30 [ 1 ] to 30 [ 5 ] connected to the wiring BL. Fig. 13B The wiring GBL provided between the amplifier circuit 51 and the driver circuit 61 is shown. In addition, the structure connecting one wiring BL to a plurality of memory cells (memory cells 32) is also referred to as a "memory string." Note that in the drawings, the wiring GBL is sometimes shown with a thick line for better visibility.

[0180] Fig. 13B An example of a circuit structure of a memory cell 32 connected to the wiring BL is shown. The memory cell 32 includes a transistor 37 and a capacitor 38. Regarding the transistor 37, the capacitor 38, and each wiring (BL, WL, etc.), for example, the wiring BL[1] and the wiring WL[1] are sometimes referred to as the wiring BL and the wiring WL, etc.

[0181] In the memory cell 32, one of the source and the drain of the transistor 37 is connected to the wiring BL. The other of the source and the drain of the transistor 37 is connected to one electrode of the capacitor 38. The other electrode of the capacitor 38 is connected to the wiring PL. The gate of the transistor 37 is connected to the wiring WL. The back gate of the transistor 37 is connected to the wiring CL.

[0182] Wiring PL is a wiring for supplying a constant potential for maintaining the potential of capacitor 38. Wiring CL is a constant potential for controlling the threshold voltage of transistor 37. The potentials of wiring PL and wiring CL may be equal. At this time, by connecting the two wirings, the number of wirings connected to memory cell 32 can be reduced.

[0183] Fig. 13B The wiring GBL shown is provided so as to connect the amplifier circuit 51 and the drive circuit 61 . Fig.14AFIG. 1 is a schematic diagram showing a semiconductor device 10D including an element layer 70 stacked with an amplifier circuit 51 and element layers 30 [ 1 ] to 30 [ m ] as a repeating unit. Fig.14A Although one wiring GBL is shown in the figure, the wiring GBL may be appropriately provided according to the number of amplifier circuits 51 in the element layer 50 .

[0184] The wiring GBL is provided in such a manner as to be in contact with the semiconductor layer of the transistor included in the amplifier circuit 51. Alternatively, the wiring GBL is provided in such a manner as to be in contact with a region of the semiconductor layer of the transistor included in the amplifier circuit 51 that functions as a source or a drain. Alternatively, the wiring GBL is provided in such a manner as to be in contact with a conductor that is in contact with a region of the semiconductor layer of the transistor included in the amplifier circuit 51 that functions as a source or a drain. That is, the wiring GBL can be said to be a wiring that connects one of the source and the drain of the transistor included in the amplifier circuit 51 of the element layer 50 to the element layer 20 in the vertical direction.

[0185] Alternatively, the semiconductor device 10D_A of one embodiment of the present invention may have a structure in which the element layer 70 including the amplifier circuit 51 and the element layers 30[1] to 30[m] are stacked. Fig. 14B The device shown may include stacked device layers 70 [1] to 70 [p] (p is an integer greater than or equal to 2). The wiring GBL is connected to the device layer 50 included in the stacked device layer 70. The wiring GBL may be appropriately provided according to the number of amplifier circuits 51.

[0186] In one embodiment of the present invention, while stacking OS transistors, wiring used as a bit line is arranged in a direction perpendicular to the substrate surface provided with the element layer 20. By providing the wiring used as a bit line extending from the element layer 30 in a direction perpendicular to the substrate surface, the length of the wiring between the element layer 30 and the element layer 20 can be shortened. Therefore, the parasitic capacitance of the bit line can be greatly reduced.

[0187] One embodiment of the present invention includes an element layer 50 in a layer provided with the element layer 30, and the element layer 50 includes an amplifier circuit 51 having a function of amplifying the data potential held in the memory cell 32 and outputting it. By adopting this structure, a small potential difference of the wiring BL used as a bit line when reading data can be amplified to drive the sense amplifier 66 included in the element layer 20. Since the circuit of the sense amplifier and the like can be miniaturized, the miniaturization of the semiconductor device 10D can be achieved. In addition, the operation can be performed even if the capacitance of the capacitor included in the memory cell 32 is reduced.

[0188] [Configuration Example of Storage Unit 32, Amplifier Circuit 51 and Control Circuit 81]

[0189] Fig.15A , Fig. 15B Show description corresponding Fig. 13B The circuit diagram of the storage unit 32 described in the etc. and the circuit block diagram corresponding to the circuit diagram. Fig.15A , Fig. 15B As shown, sometimes the storage unit 32 is represented as a block in the drawings and the like. Fig.15A , Fig. 15B As shown, the wiring LBL connected to the memory cell 32 may be a wiring LBL used as a local bit line to distinguish it from other wirings used as a bit line. The wiring WL may be a wiring WL used as a word line to distinguish it from other wirings.

[0190] Fig. 15C , Fig.15D Show description corresponding Fig.12 The circuit diagram of the element layer 50 including the amplifier circuit 51 described in the etc. and the circuit block diagram corresponding to the circuit diagram. Fig. 15C , Fig.15D As shown, the amplifier circuit 51 including transistors 52 to 55 is sometimes represented as a block of the amplifier circuit 51 in the drawings and the like. The amplifier circuit 51 has a function of amplifying the potential of the wiring LBL and transmitting the potential of the wiring GBL. The amplifier circuit 51 can perform an operation of correcting a change in the threshold voltage of the transistor 52 by setting a correction period. The wiring GBL can represent the wiring GBL used as a local bit line in order to distinguish it from other wirings used as bit lines. The signals WE, RE, and MUX are control signals for controlling the amplifier circuit 51. The wiring SL is a wiring for supplying a constant potential.

[0191] Fig.16A Show Fig.12 The circuit configuration example of the control circuit 81 including the sense amplifier 66 described in the above etc. The control circuit 81 shows the wiring SA_GBL, wiring SA_GBLB, wiring BL, BLB connected to the switch circuit 82, precharge circuit 83, precharge circuit 84, sense amplifier 66, and control circuit 81.

[0192] like Fig.16A As shown, the switch circuit 82 includes, for example, n-channel transistors 82_1 and 82_2. The transistors 82_1 and 82_2 switch the conduction state between a pair of wirings SA_GBL and SA_GBLB and a pair of wirings BL and BLB in accordance with a signal CSEL.

[0193] like Fig.16A As shown in FIG. 1 , the precharge circuit 83 is composed of n-channel transistors 83_1 to 83_3. The precharge circuit 83 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to the potential VDD / 2 in accordance with the signal EQ.

[0194] like Fig.16A As shown, the precharge circuit 84 is composed of p-channel transistors 84_1 to 84_3. The precharge circuit 84 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to the potential VDD / 2 in accordance with the signal EQB.

[0195] like Fig.16A As shown, the sense amplifier 66 is composed of p-channel transistors 85_1 and 85_2 and n-channel transistors 85_3 and 85_4 connected to wiring SAP or wiring SAN. Wiring SAP or wiring SAN is a wiring having a function of supplying VDD or VSS. Transistors 85_1 to 85_4 are transistors constituting an inverter loop.

[0196] Fig. 16B Show description corresponding Fig.16A FIG. 8 is a diagram of a circuit block of the control circuit 81 described in FIG. Fig. 16B As shown, the control circuit 81 is sometimes represented as a block in drawings and the like.

[0197] Fig.17 Yes Description Fig.12 A circuit diagram of an operating example of a semiconductor device 10D. Fig.17 Show FIG. 15A to FIG. 15D and Fig.16A , Fig. 16B The circuit blocks described in .

[0198] like Fig.17 As shown, the stacked element layer 70 including the element layer 30[m] includes a memory cell 32. The memory cell 32 is connected to a pair of wirings LBL and wiring LBL_pre. The memory cell 32 connected to the wiring LBL is a memory cell to which data is written or read. The wiring LBL_pre is a local bit line to be precharged, and the memory cell 32 connected to the wiring LBL_pre continues to hold data.

[0199] The wiring LBL is connected to the wiring GBL via the amplifier circuit 51. The wiring LBL_pre is connected to the wiring GBLB via the amplifier circuit 51_pre.

[0200] The transistor 97 is used as a switch for switching the conduction state between the wiring GBL and the wiring GBLB. The transistor 97 can be turned on or off by a signal SW0.

[0201] The transistor 98 is used as a switch for switching the conduction state between the wiring GBL and the wiring SA_GBL on the side of the control circuit 81. The transistor 98 can be turned on or off by the signal SW1.

[0202] The transistor 99 is used as a switch for switching the conduction state between the wiring GBLB and the wiring SA_GBLB on the side of the control circuit 81. The transistor 99 can be turned on or off by the signal SW2.

[0203] like Fig.17 As shown, the memory cell 32 may have a structure in which the amplifier circuit 51 is connected to the control circuit 81 through the wiring LBL and the wiring GBL arranged in the shortest vertical direction. Although the element layer 50 including the transistor constituting the amplifier circuit 51 increases, the load of the wiring LBL is reduced, so that the writing time can be shortened and the data can be easily read.

[0204] like Fig.17 As shown, each transistor included in the amplifier circuit 51, 51_pre is controlled according to the signal WE, RE and MUX. Each transistor can output the potential of the wiring LBL to the control circuit 81 through the wiring according to each signal. The amplifier circuit 51, 51_pre can be used as a readout amplifier composed of OS transistors. By adopting this structure, a small potential difference of the wiring LBL can be amplified during reading, and the readout amplifier 66 can be driven.

[0205] [Operation Example of Storage Cell 32, Amplifier Circuit 51 and Control Circuit 81]

[0206] Fig.18 Show instructions Fig.17 The timing diagram of the circuit diagram shown in FIG. 1 also illustrates an example of the operation of the storage unit 32, the amplifier circuit 51 and the control circuit 81. Fig.18 The timing diagram shows the wiring of a pair of wirings SA_GBL and SA_GBLB, and a pair of wirings GBL and GBLB in each case where data is at an H level (data=H) and data is at an L level (data=L).

[0207] exist Fig.18 In the timing chart shown, time T11 to time T13 corresponds to the data writing period. Time T13 to time T16 corresponds to the correction period. Time T16 to time T18 corresponds to the data reading period. Note that the signal CSEL is at the H level during time T11 to T20.

[0208] At time T11, the signals MUX and WE are at H level. The signals SW1 and SW2 are at H level, and the signal SW0 is at L level. Then, by supplying power supply voltage (VDD, VSS) to the wirings SAP and SAN, one of the pair of global bit lines SA_GBL and SA_GBLB, and one of the pair of global bit lines GBL and GBLB are charged. The potential of the wiring LBL rises. The potential of the wiring WL is set to H level and the potential supplied to the wiring LBL ( Fig.18 H level in) is written into the storage unit 32.

[0209] At time T12, the potential of the wiring WL is set to L level. The memory cell 32 holds data.

[0210] At time T13, the wirings SAP and SAN are both set to VDD, the signals EQ and EQB are inverted, and the pair of global bit lines SA_GBL and SA_GBLB and the pair of global bit lines GBL and GBLB are both set to H level. The wiring LBL_pre is precharged to an H level potential. Then, the signal MUX is set to L level. In addition, the signal WE may be set to a low level.

[0211] At time T14, signal RE and signal WE are set to H level. The potential of wiring LBL and the potential of wiring LBL_pre decrease due to discharge through transistor 52. This discharge stops when the voltage between the gate and source of transistor 52 reaches the threshold voltage of transistor 52.

[0212] At time T15, both the signal WE and the signal RE are set to L level. The wiring LBL and the wiring LBL_pre maintain a potential corresponding to the threshold voltage of the transistor 52. EQ and EQB are inverted again to stop precharging. That is, the pair of wiring SA_GBL and the wiring SA_GBLB, and the pair of wiring GBL and the wiring GBLB are in an electrically floating state, i.e., a floating state.

[0213] At time T16, the wiring WL is set to the H level to perform charge sharing. The potential of the wiring LBL changes according to the data written in the memory cell 32. When the H level data is written in the memory cell 32, the potential of the wiring LBL rises, and when the L level data is written in the memory cell 32, the potential of the wiring LBL decreases. On the other hand, since charge sharing using the operation of the wiring WL is not performed in the wiring LBL_pre, the potential does not change.

[0214] At time T17, by setting the signal RE and the signal MUX to the H level, a current flows through the transistor 52 included in the amplifier circuit 51 and the transistor 52 included in the amplifier circuit 51_pre according to the potential of the wiring LBL and the wiring LBL_pre. Since the potential of the wiring LBL and the wiring LBL_pre are different, there is a difference between the current flowing through the transistor 52 included in the amplifier circuit 51 and the current flowing through the transistor 52 included in the amplifier circuit 51_pre. This current difference corresponds to the potential of the wiring LBL changed by charge sharing, that is, the data read from the memory cell 32. Therefore, as Fig.18As shown, the data of the memory cell 32 can be converted into the amount of change in the potential of a pair of wirings SA_GBL and SA_GBLB, and a pair of wirings GBL and GBLB.

[0215] At time T18, signal RE is set to L level. Then, power supply voltage (VDD, VSS) is supplied to wirings SAP and SAN to operate sense amplifier 66. The operation of sense amplifier 66 determines the potentials of a pair of wirings SA_GBL and SA_GBLB, and a pair of wirings GBL and GBLB.

[0216] At time T19, the signal SW0 is set to the L level, the signal SW1 is set to the H level, and the potentials of the pair of wirings GBL and GBLB are switched according to the read data. Specifically, when the data is at the H level, the potentials of the pair of wirings GBL and GBLB are both switched to the H level. In addition, when the data is at the L level, the potentials of the pair of wirings GBL and GBLB are both switched to the L level. By setting the wiring WL to the H level in this state, a voltage corresponding to the logic of the read data can be written into the memory cell 32 again.

[0217] At time T20, signal MUX, wiring WL, and signal WE are set to L level. In memory cell 32, data corresponding to the logic of the read data can be refreshed.

[0218] The semiconductor device 10 according to one embodiment of the present invention has a structure in which the element layer 30 including the memory cell 32 is stacked. With this structure, the wiring LBL can be shortened and the capacitance of the capacitor 38 of the memory cell 32 can be reduced.

[0219] In a semiconductor device of one embodiment of the present invention, an OS transistor with extremely small off-state current is used as a transistor provided in the element layer 30. The OS transistor can be provided in a stacked manner on a substrate provided with an element layer 20 including Si transistors. Therefore, the same manufacturing process can be repeatedly used in the vertical direction for manufacturing, thereby achieving a reduction in manufacturing cost. In addition, in one embodiment of the present invention, the transistor constituting the memory cell 32 can also be arranged in the vertical direction instead of in the planar direction to increase the memory density, thereby achieving miniaturization of the semiconductor device.

[0220] In addition, one embodiment of the present invention includes an element layer 50 including an amplifier circuit 51. In the functional circuit, the wiring LBL is connected to the gate of the transistor 52, so that the transistor 52 can be used as an amplifier. By adopting this structure, the slight potential difference of the wiring LBL can be amplified during reading, and the sense amplifier 66 using the Si transistor can be driven. The circuit such as the sense amplifier 66 using the Si transistor can be miniaturized, thereby miniaturizing the semiconductor device. In addition, even if the capacitance of the capacitor 38 included in the memory cell 32 is reduced, it can work.

[0221] [Variation Examples of Semiconductor Device]

[0222] Next, a case where a CPU including a backup circuit is used as the arithmetic circuit 23 will be described as a modified example of the semiconductor device 10. By combining a CPU register and the like with a backup circuit including an OS transistor, a normally-off CPU (NoffCPU (registered trademark)) can be realized.

[0223] In NoffCPU, the power supply to the circuit that does not need to work in NoffCPU can be stopped, and the circuit can be put into a standby state. In the circuit in the standby state with the power supply stopped, no power is consumed. Therefore, NoffCPU can suppress the power consumption to the minimum.

[0224] Fig.19 The block diagram shows that the CPU 41 and the storage circuit 48 are connected via a bus BUL. The CPU 41 has a function of performing calculations to execute a program.

[0225] Fig.19 The CPU 41 shown in the figure shows a CPU core 42. The CPU core 42 includes a register unit 43 and a calculation unit 44. The register unit 43 includes a flip-flop 47. The flip-flop 47 includes a scan flip-flop 45 and a backup circuit 46.

[0226] Fig.19 The storage circuit 48 shown includes a storage cell array 31 having storage cells 32 , an amplifier circuit 51 , and a driver circuit 61 .

[0227] Fig. 20A An example of a circuit configuration of the flip-flop 47 is shown.

[0228] The scan flip-flop 45 includes a node D1 , Q1 , SD, SE, RT, CK, and a clock buffer circuit 45A.

[0229] Node D1 is a data input node, node Q1 is a data output node, and node SD is an input node for scan test data. Node SE is an input node for signal SCE. Node CK is an input node for clock signal GCLK1. Clock signal GCLK1 is input to clock buffer circuit 45A. The analog switch of scan trigger 45 is connected to nodes CK1 and CKB1 of clock buffer circuit 45A. Node RT is an input node for reset signal. Node SE is an input node for scan enable signal.

[0230] The circuit structure of the scan trigger 45 is not limited to Fig. 20A In addition, triggers prepared in a standard circuit library can also be used.

[0231] The backup circuit 46 includes nodes SD_IN, SN11, transistors M11 to M13, and a capacitor C11.

[0232] The node SD_IN is an input node of scan test data, and is connected to the node Q1 of the scan flip-flop 45. The node SN11 is a holding node of the backup circuit 46. The capacitor C11 is a storage capacitor for holding the voltage of the node SN11.

[0233] Transistor M11 controls the conduction state between node Q1 and node SN11. Transistor M12 controls the conduction state between node SN11 and node SD. Transistor M13 controls the conduction state between node SD_IN and node SD. The on / off of transistors M11 and M13 is controlled by signal BKH, and the on / off of transistor M12 is controlled by signal RCH.

[0234] The transistors M11 to M13 are OS transistors, similar to the transistors included in the memory cell 32 and the amplifier circuit 51. The figure shows that the transistors M11 to M13 have a structure including a back gate. The back gates of the transistors M11 to M13 are electrically connected to a power supply line for supplying the voltage VBG1.

[0235] Preferably, at least transistors M11 and M12 are OS transistors. Due to the extremely small off-state current of the OS transistor, the voltage drop of the node SN11 can be suppressed, and almost no power is consumed when data is retained, so the backup circuit 46 has non-volatile characteristics. Since data is rewritten by charging and discharging the capacitor C11, the backup circuit 46 has no limit on the number of rewrites in principle, and data can be written and read with low energy.

[0236] It is particularly preferred that all transistors of the backup circuit 46 are OS transistors. Fig. 20B As shown, a backup circuit 46 may be stacked on a scan flip-flop 45 formed of a silicon CMOS circuit.

[0237] Compared with the scan flip-flop 45, the backup circuit 46 has a very small number of components, so it is not necessary to change the circuit structure and layout of the scan flip-flop 45 in order to stack the backup circuit 46. In other words, the backup circuit 46 is a backup circuit with very high versatility. In addition, the backup circuit 46 can be provided in an overlapping manner in the area where the scan flip-flop 45 is formed, so that even if the backup circuit 46 is installed, the area overhead of the flip-flop 47 can be made zero. Therefore, by providing the backup circuit 46 in the flip-flop 47, the power gating of the CPU core 42 can be performed. The energy required for power gating is small, so the power gating of the CPU core 42 can be performed efficiently.

[0238] By providing the backup circuit 46, although the parasitic capacitance generated by the transistor M11 is added to the node Q1, it is smaller than the parasitic capacitance generated by the logic circuit connected to the node Q1, and therefore does not affect the operation of the scan flip-flop 45. In other words, even if the backup circuit 46 is provided, the performance of the flip-flop 47 does not substantially decrease.

[0239] As the low power consumption state (non-operating state) of the CPU core 42, for example, a clock gating state, a power gating state, and a sleep state can be set. For example, when shifting from the normal operating state to the clock gating state, the supply of the clock signal GCLK1 is stopped.

[0240] When the CPU core 42 is transferred from the normal working state to the power gating state, the data of the scan flip-flop 45 is backed up to the backup circuit 46. When the CPU core 42 is restored from the power gating state to the normal working state, the data of the backup circuit 46 is written back to the flip-flop 45 again.

[0241] exist Fig.19 In the CPU 41 and storage circuit 48 shown, the transistors included in the backup circuit 46, the amplifier circuit 51 and the storage unit 32 are OS transistors, and the layers including OS transistors can be stacked in a direction perpendicular to the surface of the substrate on which the Si transistors are arranged (also called the z direction).

[0242] Fig.21A is a cross-sectional view schematically showing a stacked layer including a Si transistor and a layer including an OS transistor. Fig.19 The configuration diagram of each component shown in FIG. Fig.21A In the embodiment, a layer SIL including Si transistors and a layer OSL including OS transistors are stacked in the z direction. In the layer OSL including OS transistors, a plurality of layers including OS transistors may be stacked, such as the element layer 50 and the element layer 30 described above. In addition, a wiring layer or the like may be appropriately provided between the layers including transistors.

[0243] exist Fig.21A In the cross-sectional schematic diagram shown, the SIL layer may include Fig.19 The arithmetic unit 44 and the scan trigger 45 of the CPU 41 described in the above and the drive circuit 61 included in the storage circuit 48. In addition, the backup circuit 46 connected to the scan trigger 45 and the amplifier circuit 51 included in the storage circuit 48 can be provided in the element layer 50 provided on the layer SIL. In addition, the memory cell array 31 can be provided in the element layer 30 provided on the element layer 50. Since the memory cells 32 included in the memory cell array 31 can be stacked in a plurality of layers, the memory cells 32 per unit area can be arranged at a high density.

[0244] like Fig.21A As shown, the following structure can be adopted: an element layer 50 including a backup circuit 46 included in the CPU 41 and an amplifier circuit 51 included in the storage circuit 48 is provided on the layer SIL where the SiCMOS circuit can be provided, and an element layer 30 including a storage unit 32 is provided on top of the element layer 50. That is, a structure (on-chip memory) in which a storage circuit 48 such as a DOSRAM is stacked on the CPU 41 in a monolithic manner can be adopted. By adopting the structure of the on-chip memory, the interface part between the CPU and the memory can be operated at high speed. In addition, by adopting the structure of the on-chip memory, the size of the connection wiring etc. can be reduced, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, so the bandwidth of the memory (also called memory bandwidth) can be improved.

[0245] Fig. 21B The semiconductor device 10E shown is a semiconductor device Fig.13A The three-dimensional diagram shown in FIG. 1 is an example of a scan trigger 45 provided in the element layer 20 and a backup circuit 46 provided in the element layer 50. In the element layer 50, by providing the amplifier circuit 51 and the backup circuit 46 in a common layer, the element layer for providing the OS transistor can be reduced. Fig. 21B As shown, the backup circuit 46 can be arranged right above the scan flip-flop 45, and the area in the element layer 50 where the amplifier circuit 51 is not provided can be effectively utilized.

[0246] like Fig.21A and Fig. 21B As shown, by integrating the circuit in three dimensions, the wiring connecting the circuits of each layer can be shortened compared to a stacked structure using a through silicon via (TSV), and the parasitic capacitance of the wiring can be reduced. The power consumption required for charging and discharging each wiring can also be reduced. As a result, the processing efficiency can be improved. In addition, Fig.21A and Fig. 21BThe circuit area can be reduced in the structure shown, thereby achieving low power consumption by miniaturizing the circuit area.

[0247] This embodiment mode can be combined with other embodiment modes described in this specification as appropriate.

[0248] (Implementation method 3)

[0249] In this embodiment, a transistor structure applicable to the semiconductor device described in the above embodiment is described. As an example, a structure in which transistors having different electrical characteristics are stacked is described. By adopting this structure, the degree of freedom in designing the semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the integration of the semiconductor device can be increased.

[0250] Fig. 22 A partial cross-sectional structure of a semiconductor device is shown. Fig. 22 The semiconductor device shown includes a transistor 550 , a transistor 500 , and a capacitor 600 . Fig.23A is a cross-sectional view of the transistor 500 in the channel length direction, Fig. 23B is a cross-sectional view of the transistor 500 in the channel width direction, Fig.23C 2 is a cross-sectional view in the channel width direction of the transistor 550. For example, the transistor 500 corresponds to the Si transistor described in the above embodiment, and the transistor 550 corresponds to the OS transistor.

[0251] exist Fig. 22 In the embodiment, the transistor 500 is disposed above the transistor 550 , and the capacitor 600 is disposed above the transistor 550 and the transistor 500 .

[0252] The transistor 550 is provided on a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of a portion of the substrate 311, and a low resistance region 314a and a low resistance region 314b functioning as a source region or a drain region.

[0253] like Fig.23C As shown, in the transistor 550, the conductor 316 covers the top surface and the side surface in the channel width direction of the semiconductor region 313 via the insulator 315. In this way, by making the transistor 550 have a Fin-type structure, the effective channel width increases, thereby improving the on-state characteristics of the transistor 550. In addition, since the effect of the electric field of the gate electrode can be enhanced, the off-state characteristics of the transistor 550 can be improved.

[0254] Furthermore, transistor 550 may be either a p-channel transistor or an n-channel transistor.

[0255] The channel formation region of the semiconductor region 313 or the region near it, the low resistance region 314a and the low resistance region 314b used as the source region or the drain region preferably include semiconductors such as silicon-based semiconductors, and more preferably include single crystal silicon. In addition, it can also be formed using materials including Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenic), etc. Silicon that controls the effective mass by subjecting the lattice to stress to change the interplanar spacing can be used. In addition, the transistor 550 can also be a HEMT (High Electron Mobility Transistor) using GaAs and GaAlAs, etc.

[0256] The low resistance regions 314 a and 314 b contain, in addition to the semiconductor material used for the semiconductor region 313 , an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron.

[0257] As the conductor 316 serving as the gate electrode, a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material containing an element imparting n-type conductivity such as arsenic and phosphorus or an element imparting p-type conductivity such as boron can be used.

[0258] In addition, since the material of the conductor determines the work function, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, materials such as titanium nitride or tantalum nitride are preferably used as the conductor. In order to have both conductivity and embeddability, a stack of metal materials such as tungsten or aluminum is preferably used as the conductor, and tungsten is particularly preferred in terms of heat resistance.

[0259] Alternatively, the transistor 550 may be formed using a SOI (Silicon on Insulator) substrate or the like.

[0260] In addition, as SOI substrates, there can be used: SIMOX (Separation by Implanted Oxygen) substrates formed by forming an oxide layer in a region at a certain depth from the surface and eliminating defects generated in the surface layer after oxygen ion implantation in a mirror-polished thin slice, and SOI substrates formed by the smart peeling method or ELTRAN method (registered trademark: Epitaxial Layer Transfer) in which a semiconductor substrate is split by growing tiny gaps formed by hydrogen ion implantation through heat treatment. A transistor formed using a single crystal substrate includes a single crystal semiconductor in a channel formation region.

[0261] An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order so as to cover the transistor 550 .

[0262] As the insulator 320 , the insulator 322 , the insulator 324 , and the insulator 326 , for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used.

[0263] Note that in this specification, silicon oxynitride refers to a material containing more oxygen than nitrogen in its composition, and silicon nitride oxide refers to a material containing more nitrogen than oxygen in its composition. Note that in this specification, aluminum oxynitride refers to a material containing more oxygen than nitrogen, and aluminum nitride oxide refers to a material containing more nitrogen than oxygen.

[0264] The insulator 322 may also be used as a planarization film for planarizing a step generated by the transistor 550 disposed thereunder, etc. For example, in order to improve the planarity of the top surface of the insulator 322, the top surface may be planarized by a planarization process such as a chemical mechanical polishing (CMP) method.

[0265] As the insulator 324 , a film having a barrier property that can prevent hydrogen, impurities, and the like from diffusing from the substrate 311 , the transistor 550 , or the like into a region where the transistor 500 is provided is preferably used.

[0266] As an example of a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor such as transistor 500, resulting in a decrease in the characteristics of the semiconductor element. Therefore, it is preferred to provide a film that inhibits the diffusion of hydrogen between transistor 500 and transistor 550. Specifically, the film that inhibits the diffusion of hydrogen refers to a film with a small amount of hydrogen released.

[0267] The amount of hydrogen released can be measured, for example, by thermal desorption spectroscopy (TDS). For example, when the amount of hydrogen released is converted to the amount per unit area of ​​the insulator 324 when the film surface temperature in the TDS analysis is in the range of 50°C to 500°C, the amount of hydrogen released from the insulator 324 is 1×10 16 atoms / cm 2 Below, preferably 5×10 15 atoms / cm 2 The following is enough.

[0268] Note that the dielectric constant of the insulator 326 is preferably lower than that of the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably lower than 4, more preferably lower than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0269] In addition, conductors 328 and 330 connected to capacitor 600 and transistor 500 are embedded in insulators 320, 322, 324, and 326. In addition, conductors 328 and 330 have the function of plugs or wiring. Note that the same symbol is sometimes used to represent a plurality of conductors having the function of plugs or wiring. In addition, in this specification, wiring and a plug connected to wiring may also be one component. That is, a part of a conductor is sometimes used as wiring, and a part of a conductor is sometimes used as a plug.

[0270] As the material of each plug and wiring (conductor 328, conductor 330, etc.), a single layer or a laminate of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used. It is preferred to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferably used. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0271] Alternatively, a wiring layer may be provided on the insulator 326 and the conductor 330. Fig. 22 In the embodiment of the present invention, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed between the insulator 350, the insulator 352, and the insulator 354. The conductor 356 has a function of a plug or wiring connected to the transistor 550. The conductor 356 can be made of the same material as the conductor 328 and the conductor 330.

[0272] In addition, similar to the insulator 324, the insulator 350 preferably uses an insulator having a barrier property to hydrogen, for example. In addition, the conductor 356 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion of the insulator 350 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, thereby suppressing the diffusion of hydrogen from the transistor 550 to the transistor 500.

[0273] Note that as a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is preferably used. Furthermore, by stacking tantalum nitride and tungsten having high conductivity, it is possible to maintain the conductivity as a wiring and suppress the diffusion of hydrogen from the transistor 550. At this time, the tantalum nitride layer having a barrier property against hydrogen is preferably in contact with the insulator 350 having a barrier property against hydrogen.

[0274] Alternatively, a wiring layer may be provided on the insulator 354 and the conductor 356. Fig. 22 In the embodiment, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. In addition, a conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 has a function of a plug or wiring. In addition, the conductor 366 can use the same material as the conductor 328 and the conductor 330.

[0275] In addition, similar to the insulator 324, the insulator 360 preferably uses an insulator having a barrier property to hydrogen. In addition, the conductor 366 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion of the insulator 360 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, thereby suppressing the diffusion of hydrogen from the transistor 550 to the transistor 500.

[0276] Alternatively, a wiring layer may be provided on the insulator 364 and the conductor 366. Fig. 22 In the embodiment, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. In addition, a conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 has a function of a plug or wiring. In addition, the conductor 376 can use the same material as the conductor 328 and the conductor 330.

[0277] In addition, similar to the insulator 324, the insulator 370 preferably uses an insulator having a barrier property to hydrogen. In addition, the conductor 376 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion of the insulator 370 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, thereby suppressing the diffusion of hydrogen from the transistor 550 to the transistor 500.

[0278] Alternatively, a wiring layer may be provided on the insulator 374 and the conductor 376. Fig. 22In the embodiment, an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. In addition, a conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 has a function of a plug or wiring. In addition, the conductor 386 can use the same material as the conductor 328 and the conductor 330.

[0279] In addition, similar to the insulator 324, the insulator 380 preferably uses an insulator having a barrier property to hydrogen. In addition, the conductor 386 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion of the insulator 380 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 500 using a barrier layer, so that the diffusion of hydrogen from the transistor 550 to the transistor 500 can be suppressed.

[0280] In the above description, the wiring layer including the conductor 356, the wiring layer including the conductor 366, the wiring layer including the conductor 376, and the wiring layer including the conductor 386 are described, but the semiconductor device according to the present embodiment is not limited thereto. The number of wiring layers similar to the wiring layer including the conductor 356 may be three or less, and the number of wiring layers similar to the wiring layer including the conductor 356 may be five or more.

[0281] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are sequentially stacked on the insulator 384. As any of the insulators 510, 512, 514, and 516, a substance having a barrier property against oxygen, hydrogen, and the like is preferably used.

[0282] For example, a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 311 or a region where the transistor 550 is provided to a region where the transistor 500 is provided is preferably used as the insulator 510 and the insulator 514. Therefore, the insulator 510 and the insulator 514 can be made of the same material as the insulator 324.

[0283] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor such as transistor 500, resulting in a decrease in the characteristics of the semiconductor element. Therefore, it is preferred to provide a film that inhibits the diffusion of hydrogen between transistor 550 and transistor 500.

[0284] For example, as a film having a barrier property against hydrogen, the insulator 510 and the insulator 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0285] In particular, aluminum oxide has a high barrier effect of preventing oxygen and impurities such as hydrogen and moisture that cause changes in the electrical characteristics of the transistor from passing through. Therefore, during and after the manufacturing process of the transistor, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500. In addition, aluminum oxide can suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0286] For example, the insulator 512 and the insulator 516 can use the same material as the insulator 320. In addition, by using a material with a low dielectric constant for the insulator, the parasitic capacitance generated between wirings can be reduced. For example, the insulator 512 and the insulator 516 can use a silicon oxide film, a silicon oxynitride film, or the like.

[0287] In addition, a conductor 518 or a conductor (for example, the conductor 503) constituting the transistor 500 is embedded in the insulator 510, the insulator 512, the insulator 514, and the insulator 516. The conductor 518 is used as a plug or wiring connected to the capacitor 600 or the transistor 550. The conductor 518 can be made of the same material as the conductor 328 and the conductor 330.

[0288] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor having a barrier property to oxygen, hydrogen, and water. With this structure, the transistor 550 can be separated from the transistor 500 by a layer having a barrier property to oxygen, hydrogen, and water, thereby suppressing the diffusion of hydrogen from the transistor 550 into the transistor 500.

[0289] The transistor 500 is provided above the insulator 516 .

[0290] like Fig.23A and Fig. 23B As shown, transistor 500 includes a conductor 503 configured in a manner of embedding insulator 514 and insulator 516, an insulator 520 configured on insulator 516 and conductor 503, an insulator 522 configured on insulator 520, an insulator 524 configured on insulator 522, an oxide 530a configured on insulator 524, an oxide 530b configured on oxide 530a, a conductor 542a and a conductor 542b configured separately from each other on oxide 530b, an insulator 580 configured on conductor 542a and conductor 542b and forming an opening in a manner overlapping between conductor 542a and conductor 542b, an insulator 545 configured on the bottom and side surfaces of the opening, and a conductor 560 configured on the formation surface of insulator 545.

[0291] In addition, if Fig.23A and Fig. 23BAs shown in FIG. 5 , an insulator 544 is preferably disposed between the oxide 530a, the oxide 530b, the conductor 542a, the conductor 542b, and the insulator 580. Fig.23A and Fig. 23B As shown in FIG. 5 , the conductor 560 preferably includes a conductor 560a disposed inside the insulator 545 and a conductor 560b disposed in a manner embedded inside the conductor 560a. Fig.23A and Fig. 23B As shown, an insulator 574 is preferably arranged on the insulator 580 , the conductor 560 , and the insulator 545 .

[0292] Note that in this specification and the like, the oxide 530 a and the oxide 530 b may be collectively referred to as an oxide 530 .

[0293] In the transistor 500, two layers of oxide 530a and oxide 530b are stacked in the channel forming region and its vicinity, but the present invention is not limited thereto. For example, the oxide 530b may have a single layer structure or a stacked structure of three or more layers.

[0294] In addition, in the transistor 500, the conductor 560 has a two-layer structure, but the present invention is not limited to this. For example, the conductor 560 may also have a single-layer structure or a stacked structure of three or more layers. Note that Fig. 22 and Fig.23A The structure of the transistor 500 shown is only an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure or driving method.

[0295] Here, the conductor 560 is used as the gate electrode of the transistor, and the conductor 542a and the conductor 542b are used as the source electrode or the drain electrode. As described above, the conductor 560 is set in a manner embedded in the opening of the insulator 580 and in the area sandwiched between the conductor 542a and the conductor 542b. The configuration of the conductor 560, the conductor 542a, and the conductor 542b is selected in a self-aligned manner according to the opening of the insulator 580. In other words, in the transistor 500, the gate electrode can be configured in a self-aligned manner between the source electrode and the drain electrode. Thus, the conductor 560 can be formed in a manner without providing room for alignment, so that the occupied area of ​​the transistor 500 can be reduced. Thus, miniaturization and high integration of semiconductor devices can be achieved.

[0296] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not include a region overlapping with the conductor 542a or the conductor 542b. Thus, the parasitic capacitance formed between the conductor 560 and the conductors 542a and 542b can be reduced. Therefore, the switching speed of the transistor 500 can be increased, so that the transistor 500 can have high frequency characteristics.

[0297] Conductor 560 is sometimes used as a first gate (also called a top gate) electrode. Conductor 503 is sometimes used as a second gate (also called a bottom gate) electrode. In this case, the threshold voltage of transistor 500 can be controlled by independently changing the potential supplied to conductor 503 without linking it with the potential supplied to conductor 560. In particular, by supplying a negative potential to conductor 503, the threshold voltage of transistor 500 can be made to exceed 0V to reduce the off-state current. Therefore, compared with when no negative potential is applied to conductor 503, when a negative potential is applied to conductor 503, the drain current when the potential applied to conductor 560 is 0V can be reduced.

[0298] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated by the conductor 560 and the electric field generated by the conductor 503 are connected to each other, and a channel formation region formed in the oxide 530 can be covered.

[0299] In this specification, etc., the structure of a transistor in which the electric field of the first gate electrode electrically surrounds the channel forming region is called a surrounded channel (S-channel) structure. In addition, the S-channel structure disclosed in this specification, etc. has a structure different from the Fin-type structure and the planar structure. On the other hand, the S-channel structure disclosed in this specification, etc. can also be regarded as a kind of Fin-type structure. In this specification, etc., the Fin-type structure refers to a structure in which the gate electrode is configured in a manner of surrounding at least two or more surfaces of the channel (specifically, two surfaces, three surfaces or four surfaces, etc.). By adopting the Fin-type structure and the S-channel structure, a transistor with improved resistance to short channel effects can be realized. In other words, a transistor that is not prone to short channel effects can be realized.

[0300] By adopting a transistor having the above-mentioned S-channel structure, the channel formation region can be electrically surrounded. In addition, the S-channel structure can also be said to be substantially equal to the GAA (Gate All Around: full surround gate) structure or the LGAA (Lateral Gate All Around: lateral full surround gate) structure because it electrically surrounds the channel formation region. By making the transistor have an S-channel structure, a GAA structure or a LGAA structure, the channel formation region formed at or near the interface between the oxide 530 and the gate insulator can be set in the entire bulk of the oxide 530. Therefore, the current density flowing through the transistor can be increased, so it can be expected that the on-state current of the transistor or the field effect mobility of the transistor can be improved.

[0301] In addition, the conductor 503 has the same structure as the conductor 518, and the conductor 503a is formed in contact with the inner wall of the opening of the insulator 514 and the insulator 516, and the conductor 503b is formed on the conductor 503a in a manner embedded in the opening. In addition, in the transistor 500, the conductor 503a and the conductor 503b are stacked, but the present invention is not limited to this. For example, the conductor 503 may have a single-layer structure or a stacked structure of three or more layers.

[0302] Here, as the conductor 503a, it is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (not allowing the above impurities to pass through easily). In addition, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (not allowing the above oxygen to pass through easily). In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the above impurities and the above oxygen.

[0303] For example, by providing the conductor 503a with a function of suppressing the diffusion of oxygen, a decrease in conductivity due to oxidation of the conductor 503b can be suppressed.

[0304] In addition, when the conductor 503 also has a wiring function, it is preferable to use a conductive material with high conductivity whose main component is tungsten, copper or aluminum as the conductor 503b. In addition, although the conductor 503 composed of a stack of conductors 503a and 503b is shown in this embodiment, the conductor 503 may also have a single-layer structure.

[0305] The insulator 520 , the insulator 522 , and the insulator 524 serve as a second gate insulating film.

[0306] Here, the insulator 524 in contact with the oxide 530 preferably contains oxygen exceeding the stoichiometric composition. This oxygen is easily released from the film by heating. In this specification, etc., the oxygen released by heating is sometimes referred to as "excess oxygen". That is, it is preferred that a region containing excess oxygen (also referred to as "excess oxygen region") is formed in the insulator 524. By providing the insulator containing excess oxygen in contact with the oxide 530, the oxygen vacancies (V O : oxygen vacancy), thereby improving the reliability of the transistor 500. In addition, when hydrogen enters the oxygen vacancy of the oxide 530, the defect (hereinafter, sometimes referred to as V O H) is used as a donor to generate electrons as carriers. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to the oxygen bonded to the metal atom. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have a normally-on characteristic. In addition, since hydrogen in oxide semiconductors is easily moved due to heat, electric field, etc., when oxide semiconductors contain a large amount of hydrogen, the reliability of the transistor may be reduced. In one embodiment of the present invention, it is preferred to minimize the V O H and become high purity intrinsic or substantially high purity intrinsic. In this way, in order to obtain such V O For an oxide semiconductor with sufficiently reduced H, it is important to: remove impurities such as water and hydrogen in the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment); and supply oxygen to the oxide semiconductor to fill oxygen vacancies (sometimes referred to as oxidation treatment). O An oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, and can provide stable electrical characteristics.

[0307] Specifically, as an insulator having an excess oxygen region, an oxide material from which a portion of oxygen is released by heating is preferably used. An oxide from which oxygen is released by heating means that the amount of oxygen released in terms of oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis is 1.0×10 18 atoms / cm 3 Above, preferably 1.0×10 19 atoms / cm 3 More preferably, 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3Furthermore, the surface temperature of the film when performing the above-mentioned TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C.

[0308] In addition, any one or more of heat treatment, microwave treatment, or RF treatment may be performed in such a manner that the insulator having the excess oxygen region and the oxide 530 are in contact with each other. By performing this treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 in which VoH bonding is severed, in other words, a “V O H→Vo+H” reaction can be dehydrogenated. A part of the hydrogen generated at this time may be bonded with oxygen and removed from the oxide 530 or the insulator near the oxide 530 as H 2 O. In addition, a part of hydrogen may be gettered by the conductors 542a and 542b.

[0309] In addition, as the above-mentioned microwave treatment, for example, it is preferred to use a device including a power supply for generating high-density plasma or a device including a power supply for applying RF to one side of the substrate. For example, by using a gas containing oxygen and a high-density plasma, a high-density oxygen radical can be generated, and by applying RF to one side of the substrate, the oxygen radical generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530. In addition, in the above-mentioned microwave treatment, the pressure is 133 Pa or more, preferably 200 Pa or more, and more preferably 400 Pa or more. In addition, as the gas introduced into the device for performing microwave treatment, for example, oxygen and argon are used, and the oxygen flow ratio (O / ) is 1:1. 2 / (O 2 +Ar)) is 50% or less, preferably 10% or more and 30% or less.

[0310] In addition, in the manufacturing process of transistor 500, it is preferred to perform heat treatment in a state where the surface of oxide 530 is exposed. The heat treatment can be performed, for example, at a temperature of 100°C or higher and 450°C or lower, more preferably 350°C or higher and 400°C or lower. In addition, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. Thus, oxygen can be supplied to oxide 530 to reduce oxygen vacancies (V O). In addition, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen or an inert gas, and then the heat treatment may be performed in an atmosphere of an oxidizing gas containing 10 ppm or more, 1% or more, or 10% or more to fill the oxygen that has been separated. Alternatively, the heat treatment may be performed in an atmosphere of an oxidizing gas containing 10 ppm or more, 1% or more, or 10% or more, and then the heat treatment may be performed continuously in an atmosphere of nitrogen or an inert gas.

[0311] In addition, by performing an oxidation treatment on the oxide 530, the supplied oxygen can fill the oxygen vacancies in the oxide 530. In other words, the reaction of "Vo+O→null" can be promoted. Furthermore, by reacting the hydrogen remaining in the oxide 530 with the supplied oxygen, the hydrogen can be removed as H 2 O (dehydration). This can prevent the hydrogen remaining in the oxide 530 from re-bonding with oxygen vacancies to form V O H.

[0312] When the insulator 524 has an excess oxygen region, the insulator 524 preferably has a function of suppressing diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (making it difficult for the oxygen to permeate).

[0313] When the insulator 522 has a function of suppressing diffusion of oxygen, impurities, and the like, it is preferable because oxygen included in the oxide 530 does not diffuse toward the insulator 520. In addition, reaction between the conductor 503 and oxygen included in the insulator 524 or the oxide 530 can be suppressed.

[0314] As the insulator 522, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ) or (Ba, Sr)TiO 3 A single layer or stack of insulators made of so-called high-k materials such as (BST). When miniaturization and high integration of transistors are being promoted, problems such as off-state current may occur due to the thinning of the gate insulating film. By using a high-k material as an insulator used as a gate insulating film, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0315] In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium as an insulating material having a function of suppressing the diffusion of impurities and oxygen (not allowing the above oxygen to pass easily). As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. When the insulator 522 is formed using such a material, the insulator 522 is used as a layer that suppresses the release of oxygen from the oxide 530 or the entry of impurities such as hydrogen into the oxide 530 from the surrounding part of the transistor 500.

[0316] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. In addition, the insulator may be nitrided. In addition, silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

[0317] The insulator 520 preferably has thermal stability. For example, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In addition, by combining an insulator of a high-k material with silicon oxide or silicon oxynitride, an insulator 520 having a laminated structure with thermal stability and a high relative dielectric constant can be formed.

[0318] In addition, Fig.23A and Fig. 23B In the transistor 500, the insulator 520, the insulator 522, and the insulator 524 are shown as the second gate insulating film having a three-layer stacked structure, but the second gate insulating film may also have a single-layer structure, a two-layer structure, or a stacked structure of four or more layers. In this case, the stacked structure is not limited to being made of the same material, and a stacked structure made of different materials may be used.

[0319] In the transistor 500 , a metal oxide that functions as an oxide semiconductor is used as the oxide 530 including a channel formation region.

[0320] The metal oxide used as the oxide semiconductor may be formed by a sputtering method or an ALD (Atomic Layer Deposition) method. The metal oxide used as the oxide semiconductor will be described in detail in other embodiments.

[0321] The metal oxide used as the channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0322] In the oxide 530 , when the oxide 530 a is provided below the oxide 530 b , diffusion of impurities from a structure formed below the oxide 530 a to the oxide 530 b can be suppressed.

[0323] In addition, the oxide 530 preferably has a structure of multiple oxide layers in which the atomic number ratios of the metal atoms are different from each other. Specifically, the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 530a is preferably greater than the atomic number ratio of the element M in the constituent elements of the metal oxide used for the oxide 530b. In addition, the atomic number ratio of the element M relative to In in the metal oxide used for the oxide 530a is preferably greater than the atomic number ratio of the element M relative to In in the metal oxide used for the oxide 530b. In addition, the atomic number ratio of In in the metal oxide used for the oxide 530b is preferably greater than the atomic number ratio of In in the metal oxide used for the oxide 530a.

[0324] It is preferred that the energy of the conduction band bottom of oxide 530a be higher than that of the conduction band bottom of oxide 530b. In other words, the electron affinity of oxide 530a is preferably lower than that of oxide 530b.

[0325] Here, in the junction of oxide 530a and oxide 530b, the energy level of the conduction band bottom changes smoothly. In other words, the above situation can also be expressed as the energy level of the conduction band bottom of the junction of oxide 530a and oxide 530b continuously changes or continuously joins. For this reason, it is preferable to reduce the defect state density of the mixed layer formed at the interface between oxide 530a and oxide 530b.

[0326] Specifically, by making the oxide 530a and the oxide 530b contain a common element (as a main component) in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, it is preferable to use In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. as the oxide 530a.

[0327] At this time, the main path of the carrier is oxide 530b. By making oxide 530a have the above structure, the defect state density at the interface between oxide 530a and oxide 530b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the on-state current of transistor 500 can be increased.

[0328] Conductors 542a and 542b serving as a source electrode and a drain electrode are provided on the oxide 530b. As the conductors 542a and 542b, metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, alloys containing the above metal elements as components, or alloys combining the above metal elements are preferably used. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, and the like are preferably used. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred. Metal nitride films such as tantalum nitride have barrier properties against hydrogen or oxygen, so they are more preferred.

[0329] In addition, although Fig.23A Although the single-layer structure of the conductor 542a and the conductor 542b is shown, a stacked structure of two or more layers may be adopted. For example, it is preferable to stack a tantalum nitride film and a tungsten film. In addition, a titanium film and an aluminum film may be stacked. In addition, a two-layer structure of stacking an aluminum film on a tungsten film, a two-layer structure of stacking a copper film on a copper-magnesium-aluminum alloy film, a two-layer structure of stacking a copper film on a titanium film, and a two-layer structure of stacking a copper film on a tungsten film may also be adopted.

[0330] In addition, a three-layer structure may be used in which an aluminum film or a copper film is stacked on a titanium film or a titanium nitride film and a titanium film or a titanium nitride film is formed thereon, a three-layer structure may be used in which an aluminum film or a copper film is stacked on a molybdenum film or a molybdenum nitride film and a molybdenum film or a molybdenum nitride film is formed thereon, etc. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

[0331] In addition, if Fig.23A As shown, sometimes, a region 543a and a region 543b are formed as a low resistance region at the interface between the oxide 530 and the conductor 542a (conductor 542b) and in the vicinity thereof. In this case, the region 543a is used as one of the source region and the drain region, and the region 543b is used as the other of the source region and the drain region. In addition, a channel formation region is formed in a region sandwiched between the region 543a and the region 543b.

[0332] The oxygen concentration of the region 543a (region 543b) may be reduced by providing the above-mentioned conductor 542a (conductor 542b) in contact with the oxide 530. In addition, a metal compound layer containing a metal contained in the conductor 542a (conductor 542b) and a component of the oxide 530 may be formed in the region 543a (region 543b). In this case, the carrier concentration of the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low resistance region.

[0333] The insulator 544 is provided so as to cover the conductors 542 a and 542 b to suppress oxidation of the conductors 542 a and 542 b. In this case, the insulator 544 may be provided so as to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0334] The insulator 544 can be made of a metal oxide containing one or more metals selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, or magnesium. Alternatively, the insulator 544 can be made of silicon nitride oxide or silicon nitride.

[0335] In particular, as the insulator 544, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., which are insulators containing oxides of one or both of aluminum and hafnium, are preferably used. In particular, hafnium aluminate has higher heat resistance than hafnium oxide film. Therefore, it is not easy to crystallize in the heat treatment of the subsequent process, so it is preferred. In addition, insulator 544 does not necessarily need to be provided when conductor 542a and conductor 542b are composed of a material having oxidation resistance or a material whose conductivity does not significantly decrease even when oxygen is absorbed. It can be appropriately designed according to the required transistor characteristics.

[0336] By including the insulator 544, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in the insulator 580 into the oxide 530b. In addition, it is possible to suppress the oxidation of the conductors 542a and 542b by excess oxygen contained in the insulator 580.

[0337] The insulator 545 is used as a first gate insulating film. The insulator 545 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating, similarly to the insulator 524 described above.

[0338] Specifically, silicon oxide containing excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and silicon oxide having pores can be used. In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability.

[0339] By providing an insulator containing excess oxygen as the insulator 545, oxygen can be effectively supplied to the channel formation region of the oxide 530b from the insulator 545. In addition, as with the insulator 524, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 545. The thickness of the insulator 545 is preferably not less than 1 nm and not more than 20 nm.

[0340] In addition, in order to efficiently supply the excess oxygen contained in the insulator 545 to the oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 545 to the conductor 560. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of excess oxygen from the insulator 545 to the conductor 560 is suppressed. In other words, the amount of excess oxygen supplied to the oxide 530 can be suppressed from decreasing. In addition, the oxidation of the conductor 560 due to the excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 can be used.

[0341] In addition, like the second gate insulating film, the insulator 545 may also have a stacked structure. When miniaturization and high integration of transistors are performed, sometimes the thinning of the gate insulating film leads to problems such as off-state current. Therefore, by using the insulator used as the gate insulating film to have a stacked structure of a high-k material and a material with thermal stability, the gate potential of the transistor during operation can be reduced while maintaining the physical thickness. In addition, a stacked structure with thermal stability and a high relative dielectric constant can be achieved.

[0342] exist Fig.23A and Fig. 23B In the embodiment, the conductor 560 serving as the first gate electrode has a two-layer structure, but may have a single-layer structure or a stacked-layer structure of three or more layers.

[0343] As the conductor 560a, it is preferable to use a conductor having a property of suppressing hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2, etc.), a conductive material having the function of inhibiting the diffusion of impurities such as copper atoms. In addition, it is preferred to use a conductive material having the function of inhibiting the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). By making the conductor 560a have the function of inhibiting the diffusion of oxygen, it is possible to inhibit the oxidation of the conductor 560b due to the oxygen contained in the insulator 545 and the decrease in conductivity. As a conductive material having the function of inhibiting the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium or ruthenium oxide is preferably used. In addition, as the conductor 560a, an oxide semiconductor that can be applied to the oxide 530 can be used. In this case, by forming the conductor 560b by a sputtering method, the resistance value of the conductor 560a can be reduced to make it a conductor. It can be called an OC (Oxide Conductor) electrode.

[0344] As the conductor 560b, a conductive material mainly composed of tungsten, copper or aluminum is preferably used. Since the conductor 560b is also used as wiring, it is preferable to use a conductor with high conductivity. The conductor 560b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive materials may be used.

[0345] The insulator 580 is preferably disposed on the conductor 542a and the conductor 542b via the insulator 544. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores, or resin. In particular, silicon oxide and silicon oxynitride are thermally stable and therefore are preferred. In particular, silicon oxide and silicon oxide with pores are preferred because they are easy to form an excess oxygen region in the subsequent process.

[0346] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580 that releases oxygen by heating, the oxygen in the insulator 580 can be efficiently supplied to the oxide 530. In addition, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 580.

[0347] The opening of the insulator 580 is formed so as to overlap with the region between the conductor 542a and the conductor 542b. Thus, the conductor 560 is provided so as to be embedded in the opening of the insulator 580 and in the region between the conductor 542a and the conductor 542b.

[0348] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is necessary to prevent the conductivity of the conductor 560 from decreasing. For this reason, when the thickness of the conductor 560 is increased, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, since the conductor 560 is provided in a manner embedded in the opening of the insulator 580, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 does not collapse during the process.

[0349] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. By forming the insulator 574 by sputtering, an excess oxygen region can be formed in the insulator 545 and the insulator 580. Thus, oxygen can be supplied to the oxide 530 from the excess oxygen region.

[0350] For example, as the insulator 574, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used.

[0351] In particular, aluminum oxide has high barrier properties and can inhibit the diffusion of hydrogen and nitrogen even in a thin film of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can be used as an oxygen supply source while also functioning as a barrier film for impurities such as hydrogen.

[0352] Furthermore, an insulator 581 serving as an interlayer film is preferably provided over the insulator 574. As with the insulator 524 and the like, the concentration of impurities such as water and hydrogen in the insulator 581 is preferably reduced.

[0353] In addition, the conductors 540a and 540b are arranged in the openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductors 540a and 540b are provided so as to face each other via the conductor 560. The conductors 540a and 540b have the same structure as the conductors 546 and 548 described later.

[0354] An insulator 582 is provided on the insulator 581. The insulator 582 is preferably made of a material having a barrier property against oxygen, hydrogen, and the like. Therefore, the insulator 582 can be made of the same material as the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0355] In particular, aluminum oxide has a high barrier effect of preventing oxygen and impurities such as hydrogen and moisture that cause changes in the electrical characteristics of the transistor from passing through. Therefore, during and after the manufacturing process of the transistor, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500. In addition, aluminum oxide can suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0356] In addition, an insulator 586 is provided on the insulator 582. As the insulator 586, the same material as the insulator 320 can be used. In addition, by using a material with a low dielectric constant as these insulators, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulator 586, a silicon oxide film or a silicon oxynitride film can be used.

[0357] In addition, the conductor 546 and the conductor 548 are embedded in the insulator 520 , the insulator 522 , the insulator 524 , the insulator 544 , the insulator 580 , the insulator 574 , the insulator 581 , the insulator 582 , and the insulator 586 .

[0358] The conductor 546 and the conductor 548 are used as plugs or wirings connected to the capacitor 600, the transistor 500, or the transistor 550. The conductor 546 and the conductor 548 can be made of the same material as the conductor 328 and the conductor 330.

[0359] In addition, after forming the transistor 500, an opening may be formed around the transistor 500, and an insulator having a high barrier to hydrogen or water may be formed to cover the opening. By wrapping the transistor 500 with the above-mentioned high barrier insulator, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be wrapped with an insulator having a high barrier to hydrogen or water. In addition, in the case of forming an opening around the transistor 500, for example, when an opening is formed to reach the insulator 522 or the insulator 514 and the above-mentioned high barrier insulator is formed in contact with the insulator 522 or the insulator 514, it can also serve as a part of the manufacturing process of the transistor 500, so it is preferred. In addition, as an insulator having a high barrier to hydrogen or water, for example, the same material as the insulator 522 or the insulator 514 can be used.

[0360] The transistors that can be used in the present invention are not limited to Fig.23A and Fig. 23B The transistor 500 shown. For example, it is also possible to use Fig.24 A transistor 500 having a structure as shown. Fig.24 The transistor 500 is shown with Fig.23A and Fig. 23BThe transistor shown is different in that an insulator 555 is used and the conductor 542a (conductor 542a1 and conductor 542a2) and the conductor 542b (conductor 542b1 and conductor 542b2) have a stacked-layer structure.

[0361] The conductor 542a has a laminated structure of a conductor 542a1 and a conductor 542a2 on the conductor 542a1, and the conductor 542b has a laminated structure of a conductor 542b1 and a conductor 542b2 on the conductor 542b1. The conductors 542a1 and 542b1 in contact with the oxide 530b are preferably conductors that are not easily oxidized, such as metal nitrides. Thus, the conductors 542a and 542b can be prevented from being excessively oxidized by oxygen contained in the oxide 530b. In addition, the conductors 542a2 and 542b2 are preferably conductors such as metal layers having higher conductivity than the conductors 542a1 and 542b1. Thus, the conductors 542a and 542b can be used as wiring or electrodes with high conductivity. In this manner, a semiconductor device can be provided in which the conductors 542a and 542b serving as wiring or electrodes are provided in contact with the top surface of the oxide 530 serving as an active layer.

[0362] As the conductors 542a1 and 542b1, metal nitrides are preferably used, for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. In one embodiment of the present invention, nitrides containing tantalum are particularly preferably used. In addition, for example, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. can also be used. These materials are conductive materials that are not easily oxidized or materials that maintain conductivity even if they absorb oxygen, so they are preferred.

[0363] The electrical conductivity of the conductor 542a2 and the conductor 542b2 is preferably higher than that of the conductor 542a1 and the conductor 542b1. For example, the thickness of the conductor 542a2 and the conductor 542b2 is preferably greater than that of the conductor 542a1 and the conductor 542b1. As the conductor 542a2 and the conductor 542b2, the conductor that can be used for the conductor 560b described above can be used. By adopting the above structure, the resistance of the conductor 542a2 and the conductor 542b2 can be reduced.

[0364] For example, tantalum nitride or titanium nitride can be used as the conductor 542a1 and the conductor 542b1, and tungsten can be used as the conductor 542a2 and the conductor 542b2.

[0365] like Fig.24As shown in FIG. 1 , when viewed from a cross section in the channel length direction of the transistor 500, the distance between the conductor 542a1 and the conductor 542b1 is smaller than the distance between the conductor 542a2 and the conductor 542b2. By adopting this structure, the distance between the source and the drain can be further shortened, and the channel length can be shortened accordingly. Therefore, the frequency characteristics of the transistor 500 can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0366] The insulator 555 is preferably an insulator that is not easily oxidized, such as a nitride. The insulator 555 is formed in a manner that contacts the side surface of the conductor 542a2 and the side surface of the conductor 542b2, and has the function of protecting the conductor 542a2 and the conductor 542b2. Since the insulator 555 is exposed to an oxidizing atmosphere, it is preferably an inorganic insulator that is not easily oxidized. In addition, since the insulator 555 contacts the conductor 542a2 and the conductor 542b2, it is preferably an inorganic insulator that is not easily oxidized by the conductors 542a2 and 542b2. Therefore, the insulator 555 is preferably an insulating material that has a barrier property against oxygen. For example, silicon nitride can be used as the insulator 555.

[0367] Openings are formed in the insulator 580 and the insulator 544, and the insulator 555 is formed so as to be in contact with the side walls of the openings. The conductor 542a1 and the conductor 542b1 are separated using a mask, thereby forming Fig.24 The transistor 500 shown in FIG. 1 is a transistor 500. Here, the opening overlaps the region between the conductor 542a2 and the conductor 542b2. In addition, a portion of the conductor 542a1 and the conductor 542b1 protrude into the opening. Therefore, the insulator 555 is in contact with the top surface of the conductor 542a1, the top surface of the conductor 542b1, the side surface of the conductor 542a2, and the side surface of the conductor 542b2 in the opening. In addition, the insulator 545 is in contact with the top surface of the oxide 530 in the region between the conductor 542a1 and the conductor 542b1.

[0368] Preferably, after the conductor 542a1 is separated from the conductor 542b1, a heat treatment is performed in an oxygen-containing atmosphere before the insulator 545 is deposited. Thus, oxygen is supplied to the oxide 530a and the oxide 530b, thereby reducing oxygen vacancies. Furthermore, by forming the insulator 555 in contact with the side of the conductor 542a2 and the side of the conductor 542b2, the conductor 542a2 and the conductor 542b2 can be prevented from being excessively oxidized. Thus, the electrical characteristics and reliability of the transistor can be improved. In addition, the uneven electrical characteristics of a plurality of transistors formed on the same substrate can be suppressed.

[0369] like Fig.24As shown, in the transistor 500 , the insulator 524 may be formed in an island shape. Here, the side end of the insulator 524 may be substantially aligned with the oxide 530 .

[0370] like Fig.24 As shown in FIG. 5 , in the transistor 500, the insulator 522 may be in contact with the insulator 516 and the conductor 503. In other words, it is also possible not to set Fig.23A and Fig. 23B Insulator 520 is shown.

[0371] Next, a capacitor 600 is provided above the transistor 500 . The capacitor 600 includes a conductor 610 , a conductor 620 , and an insulator 630 .

[0372] Furthermore, a conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 is used as a plug or wiring connected to the transistor 500. The conductor 610 is used as an electrode of the capacitor 600. Alternatively, the conductor 612 and the conductor 610 may be formed at the same time.

[0373] As the conductor 612 and the conductor 610, a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above elements as a component (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), etc. can be used. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be used.

[0374] In this embodiment, the conductor 612 and the conductor 610 have a single-layer structure, but the present invention is not limited thereto and they may have a stacked structure of two or more layers. For example, a conductor having high tightness to the conductor having a barrier property and the conductor having a high conductivity may be formed between the conductor having a barrier property and the conductor having a high conductivity.

[0375] The conductor 620 is provided so as to overlap the conductor 610 via the insulator 630. Conductive materials such as metal materials, alloy materials, and metal oxide materials can be used as the conductor 620. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. When the conductor 620 is formed simultaneously with other components such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used.

[0376] An insulator 640 is provided on the conductor 620 and the insulator 630. The insulator 640 can be made of the same material as the insulator 320. In addition, the insulator 640 can be used as a planarization film that covers the uneven shape thereunder.

[0377] By adopting this structure, miniaturization or high integration of a semiconductor device using a transistor including an oxide semiconductor can be achieved.

[0378] As a substrate for a semiconductor device that can be used in one embodiment of the present invention, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate (for example, a stainless steel substrate, a substrate containing a stainless steel foil, a tungsten substrate, a substrate containing a tungsten foil, etc.), a semiconductor substrate (for example, a single crystal semiconductor substrate, a polycrystalline semiconductor substrate or a compound semiconductor substrate), an SOI (SOI: Silicon on Insulator) substrate, etc. can be used. In addition, a heat-resistant plastic substrate that can withstand the processing temperature of this embodiment can also be used. As an example of a glass substrate, barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass or soda-lime glass can be cited. In addition, crystallized glass, etc. can also be used.

[0379] In addition, as a substrate, a flexible substrate, a laminated film, paper or a base film containing a fibrous material can be used. As a flexible substrate, a laminated film, a base film, etc., the following examples can be cited. For example, plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE) can be cited. Or, as an example, synthetic resins such as acrylic resins can be cited. Or, as an example, polypropylene, polyester, polyvinyl fluoride or polyvinyl chloride can be cited. Or, as an example, polyamide, polyimide, aramid resin, epoxy resin, inorganic vapor-deposited film, paper, etc. can be cited. In particular, by using semiconductor substrates, single crystal substrates or SOI substrates to manufacture transistors, it is possible to manufacture transistors with small deviations in characteristics, size or shape, high current capacity and small size. When the above-mentioned transistors are used to form a circuit, low power consumption of the circuit or high integration of the circuit can be achieved.

[0380] In addition, a flexible substrate may be used as a substrate, and transistors, resistors and / or capacitors may be directly formed on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate and the transistors, resistors and / or capacitors. The peeling layer may be used in a case where a part or all of a semiconductor device is manufactured on the peeling layer, and then the semiconductor device is separated from the substrate and transferred to another substrate. In this case, the transistors, resistors and / or capacitors may be transferred to a substrate with low heat resistance or a flexible substrate. In addition, as the above-mentioned peeling layer, for example, a laminated structure of an inorganic film of a tungsten film and a silicon oxide film, a structure in which an organic resin film such as polyimide is formed on a substrate, or a silicon film containing hydrogen may be used.

[0381] That is, after forming a semiconductor device on one substrate, the semiconductor device can be transferred to another substrate. As the substrate to which the semiconductor device is transferred, not only the above-mentioned substrate on which a transistor can be formed can be used, but also paper substrates, glass paper substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, cuprammonium, rayon, regenerated polyester)), leather substrates, rubber substrates, etc. can be used. By using such a substrate, it is possible to manufacture a flexible semiconductor device, manufacture a semiconductor device that is not easily damaged, improve heat resistance, and reduce weight or thickness.

[0382] By providing a semiconductor device on a flexible substrate, it is possible to provide a semiconductor device that is less likely to be damaged while suppressing an increase in weight.

[0383] Fig. 22 The structure of transistor 550 shown is only an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure, driving method, etc. For example, when the semiconductor device is a unipolar circuit with only OS transistors (transistors of the same polarity such as only n-channel transistors), transistor 550 can have the same structure as transistor 500.

[0384] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments and examples as appropriate.

[0385] (Implementation 4)

[0386] In this embodiment, a cross-sectional structure example of a memory device including an OS transistor such as a DOSRAM and a NOSRAM described in the above embodiments will be described.

[0387] Fig.25 An example of a cross-sectional structure when a circuit structure using DOSRAM is shown. Fig.25 An example is shown in which the memory layers 700 [ 1 ] to 700 [ 4 ] are stacked on the driver circuit layer 701 .

[0388] also, Fig.25 An example of the transistor 550 included in the driver circuit layer 701 is shown. As the transistor 550, the transistor 550 described in the above embodiment mode can be applied.

[0389] also, Fig.25 The transistor 550 shown is just an example, and an appropriate transistor may be used according to the circuit structure or driving method without being limited to the structure.

[0390] A wiring layer including an interlayer film, wiring, and plugs may be provided between the driving circuit layer 701 and the storage layer 700 or between the k-th storage layer 700 and the k+1-th storage layer 700. In addition, in the present embodiment, the k-th storage layer 700 is sometimes referred to as the storage layer 700[k], and the k+1-th storage layer 700 is sometimes referred to as the storage layer 700[k+1]. Here, k is an integer greater than 1 and less than N. In addition, in the present embodiment, when referred to as "k+α (α is an integer greater than 1)" or "k-α", the solutions of "k+α" and "k-α" are each integer greater than 1 and less than N.

[0391] In addition, the wiring layer may be provided in a plurality of layers according to the design. In addition, in this specification, wiring and a plug connected to the wiring may also be one component. That is, a part of the conductor may be used as wiring, and a part of the conductor may be used as a plug.

[0392] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on the transistor 550. In addition, a conductor 328 or the like is embedded in the insulator 320 and the insulator 322. In addition, a conductor 330 or the like is embedded in the insulator 324 and the insulator 326. In addition, the conductor 328 and the conductor 330 are used as contact plugs or wirings.

[0393] In addition, the insulator used as the interlayer film can be used as a planarization film that covers the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulator 320, planarization can also be achieved by a planarization process using a CMP method or the like.

[0394] Alternatively, a wiring layer may be provided on the insulator 326 and the conductor 330. Fig.25 In the embodiment, an insulator 350, an insulator 357, an insulator 352, and an insulator 354 are sequentially stacked on the insulator 326 and the conductor 330. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 357, and the insulator 352. The conductor 356 is used as a contact plug or a wiring.

[0395] The insulator 514 included in the memory layer 700[1] is provided on the insulator 354. In addition, the conductor 358 is embedded in the insulator 514 and the insulator 354. The conductor 358 is used as a contact plug or wiring. For example, the wiring BL and the transistor 550 are connected through the conductor 358, the conductor 356, and the conductor 330.

[0396] Fig.26A An example of a cross-sectional structure of a storage layer 700[k] is shown. Fig.26B yes Fig.26A Equivalent circuit diagram of . Fig.26A An example is shown in which one wiring BL is connected to two memory cells MC.

[0397] Fig.25 and Fig.26A The memory cell MC shown includes a transistor M1 and a capacitor C. As the transistor M1 , for example, the transistor 500 shown in the above embodiment can be used.

[0398] In this embodiment, a modified example of the transistor 500 is described as the transistor M1. Specifically, the transistor M1 is different from the transistor 500 in that the conductors 542a and 542b extend beyond the ends of the metal oxide 531 (the metal oxide 531a and the metal oxide 531b).

[0399] also, Fig.25 and Fig.26A The memory cell MC shown includes a conductor 156 serving as one terminal of the capacitor C, an insulator 153 serving as a dielectric, and a conductor 160 (conductor 160a and conductor 160b) serving as the other terminal of the capacitor C. The conductor 156 is connected to a portion of the conductor 542b. In addition, the conductor 160 is connected to the wiring PL (in Fig.26A (not shown) connection.

[0400] Capacitor C is formed in an opening portion provided by removing a portion of insulator 574, insulator 580, and insulator 554. Since conductor 156, insulator 580, and insulator 554 are formed along the side surface of the opening portion, they are preferably deposited using ALD or CVD.

[0401] In addition, as the conductor 156 and the conductor 160, a conductor that can be used for the conductor 505 or the conductor 560 can be used. For example, as the conductor 156, titanium nitride deposited by the ALD method can be used. In addition, as the conductor 160a, titanium nitride deposited by the ALD method can be used, and as the conductor 160b, tungsten deposited by the CVD method can be used. In addition, when the adhesion between tungsten and the insulator 153 is sufficiently high, a single layer film of tungsten deposited by the CVD method can also be used as the conductor 160.

[0402] As the insulator 153, it is preferred to use an insulator composed of a high dielectric constant (high-k) material (a material with a relatively high dielectric constant). For example, as an insulator composed of a high dielectric constant material, an oxide, an oxynitride, an oxynitride or a nitride containing one or more metal elements selected from aluminum, hafnium, zirconium and gallium can be used. In addition, the above-mentioned oxide, oxynitride, oxynitride or nitride may also contain silicon. In addition, an insulating layer composed of the above-mentioned materials may also be stacked. As the insulator 153, for example, a three-layer stacked structure of zirconium oxide, aluminum oxide and zirconium oxide can be cited. In addition, the three-layer stacked structure may also be referred to as ZrO xa \AlO xb \ZrO xc (ZAZ). The above xa, xb and xc are all arbitrary units.

[0403] For example, as an insulator composed of a high dielectric constant material, aluminum oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, an oxide containing silicon and zirconium, an oxynitride containing silicon and zirconium, an oxide containing hafnium and zirconium, an oxynitride containing hafnium and zirconium, etc. can be used. By using such a high dielectric constant material, the thickness of the insulator 153 can be increased to a degree that can suppress the off-state current, and the electrostatic capacitance of the capacitor element C can be fully ensured.

[0404] In addition, it is preferred to stack an insulating layer composed of the above-mentioned materials, and it is preferred to use a laminated structure of a high dielectric constant material and a material whose insulation resistance is higher than that of the high dielectric constant material. For example, as an insulator 153, an insulating film stacked with zirconium oxide, aluminum oxide and zirconium oxide can be used. In addition, for example, an insulating film stacked with zirconium oxide, aluminum oxide, zirconium oxide and aluminum oxide can be used. In addition, for example, an insulating film stacked with hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide and aluminum oxide can be used. By stacking an insulator with relatively high insulation resistance such as aluminum oxide, the insulation resistance can be improved to suppress the electrostatic destruction of the capacitor element C.

[0405] Fig.27A The capacitive element C1 shown is Fig.26A A modified example of the capacitor element C is shown.

[0406] Fig.27A The capacitance element C1 is shown with Fig.26A The difference between the capacitor element C shown is that the shapes of the conductor 156, the insulator 153 and the conductor 160 are different. Fig.27A The structure of the capacitor element C1 shown can increase the overlapping area of ​​the conductor 156, the insulator 153, and the conductor 160, thereby increasing the capacitance.

[0407] Insulator 153 contacts the inside of the recess included in conductor 156 and the top surface of conductor 156. In addition, insulator 153 includes a region in contact with a portion of the outer side surface of conductor 156. In addition, insulator 153 includes a region in contact with insulator 574.

[0408] The conductor 160 is provided so as to be embedded in the opening included in the conductor 156. Furthermore, the conductor 160 includes a region overlapping with a part of the outer side surface of the conductor 156 via the insulator 153.

[0409] With the above structure, the electrostatic capacitance per unit area can be further increased.

[0410] Fig.27B The capacitive element C2 shown is Fig.26A A modified example of the capacitor element C is shown.

[0411] Fig.27B The capacitance element C2 shown is Fig.26A The capacitor element C shown is different in the shapes of the conductor 156 , the insulator 153 , and the conductor 160 .

[0412] The conductor 156 includes a conductor 156a on the conductor 542b and a conductor 156b on the conductor 156a. The conductor 156b has a cylindrical shape having a hollow portion.

[0413] The insulator 153 is provided so as to be in contact with the side surfaces and the top surface of the conductor 156 b and the top surface of the conductor 156 a .

[0414] The conductor 160 is provided so as to be embedded in the hollow portion included in the conductor 156 b via the insulator 153 .

[0415] With the above structure, the electrostatic capacitance per unit area can be further increased.

[0416] Fig.27C The capacitive element C3 shown is Fig.26A A modified example of the capacitor element C is shown.

[0417] Fig.27C The capacitance element C3 shown is Fig.26A The capacitor element C shown is different in the shapes of the conductor 156 , the insulator 153 , and the conductor 160 .

[0418] The conductor 156 includes a conductor 156a on the conductor 542b and a conductor 156b on the conductor 156a. The conductor 156b has a cylindrical shape.

[0419] The insulator 153 is provided so as to be in contact with the side surfaces and the top surface of the conductor 156 b and the top surface of the conductor 156 a .

[0420] The conductor 160 is provided so as to cover the top surface and the side surfaces of the conductor 156 b via the insulator 153 .

[0421] With the above structure, the electrostatic capacitance per unit area can be further increased.

[0422] Fig.27C The side surface of the conductor 156b is shown to be perpendicular to the structure of the conductor 542b, but the present invention is not limited to this. Fig.27D As shown, the side surface of the conductor 156b may also have a tapered shape. When the side surface of the opening has a tapered shape, the coverage of the insulator 153 and the conductor 160 is improved in the subsequent steps, thereby reducing defects such as voids.

[0423] Fig.25 The structure in which the transistors M1 and the capacitors C in the stacked storage layer 700 overlap is shown, that is, the transistors M1 overlap each other and the capacitors C overlap each other, but other structures may also be used. Fig.28 As shown, the electrode of the capacitor element C in the stacked storage layer 700 may also be arranged at a position overlapping with the conductor used as the back gate of the transistor M1. Fig.28 The structure can simplify the process of forming a conductor used as the back gate of the transistor M1.

[0424] Fig.29 An example of a cross-sectional structure when a circuit structure of a memory cell using NOSRAM is shown. Fig.29 Too Fig.25 In addition, Fig. 30A An example of a cross-sectional structure of a storage layer 700[k] is shown. Fig. 30B yes Fig. 30A Equivalent circuit diagram of .

[0425] Fig.29 and Fig. 30A The illustrated memory cell MC includes a transistor M1, a transistor M2, and a transistor M3 on an insulator 514. In addition, a conductor 215 is provided on the insulator 514. The conductor 215 can be formed simultaneously with the conductor 505 using the same material and the same process.

[0426] also, Fig.29 and Fig. 30AThe transistor M2 and the transistor M3 shown in the figure share an island-shaped metal oxide 531. In other words, a portion of the island-shaped metal oxide 531 is used as a channel formation region of the transistor M2, and another portion is used as a channel formation region of the transistor M3. In addition, the source of the transistor M2 and the drain of the transistor M3 or the drain of the transistor M2 and the source of the transistor M3 are shared. Therefore, compared with the case where the transistor M2 and the transistor M3 are provided separately, the occupied area of ​​the transistor is small.

[0427] In addition, Fig.29 and Fig. 30A In the illustrated memory cell MC, an insulator 287 is provided on an insulator 581, and a conductor 161 is embedded in the insulator 287. In addition, an insulator 514 of a memory layer 700[k+1] is provided on the insulator 287 and the conductor 161.

[0428] exist Fig.29 and Fig. 30A In the embodiment, the conductor 215 of the storage layer 700[k+1] is used as one terminal of the capacitor C, the insulator 514 of the storage layer 700[k+1] is used as a dielectric of the capacitor C, and the conductor 161 is used as the other terminal of the capacitor C. In addition, the other of the source and the drain of the transistor M1 is connected to the conductor 161 through a contact plug, and the gate of the transistor M2 is connected to the conductor 161 through another contact plug.

[0429] Fig.29 The example in which the conductor used as the back gate and the conductor used as one terminal of the capacitor C included in the stacked memory layer 700 are different in structure is shown, but other structures may also be adopted. Fig.31 As shown, the conductors 215 of one terminal of the capacitor C of the stacked memory layer 700 and the conductors used as the back gates of the conductors of the transistors M1 to M3 may be connected to each other in such a manner that they have the same potential. Fig.28 The structure can increase the conductor 215 of the capacitor element C, thereby increasing the capacitance of the capacitor element C.

[0430] This embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0431] (Implementation method 5)

[0432] In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) is described. In addition, in the description of the OS transistor, a comparison with a transistor including silicon in a channel formation region (also referred to as a Si transistor) is briefly described.

[0433] [OS Transistor]

[0434] It is preferable to use an oxide semiconductor with a low carrier concentration for the OS transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably below 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , and more preferably less than 1×10 13 cm -3 , and further preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 In the case of reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0435] Since high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect state density, they sometimes have a low trap state density. In addition, it takes a long time for the charges captured by the trap states of the oxide semiconductor to disappear, and sometimes they act like fixed charges. Therefore, sometimes the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density are unstable.

[0436] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. As impurities, hydrogen, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0437] In an OS transistor, when impurities and oxygen vacancies exist in the channel formation region of an oxide semiconductor, the electrical characteristics are easily changed and reliability may be reduced. In addition, in an OS transistor, hydrogen enters the oxygen vacancies in the oxide semiconductor to form defects (hereinafter sometimes referred to as V O H), electrons that become carriers may be generated. In addition, when V OWhen the voltage is V, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may become uneven. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor may have a normally-on characteristic (a characteristic in which a channel exists and current flows in the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V. O H.

[0438] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and more preferably 3.0 eV or more. By using an oxide semiconductor with a larger band gap than silicon, the off-state current (also called Ioff) of the transistor can be reduced.

[0439] For example, in Si transistors, as the miniaturization of transistors progresses, short channel effects (Short Channel Effect: also called SCE) appear. Therefore, miniaturization of Si transistors is difficult. One of the reasons for the short channel effect is that the band gap of silicon is small. On the other hand, in OS transistors, oxide semiconductors, which are semiconductor materials with large band gaps, are used, so the short channel effect can be suppressed. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0440] The short channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a reduction in threshold voltage, an increase in subthreshold swing value (sometimes recorded as S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage in the subthreshold region that changes the drain current value by one digit with a fixed drain voltage.

[0441] As an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist short channel effects is high.

[0442] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region and the characteristic length between the drain region and the channel formation region in OS transistors are smaller. Therefore, OS transistors have a higher ability to resist short channel effects than Si transistors. That is, when you want to manufacture transistors with a small channel length, OS transistors are more suitable than Si transistors.

[0443] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is lowered due to the conduction-band-lowering (CBL) effect in the short channel transistor, so the energy difference of the conduction band bottom between the source region or the drain region and the channel formation region is likely to be reduced to more than 0.1 eV and less than 0.2 eV. Thus, the OS transistor can be regarded as having n + / n - / n + The accumulation type junctionless transistor structure or n + / n - / n + The accumulation type non-junction transistor structure, in which the channel formation region is n - Type region, source region and drain region are n + Type area.

[0444] When the above structure is used as an OS transistor, good electrical characteristics can be achieved even if the semiconductor device is miniaturized or highly integrated. For example, even if the gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of less than 20nm or less than 15nm due to the occurrence of a short channel effect. Therefore, compared with Si transistors, OS transistors are more suitable for use as transistors with a small channel length. The gate length is the length of the gate electrode in the direction of the carrier movement channel formation region when the transistor is working, and is the width of the bottom surface of the gate electrode in the top view of the transistor.

[0445] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cutoff frequency of the transistor can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz.

[0446] As described above, the OS transistor has advantages superior to the Si transistor, such as a small off-state current and the ability to manufacture a transistor with a small channel length.

[0447] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments mode and the like as appropriate.

[0448] (Implementation 6)

[0449] In this embodiment, electronic components, electronic devices, mainframe computers, space equipment, and data centers (also referred to as DC) that can use the semiconductor device described in the above embodiment are described. Electronic components, electronic devices, mainframe computers, space equipment, and data centers that use a semiconductor device in one embodiment of the present invention are effective in achieving high performance such as low power consumption.

[0450] [Electronic components]

[0451] Fig.32A A perspective view of a substrate (circuit board 704 ) on which electronic components 709 are mounted is shown. Fig.32A The electronic component 709 shown includes a semiconductor device 710 within a mold 711. Fig.32A 709 is partially omitted to show the inside. The electronic component 709 includes a land 712 on the outside of the mold 711. The land 712 is connected to an electrode pad 713, and the electrode pad 713 is connected to the semiconductor device 710 through a lead 714. The electronic component 709 is mounted on, for example, a printed circuit board 702. By combining a plurality of these electronic components and connecting them on the printed circuit board 702, the circuit board 704 is completed.

[0452] In addition, the semiconductor device 710 includes a driving circuit layer 715 and a storage layer 716. The storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the driving circuit layer 715 and the storage layer 716 are stacked can adopt a monolithic stacked structure. In the monolithic stacked structure, it is possible to connect the layers without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. When the driving circuit layer 715 and the storage layer 716 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be achieved.

[0453] In addition, by adopting an on-chip memory structure, the size of the connection wiring can be reduced compared to the technology using through-electrodes such as TSV, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, thereby increasing the bandwidth of the memory (also called memory bandwidth).

[0454] In addition, it is preferred that multiple memory cell arrays in the storage layer 716 are formed using OS transistors, and the multiple memory cell arrays are stacked in a monolithic manner. When multiple memory cell arrays are stacked in a monolithic manner, either or both of the bandwidth of the memory and the access delay of the memory can be improved. Bandwidth refers to the amount of data transmitted per unit time, and access delay refers to the time between access and the start of data exchange. When Si transistors are used in the storage layer 716, it is more difficult to implement a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0455] In addition, the semiconductor device 710 may be referred to as a bare chip. In this specification, etc., a bare chip refers to a chip obtained by forming a circuit pattern on a disc-shaped substrate (also called a wafer) in the manufacturing process of a semiconductor chip, for example, and cutting it into rectangular small pieces. As semiconductor materials that can be used for bare chips, for example, silicon (Si), silicon carbide (SiC) or gallium nitride (GaN) can be cited. For example, a bare chip obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon chip.

[0456] then, Fig.32B The electronic component 730 is a perspective view. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0457] The electronic component 730 shows an example of using the semiconductor device 710 as a high bandwidth memory (HBM). In addition, the semiconductor device 735 can be used in an integrated circuit such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0458] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0459] The plug board 731 has a plurality of wirings and has the function of connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the plug board 731 has the function of connecting the integrated circuit disposed on the plug board 731 to the electrode disposed on the package substrate 732. Therefore, the plug board is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the plug board 731, and the integrated circuit is connected to the package substrate 732 through the through electrode. In addition, in the case of using a silicon plug board, TSV can also be used as a through electrode.

[0460] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0461] In addition, in SiP and MCM using silicon interposers, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not easy to occur. In addition, since the surface flatness of the silicon interposer is high, the connection between the integrated circuit arranged on the silicon interposer and the silicon interposer is not easy to occur. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and configured on the interposer.

[0462] On the other hand, when a plurality of integrated circuits with different terminal pitches are connected using silicon interposers and TSV, a space such as the width of the terminal pitch is required. Therefore, when the size of the electronic component 730 is to be reduced, the width of the terminal pitch becomes a problem, and it is sometimes difficult to set up a large number of wirings required to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. In addition, a composite structure combining a memory cell array stacked using TSV and a memory cell array stacked in a monolithic manner can also be used.

[0463] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 consistent.

[0464] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig.32BAn example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive needles. By arranging conductive needles in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0465] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0466] [Electronic equipment]

[0467] then, Fig.33A A perspective view of electronic device 6500 is shown. Fig.33A The electronic device 6500 shown is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be used for the display unit 6502, the control device 6509, and the like.

[0468] Fig.33B The electronic device 6600 shown is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, a control device 6616, etc. The control device 6616 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. A semiconductor device of one embodiment of the present invention can be used for the display unit 6615, the control device 6616, etc. In addition, by using a semiconductor device of one embodiment of the present invention for the above-mentioned control device 6509 and the control device 6616, power consumption can be reduced, so it is preferred.

[0469] [Mainframe computer]

[0470] then, Fig.33C A perspective view of a mainframe computer 5600 is shown. Fig.33C In the illustrated mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610. The mainframe computer 5600 may also be referred to as a supercomputer.

[0471] Computer 5620 may have, for example, Fig.33D The structure of the stereogram is shown. Fig.33D In the embodiment, the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slot 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0472] Fig.33E The personal computer card 5621 shown is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Fig.33E Semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0473] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe and the like.

[0474] The connection terminals 5623, 5624, and 5625 can be used as interfaces for supplying power to the personal computer card 5621 or inputting signals, for example. In addition, for example, they can be used as interfaces for outputting signals calculated by the personal computer card 5621, for example. Examples of the specifications of the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when video signals are output from the connection terminals 5623, 5624, and 5625, HDMI (registered trademark) and the like can be cited as the specifications.

[0475] The semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal, and the semiconductor device 5626 and the board 5622 can be connected by inserting the terminal into a socket (not shown) included in the board 5622 .

[0476] The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. Examples of the semiconductor device 5627 include FPGA, GPU, and CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0477] The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. As the semiconductor device 5628, for example, a storage device can be cited. As the semiconductor device 5628, for example, the electronic component 709 can be used.

[0478] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0479] [Space Equipment]

[0480] The semiconductor device of one embodiment of the present invention can be applied to space equipment such as equipment for processing and storing information.

[0481] A semiconductor device according to one embodiment of the present invention may include an OS transistor. The OS transistor has a small change in electrical characteristics due to exposure to radiation. In other words, it has high resistance to radiation, so it can be appropriately used in an environment where radiation may be incident. For example, an OS transistor can be appropriately used when used in outer space.

[0482] exist Fig.34 In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig.34 An example is shown in which the outer space includes the planet 6804. Note that the outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0483] In addition, although Fig.34 Although not shown in the figure, a battery management system (also called BMS) or a battery control circuit may be provided in the secondary battery 6805. When an OS transistor is used for the above-mentioned battery management system or battery control circuit, power consumption is low and high reliability is achieved even in outer space, so it is preferable.

[0484] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. Examples of radiation include: electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays; and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, muon rays, etc.

[0485] When sunlight shines on the solar cell panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar cell panel or when the amount of sunlight shining on the solar cell panel is small, the amount of power generated is reduced. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the generated power is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel is sometimes referred to as a solar cell module.

[0486] The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803, and a receiver on the ground or other artificial satellites can receive the signal. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver receiving the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0487] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, any one or more selected from a CPU, a GPU, and a storage device. In addition, it is preferable to use a semiconductor device of one embodiment of the present invention for the control device 6807. Compared with Si transistors, the electrical characteristics of OS transistors change less due to exposure to radiation. Therefore, OS transistors are highly reliable and can be appropriately used even in an environment where radiation may be incident.

[0488] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0489] Note that although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as a spacecraft, a space capsule, and a space probe.

[0490] As described above, OS transistors have superior effects compared to Si transistors, such as being able to achieve a wider memory bandwidth and having high radiation resistance.

[0491] [Data Center]

[0492] For example, a semiconductor device according to one embodiment of the present invention can be applied to a storage system used in a data center or the like. A data center is required to manage data over a long period of time by ensuring data invariance. When managing data over a long period of time, it is necessary to enlarge facilities, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply to maintain data, or ensuring cooling equipment required for maintaining data.

[0493] By using a semiconductor device of one embodiment of the present invention in a storage system used in a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device for retaining data. Therefore, it is possible to miniaturize the storage system, miniaturize the power supply for retaining data, and reduce the scale of cooling equipment. As a result, it is possible to save space in the data center.

[0494] In addition, the power consumption of the semiconductor device of one embodiment of the present invention is low, so the heat generation of the circuit can be reduced. As a result, the negative impact of the heat generation on the circuit itself, the peripheral circuits and the modules can be reduced. In addition, by using the semiconductor device of one embodiment of the present invention, a data center that can operate stably even in a high temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0495] Fig.35 A storage system that may be used in a data center is shown. Fig.35 The storage system 7000 shown includes a plurality of servers 7001sb as a host 7001 (shown as a host computer). In addition, it includes a plurality of storage devices 7003md as storage 7003 (shown as storage). The host 7001 and the storage 7003 are shown to be connected via a storage area network 7004 (shown as SAN: Storage Area Network) and a storage control circuit 7002 (shown as a storage controller).

[0496] The host 7001 is equivalent to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0497] In the storage 7003, the access speed of data is shortened by using a flash memory, that is, the time required for data storage and output is shortened, but this time is much longer than the time required for DRAM which can be used as a cache memory in the storage. In the storage system, in order to solve the problem of the long access speed of the storage 7003, a cache memory is generally provided in the storage to shorten the storage and output of data.

[0498] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003 and then output to the host 7001 or the storage 7003.

[0499] When an OS transistor is used as a transistor for storing data in the cache memory to hold a potential corresponding to the data, the refresh frequency can be reduced to reduce power consumption. In addition, miniaturization can be achieved by stacking memory cell arrays.

[0500] Note that by using a semiconductor device of one embodiment of the present invention for any one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, it is expected that the effect of reducing power consumption can be expected. Therefore, it is currently believed that as the energy demand for semiconductor devices increases with the high performance or high integration, by using a semiconductor device of one embodiment of the present invention, it is also possible to reduce carbon dioxide (CO 2 ) is a representative greenhouse gas emission. In addition, a semiconductor device according to one embodiment of the present invention has low power consumption and is therefore also effective as a measure against global warming.

[0501] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments mode and the like as appropriate.

[0502] <Notes on the Descriptions in This Manual, etc.>

[0503] Hereinafter, comments will be added to the description of the above-mentioned embodiment and each configuration in the embodiment.

[0504] The structure described in each embodiment can be appropriately combined with the structure described in other embodiments to constitute one mode of the present invention. In addition, when a plurality of structural examples are described in one embodiment, these structural examples can be appropriately combined.

[0505] In addition, the content (or part thereof) described in a certain embodiment may be applied, combined or replaced with other content (or part thereof) described in that embodiment and / or content (or part thereof) described in one or more other embodiments.

[0506] The contents described in the embodiments refer to the contents described using various drawings in each embodiment or the contents described using articles described in the specification.

[0507] In addition, more figures may be formed by combining a drawing (or part thereof) shown in a certain embodiment with other parts of the drawing, other drawings (or parts thereof) shown in the embodiment, and / or drawings (or parts thereof) shown in one or more other embodiments.

[0508] In this specification, etc., constituent elements are classified according to function and are represented as independent blocks in a block diagram. However, it is difficult to classify constituent elements according to function in actual circuits, etc., and sometimes one circuit involves multiple functions or multiple circuits involve one function. Therefore, the division of blocks in a block diagram is not limited to the constituent elements described in the specification, but can be appropriately different according to the situation.

[0509] In the drawings, the size, thickness of a layer or area is sometimes exaggerated for the sake of clarity. Therefore, the present invention is not limited to the dimensions in the drawings. The drawings are for the sake of clarity and are not limited to the shapes or values ​​shown in the drawings. For example, it may include uneven signals, voltages or currents caused by noise or timing deviations.

[0510] In this specification, etc., when describing the connection relationship of a transistor, the expressions "one of the source and the drain" (first electrode or first terminal) and "the other of the source and the drain" (second electrode or second terminal) are used. This is because the source and the drain of a transistor are interchangeable depending on the structure or operating conditions of the transistor. Note that the source and the drain of a transistor may be appropriately referred to as a source (drain) terminal or a source (drain) electrode, etc., depending on the situation.

[0511] In addition, in this specification, "electrode" or "wiring" does not limit the function of a component. For example, an "electrode" is sometimes used as a part of a "wiring", and vice versa. Furthermore, "electrode" and "wiring" also include a case where a plurality of "electrodes" or "wiring" are formed as one.

[0512] In addition, in this specification, etc., voltage and potential can be appropriately exchanged. Voltage refers to the potential difference from the reference potential. For example, when the reference potential is the ground voltage (ground voltage), voltage can be exchanged for potential. The ground potential does not necessarily mean 0V. Note that potential is relative, and the potential supplied to wiring, etc. sometimes changes according to the reference potential.

[0513] In this specification, the words "film" and "layer" may be interchanged depending on the situation or state. For example, "conductive layer" may be interchanged with "conductive film". Also, "insulating film" may be interchanged with "insulating layer".

[0514] In this specification, etc., a switch refers to an element having a function of controlling whether current flows by changing to a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to an element having a function of selecting and switching a current path.

[0515] In this specification, etc., for example, the channel length refers to the distance between the source and the drain in the area where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in an on state) and the gate overlap or in the area where the channel is formed in a top view of the transistor.

[0516] In this specification, etc., for example, the channel width refers to the length of the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in an on state) and the gate electrode overlap, or the portion where the source and drain electrodes face each other in the region where the channel is formed.

[0517] In this specification, etc., a node may be referred to as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc. depending on the circuit structure or device structure, etc. In addition, a terminal, wiring, etc. may also be referred to as a node.

[0518] In this specification, etc., "A and B are connected" means that A and B are electrically connected. Here, "A and B are electrically connected" means a connection that can transmit an electric signal between A and B when an object (element such as a switch, transistor element or diode, or a circuit including the element and wiring, etc.) exists between A and B. Note that the case where A and B are electrically connected includes the case where A and B are directly connected. Here, direct connection between A and B means a connection that can transmit an electric signal between A and B through wiring (or electrodes) etc. without passing through the above-mentioned object. In other words, direct connection means a connection that can be regarded as the same circuit diagram when expressed using an equivalent circuit.

[0519] [Example]

[0520] In this embodiment, a semiconductor device in which a plurality of layers including OS transistors are stacked is manufactured, and then a cross section of the semiconductor device is observed. In addition, a simulation of a writing operation and a reading operation of the semiconductor device based on the design is performed.

[0521] <Structure of manufactured semiconductor device>

[0522] In the manufactured semiconductor device, the element layer including the OS transistor has a four-layer stack, and an intermediate layer (wiring layer) is included between the first and second element layers. Fig.36 The results of cross-sectional STEM (Scanning Transmission Electron Microscope) observation of the semiconductor device are shown.

[0523] exist Fig.36 In the device layers 30_1 to 30_4 shown in FIG. 1 , a cross section of the manufactured OS transistor (transistor 37) can be confirmed. Fig.36 In the device layers 30_2 to 30_4 shown, a cross section of the capacitor 38 can be confirmed. In the device layers 30_1 to 30_4 and the intermediate layer between the device layers 30_1 and 30_2, an OS transistor (transistor 37) and a capacitor 38 are monolithically stacked with an electrode 39 serving as a wiring therebetween.

[0524] <Comparison results between OS memory manufactured using stacked OS transistors and DRAM and SRAM>

[0525] The comparison results of OS memory including OS transistors manufactured in stacked element layers and DRAM formed of Si transistors are described. Table 1 shows the comparison results of write time, read time, density and retention of DOSRAM of OS memory and DRAM formed of Si transistors.

[0526] [Table 1]

[0527]

[0528] Table 1 shows a state where temperature correction is not performed (initial state) and a state where temperature correction is performed (temperature correction) for a DOSRAM including an OS transistor. The temperature correction of the DOSRAM can be performed by controlling the back gate voltage of the OS transistor described in the above-mentioned embodiment 1, etc. In addition, the DOSRAM is estimated to be manufactured with an OS transistor with a design rule of 20 nm and Fig.25The structure shown (a structure in which four layers of element layers including OS transistors are stacked on an element layer including Si transistors) is estimated to have a cell capacitance of 1.5 fF. In addition, as shown in Table 1, a DRAM including Si transistors is estimated to manufacture Si transistors with a design rule of 14 nm.

[0529] As a result, as shown in Table 1, it can be seen that compared with the write time and read time of DRAM, which are 20ns, the write period of DOSRAM is short, and the read time of DOSRAM is roughly equal to that of DRAM after temperature correction. That is, it can be seen that DOSRAM has performance equal to or higher than DRAM after temperature correction.

[0530] Comparing the density of memory, we can see that it is 383 cell / μm compared to DRAM. 2 Compared with DOSRAM, the density of each layer is 181 cell / μm 2 And by achieving multi-layer three-layer stacking, the cell / μm 2 , ten layers stacked over 5000cell / μm 2 As a result, it is known that DOSRAM has the potential to exceed the performance of existing DRAM.

[0531] In addition, regarding the retention of the comparative data retention time, it is estimated that DOSRAM refreshes once more than once in 6.4s, while DRAM refreshes the data of all storage cells once in 64ms. As a result, it is known that the power of DOSRAM may be reduced to 1 / 100 of the power required when refreshing DRAM.

[0532] Table 2 shows the results of comparing the write time, read time, density, and retention of the OS memory NOSRAM and the SRAM formed of Si transistors as another example of an OS memory including OS transistors manufactured in a stacked element layer.

[0533] [Table 2]

[0534]

[0535] Table 2 shows a state where temperature correction is not performed (initial state) and a state where temperature correction is performed (temperature correction) for a NOSRAM including an OS transistor. Temperature correction of the NOSRAM can be performed by controlling the back gate voltage of the OS transistor described in the above-mentioned embodiment 1, etc. In addition, the NOSRAM is estimated to be manufactured with an OS transistor with a design rule of 20 nm and Fig.29The structure shown (a structure in which four layers of element layers including OS transistors are stacked on an element layer including Si transistors) is estimated to have a cell capacitance of 0.4 fF. As shown in Table 2, the SRAM including Si transistors is estimated to be manufactured with a design rule of 5 nm.

[0536] As a result, as shown in Table 2, it can be seen that compared with the write time and read time of SRAM, which is 1ns for the L1 cache and 10ns for the last level cache (large capacity chip memory), the write time and read time in NOSRAM are less than the L1 cache, but are roughly equal to the last level cache through temperature correction.

[0537] Comparing the density of memory, we can see that it is 47.6 cell / μm compared to SRAM. 2 In comparison, the density of each layer of NOSRAM is 45cell / μm 2 Therefore, even without multi-layering, the performance of NOSRAM is roughly equal to that of SRAM. As a result, it is known that NOSRAM may exceed the performance of existing SRAM by multi-layering.

[0538] Regarding the retention time of comparative data, it is estimated that NOSRAM is refreshed once more than 6.4 seconds compared to the structure of SRAM where data does not change when the power is turned on but disappears when the power is turned off. As a result, it is known that the power of NOSRAM may be reduced to 1 / 100 of the power required for refreshing DRAM.

[0539] <Simulation results based on OS transistor characteristics>

[0540] In order to evaluate the characteristics of the OS memory that can use the manufactured semiconductor device, a semiconductor chip is provided based on the structure of the DOSRAM described in the second embodiment, and a simulation is performed.

[0541] Fig.37 The planar layout of the designed semiconductor chip is shown. Fig.37 In the semiconductor chip shown, OS transistors are arranged according to a 60 nm rule and Si transistors are arranged according to a 130 nm rule, and the chip size is 4 mm square.

[0542] exist Fig.37 In the example, region 801 is provided with three layers of memory cells, one layer of amplification circuit, and one layer of readout amplifier including Si transistors. Region 802 is provided with driving circuits such as word line driver and OS circuit driver. Region 803 is provided with readout amplifier including Si transistors. Region 804 is provided with column driver. Region 805 is provided with controller.

[0543] FIG. 38A to FIG. 38D shows the I of the OS transistor using simulationd -V g characteristic. Fig.38A The I of the OS transistor of the element layer (first layer) including the OS transistor in which the amplifier circuit is provided d -V g characteristic. FIG. 38B to FIG. 38D FIG. 1 shows an OS transistor included in an element layer (second to fourth layers) including an OS transistor in which a memory cell is provided. d -V g Measurement results: The channel length (L) and channel width (W) of the OS transistor were estimated to be 60 nm and 60 nm.

[0544] In the memory cells of the DOSRAM arranged in the second to fourth layers, the write time (Write time) and the read time (Read time) are estimated by simulation. Table 3 shows the write time and the read time of the memory using the OS transistors (OSFETs) of the second to fourth layers. In addition, since the first layer OS transistors are OS transistors of the amplifier circuit, the write time and the read time are not estimated.

[0545] [Table 3]

[0546]

[0547] As shown in Table 3, in the memory using stacked OSFETs, both the write time and the read time have good results.

[0548] Fig.39A , Fig.39B The diagram shows simulation waveforms of signals on a bit line (BL) and a storage node (SN) (a node connected to a capacitor) included in a memory cell during a write operation. Fig.39A 2 is a diagram showing the charging of the bit line and the change in voltage of the storage node. Fig.39A FIG. 1 is a diagram showing the voltage change of the storage node caused by discharging the bit line. Fig.39A , Fig.39B As shown, the charging and discharging of the storage node can be confirmed when the bit line is charged and discharged.

[0549] Fig.39C , Fig.39D 1 is a diagram showing simulation waveforms of signals of a word line (WL), a bit line (BL), and an inverted bit line (BLB) in a read operation. The bit line (BL) and the inverted bit line (BLB) correspond to the wirings GBL and GBLB in the second embodiment. Fig.39C The diagram shows voltage changes of a bit line (BL) and an inverted bit line (BLB) that charge-share the charged data held in a storage node (SN) when the word line is set to an H level and the OS transistor is turned on. Fig.39D1 is a diagram showing the voltage changes of the bit line (BL) and the inverted bit line (BLB) when the word line is set to the H level and the OS transistor is turned on to charge-share the inverted data stored in the storage node (SN). Fig.39C , Fig.39D As shown, it can be confirmed that potential changes occur in the bit line (BL) and the inverted bit line (BLB).

[0550] At least a part of this embodiment can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0551] [Explanation of symbols]

[0552] 10: semiconductor device, 15: temperature detection circuit, 16: voltage generation circuit, 20: element layer, 21: voltage control circuit, 22: peripheral circuit, 23: calculation circuit, 30: element layer, 31: memory cell array, 32: memory cell, 37: transistor

Claims

1. A semiconductor device comprising: A first element layer is provided with a temperature detection circuit and a voltage generation circuit; as well as A plurality of second element layers of the memory cell are provided, Wherein, a plurality of the second component layers are stacked on the first component layer, The memory cell includes a transistor having a semiconductor layer including an oxide semiconductor and having a channel formation region. The transistor comprises a back gate, The voltage generating circuit has a function of generating a back gate voltage supplied to the back gate. The temperature detection circuit has a function of controlling the back gate voltage according to the detected temperature. Furthermore, the voltage generating circuit has a function of supplying the back gate voltage as a different voltage to each of the plurality of second element layers.

2. The semiconductor device according to claim 1, Among the plurality of second element layers, a back gate voltage supplied to the transistor included in the second element layer arranged in an upper layer is larger than a back gate voltage supplied to the transistor included in the second element layer arranged in a lower layer.

3. The semiconductor device according to claim 1, The first component layer includes a computing circuit, The stacked second element layer is overlapped in a region where the operation circuit is provided.

4. The semiconductor device according to claim 1, The oxide semiconductor includes In, Ga, and Zn.

5. A semiconductor device comprising: a first component layer; as well as A plurality of second element layers including a temperature detection circuit, a voltage generation circuit and a storage unit are provided in each layer. Wherein, a plurality of the second component layers are stacked on the first component layer, The memory cell includes a transistor having a semiconductor layer including an oxide semiconductor and having a channel formation region. The transistor comprises a back gate, The voltage generating circuit provided in each layer has a function of generating a back gate voltage supplied to the back gate of the transistor included in the memory cell provided in the same layer, Furthermore, the temperature detection circuit has a function of controlling the back gate voltage according to the detected temperature.

6. The semiconductor device according to claim 5, Among the plurality of second element layers, a back gate voltage supplied to the transistor included in the second element layer arranged in an upper layer is larger than a back gate voltage supplied to the transistor included in the second element layer arranged in a lower layer.

7. The semiconductor device according to claim 5, The first component layer includes a computing circuit, The stacked second element layer is overlapped in a region where the operation circuit is provided.

8. The semiconductor device according to claim 5, The oxide semiconductor includes In, Ga, and Zn.

9. The semiconductor device according to claim 5, The temperature detection circuit includes a transistor having a semiconductor layer including an oxide semiconductor and having a channel formation region.

10. A semiconductor device comprising: A first element layer is provided with a temperature detection circuit and a voltage generation circuit; a second component layer including an amplifying circuit; as well as A plurality of third element layers of the memory cell are provided, Wherein, a plurality of the second component layers are stacked on the first component layer, A plurality of the third element layers are stacked on the second element layer, The amplifier circuit has a function of amplifying the signal of the storage unit. The amplifier circuit and the memory cell include a transistor having a semiconductor layer including an oxide semiconductor and having a channel formation region. The transistor comprises a back gate, The voltage generating circuit has a function of generating a back gate voltage supplied to the back gate. The temperature detection circuit has a function of controlling the back gate voltage according to the detected temperature. Furthermore, the voltage generating circuit has a function of supplying the back gate voltage as different voltages to each of the second element layer and the plurality of third element layers.

11. The semiconductor device according to claim 10, Among the plurality of second element layers, a back gate voltage supplied to the transistor included in the second element layer arranged in an upper layer is larger than a back gate voltage supplied to the transistor included in the second element layer arranged in a lower layer.

12. The semiconductor device according to claim 10, The oxide semiconductor includes In, Ga, and Zn.

13. The semiconductor device according to claim 10, The first component layer includes an operation circuit having a scan trigger, The scan trigger is electrically connected to a backup circuit having a function of holding data of the scan trigger. And the backup circuit is provided in a region of the second element layer overlapping a region where the scan trigger is provided.

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