Wafer processing method and wafer processing system

Abstract

The purpose of the present invention is to provide a technique capable of etching silicon with high accuracy by removing a natural oxide film. One of the wafer processing methods according to the present invention is a wafer processing method in which a semiconductor wafer having a silicon film formed on the upper surface thereof is disposed in a processing chamber and the silicon film is processed. The wafer processing method includes: forming a first modified layer by supplying particles of a gas of hydrogen, nitrogen, and fluorine to an oxide film formed on the surface of the silicon film; a first detachment step in which the first modified layer is heated and detached; a second modified layer forming step for forming a second modified layer by supplying particles of a chlorine gas to the silicon film after the first detachment step; and a second detachment step for heating the second modified layer to detach the second modified layer.

Description

Technical Field

[0001] The invention relates to a wafer processing method and a wafer processing system. Background Art

[0002] In the field of semiconductor devices, further miniaturization and high integration due to three-dimensional stacking of device structures are being promoted to reduce power consumption and increase storage capacity. Compared with conventional devices, stacked three-dimensional devices are more complex in structure and are often made of isotropic etching that can etch the wafer surface in the lateral direction. On the other hand, the demand for atomic layer-level lateral processing technology has also increased with the progress of miniaturization, and the development of this technology is important.

[0003] As a processing technology at the atomic layer level, atomic layer etching (ALE) is known. Patent document 1 discloses a method for etching a material on a substrate. The method disclosed in Patent document 1 includes: determining process conditions for an atomic layer etching process for a material using a modifying gas and a removal gas; and performing an atomic layer etching process on the material on the substrate as follows: exposing the substrate to a modifying gas to modify the surface of the material, the modifying gas having a modification energy and a release energy relative to the material to be etched, exposing the modified surface to a removal gas and igniting plasma to remove the modified surface, wherein the modification energy is less than the release energy, and the release energy is less than the surface bond energy of the material. Patent document 1 specifically discloses an atomic layer etching (ALE) technology for silicon, which repeats the following cycle: using chlorine gas to generate plasma, forming SiCl on the silicon surface, and then removing the modified surface. x After the metamorphic layer is formed, a wafer bias is applied and Ar ions are used to convert SiCl x Atomic layer etching of silicon is achieved by searching for an ALE Window (hereinafter also referred to as "ALE window") having a self-limiting property in which the etching rate changes according to a bias voltage.

[0004] On the other hand, before etching silicon, a process for removing the natural oxide film is required. Patent document 2 discloses that in a method for removing a silicon oxide film formed on the surface of a processed object W, a removal process is performed, in which HF and NH3 gases are used, and the processing temperature is set within a range of 150 to 200° C., thereby removing the silicon oxide film.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: U.S. Patent Application Publication No. 2020 / 0118835

[0008] Patent Document 2: Japanese Patent Application Publication No. 2010-109335 Summary of the invention

[0009] Problems to be solved by the invention

[0010] In the ALE technology for silicon disclosed in Patent Document 1, the following three points are not fully considered.

[0011] First, since the process is carried out in an ion environment, it is difficult to carry out processing in the horizontal direction.

[0012] Secondly, there is the possibility of roughness caused by ion sputtering.

[0013] Third, the ALE window with self-limiting speed is narrow.

[0014] In addition, in the technology for etching the silicon natural oxide film shown in Patent Document 2, although the silicon natural oxide film is removed, the etching process of silicon after the removal is not studied. Therefore, when etching silicon continues, the semiconductor wafer needs to be transferred to another device, which poses a problem in the efficiency of semiconductor device manufacturing.

[0015] That is, in the above-mentioned conventional technology, the following problems are not considered: in the silicon etching process, the natural oxide film on the silicon is removed to etch the silicon layer isotropically, and the etching amount is controlled with high precision and uniformity over the entire surface of the three-dimensional structure.

[0016] The present invention has been made in consideration of the problems of the related art, and an object of the present invention is to provide a technology capable of removing a natural oxide film and etching silicon with high precision.

[0017] Means for solving problems

[0018] In order to solve the above-mentioned problems, one of the representative wafer processing methods of the present invention is a wafer processing method in which a semiconductor wafer having a silicon film formed on its upper surface is arranged in a processing chamber to process the silicon film, and the method comprises the following steps: supplying particles of hydrogen, nitrogen and fluorine gases to an oxide film formed on the surface of the silicon film to form a first modified layer; a first detachment step of heating the first modified layer to detach it; after the first detachment step, supplying particles of chlorine gas to the silicon film to form a second modified layer; and a second detachment step of heating the second modified layer to detach it.

[0019] Effects of the Invention

[0020] According to the present invention, it is possible to remove the natural oxide film and perform silicon etching with high precision.

[0021] Problems, structures, and effects other than those described above will become apparent from the following description of embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic diagram of an etching process in the manufacturing process of a semiconductor device.

[0023] Figure 2 This is a schematic diagram of an etching processing apparatus.

[0024] Figure 3A This is a schematic diagram of the process of the etching method according to this embodiment.

[0025] Figure 3B This is a schematic diagram of the process of the etching method according to this embodiment.

[0026] Figure 4 This is a diagram showing the experimental results of the relationship between the etching amount and the cycle dependency in the etching method according to the present embodiment.

[0027] Figure 5A The etching amount of polysilicon and the etching rate of the polysilicon in the etching process of this embodiment are shown in FIG. Figure 3B A graph showing experimental results related to the dependence of fluorine radicals, nitrogen radicals, and hydrogen radicals on irradiation time in step (a).

[0028] Figure 5B The etching amount of polysilicon and the etching rate of the polysilicon in the etching process of this embodiment are shown in FIG. Figure 3B A graph showing experimental results related to the time dependence of the adsorption of chlorine radicals in step (b).

[0029] Figure 6 It is the overlap between the etching amount of polysilicon and oxide film. Figure 3B Steps (a) to Figure 3B Plot of the cycle number dependence for the case of step (d).

[0030] Figure 7 This is a schematic diagram of the structure of a wafer processing system that executes the wafer processing method of this embodiment. DETAILED DESCRIPTION

[0031] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present invention is not limited by the embodiments. In addition, in the description of the accompanying drawings, the same reference numerals are used to indicate the same parts.

[0032] In the present disclosure, the so-called "natural oxide film" refers to an oxide film other than an intentionally formed oxide film. It is distinguished from an oxide film formed by thermal oxidation of Si, an oxide film formed by CVD (Chemical Vapor Deposition), an oxide film formed using oxygen free radicals, etc. In addition, when an oxide film is to be formed on a surface parallel to the main surface of the wafer, an oxide film that is not formed in an intentional location, such as an oxide film formed on a surface perpendicular to the main surface of the wafer, is also called a natural oxide film.

[0033] The term "window" refers to appropriate process conditions under which a certain process is performed.

[0034] In addition, the term "upper" refers to the vertically upper direction when a plate-like member or layer is placed horizontally. The term "lower" refers to the vertically lower direction when a plate-like member or layer is placed horizontally. For example, when a plate-like member or a layer included in a plate-like member is shown in the figure, the surface shown above or below in the figure is sometimes referred to as the "upper surface" or "lower surface".

[0035] (Existing example)

[0036] use Figure 1 An example of etching target film and pattern processing of silicon will be described. Figure 1 This is a schematic diagram of an etching process in the manufacturing process of a semiconductor device. Figure 1 (a) is a diagram showing an example of a cross section of an object to be etched. Figure 1 (b) is a diagram showing the object to be processed after etching. Figure 1 As shown in (a), the processing object, i.e., the silicon film 4, is, for example, a silicon film formed on a wafer Wf. The silicon film 4 has a concave-convex shape formed in a direction perpendicular to the main surface of the wafer Wf, and is in a state where a so-called groove (groove) structure is formed. The width of the convex part of the groove (the length in a direction parallel to the direction of the main surface of the wafer Wf) is W1. The silicon nitride film 1 is a film containing a compound of silicon and nitrogen. The silicon oxide film 2 is a film containing a compound of silicon and oxygen. The silicon nitride film 1 and the silicon oxide film 2 have a given pattern shape and function as a mask (hard mask) in the etching process. In addition, a natural oxide film 3 is formed on the surface of the silicon film 4. In addition, a natural oxide film 3 is formed on the surface of the silicon film 4 due to the influence of oxygen and moisture. The silicon oxide film 2 is an oxide film that is intentionally formed so as to function as a mask, but the natural oxide film 3 is an oxide film that is not intentionally formed.

[0037] Figure 1(b) shows the case of an ideal etching process. Since the etching is performed isotropically, the groove expands in a direction parallel to the main surface of the wafer Wf. The width W2 of the convex portion is smaller than the width W1 before the process. In addition, the natural oxide film 3 is also removed by the amount formed, and the shape of the silicon film 4 is maintained unchanged.

[0038] But in reality, it is difficult to obtain Figure 1 When the etching process is performed without removing the natural oxide film 3, the surface roughness of the silicon film 4 deteriorates, which may adversely affect the electrical characteristics of the semiconductor device.

[0039] (Structure of Etching Processing Apparatus)

[0040] use Figure 2 The overall structure of the etching processing apparatus 100 will be described in detail. Figure 2 1 is a schematic diagram of an etching processing apparatus 100. The processing chamber 34 is composed of a bottom chamber (vacuum container) 37, in which a wafer stage 10 for mounting a wafer 9 is provided. A plasma source (ICP plasma source) using an ICP (Inductively Coupled Plasma) discharge method is provided above the processing chamber 34. The ICP plasma source is used to generate a plasma-based reactive gas, and is used for cleaning the inner wall of the chamber and processing a film layer of a processing object on a wafer.

[0041] The cylindrical discharge tube 12 constituting the ICP plasma source is arranged above the processing chamber 34, and the ICP coil 11 is arranged outside the discharge tube 12. The ICP coil 11 is connected to the high-frequency power supply 35 via the matching device 36, and the high-frequency power for plasma generation is supplied. The frequency of the high-frequency power is a frequency of several tens of MHz such as 13.56MHz. A top plate 13 is arranged above the discharge tube 12. A gas dispersion plate 14 and a shower plate 15 are arranged below the top plate 13, and the processing gas is introduced into the discharge tube 12 via the gas dispersion plate 14 and the shower plate 15.

[0042] The supply flow rate of the processing gas is adjusted by a mass flow controller 30 provided for each gas type. In addition, a gas distributor 31 is provided on the downstream side of the mass flow controller 30 to independently control the flow rate and combination of the gas supplied to the center of the discharge tube 12 and the gas supplied to the periphery. In this way, the spatial distribution of the partial pressure of the processing gas can be controlled in detail. Figure 2 , examples of using argon (Ar) gas, nitrogen (N2) gas, hydrogen (H2) gas, sulfur hexafluoride (SF6) gas, difluoromethane (CH2F2) gas, oxygen (O2) gas, and chlorine (Cl2) gas as processing gases are shown, but other gases may also be used.

[0043] At the lower part of the processing chamber 34, an exhaust mechanism 20 is connected via a vacuum exhaust pipe 19 to reduce the pressure of the processing chamber 34. The exhaust mechanism 20 is configured by, for example, a turbomolecular pump, a mechanical intensification pump, or a dry pump, but the structure is not limited thereto. In addition, a pressure regulating mechanism 21 is provided in the vacuum exhaust pipe 19 to adjust the pressure of the processing chamber 34.

[0044] An IR lamp unit for heating the wafer 9 is provided on the wafer stage 10. The IR lamp unit includes an IR lamp 60, a reflector 61 for reflecting IR light, and an IR light transmission window 72. Here, the IR lamp 60 uses circular (round) IR lamps 60-1, 60-2, and 60-3.

[0045] The IR lamp 60 emits light mainly in the visible to infrared region (herein referred to as IR light). In this example, three circles of IR lamps 60-1, 60-2, and 60-3 can be arranged in concentric circles, but can also be arranged in two circles or more than four circles. A reflector 61 is arranged above the IR lamp 60 to reflect the IR light downward (in the wafer setting direction).

[0046] The IR lamp 60 is connected to an IR lamp power supply 73 , and a high-frequency cut filter 74 is provided in the middle of the IR lamp power supply 73 to prevent noise of high-frequency power from flowing into the IR lamp power supply 73 .

[0047] Furthermore, the IR lamp power supply 73 is provided with a function of independently controlling the power supplied to the IR lamps 60 - 1 , 60 - 2 , and 60 - 3 , and can adjust the radial distribution of the heating amount of the wafer (part of the wiring is omitted in the figure).

[0048] A flow path 27 is formed in the center of the IR lamp unit. An ion shielding plate 26 having a plurality of holes for suppressing ions and electrons generated in plasma and allowing neutral gas and neutral radicals to pass therethrough and irradiate the wafer is provided in the flow path 27 .

[0049] A flow path 39 of a coolant for cooling the wafer stage 10 is formed inside the wafer stage 10, and the coolant is circulated and supplied through the flow path 39 by a cooler 38. In addition, in order to fix the wafer 9 by electrostatic adsorption, a plate-shaped electrode plate 40 is embedded in the wafer stage 10 and connected to a DC power supply.

[0050] In order to efficiently cool the wafer 9, helium (He) gas whose flow rate is regulated by the mass flow controller 32 can be supplied between the back side of the wafer 9 and the wafer stage 10. In addition, when heating or cooling is performed while the wafer 9 is adsorbed, the surface (wafer mounting surface) of the wafer stage 10 is coated with a resin such as polyimide so as not to damage the back side of the wafer 9. Furthermore, a thermocouple 70 for measuring the temperature of the wafer stage 10 is provided inside the wafer stage 10, and the thermocouple 70 is connected to a thermocouple thermometer 71.

[0051] (Etching process)

[0052] use Figure 3A as well as Figure 3B The wafer processing method of this embodiment is described below. In the wafer processing method, a semiconductor wafer having a silicon film (silicon film 4) as a processing target formed on its upper surface is placed in a processing chamber, and the silicon film is processed. Figure 3A as well as Figure 3B FIG. 1 is a schematic diagram of the etching process of this embodiment. Figure 3A as well as Figure 3B In FIG. 1 , a portion of the cross-sectional structure of the structure of the processing object is shown, and the atoms constituting the processing object are schematically displayed. Figure 3A In the process shown, the natural oxide film is removed and Figure 3B In the process shown, an etching process is performed on the film to be processed. Figure 3A as well as Figure 3B The processing shown is performed while the wafer 9 is mounted on the wafer stage 10.

[0053] exist Figure 3A The step (a) shows the initial state of the silicon film 4, which is the object to be processed, as a film made of silicon. The natural oxide film 3 is a natural oxide film pre-formed on the surface of the silicon film 4. The silicon film 4 is a silicon layer that is the base of the natural oxide film 3. The silicon film 4 contains regularly arranged silicon atoms. The natural oxide film 3 contains silicon atoms on the surface of the silicon film 4 and oxygen atoms attached in a manner that covers the silicon atoms on the surface. In the present disclosure, the two film types, the natural oxide film 3 and the silicon film 4, are consistently etched in the same device. The detailed process steps are described as follows.

[0054] The silicon film 4 is not limited to being formed on the upper surface of the wafer 9, and may be a silicon film formed on the wafer 9. Furthermore, when the wafer 9 is a silicon wafer, the silicon film 4 may be formed on the surface of the wafer 9.

[0055] In addition, Figure 3A as well as Figure 3B In FIG. 1 , a silicon film 4 is formed on the upper surface of the wafer 9 and a gas is supplied from the upper surface of the silicon film 4. However, the silicon film 4 may also be formed as shown in FIG. Figure 4 That is, the present disclosure is applicable not only to the natural oxide film 3 formed in a direction parallel to the main surface of the wafer 9 but also to the natural oxide film 3 formed in a direction perpendicular to the main surface of the wafer 9 .

[0056] In addition, the natural oxide film 3 in the present disclosure is assumed to be formed under the condition of being placed in the processing chamber 34 during the semiconductor manufacturing process. Since it is known that the thickness is about 1 nanometer (nm), which is equivalent to the thickness of 1 atomic layer, Figure 3A The amount of the film represented by 1 layer.

[0057] Figure 3A Step (b) is a step of supplying particles of hydrogen, nitrogen and fluorine gases to an oxide film previously formed on the surface of a silicon film to form a first modified layer. In addition, the first modified layer contains ammonium fluorosilicate. Figure 3A In the step (b), first, sulfur hexafluoride gas, nitrogen gas and hydrogen gas are supplied and introduced into the discharge region 50. Then, the high-frequency power supply 35 is turned on to supply high-frequency power, and plasma is formed in the discharge region 50. Fluorine (F) radicals, nitrogen (N) radicals, and hydrogen (H) radicals generated in the plasma are supplied to the processing chamber 34 via the flow path 27 and the ion shielding plate 26, and adsorbed on the surface of the wafer 9. The natural oxide film 3 is modified by the reaction of fluorine radicals, nitrogen radicals and hydrogen radicals with the natural oxide film 3, and an ammonium fluorosilicate (NH4)2SiF6 layer (first modified layer) 5 as a compound containing silicon, nitrogen, fluorine and hydrogen is formed on the surface of the silicon film 4.

[0058] Figure 3A Step (c) of the present invention is a first detachment step of heating the first modified layer 5 to detach the first modified layer 5. In the first detachment step, the heating is performed by irradiating the inside of the treatment chamber 34 with electromagnetic waves. Figure 3A In step (c), argon (Ar) of an inert gas is supplied, the high-frequency power supply 35 is turned on to form plasma in the discharge region 50, and the wafer 9 is heated by irradiating infrared rays (IR) through the IR lamp 60. By this method, the natural oxide film 3 is etched (removed) by thermally decomposing and detaching the first modified layer 5 formed on the surface of the silicon film 4. The temperature of the wafer 9 during this reaction is preferably set to 150°C or more. In other words, the silicon film 4 is heated to 150°C or more. Thereafter, the IR lamp is turned off, and the wafer 9 is cooled by supplying helium (He) gas for cooling the wafer to the back side of the wafer 9, so that the temperature of the wafer 9 returns to the temperature of the wafer stage 10. This is to avoid diffusion of silicon atoms from the surface of the silicon film 4.

[0059] In addition, you can also Figure 3A Process (b) and Figure 3AThe step (c) includes a purge step to exhaust the interior of the processing chamber 34 to reduce the pressure. The purge step is performed by operating the exhaust mechanism 20.

[0060] In implementation Figure 3A From step (a) to Figure 3A After the natural oxide film removal process of step (c), the Figure 3B From step (a) to Figure 3B The etching process of the silicon film 4 in step (d) is performed.

[0061] Figure 3B The process (a) is Figure 3A The process after step (c) (first separation step). Figure 3B In step (a), a layer (damaged layer 6) to which particles of hydrogen, nitrogen or fluorine are attached is formed on the surface of the silicon film 4. Specifically, Figure 3B In step (a), first, supply Figure 3A In step (b), sulfur hexafluoride gas, nitrogen gas, and hydrogen gas of the same gas system are introduced into the discharge region 50. Next, the high-frequency power supply 35 is turned on to supply high-frequency power, and plasma is formed in the discharge region 50. Fluorine radicals, nitrogen radicals, and hydrogen radicals generated in the plasma are supplied to the processing chamber 34 via the flow path 27 and the ion shielding plate 26, and adsorbed on the surface of the wafer 9. The fluorine radicals, nitrogen radicals, and hydrogen radicals react with the silicon film 4 to form a damaged layer 6. Thereafter, the gas containing fluorine, nitrogen, and hydrogen atoms remaining in the gas phase is vacuum exhausted (purged).

[0062] Figure 3B Step (a) and Figure 3A Step (b) of the present invention utilizes the same gas system, but by adjusting the flow rate ratio of sulfur hexafluoride gas, nitrogen gas, and hydrogen gas, the amount of Figure 3B The selectivity of the natural oxide film that may be produced during the silicon layer etching process from step (a) to (d). Figure 4 in Figure 3B Step (a) and Figure 3A In step (b), the etching amount of the oxide film before and after adjusting the flow rate ratio of sulfur hexafluoride gas, nitrogen gas, and hydrogen gas is shown as an example. Figure 4 Graph showing the experimental results of the relationship between the etching amount and the cycle dependency in the etching treatment method of this embodiment. By adjusting the flow rate ratio, such as Figure 4 In Figure 3B As shown in the graph (a) of , the generation of the natural oxide film can be almost suppressed.

[0063] Figure 3B The step (b) is a step after the first separation step. Figure 3BStep (b) is a step of supplying chlorine gas particles to the silicon film to form a second modified layer. Figure 3B In step (b), first, a gas containing chlorine atoms (chlorine (Cl2) gas, boron trichloride (BCl3) gas, etc.) is introduced into the discharge region 50. The high-frequency power supply 35 is turned on to supply high-frequency power, and plasma is formed in the discharge region 50. The chlorine (Cl) radicals generated in the plasma are supplied to the processing chamber 34 via the flow path 27 and the ion shielding plate 26, and adsorbed on the surface of the wafer 9. The chlorine radicals react with the damaged layer 6 to form a layer (second modified layer) 7 containing a compound of silicon, fluorine, hydrogen, nitrogen and chlorine. Thereafter, the high-frequency power supply 35 is turned off to stop the plasma generation. Thereafter, the gas containing chlorine atoms remaining in the gas phase is evacuated by vacuum.

[0064] Figure 3B Step (c) of the present invention is a second desorption step of heating the second modified layer to desorb the second modified layer. In the second desorption step, the heating is performed by irradiating electromagnetic waves. Specifically, Figure 3B In step (c), argon (Ar) gas, which is an inert gas, is supplied, and the high frequency power supply 35 is turned on to form plasma in the discharge region 50, and the wafer is heated by the IR lamp 60. By this method, the second modified layer 7 formed on the surface of the silicon film 4 is thermally decomposed and separated, thereby Figure 3B As shown in step (d) of , the second modified layer 7 is removed.

[0065] In addition, you can Figure 3B Process (b) and Figure 3B The step (c) includes a purge step to exhaust the interior of the processing chamber 34 to reduce the pressure. The purge step is performed by operating the exhaust mechanism 20.

[0066] (Process conditions)

[0067] Figure 5A The etching amount of polysilicon and the etching rate of the polysilicon in the etching process of this embodiment are shown in FIG. Figure 3B A graph showing test results related to the dependence of fluorine radicals, nitrogen radicals and hydrogen radicals on irradiation time in step (a). Figure 5B The etching amount of polysilicon and the etching rate of the polysilicon in the etching process of this embodiment are shown in FIG. Figure 3B A graph showing test results related to the dependence of adsorption of chlorine radicals on time in step (b).

[0068] like Figure 5A As shown, in Figure 3B In the case where the irradiation time of the free radicals in step (a) is in the range of 5 (s) to 30 (s), when the second modified layer 7 is formed ( Figure 3B From process (a) to separation ( Figure 3BThe etching amount during the period from step (d) to step (d) is saturated at about 1.2 nm. Figure 5B As shown, in Figure 3B In the step (b), when the time for adsorbing chlorine radicals on the damaged layer 6, i.e., the adsorption time, is set in the range of 10 (s) to 30 (s), when the second modified layer 7 is formed ( Figure 3B process (a)) and when separating ( Figure 3B The etching amount between steps (d) is saturated at about 1.5 nm.

[0069] Therefore, in Figure 3B The irradiation time in (a) is set to the range of 5 (s) to 30 (s) and Figure 3B When the adsorption time in (b) is set in the range of 10 (s) to 30 (s), uniform etching capable of removing one atomic layer can be performed.

[0070] In addition, when etching a pattern having a complex structure such as a deep groove structure, the irradiation time and adsorption time of the free radicals need to be increased so that the free radicals can reach the portion of the film to be processed. On the other hand, if the irradiation time and adsorption time of the free radicals are increased too much, it may turn into a deposit, and there is a concern that the surface roughness may be deteriorated. Therefore, it is desirable to adjust the irradiation time and adsorption time of the free radicals according to the structure of the target pattern.

[0071] Here, according to the wafer processing method disclosed in the present invention, a plurality of steps including the step of forming the second modified layer and the second separation step are regarded as one cycle, and the cycle is performed multiple times to process the silicon film. Figure 3B From step (a) to Figure 3B The process of step (d) is performed to expose the surface of the silicon film 4. If the desired etching amount is not satisfied, the process returns to step (d). Figure 3B Step (a) is repeated Figure 3B From step (a) to Figure 3B The step (d) can finally make the etching amount reach the desired value. Figure 6 It is the overlap between the etching amount of polysilicon and oxide film. Figure 3B From step (a) to Figure 3BThe figure is a graph of the dependence of the etching amount on the number of cycles in the case of step (d). The circular mark shown by point 301 represents the test result of the etching amount of polysilicon, and the square mark shown by point 302 represents the test result of the etching amount of oxide film. The dotted line 401 represents the result of linear regression of the test result of the etching amount in the case of polysilicon. The test result is formed by the dotted line 401 passing through the circular mark representing the measurement result. In this way, as shown by the dotted line 401, polysilicon can be etched linearly by increasing the number of cycles. In addition, since the etching amount of the oxide film does not increase even if the number of cycles is increased, polysilicon can be selectively etched.

[0072] In the present invention, the embodiments are described using a polycrystalline silicon sample as an example of a silicon layer, but the same effect can be obtained even if a single crystal silicon layer or an amorphous silicon layer is used. Figure 6 The comparison between the etching amount of the silicon layer of the present invention and the etching amount of the polycrystalline silicon sample is shown. Point 303 is the etching amount of the single crystal silicon layer processed under the same conditions.

[0073] (Wafer Processing System)

[0074] Figure 7 1 is a schematic diagram of a configuration of a wafer processing system 200 for executing the wafer processing method of the present embodiment. The wafer processing system 200 includes an etching processing apparatus 100 and a control apparatus 500. The control apparatus 500 includes at least one processor 501 and at least one memory 502.

[0075] The control device 500 obtains the temperature from the thermocouple thermometer 71. In addition, the control device 500 controls the operation of the exhaust mechanism 20, the pressure regulating mechanism 21, the high-frequency power supply 35, the mass flow controllers 30, 32, 33, the cooler 38, and the IR lamp power supply 73. In addition, in order to control the operation of the etching processing device 100, the control device 500 is connected to a sensor not shown in the figure, and controls the power supply and the like.

[0076] The memory 502 stores a program. The program is configured to cause the etching processing apparatus 100 to execute the wafer processing method described in this embodiment mode when the program is executed by the processor 501 .

[0077] (Function / Effect)

[0078] like Figure 6 As shown by the dotted line 401, according to the wafer processing method disclosed in the present invention, linear etching can be performed by increasing the number of cycles. Therefore, self-limiting atomic layer etching of the silicon film can be achieved.

[0079] Furthermore, according to the wafer processing method of the present disclosure, the etching process of the silicon film is particularly as follows Figure 3BAs shown in step (a) and step (b), the process is carried out in a radical environment. Since the process in an ion environment can be avoided, it is easy to carry out processing in a direction parallel to the main surface of the wafer in addition to processing in a direction perpendicular to the main surface of the wafer.

[0080] In addition, the condition for making the etching amount uniform is that the irradiation time and adsorption time of the radicals have a margin, and the process window can be ensured. Since the irradiation time and adsorption time are relatively easy to control parameters, it is easy to cope with the deterioration of the surface roughness.

[0081] In addition, according to the wafer processing method disclosed in the present invention, since the processing gas is common, the removal of the natural oxide film and the atomic layer etching of the silicon film can be performed in the same etching processing device. There is no need to transfer the wafer, which can avoid damaging the efficiency of semiconductor device manufacturing.

[0082] As described above, according to the present invention, the natural oxide film can be removed and silicon can be etched with high precision.

[0083] In addition, in this embodiment, an example in which the IR lamp 60 is used to heat the wafer is shown, but the heating method is not limited to this.

[0084] In addition, the present invention is not limited to the above-mentioned embodiments, and includes various modifications. For example, the above-mentioned embodiments are described in detail for easy understanding of the present invention, but are not necessarily limited to all structures described. In addition, a part of the structure in a certain embodiment can be replaced with the structure of other embodiments, and the structure of other embodiments can be added to the structure of a certain embodiment. In addition, other structures can be added, deleted, or replaced with a part of the structure in each embodiment.

[0085] The following description is an example of a method that can be used to implement the present invention, but the present invention is not limited thereto.

[0086] (Method 1)

[0087] An etching method is a method for etching a natural oxide film and a silicon layer formed on silicon, comprising the following steps: placing the wafer on a wafer carrier in a processing chamber inside a vacuum container, supplying fluorine, nitrogen, and hydrogen radicals to the wafer to form a modified layer on the natural oxide film; heating the wafer to remove the modified layer formed on the natural oxide film, and comprising the following steps: supplying fluorine, nitrogen, and hydrogen radicals to the wafer to form a modified layer on the silicon surface after the natural oxide film is removed; supplying chlorine radicals to the wafer to further modify the modified layer formed on the silicon surface, using heating and inert gas plasma discharge to remove the modified layer formed by the adsorption of the chlorine radicals, and repeating the steps of forming a modified layer on the silicon and removing the formed modified layer.

[0088] (Method 2)

[0089] In the etching processing method in mode 1, in the following process, the same gas system containing fluorine, nitrogen, and hydrogen radicals is used, but the selectivity for other films is maintained by adjusting the gas flow ratio, wherein the above process is the following process: fluorine, nitrogen, and hydrogen radicals are supplied to the chip to form a modified layer on the natural oxide film; fluorine, nitrogen, and hydrogen radicals are supplied to the chip to form a modified layer on the silicon surface after the natural oxide film is removed.

[0090] (Method 3)

[0091] In the etching processing apparatus according to Embodiment 1, the modified layer formed on the silicon surface is a layer containing a compound of silicon, fluorine, nitrogen, hydrogen, and chlorine.

[0092] (Method 4)

[0093] In the embodiment 1, the etching treatment method is a uniform treatment method in which silicon oxide film etching including native oxide film etching and silicon etching are performed in the same apparatus.

[0094] Description of Reference Numerals

[0095] 1: Silicon nitride film, 2: Silicon oxide film, 3: Natural oxide film, 4: Silicon film, 5: First modified layer, 6: Damaged layer, 7: Second modified layer, 9: Wafer, 10: Wafer stage, 11: ICP coil, 12: Discharge tube, 13: Top plate, 14: Gas dispersion plate, 15: Shower plate, 19: Vacuum exhaust pipe, 20: Exhaust mechanism, 21: Pressure regulating mechanism, 26: Ion shielding plate, 27: Flow path, 30, 32, 33: Mass flow controller, 34: Processing chamber, 35: high frequency power supply, 36: matching device, 37: bottom chamber, 38: cooler, 39: flow path, 40: electrode plate, 50: discharge area, 60: IR lamp, 61: reflecting plate, 70: thermocouple, 71: thermocouple thermometer, 72: IR light transmission window, 73: power supply for IR lamp, 74: high frequency cutoff filter, 100: etching processing device, 200: wafer processing system, 500: control device, 501: processor, 502: memory.

Claims

1. A wafer processing method, wherein a semiconductor wafer having a silicon film formed on its upper surface is disposed in a processing chamber to process the silicon film, wherein the wafer processing method is characterized by comprising the following steps: supplying particles of hydrogen, nitrogen, and fluorine gases to an oxide film formed on a surface of the silicon film to form a first modified layer; a first detaching step of heating the first modified layer to detach it; After the first release step, supplying chlorine gas particles to the silicon film to form a second modified layer; and The second removal step is to heat the second modified layer to remove it.

2. The wafer processing method according to claim 1, wherein: The plurality of steps including the step of forming the second modified layer and the second desorption step is regarded as one cycle, and this cycle is performed a plurality of times to treat the silicon film.

3. The wafer processing method according to claim 1 or 2, wherein: In the first detachment step or the second detachment step, the heating is performed by irradiating the interior of the processing chamber with electromagnetic waves.

4. The wafer processing method according to claim 1 or 2, wherein: In the first release step, the silicon film is heated to 150° C. or higher.

5. The wafer processing method according to claim 1 or 2, wherein: The first modified layer contains ammonium fluorosilicate.

6. The wafer processing method according to claim 1 or 2, wherein: A layer to which the particles of hydrogen, nitrogen or fluorine are attached is formed on the surface of the silicon film after the first release step.

7. The wafer processing method according to claim 1 or 2, wherein: A purge step is provided between the step of forming the first modified layer and the first detachment step, or between the step of forming the second modified layer and the second detachment step, to exhaust the interior of the processing chamber to reduce the pressure.

8. A wafer processing method, wherein a semiconductor wafer having a silicon film formed thereon is disposed in a processing chamber to process the silicon film, the wafer processing method comprising the following steps: supplying gas particles of hydrogen, nitrogen and fluorine to the silicon film to form a first modified layer; supplying chlorine gas particles to the first modified layer to form a second modified layer; and The second removal step is to heat the second modified layer to remove it.

9. The wafer processing method according to claim 8, wherein: The plurality of steps including the step of forming the second modified layer and the second desorption step is regarded as one cycle, and this cycle is performed a plurality of times to treat the silicon film.

10. The wafer processing method according to claim 8 or 9, wherein: A purge step of exhausting the interior of the processing chamber to reduce the pressure is provided between the step of forming the first modified layer and the step of forming the second modified layer, or between the step of forming the second modified layer and the detachment step.

11. A wafer processing system, comprising placing a semiconductor wafer having a silicon film formed on its upper surface in a processing chamber to process the silicon film, The wafer processing system is characterized by having: Etching treatment device; Processor; and A memory with a program, The program is configured to cause the etching processing apparatus to execute the wafer processing method according to claim 1 when executed by the processor.

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